JP2021019181A - 回路構造 - Google Patents
回路構造 Download PDFInfo
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- JP2021019181A JP2021019181A JP2019235821A JP2019235821A JP2021019181A JP 2021019181 A JP2021019181 A JP 2021019181A JP 2019235821 A JP2019235821 A JP 2019235821A JP 2019235821 A JP2019235821 A JP 2019235821A JP 2021019181 A JP2021019181 A JP 2021019181A
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- Prior art keywords
- transistor
- channel layer
- gate structure
- gate
- connection channel
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Abstract
Description
102、602、1000a、1000b、1114、1216、G1〜G9、GA2、GA3、GA4、GS ゲート構造
102a 第1の端
102b 第2の端
104、1102、1210a、1301、1401、1402、1510、1610、1710、2410、2510 多重接続チャンネル層
106 チャンネル
200 金属絶縁体半導体コンデンサ
202、906 誘電体層
300 電界効果トランジスタ
302、502、1108、1208、S1、S2 ソース領域
304、504、1116、1214、D1、D2 ドレイン領域
306a、306b、I1、I2、I3、I4、IA2〜IA4 絶縁スペーサ
400 金属絶縁体半導体FET
402 ゲート絶縁層
500 トンネルFET
506 ポケットドープ領域
600 全周ゲートチャンネル型FET
604 内部閉チャンネル構造
900 全周ゲート型素子
902 閉チャンネル
904 外部ゲート
1100、1200 基板
1104、1204 マスク層
1106 ゲート孔
1107、1207 ドーピング処理
1110、1202 導電性材料
1112、1212 フィルム層
1118 分離構造
1206 接続トレンチ
1210 チャンネル材料
1300、1400、1500、1600、1700、1810、1820、1910、1920、1930、2000、2100、2200、2300、2400、2500、2600 回路構造
1410 ワイヤ層
2201〜2204 ドープ領域
A1、A1B、B1、B1B 信号
BL、BLB ビット線
CA2、CA3、CA4 分離チャンネル層
CE1〜CE4、CER1、CE、CPE2 チャンネル端
CK1、CK2、CK3、CK1B、CK2B、CK3B クロック信号
COUT、COUT1〜COUT3 チャンネル出力信号
d1 延伸方向
d2 面方向
DIR1 延伸方向
DE1〜DE4、DE、DPE2 ドレイン端
DOUT、DOUT1〜DOUT3 ドレイン出力信号
EW1 外部接続ワイヤ
GE1〜GE4、GAE1、GAE4、GARE1 ゲート端
GS1、GS1B、GS2、GS2B、GS3、GS3B 制御信号
IN、IN1、IN2、C0〜C3、AIN1〜AIN4 入力信号
OUT、OUT0〜OUT3、OUTT 出力信号
s1、s2 間隔
s3 距離
SE1、SE2 ソース端
SIN ソース入力信号
T1〜T8、TR1〜TR4、TO1、TS1〜TS4、TP1、TP2 トランジスタ
VDD 動作電圧
VSS 基準接地電圧
WL ワード線
Z1〜Z3 ゾーン
Claims (13)
- 第1の延伸方向を有する第1のゲート構造であって、互いに向かい合う第1の端および第2の端を有する前記第1のゲート構造と、
前記第1のゲート構造を完全に囲む第1の多重接続チャンネル層と、を備え、前記第1の多重接続チャンネル層の面方向は、前記第1のゲート構造の前記第1の延伸方向に垂直であり、前記第1のゲート構造および前記第1の多重接続チャンネル層は、第1のトランジスタを形成し、
前記第1の多重接続チャンネル層に配置された第2のトランジスタを備え、前記第2のトランジスタの第2のゲート構造またはチャンネルは、前記第1の多重接続チャンネル層に電気的に接続される、回路構造。 - 前記第2のトランジスタは、前記第1のゲート構造の第1の延伸方向と同じ前記第1の延伸方向を有し、互いに向かい合う第1の端および第2の端を有する前記第2のゲート構造を備え、前記第1の多重接続チャンネル層は、前記第2のゲート構造を完全に囲み、前記第2のゲート構造は、前記第1の多重接続チャンネル層に、前記第2のトランジスタのチャンネルを形成する、請求項1に記載の回路構造。
- 前記第1のトランジスタは、前記第1の多重接続チャンネル層を介して、前記第2のトランジスタのチャンネルに電気的に接続される、請求項2に記載の回路構造。
- 前記第2のトランジスタは、
前記第1のゲート構造の第1の延伸方向と同じ前記第1の延伸方向を有し、互いに向かい合う第1の端および第2の端を有する前記第2のゲート構造であって、前記第1の多重接続チャンネル層に配置され、閉領域を囲む、前記第2のゲート構造と、
前記閉領域に配置された分離チャンネル層と、を備え、前記分離チャンネル層と前記第1の多重接続チャンネル層の導電型は同じまたは反対である、請求項1に記載の回路構造。 - 前記第1のトランジスタは、前記第1の多重接続チャンネル層を介して、前記第2のトランジスタの前記第2のゲート構造に電気的に接続された、請求項4に記載の回路構造。
- 第2の延伸方向を有し、互いに向かい合う第1の端および第2の端を有する第3のゲート構造と、
前記第3のゲート構造を完全に囲む第2の多重接続チャンネル層と、をさらに備え、前記第2の多重接続チャンネル層の面方向は、前記第2のゲート構造の前記第2の延伸方向に垂直であり、前記第3のゲート構造および前記第2の多重接続チャンネル層は、第3のトランジスタを形成する、請求項1から5のいずれか一項に記載の回路構造。 - 前記第1のトランジスタは、
第1のソース領域および第1のドレイン領域をさらに備え、前記第1のトランジスタの前記第1のソース領域および前記第1のドレイン領域はそれぞれ、前記第1のゲート構造の前記第1の端および前記第2の端を囲み、
前記第3のトランジスタは、
第2のソース領域および第2のドレイン領域をさらに備え、前記第3のトランジスタの前記第2のソース領域および前記第2のドレイン領域はそれぞれ、前記第3のゲート構造の前記第1の端および前記第2の端を囲み、
前記回路構造は、前記第1のドレイン領域および前記第2のドレイン領域を電気的に接続するように構成されたワイヤ層をさらに備えた、請求項6に記載の回路構造。 - 前記第1の多重接続チャンネル層および前記第2の多重接続チャンネル層の導電型は反対である、請求項7に記載の回路構造。
- 前記第1のトランジスタは、
それぞれ、前記第1のソース領域と前記第1のゲート構造との間に配置され、前記第1のドレイン領域と前記第1のゲート構造との間に配置された、複数の第1の絶縁スペーサをさらに備え、
前記第3のトランジスタは、
それぞれ、前記第2のソース領域と前記第3のゲート構造との間に配置され、前記第2のドレイン領域と前記第3のゲート構造との間に配置された、複数の第2の絶縁スペーサをさらに備えた、請求項7に記載の回路構造。 - 前記回路構造は、論理回路、アナログ回路、およびメモリ回路のうちの少なくとも1つである、請求項1から9のいずれか一項に記載の回路構造。
- 前記回路構造が前記論理回路を備えている場合、前記回路構造は、チャンネル内論理によって論理演算を実行する、請求項10に記載の回路構造。
- 前記回路構造が前記アナログ回路を備えている場合、前記回路構造は、チャンネル内フィードバックを介してフィードバック信号を送信する、請求項10に記載の回路構造。
- 前記回路構造は、チャンネル内電荷伝送による信号伝送を実行する、請求項10に記載の回路構造。
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