JP6965377B2 - 全周チャンネル型半導体装置およびその製造方法 - Google Patents
全周チャンネル型半導体装置およびその製造方法 Download PDFInfo
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Description
102、602、1000a、1000b、1114、1216、G1〜G9、GA2、GA3、GA4、GS ゲート構造
102a 第1の端
102b 第2の端
104、1102、1210a、1301、1401、1402、1510、1610、1710、2410、2510 多重接続チャンネル層
106 チャンネル
200 金属絶縁体半導体コンデンサ
202、906 誘電体層
300 電界効果トランジスタ
302、502、1108、1208、S1、S2 ソース領域
304、504、1116、1214、D1、D2 ドレイン領域
306a、306b、I1、I2、I3、I4、IA2〜IA4 絶縁スペーサ
400 金属絶縁体半導体FET
402 ゲート絶縁層
500 トンネルFET
506 ポケットドープ領域
600 全周ゲートチャンネル型FET
604 内部閉チャンネル構造
900 全周ゲート型素子
902 閉チャンネル
904 外部ゲート
1100、1200 基板
1104、1204 マスク層
1106 ゲート孔
1107、1207 ドーピング処理
1110、1202 導電性材料
1112、1212 フィルム層
1118 分離構造
1206 接続トレンチ
1210 チャンネル材料
1300、1400、1500、1600、1700、1810、1820、1910、1920、1930、2000、2100、2200、2300、2400、2500、2600 回路構造
1410 ワイヤ層
2201〜2204 ドープ領域
A1、A1B、B1、B1B 信号
BL、BLB ビット線
CA2、CA3、CA4 分離チャンネル層
CE1〜CE4、CER1、CE、CPE2 チャンネル端
CK1、CK2、CK3、CK1B、CK2B、CK3B クロック信号
COUT、COUT1〜COUT3 チャンネル出力信号
d1 延伸方向
d2 面方向
DE1〜DE4、DE、DPE2 ドレイン端
DOUT、DOUT1〜DOUT3 ドレイン出力信号
EW1 外部接続ワイヤ
GE1〜GE4、GAE1、GAE4、GARE1 ゲート端
GS1、GS1B、GS2、GS2B、GS3、GS3B 制御信号
IN、IN1、IN2、C0〜C3、AIN1〜AIN4 入力信号
OUT、OUT0〜OUT3、OUTT 出力信号
s1、s2 間隔
s3 距離
SE1、SE2 ソース端
SIN ソース入力信号
T1〜T8、TR1〜TR4、TO1、TS1〜TS4、TP1、TP2 トランジスタ
VDD 動作電圧
VSS 基準接地電圧
WL ワード線
Z1〜Z3 ゾーン
Claims (28)
- 複数のゲート構造であって、同じ延伸方向を有し、前記複数のゲート構造のそれぞれは、互いに向かい合う第1の端および第2の端を有する、複数のゲート構造と、
多重接続チャンネル層であって、前記複数のゲート構造はすべて前記多重接続チャンネル層に囲まれており、前記多重接続チャンネル層の面方向は、前記複数のゲート構造の前記延伸方向に垂直であるため、前記複数のゲート構造のチャンネルは互いに接続される、
多重接続チャンネル層と、
前記複数のゲート構造のそれぞれの前記第1の端および前記第2の端をそれぞれ囲むソース領域およびドレイン領域と、
それぞれ前記ソース領域と前記ゲート構造との間に配置され、同様に前記ドレイン領域と前記ゲート構造との間に配置された複数の絶縁スペーサと、
を備えた、全周チャンネル型半導体装置。 - 前記複数のゲート構造間の間隔は、前記複数のゲート構造のそれぞれの前記第1の端と前記第2の端との間の距離よりも小さく、前記間隔は、前記延伸方向に対して垂直な、前記複数のゲート構造の2つのゲート構造間の距離である、請求項1に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造のそれぞれの断面は、円形、楕円形、長方形、十字形、多角形、または不規則な形状であり、前記断面は、前記延伸方向に対して垂直である、請求項1に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造のそれぞれと、前記多重接続チャンネル層との間に配置された誘電体層をさらに備えた、請求項1に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造のそれぞれと、前記多重接続チャンネル層とがP−N接合を形成する、請求項1に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造のそれぞれと、前記多重接続チャンネル層とが金属半導体接点を形成する、請求項1に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造のそれぞれと、前記多重接続チャンネル層との間に配置されたヘテロ構造であって、ドープされていないヘテロ構造または変調ドープヘテロ構造である前記ヘテロ構造と、をさらに備えた、請求項1に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造のそれぞれは、中空構造であり、前記半導体装置はさらに、
前記複数のゲート構造のそれぞれの中空領域に形成された内部密閉チャンネル構造を、備えた、請求項1に記載の全周チャンネル型半導体装置。 - 前記複数のゲート構造のそれぞれと、前記多重接続チャンネル層との間に配置されたゲート絶縁層と、をさらに備えた、請求項1に記載の全周チャンネル型半導体装置。
- 異なる導電型である前記ソース領域および前記ドレイン領域と、
前記複数のゲート構造のそれぞれと、前記多重接続チャンネル層との間に配置されたゲート絶縁層と、
各ソース領域に配置され、前記複数のゲート構造のそれぞれを囲むポケットドープ領域であって、前記ポケットドープ領域および前記ソース領域は、異なる導電型である前記ポケットドープ領域と、をさらに備えた、請求項1に記載の全周チャンネル型半導体装置。 - 前記絶縁スペーサの厚さは、前記ゲート絶縁層の厚さ以上である、請求項9に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造間の間隔は、前記ソース領域と前記ドレイン領域との間の距離の1倍以内であり、前記間隔は、前記延伸方向に対して垂直な、前記複数のゲート構造の2つのゲート構造間の距離である、請求項1に記載の全周チャンネル型半導体装置。
- 前記ドレイン領域の断面の面積は、前記多重接続チャンネル層の平面の面積よりも小さく、前記断面は、前記延伸方向に垂直である、請求項1に記載の全周チャンネル型半導体装置。
- 前記面方向における前記複数のゲート構造の配置は、ペア配置、規則的配置、または不規則配置である、請求項1に記載の全周チャンネル型半導体装置。
- 前記規則的配置は、三角形配置、四角形配置、五角形配置、または六角形配置を備えた、請求項14に記載の全周チャンネル型半導体装置。
- 前記多重接続チャンネル層に配置された少なくとも1つの全周ゲート型装置をさらに備え、前記全周ゲート型装置の延伸方向は、前記複数のゲート構造の前記延伸方向と同じである、請求項1に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造の一部が、前記面方向に沿って、前記多重接続チャンネル層から外へ延びている、請求項1に記載の全周チャンネル型半導体装置。
- 前記複数のゲート構造は、異なる装置のゲート構造であり、前記異なる装置のゲート構造は、電流または電位によってブロックされる、請求項1に記載の全周チャンネル型半導体装置。
- 複数のゲート構造を形成し、前記複数のゲート構造は、同じ延伸方向を有し、前記複数のゲート構造のそれぞれは、互いに向かい合う第1の端および第2の端を備え、
基板上に多重接続チャンネル層を形成し、前記複数のゲート構造はすべて、前記多重接続チャンネル層に囲まれ、前記多重接続チャンネル層の面方向は、前記ゲート構造の前記延伸方向に垂直であるため、前記ゲート構造のチャンネルは、互いに電気的に接続され、
前記複数のゲート構造を形成する方法は、
前記多重接続チャンネル層を形成した後、前記多重接続チャンネル層に複数のゲート孔を形成することと、
前記複数のゲート孔を、導電性材料で充填することと、
前記複数のゲート孔の外側の前記導電性材料を除去するために、前記導電性材料を平坦化することと、を備えた、全周チャンネル型半導体装置を製造する方法。 - 前記多重接続チャンネル層を形成する方法は、前記基板上にエピタキシャル処理を実行することを備えた、請求項19に記載の全周チャンネル型半導体装置を製造する方法。
- 前記複数のゲート孔を形成した後、前記複数のゲート孔内の前記基板内に複数のソース領域を形成するために、および、前記多重接続チャンネル層の表面に複数のドレイン領域を形成するために、少なくとも1つのドーピング処理を実行することをさらに備えた、請求項19に記載の全周チャンネル型半導体装置を製造する方法。
- 前記複数のゲート孔を形成した後、前記複数のゲート孔のそれぞれの内面に誘電体層、絶縁層、またはヘテロ構造を共形的に形成することをさらに備えた、請求項19に記載の全周チャンネル型半導体装置を製造する方法。
- 複数のゲート構造を形成し、前記複数のゲート構造は、同じ延伸方向を有し、前記複数のゲート構造のそれぞれは、互いに向かい合う第1の端および第2の端を備え、
基板上に多重接続チャンネル層を形成し、前記複数のゲート構造はすべて、前記多重接続チャンネル層に囲まれ、前記多重接続チャンネル層の面方向は、前記ゲート構造の前記延伸方向に垂直であるため、前記ゲート構造のチャンネルは、互いに電気的に接続され、
前記複数のゲート構造を形成する方法は、
前記基板上に導電性材料を形成することと、
前記導電性材料に接続トレンチを形成することと、
前記接続トレンチ内にチャンネル材料を形成することと、
前記接続トレンチの外側の前記チャンネル材料を除去し、前記接続トレンチ内に前記多重接続チャンネル層を得るために、前記チャンネル材料を平坦化することと、
前記導電性材料を金属化することと、を備えた、全周チャンネル型半導体装置を製造する方法。 - 前記導電性材料を形成する方法は、前記基板上にエピタキシャル処理を実行することを備えた、請求項23に記載の全周チャンネル型半導体装置を製造する方法。
- 前記接続トレンチを形成した後、前記接続トレンチ内の前記基板内にソース領域を形成するために、少なくとも1つのドーピング処理を実行することをさらに備えた、請求項23に記載の全周チャンネル型半導体装置を製造する方法。
- 前記チャンネル材料を形成する前に、前記接続トレンチに絶縁分離層を共形的に堆積させることをさらに備えた、請求項23に記載の全周チャンネル型半導体装置を製造する方法。
- 前記チャンネル材料を平坦化した後、前記チャンネル材料の表面にドレイン領域を形成することをさらに備えた、請求項23に記載の全周チャンネル型半導体装置を製造する方法。
- 前記接続トレンチを形成した後、前記接続トレンチの内面に、誘電体層、絶縁層、またはヘテロ構造を共形的に形成することをさらに備えた、請求項23に記載の全周チャンネル型半導体装置を製造する方法。
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US8823090B2 (en) | 2011-02-17 | 2014-09-02 | International Business Machines Corporation | Field-effect transistor and method of creating same |
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US9123802B2 (en) | 2013-10-03 | 2015-09-01 | Texas Instruments Incorporated | Vertical trench MOSFET device in integrated power technologies |
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US10170378B2 (en) | 2016-11-29 | 2019-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate all-around semiconductor device and manufacturing method thereof |
US10186510B2 (en) * | 2017-05-01 | 2019-01-22 | Advanced Micro Devices, Inc. | Vertical gate all around library architecture |
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US11139402B2 (en) * | 2018-05-14 | 2021-10-05 | Synopsys, Inc. | Crystal orientation engineering to achieve consistent nanowire shapes |
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