WO2023173327A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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WO2023173327A1
WO2023173327A1 PCT/CN2022/081202 CN2022081202W WO2023173327A1 WO 2023173327 A1 WO2023173327 A1 WO 2023173327A1 CN 2022081202 W CN2022081202 W CN 2022081202W WO 2023173327 A1 WO2023173327 A1 WO 2023173327A1
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layer
electrode
substrate
light
emitting
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PCT/CN2022/081202
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English (en)
French (fr)
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彭锦涛
牛亚男
高志坤
周婷婷
秦斌
孙双
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京东方科技集团股份有限公司
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Priority to CN202280000491.2A priority Critical patent/CN117204136A/zh
Priority to PCT/CN2022/081202 priority patent/WO2023173327A1/zh
Publication of WO2023173327A1 publication Critical patent/WO2023173327A1/zh

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  • Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically relate to a display substrate and a display device.
  • Silicon-based organic light-emitting diode (OLED) technology as a near-eye micro-display technology, is increasingly used in industry, cultural tourism, medical, drones and other fields, augmented reality (AR) glasses, virtual reality (VR) helmets , infrared detectors, 3D medical equipment, etc. have strong demand for silicon-based OLED display panels, and there is broad room for development of silicon-based OLED display technology.
  • AR augmented reality
  • VR virtual reality
  • CGL charge generation layer
  • Embodiments of the present disclosure provide a display substrate, including a driving structure layer and a light-emitting structure layer sequentially stacked on a substrate.
  • the light-emitting structure layer includes a first electrode layer, a pixel definition layer, a light-emitting functional layer, and a second electrode layer. , the third electrode layer and the electrode insulation layer;
  • the first electrode layer includes a plurality of first electrodes disposed on the driving structure layer, and the pixel defining layer is disposed on a side of the plurality of first electrodes away from the substrate and is provided with a plurality of pixels.
  • Each of the pixel openings exposes the surface of the corresponding first electrode away from the substrate;
  • the pixel definition layer is also provided with a grid-like isolation trench structure, and the isolation trench structure Comprising a plurality of grid units, each grid unit of the isolation trench structure surrounds one of the pixel openings;
  • the third electrode layer and the electrode insulation layer are sequentially stacked on the side of the pixel definition layer away from the substrate, and expose the pixel opening and the isolation trench structure, and the electrode insulation layer Cover the edge portion of the third electrode layer close to the pixel opening;
  • the light-emitting functional layer and the second electrode layer are sequentially stacked on the side of the plurality of first electrodes and the electrode insulating layer away from the substrate, and each of the first electrodes, the light-emitting functional layer
  • the second electrode layer and the second electrode layer form a light-emitting device; the second electrode layer and the third electrode layer are set to the same potential;
  • the light-emitting functional layer includes at least two stacked light-emitting units, and a charge generation layer located between two adjacent light-emitting units.
  • the charge generation layer is disposed between the first electrode and the second electrode layer. Holes and electrons are generated under the action of a voltage, and the charge generation layer is isolated by the isolation trench structure.
  • An embodiment of the present disclosure also provides a display device, including the display substrate.
  • Figure 1a is a partial structural diagram of a display substrate according to some exemplary embodiments
  • Figure 1b is a partial structural schematic diagram of a display substrate according to other exemplary embodiments.
  • Figure 2 is a schematic plan view of a pixel definition layer of a display substrate according to some exemplary embodiments
  • Figure 3 is a schematic structural diagram after forming a driving structure layer and a plurality of first electrodes on a substrate in some exemplary embodiments;
  • Figure 4 is a schematic structural diagram after forming a pixel defining layer in some exemplary embodiments
  • Figure 5 is a schematic structural diagram after forming a third electrode layer in some exemplary embodiments.
  • Figure 6 is a schematic structural diagram after forming an isolation trench structure in some exemplary embodiments.
  • Figure 7 is a schematic structural diagram after forming an electrode insulating layer in some exemplary embodiments.
  • FIG. 8 is a schematic structural diagram after forming a charge generation layer in some exemplary embodiments.
  • Some silicon-based OLED display panels in order to solve problems such as crosstalk between adjacent sub-pixels caused by lateral leakage of CGL, use a method of setting grooves between adjacent sub-pixels to isolate the CGL. Although this method can alleviate the problem to a certain extent.
  • the cathode layer will be concave and form a sharp topography (cathode puncture position) at the position corresponding to the groove.
  • the cathode puncture position due to the tip effect of the electric field, the electric field intensity will rise sharply at this position, which will eventually cause the edge of the sub-pixel to light up in advance and affect the control and realization of the low gray level of the sub-pixel.
  • FIG. 1a is a partial structural schematic diagram of a display substrate of some exemplary embodiments
  • FIG. 2 is a schematic diagram of some exemplary implementations.
  • the display substrate includes a driving structure layer 20 and a light-emitting structure layer 30 that are sequentially stacked on the substrate 10.
  • the light-emitting structure layer 30 includes a first electrode layer, a pixel defining layer 32, light-emitting functional layer 35, second electrode layer 36, third electrode layer 33 and electrode insulating layer 34;
  • the first electrode layer includes a plurality of first electrodes 31 disposed on the driving structure layer 20 , and the pixel definition layer 32 is disposed on a side of the plurality of first electrodes 31 away from the substrate 10 and A plurality of pixel openings 321 are provided, and each pixel opening 321 exposes the surface of a corresponding first electrode 31 away from the substrate 10; the pixel defining layer 32 is also provided with a grid-shaped
  • the isolation trench structure 322 includes a plurality of grid units 3221 (shown in FIG. 2 ), and each grid unit 3221 of the isolation trench structure 322 surrounds one of the pixel openings 321;
  • the third electrode layer 33 and the electrode insulation layer 34 are sequentially stacked on the side of the pixel defining layer 32 away from the substrate 10, and expose the pixel opening 321 and the isolation trench structure 322, And the electrode insulation layer 34 covers the edge portion of the third electrode layer 33 close to the pixel opening 321;
  • the light-emitting functional layer 35 and the second electrode layer 36 are sequentially stacked on the side of the plurality of first electrodes 31 and the electrode insulating layer 34 away from the substrate 10. Each of the first electrodes 31.
  • the light-emitting functional layer 35 and the second electrode layer 36 form a light-emitting device; the second electrode layer 36 and the third electrode layer 33 are set to the same potential;
  • the light-emitting functional layer 35 includes at least two stacked light-emitting units, and a charge generation layer 353 located between two adjacent light-emitting units.
  • the charge generation layer 353 is disposed between the first electrode 31 and the Holes and electrons are generated under the voltage of the second electrode layer 36 , and the charge generation layer 353 is isolated by the isolation trench structure 322 .
  • the pixel definition layer 32 is provided with an isolation trench structure 322 between adjacent sub-pixel areas (ie, the pixel opening 321 area) to isolate the charge generation layer 353, thereby mitigating the problem caused by the charge generation layer 353. Problems such as crosstalk between adjacent sub-pixels caused by lateral leakage occur.
  • a third electrode layer 33 and an electrode insulation layer 34 are sequentially stacked on the side of the pixel definition layer 32 away from the substrate 10 , and the third electrode layer 33 and the second electrode layer 36 are set to the same potential, so that they can be passed through
  • the provided third electrode layer 33 weakens the electric field intensity at the puncture position of the second electrode layer 36, thereby improving the puncture phenomenon of the second electrode layer 36 at the position corresponding to the isolation groove structure 322.
  • the potential of the third electrode layer 33 and the second electrode layer 36 is the same, which can avoid the luminescent material between adjacent sub-pixels due to the existence of voltage between the third electrode layer 33 and the second electrode layer 36. Luminous problem.
  • the electrode insulating layer 34 is configured to cover the edge portion of the third electrode layer 33 close to the pixel opening 321 , so that the first electrode 31 and the third electrode can be connected through the electrode insulating layer 34 .
  • the three electrode layers 33 are separated to avoid leakage problems caused by the overlapping of the light-emitting functional layer 35 between the first electrode 31 and the third electrode layer 33, thereby avoiding an increase in power consumption of the light-emitting device.
  • the third electrode layer 33 is provided with a first opening 331 that exposes the pixel opening 321 , and the first opening 331 is on the substrate 10
  • the orthographic projection includes the orthographic projection of the pixel opening 321 on the substrate 10 .
  • the circumferential sidewalls of the first opening 331 of the third electrode layer 33 are located on the surface of the pixel defining layer 32 away from the substrate 10 to avoid contact with the first electrode 31 to cause leakage.
  • it is beneficial for the electrode insulating layer 34 to completely cover the circumferential sidewall of the first opening 331 of the third electrode layer 33 .
  • the orthographic projection of A contains the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.
  • the circumferential sidewalls of the pixel opening 321 may be sloped, and the end of the pixel opening 321 away from the substrate 10 is larger than the end close to the substrate 10.
  • the pixel opening 321 is located on the substrate.
  • the orthographic projection on 10 may refer to the orthographic projection of an end of the pixel opening 321 away from the substrate 10 on the substrate 10 .
  • the shape of the pixel opening 321 may be a rectangle, a hexagon, a pentagon, a rhombus, etc., and the shape of the pixel opening 321 may be adapted to the shape of the first electrode 31 .
  • the shapes of the plurality of pixel openings 321 may be the same or different. In the embodiment of the present disclosure, the shape and arrangement of the pixel openings 321 are not limited.
  • Each grid unit 3221 of the isolation trench structure 322 is a closed annular structure, and the shape of the grid unit 3221 can be adapted to the shape of the pixel opening 321 it surrounds. In the example of FIG. 2 , the pixel opening 321 is rectangular, and each grid unit 3221 of the isolation trench structure 322 is rectangular.
  • the electrode insulation layer 34 covers the circumferential sidewalls of the pixel opening 321 . In this way, it is beneficial to ensure that the electrode insulating layer 34 completely covers the circumferential sidewall of the first opening 331 of the third electrode layer 33 to isolate the first electrode 31 from the third electrode layer 33 .
  • the material of the electrode insulating layer 34 may be an inorganic insulating material, such as silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ). any one or more.
  • the material of the third electrode layer 33 may be a metal material or an alloy material, for example, it may include any one or more of titanium, aluminum, silver, and copper.
  • the third electrode layer 33 is provided with a second opening 332 exposing the isolation trench structure 322 on the substrate 10
  • the orthographic projection of may include the orthographic projection of the second opening 332 on the substrate 10 .
  • the circumferential sidewalls of the second opening 332 of the third electrode layer 33 can protrude from or be flush with the notch of the isolation trench structure 322, which is beneficial to the isolation trench structure 322 to effectively isolate the charges.
  • Layer 353 is generated.
  • the electrode insulating layer 34 is provided with a third opening 341 that exposes the isolation trench structure 322 , and the third opening 341 is located on the substrate 10
  • the orthographic projection may include the orthographic projection of the second opening 332 on the substrate 10 ; the orthographic projection of the electrode insulation layer 34 on the substrate 10 and the orthographic projection of the isolation trench structure 322 on the substrate 10 Orthographic projections on can have overlapping portions.
  • the circumferential sidewall of the third opening 341 may be slightly indented compared to the circumferential sidewall of the second opening 332 to prevent the electrode insulating layer 34 from protruding and causing the risk of breakage.
  • the orthographic projection of the electrode insulating layer 34 on the substrate 10 may include The orthographic projection of the third electrode layer 33 on the substrate 10 .
  • the third electrode layer 33 is provided with a second opening 332 that exposes the isolation trench structure 322
  • the electrode insulation layer 34 is provided with a second opening 332 that exposes the isolation groove structure 322
  • the orthographic projection of the third opening 341 of the groove structure 322 and the second opening 332 on the substrate 10 may include the orthographic projection of the third opening 341 on the substrate 10
  • the electrode insulating layer 34 may completely cover the circumferential sidewall of the second opening 332 of the third electrode layer 33 .
  • the orthographic projection of the isolation trench structure 322 on the substrate 10 may include the orthographic projection of the third opening 341 on the substrate 10 .
  • the circumferential sidewall of the third opening 341 may protrude from or be flush with the notch of the isolation groove structure 322 .
  • the sidewalls of the first electrode 31 in the thickness direction are slope-shaped, and the sidewalls of the first electrode 31 in the thickness direction are in contact with the first electrode.
  • the included angle ⁇ of the surface of 31 facing the substrate 10 may be 60 degrees to 80 degrees. In this way, the sidewall slope of the first electrode 31 in the thickness direction is gentle, which can alleviate the sharp topography of the second electrode layer 36 at the position corresponding to the edge of the first electrode 31 and alleviate the sharp shape of the second electrode layer 36 at this position. puncture phenomenon.
  • the circumferential side surfaces of the isolation groove structure 322 may be recessed compared to the slot openings of the isolation groove structure 322 . In this way, when the charge generation layer 353 is formed by evaporation, it is more conducive for the isolation trench structure 322 to isolate the charge generation layer 353 .
  • the bottom surface of the isolation trench structure 322 may be an arc-shaped concave surface that is concave toward the substrate 10 .
  • the circumferential side of the isolation groove structure 322 can be an arc surface and is smoothly connected to the bottom surface.
  • the subsequently formed second electrode layer 36 has a relatively gentle shape at the position corresponding to the isolation trench structure 322, and is less likely to form a sharp shape, thereby alleviating the puncture phenomenon of the second electrode layer 36 at this position.
  • the isolation trench structure 322 may penetrate the pixel definition layer 32 and be partially located in the driving structure layer 20 .
  • the driving structure layer 20 may include a pixel driving circuit disposed on the substrate 10 and a flat layer away from the substrate 10 , and the first electrode 31 is disposed on the flat layer and passes through The via hole provided in the flat layer is connected to the pixel driving circuit.
  • the isolation trench structure 322 may penetrate the pixel defining layer 32 and be partially located in the planarization layer. In other embodiments, when the thickness of the pixel defining layer 32 is relatively thick, the isolation trench structure 322 may not penetrate the pixel defining layer 32 .
  • the display substrate includes a display area and a non-display area located at the periphery of the display area.
  • the third electrode layer is located in the display area and can extend to the non-display area, and can be driven by the non-display area.
  • the via holes provided in the structural layer are connected to the wiring in the driving structural layer in the non-display area, so that the potentials of the third electrode layer and the second electrode layer are the same.
  • the display substrate may be a silicon-based OLED display substrate
  • the driving structure layer 20 includes a plurality of pixel driving circuits disposed on the silicon-based substrate 10.
  • the pixel driving circuit can be manufactured using CMOS (complementary metal oxide semiconductor) integrated circuit technology.
  • the pixel driving circuit may include a plurality of transistors (T) 201 and a storage capacitor (C).
  • the pixel driving circuit may be a 3T1C, 5T1C or 7T1C circuit structure, which is not limited in this disclosure.
  • the display substrate may be a silicon-based OLED display substrate.
  • the light-emitting functional layer 35 may include a first light-emitting unit 351, the charge generation layer 353 and a second light-emitting unit 352 stacked sequentially in a direction away from the substrate 10; the first light-emitting unit 351 includes a stacked
  • the second light-emitting unit 352 includes a first light-emitting layer capable of emitting red light and a second light-emitting layer capable of emitting green light.
  • the second light-emitting unit 352 includes a third light-emitting layer capable of emitting blue light. In this way, under the voltage of the first electrode 31 and the second electrode layer 36, the light emitting device can emit light through the superposition of the light emitted by the first light emitting layer, the second light emitting layer and the third light emitting layer. white light.
  • the light-emitting device may include a first electrode (anode), a first hole injection layer, a first hole transport layer, a first light-emitting layer, and a second light-emitting layer sequentially stacked in a direction away from the substrate. layer, first electron transport layer, charge generation layer, second hole injection layer, second hole transport layer, third hole transport layer, third light emitting layer, hole blocking layer, second electron transport layer, electron injection layer and second electrode (cathode) layer.
  • the display substrate may further include an encapsulation structure layer 40 disposed on a side of the second electrode layer 36 away from the substrate 10 .
  • the encapsulation structure layer 40 may include multiple stacked layers of inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) to block external water and oxygen and protect the light-emitting device.
  • the display substrate may further include a color filter layer disposed on a side of the packaging structure layer away from the substrate.
  • the color filter layer may include a plurality of filter units that can transmit light of a set color, such as , including a red filter unit that transmits red light, a green filter unit that transmits green light, and a blue filter unit that transmits blue light.
  • the white light emitted by each light-emitting device can illuminate a filter unit and emit light of a corresponding color.
  • the following is an exemplary description of the preparation process of the display substrate according to the embodiment of the present disclosure.
  • the "patterning process” referred to in this disclosure includes photoresist coating, mask exposure, development, etching and photoresist stripping processes.
  • Deposition can use any one or more of sputtering, evaporation and chemical vapor deposition.
  • Coating can use any one or more of spraying and spin coating.
  • Etching can use any one or more of dry etching and wet etching. one or more.
  • Thin film refers to a thin film produced by depositing or coating a certain material on a substrate.
  • the "thin film” can also be called a "layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • a and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.
  • the display substrate illustrated in Figure 1a is a silicon-based OLED display substrate as an example.
  • the preparation process may include the following steps:
  • the substrate 10 may be a silicon-based substrate 10, such as a single crystal silicon substrate 10.
  • a CMOS integrated circuit process is used to prepare a pixel driving circuit and some signal lines (including data signal lines) on the silicon-based substrate 10. , scanning signal lines, power lines, etc.).
  • the pixel driving circuit may include a plurality of transistors (T) 201 and a storage capacitor (C).
  • the pixel driving circuit may be a 3T1C, 5T1C or 7T1C circuit structure, which is not limited in this disclosure.
  • a plurality of first electrodes 31 are formed on the driving structure layer 20 .
  • forming the plurality of first electrodes 31 may include: depositing a first electrode 31 film on the driving structure layer 20, patterning the first electrode 31 film through a patterning process to form a first electrode layer, and a first electrode layer.
  • the electrode layer includes a plurality of first electrodes 31 .
  • the first electrode 31 is connected to the pixel driving circuit in the driving structure layer 20 through a via hole provided in the driving structure layer 20 . As shown in Figure 3.
  • Form the pixel defining layer 32 may include: forming a pixel defining film on the substrate 10 on which the foregoing pattern is formed, and patterning the pixel defining film through a patterning process to form the pixel defining layer 32 .
  • the pixel defining layer 32 is provided with a plurality of pixel openings 321 , and each pixel opening 321 exposes the surface of a corresponding first electrode 31 away from the substrate 10 . As shown in Figure 4.
  • the third electrode layer 33 is formed.
  • forming the third electrode layer 33 may include: depositing a third electrode film on the substrate 10 on which the foregoing pattern is formed, and patterning the third electrode film through a patterning process to form the third electrode layer 33 .
  • the third electrode layer 33 is provided with a first opening 331 and a second opening 332 that expose the pixel opening 321 , wherein the orthographic projection of the first opening 331 on the substrate 10 includes the pixel opening 321 on the substrate 10 . Orthographic projection on the substrate 10 . As shown in Figure 5.
  • forming the isolation trench structure 322 may include: coating a photoresist on the substrate 10 on which the foregoing pattern is formed, and then removing the photoresist at the position of the second opening 332 through exposure and development, and forming the pixel definition layer. The portion of 32 exposed by the second opening 332 is etched to form an isolation trench structure 322 on the pixel defining layer 32, and then the photoresist is removed. For example, the isolation trench structure 322 may penetrate the pixel definition layer 32 and be partially located in the driving structure layer 20 . As shown in Figure 6.
  • the electrode insulating layer 34 is formed.
  • forming the electrode insulating layer 34 may include: forming an electrode insulating film on the substrate 10 on which the foregoing pattern is formed, and patterning the electrode insulating film through a patterning process to form the electrode insulating layer 34 .
  • the electrode insulation layer 34 completely covers the third electrode layer 33 and exposes the pixel opening 321 and the isolation trench structure 322 (the third opening 341 provided in the electrode insulation layer 34 exposes the isolation trench structure 322). As shown in Figure 7.
  • Form the light-emitting functional layer 35 may include: sequentially evaporating various film layers of the light-emitting functional layer 35 on the substrate 10 on which the foregoing pattern is formed, wherein the light-emitting functional layer 35 may include a film along a line away from the substrate 10
  • the first light-emitting unit 351, the charge generation layer 353 and the second light-emitting unit 352 are stacked in sequence; the first light-emitting unit 351 includes a stacked first light-emitting layer capable of emitting red light and a layer capable of emitting green light.
  • the second light-emitting layer, the second light-emitting unit 352 includes a third light-emitting layer capable of emitting blue light.
  • the charge generation layer 353 will be naturally disconnected at the isolation trench structure 322 . As shown in Figure 8.
  • the second electrode layer 36 is formed.
  • an evaporation process may be used to form the second electrode layer 36 on the substrate 10 on which the foregoing pattern is formed. As shown in Figure 1a.
  • film layers such as the packaging structure layer 40 and the color filter layer are sequentially formed on the side of the second electrode layer 36 away from the substrate 10 .
  • the electrode insulating layer 34 pattern may be formed, and then the isolation trench may be formed on the pixel defining layer 32 Structure322.
  • the specific process please refer to the preparation process of the display substrate illustrated in Figure 1a.
  • An embodiment of the present disclosure also provides a display device, including the display substrate described in any of the previous embodiments.
  • the display device may be a near-eye display device, such as AR/VR glasses, helmet-mounted display, virtual reality all-in-one machine, etc.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to a region through which current mainly flows.
  • first pole in order to distinguish the two poles of the transistor except the control electrode, one pole is directly described as the first pole and the other pole is the second pole.
  • the first pole can be the drain electrode and the second pole can be the source electrode.
  • the first electrode can be the source electrode and the second electrode can be the drain electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and less than 10°, and therefore includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • connection means a fixed connection or a detachable connection, or Integrated connection
  • installation means a fixed connection or a detachable connection, or Integrated connection
  • installation can be directly connected, or indirectly connected through an intermediary, or internal communication between two components.

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Abstract

一种显示基板，包括设于衬底上的发光结构层，发光结构层包括第一电极层、像素界定层、发光功能层、第二电极层、第三电极层以及电极绝缘层；第一电极层包括多个第一电极，像素界定层设有暴露出第一电极的像素开口和呈网格状的隔离槽结构；第三电极层和电极绝缘层依次叠设于像素界定层的远离衬底一侧，并暴露出像素开口和隔离槽结构，且电极绝缘层将第三电极层的靠近像素开口的边缘部分包覆；发光功能层和第二电极层依次叠设于多个第一电极和电极绝缘层的远离衬底一侧；第二电极层与第三电极层设置为等电位；发光功能层包括叠设的至少两个发光单元以及位于相邻两个发光单元之间的电荷产生层，电荷产生层被隔离槽结构隔断。

Description

显示基板及显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及一种显示基板及显示装置。
背景技术
硅基有机发光二极管(OLED)技术作为一种近眼微显示技术，越来越广泛地应用于工业、文旅、医疗、无人机等领域，增强现实(AR)眼镜、虚拟现实(VR)头盔、红外探测器、3D医疗设备等对硅基OLED显示面板需求旺盛，硅基OLED显示技术发展空间广阔。
硅基OLED显示面板因像素密度(PPI)较高，导致子像素及子像素间距特别小，因此一般采用整面蒸镀发光材料制备白光器件，配合RGB(红绿蓝)彩膜来实现全彩显示。此外，为了提升硅基OLED微型显示器的效能、亮度和寿命，带有两个以上发光层的叠层OLED器件(串联式OLED器件)被采用，即应用电荷产生层(CGL)串连两个发光单元，使器件实现发光叠加的效果，可成功提升电流效率、输出亮度、操作寿命等重要光电性能。其中，CGL的载流子迁移率较高，具备较高的导电性，当相邻子像素的阳极电位不同时，沿CGL会产生一定的横向漏电，引发相邻子像素的串扰等问题。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板，包括依次叠设于衬底上的驱动结构层和发光结构层，所述发光结构层包括第一电极层、像素界定层、发光功能层、第二电极层、第三电极层以及电极绝缘层；
所述第一电极层包括设置在所述驱动结构层上的多个第一电极，所述像素界定层设于所述多个第一电极的远离所述衬底一侧并设有多个像素开口， 每个所述像素开口将对应的一个所述第一电极的远离所述衬底的表面暴露出；所述像素界定层还设有呈网格状的隔离槽结构，所述隔离槽结构包括多个网格单元，所述隔离槽结构的每个网格单元将一个所述像素开口包围；
所述第三电极层和所述电极绝缘层依次叠设于所述像素界定层的远离所述衬底一侧，并暴露出所述像素开口和所述隔离槽结构，且所述电极绝缘层将所述第三电极层的靠近所述像素开口的边缘部分包覆；
所述发光功能层和所述第二电极层依次叠设于所述多个第一电极和所述电极绝缘层的远离所述衬底一侧，每个所述第一电极、所述发光功能层和所述第二电极层形成一个发光器件；所述第二电极层与所述第三电极层设置为等电位；
所述发光功能层包括叠设的至少两个发光单元，以及位于相邻两个发光单元之间的电荷产生层，所述电荷产生层设置为在所述第一电极和所述第二电极层的电压作用下产生空穴和电子，所述电荷产生层被所述隔离槽结构隔断。
本公开实施例还提供一种显示装置，包括所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1a为一些示例性实施例的显示基板的局部结构示意图；
图1b为另一些示例性实施例的显示基板的局部结构示意图；
图2为一些示例性实施例的显示基板的像素界定层的平面结构示意图；
图3为在一些示例性实施例中在衬底上形成驱动结构层和多个第一电极后的结构示意图；
图4为在一些示例性实施例中形成像素界定层后的结构示意图；
图5为在一些示例性实施例中形成第三电极层后的结构示意图；
图6为在一些示例性实施例中形成隔离槽结构后的结构示意图；
图7为在一些示例性实施例中形成电极绝缘层后的结构示意图；
图8为在一些示例性实施例中形成电荷产生层后的结构示意图。
具体实施方式
本领域的普通技术人员应当理解，可以对本公开实施例的技术方案进行修改或者等同替换，而不脱离本公开实施例技术方案的精神和范围，均应涵盖在本公开的权利要求范围当中。
一些硅基OLED显示面板，为了解决由于CGL产生横向漏电导致的相邻子像素的串扰等问题，采用在相邻子像素之间设置凹槽的方式来隔断CGL，该方式虽然能一定程度上缓解相邻子像素之间的串扰问题，但由于设置凹槽，阴极层会在对应于凹槽的位置呈凹陷状且形成尖锐形貌(阴极穿刺位置)。阴极穿刺位置，因为电场的尖端效应，电场强度会在该位置急剧升高，最终会导致子像素边缘提前起亮，并影响子像素低灰阶的控制和实现。
本公开实施例提供一种显示基板，在一些示例性实施例中，如图1a和图2所示，图1a为一些示例性实施例的显示基板的局部结构示意图，图2为一些示例性实施例的显示基板的像素界定层的平面结构示意图，所述显示基板包括依次叠设于衬底10上的驱动结构层20和发光结构层30，所述发光结构层30包括第一电极层、像素界定层32、发光功能层35、第二电极层36、第三电极层33以及电极绝缘层34；
所述第一电极层包括设置在所述驱动结构层20上的多个第一电极31，所述像素界定层32设于所述多个第一电极31的远离所述衬底10一侧并设有多个像素开口321，每个所述像素开口321将对应的一个所述第一电极31的远离所述衬底10的表面暴露出；所述像素界定层32还设有呈网格状的隔离槽结构322，所述隔离槽结构322包括多个网格单元3221(图2示出)，所述隔离槽结构322的每个网格单元3221将一个所述像素开口321包围；
所述第三电极层33和所述电极绝缘层34依次叠设于所述像素界定层32 的远离所述衬底10一侧，并暴露出所述像素开口321和所述隔离槽结构322，且所述电极绝缘层34将所述第三电极层33的靠近所述像素开口321的边缘部分包覆；
所述发光功能层35和所述第二电极层36依次叠设于所述多个第一电极31和所述电极绝缘层34的远离所述衬底10一侧，每个所述第一电极31、所述发光功能层35和所述第二电极层36形成一个发光器件；所述第二电极层36与所述第三电极层33设置为等电位；
所述发光功能层35包括叠设的至少两个发光单元，以及位于相邻两个发光单元之间的电荷产生层353，所述电荷产生层353设置为在所述第一电极31和所述第二电极层36的电压作用下产生空穴和电子，所述电荷产生层353被所述隔离槽结构322隔断。
本公开实施例的显示基板，像素界定层32在相邻子像素区域(即像素开口321区域)之间设有隔离槽结构322，以隔断电荷产生层353，由此可以缓解由于电荷产生层353产生横向漏电导致的相邻子像素的串扰等问题。此外，在像素界定层32的远离衬底10一侧依次叠设有第三电极层33和电极绝缘层34，且第三电极层33与第二电极层36设置为等电位，由此可通过设置的第三电极层33减弱第二电极层36穿刺位置的电场强度，进而改善第二电极层36在对应于隔离槽结构322位置处的穿刺现象。所述第三电极层33与所述第二电极层36的电位相同，可以避免由于第三电极层33与所述第二电极层36之间存在电压而导致相邻子像素之间的发光材料发光问题。另外，所述电极绝缘层34设置为将所述第三电极层33的靠近所述像素开口321的边缘部分包覆，这样，可以通过电极绝缘层34将所述第一电极31和所述第三电极层33隔开，避免所述第一电极31和所述第三电极层33之间通过所述发光功能层35搭接而导致的漏电问题，从而避免导致发光器件功耗增加。
在一些示例性实施例中，如图1a所示，所述第三电极层33设有暴露出所述像素开口321的第一开口331，所述第一开口331在所述衬底10上的正投影包含所述像素开口321在所述衬底10上的正投影。这样，所述第三电极层33的所述第一开口331的周向侧壁是位于所述像素界定层32的远离所述衬底10的表面上，避免与第一电极31接触而产生漏电，且有利于电极绝缘 层34将所述第三电极层33的所述第一开口331的周向侧壁完全包覆。
本文中所说的“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
本文中，所述像素开口321的周向侧壁可以是斜面，像素开口321的远离衬底10的一端相较于靠近衬底10的一端开口较大，所述像素开口321在所述衬底10上的正投影可以是指像素开口321的远离衬底10的一端在所述衬底10上的正投影。
示例性地，所述像素开口321的形状可以是矩形、六边形、五边形、菱形等，像素开口321的形状可以与第一电极31的形状相适配。多个像素开口321的形状可以相同或不同。本公开实施例中对所述像素开口321的形状和排布方式不做限制。所述隔离槽结构322的每个网格单元3221为闭合的环状结构，网格单元3221的形状可以与其包围的像素开口321的形状相适配。图2的示例中，像素开口321为矩形，所述隔离槽结构322的每个网格单元3221为矩形。
在一些示例性实施例中，如图1a所示，所述电极绝缘层34将所述像素开口321的周向侧壁覆盖。这样，有利于保证所述电极绝缘层34将所述第三电极层33的所述第一开口331的周向侧壁完全包覆，以将第一电极31与第三电极层33隔绝。
在一些示例性实施例中，所述电极绝缘层34的材料可以采用无机绝缘材料，比如可以包括氮化硅(SiN x)、氧化硅(SiO x)、氮氧化硅(SiO xN y)中的任一种或多种。所述第三电极层33的材料可以为金属材料或者合金材料，比如可以包括钛、铝、银、铜中的任一种或多种。
在一些示例性实施例中，如图1a所示，所述第三电极层33设有暴露出所述隔离槽结构322的第二开口332，所述隔离槽结构322在所述衬底10上的正投影可以包含所述第二开口332在所述衬底10上的正投影。这样，所述第三电极层33的所述第二开口332的周向侧壁可以凸出于或平齐于所述隔离槽结构322的槽口，有利于隔离槽结构322有效隔断所述电荷产生层353。
本实施例的一个示例中，如图1a所示，所述电极绝缘层34设有暴露出所述隔离槽结构322的第三开口341，所述第三开口341在所述衬底10上的 正投影可以包含所述第二开口332在所述衬底10上的正投影；所述电极绝缘层34在所述衬底10上的正投影与所述隔离槽结构322在所述衬底10上的正投影可以存在交叠部分。本示例中，所述第三开口341的周向侧壁相较于所述第二开口332的周向侧壁可以有少量的内缩量，以避免电极绝缘层34凸出而发生断裂风险。
在另一些示例性实施例中，如图1b所示，图1b为另一些示例性实施例的显示基板的局部结构示意图，所述电极绝缘层34在所述衬底10上的正投影可以包含所述第三电极层33在所述衬底10上的正投影。
本实施例的一个示例中，如图1b所示，所述第三电极层33设有暴露出所述隔离槽结构322的第二开口332，所述电极绝缘层34设有暴露出所述隔离槽结构322的第三开口341，所述第二开口332在所述衬底10上的正投影可以包含所述第三开口341在所述衬底10上的正投影。本示例中，电极绝缘层34可以将第三电极层33的第二开口332的周向侧壁完全包覆。
本实施例的一个示例中，如图1b所示，所述隔离槽结构322在所述衬底10上的正投影可以包含所述第三开口341在所述衬底10上的正投影。本示例中，所述第三开口341的周向侧壁可以可以凸出于或平齐于所述隔离槽结构322的槽口。
在一些示例性实施例中，如图1a所示，所述第一电极31在厚度方向上的侧壁为斜坡状，所述第一电极31在厚度方向上的侧壁与所述第一电极31的朝向所述衬底10的表面的夹角α可以为60度至80度。这样，所述第一电极31在厚度方向上的侧壁坡度较缓，可以缓解第二电极层36在对应于第一电极31边缘位置处的尖锐形貌，缓解第二电极层36在该位置的穿刺现象。
在一些示例性实施例中，如图1a所示，所述隔离槽结构322的周向侧面相较于所述隔离槽结构322的槽口可以内缩。这样，在蒸镀形成所述电荷产生层353时，更有利于所述隔离槽结构322将所述电荷产生层353隔断。
本实施例的一个示例中，如图1a所示，所述隔离槽结构322的底面可以为向靠近所述衬底10的方向凹陷的弧形凹面。所述隔离槽结构322的周向侧面可以为弧面并与底面之间圆滑连接。这样，后续形成的第二电极层36在对应于所述隔离槽结构322的位置处形貌较为平缓，不易形成尖锐形貌，缓解 第二电极层36在该位置的穿刺现象。
在一些示例性实施例中，如图1a所示，所述隔离槽结构322可以贯穿所述像素界定层32并部分地位于所述驱动结构层20中。示例性地，所述驱动结构层20可以包括设置在所述衬底10上的像素驱动电路和远离所述衬底10的平坦层，所述第一电极31设置在所述平坦层上并通过所述平坦层设置的过孔与所述像素驱动电路连接。所述隔离槽结构322可以贯穿所述像素界定层32并部分地位于所述平坦层中。在其他实施方式中，所述像素界定层32的厚度较厚的情况下，所述隔离槽结构322可以不贯穿所述像素界定层32。
在一些示例性实施例中，所述显示基板包括显示区和位于显示区外围的非显示区，所述第三电极层位于显示区并可以延伸至非显示区，并可通过非显示区的驱动结构层设置的过孔与非显示区的驱动结构层中的走线连接，使得所述第三电极层与所述第二电极层的电位相同。
在一些示例性实施例中，如图1a所示，所述显示基板可以为硅基OLED显示基板，所述驱动结构层20包括设置在硅基衬底10上的多个像素驱动电路，所述像素驱动电路可以采用CMOS(互补金属氧化物半导体)集成电路工艺制备。所述像素驱动电路可以包括多个晶体管(T)201和存储电容(C)，所述像素驱动电路可以是3T1C、5T1C或7T1C等电路结构，本公开对此不做限定。
在一些示例性实施例中，如图1a所示，所述显示基板可以为硅基OLED显示基板。所述发光功能层35可以包括沿远离所述衬底10方向依次叠设的第一发光单元351、所述电荷产生层353和第二发光单元352；所述第一发光单元351包括叠设的能够发射红光的第一发光层和能够发射绿光的第二发光层，所述第二发光单元352包括能够发射蓝光的第三发光层。这样，在所述第一电极31和所述第二电极层36的电压作用下，通过第一发光层、第二发光层和第三发光层发射的光线的叠加，可使得所述发光器件发射白光。
示例性地，所述发光器件可以包括沿远离所述衬底方向依次叠设的第一电极(阳极)、第一空穴注入层、第一空穴传输层、第一发光层、第二发光层、第一电子传输层、电荷产生层、第二空穴注入层、第二空穴传输层、第三空穴传输层、第三发光层、空穴阻挡层、第二电子传输层、电子注入层和 第二电极(阴极)层。
在一些示例性实施例中，如图1a所示，所述显示基板还可以包括设于所述第二电极层36的远离所述衬底10一侧的封装结构层40，所述封装结构层40可以包括叠设的多个无机材料(比如氧化硅、氮化硅、氮氧化硅等)层，起到阻隔外界水氧的作用，保护发光器件。所述显示基板还可以包括设置在所述封装结构层的远离所述衬底一侧的彩色滤光层，所述彩色滤光层可以包括多个可以透射设定颜色光的滤光单元，比如，包括透射红光的红色滤光单元、透射绿光的绿色滤光单元和透射蓝光的蓝色滤光单元。每个发光器件发射的白光可以照射到一个滤光单元并出射相应颜色的光。
下面对本公开实施例的显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”包括涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成。本公开中所说的“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
以图1a示例的显示基板的结构为例，说明本公开实施例的显示基板的制备过程，图1a示例的显示基板为硅基OLED显示基板为例，所述制备过程可以包括如下步骤：
(1)在衬底10上形成驱动结构层20。示例性地，所述衬底10可以为硅基衬底10，比如单晶硅衬底10，采用CMOS集成电路工艺在硅基衬底10上制备像素驱动电路和一些信号线(包括数据信号线、扫描信号线、电源线等)。所述像素驱动电路可以包括多个晶体管(T)201和存储电容(C)，所述像素驱动电路可以是3T1C、5T1C或7T1C等电路结构，本公开对此不做限定。
(2)在驱动结构层20上形成多个第一电极31。示例性地，形成多个第一电极31可以包括：在驱动结构层20上沉积第一电极31薄膜，通过图案化工艺对第一电极31薄膜进行图案化处理，形成第一电极层，第一电极层包括多个第一电极31。第一电极31通过所述驱动结构层20设置的过孔与所述驱动结构层20中的像素驱动电路连接。如图3所示。
(3)形成像素界定层32。示例性地，形成像素界定层32可以包括：在形成前述图案的衬底10上形成像素界定薄膜，通过图案化工艺对像素界定薄膜进行图案化处理，形成像素界定层32。像素界定层32设有多个像素开口321，每个像素开口321将对应的一个第一电极31的远离所述衬底10的表面暴露出。如图4所示。
(4)形成第三电极层33。示例性地，形成第三电极层33可以包括：在形成前述图案的衬底10上沉积第三电极薄膜，通过图案化工艺对第三电极薄膜进行图案化处理，形成第三电极层33。第三电极层33设有暴露出所述像素开口321的第一开口331以及第二开口332，其中，所述第一开口331在所述衬底10上的正投影包含所述像素开口321在所述衬底10上的正投影。如图5所示。
(5)形成隔离槽结构322。示例性地，形成隔离槽结构322可以包括：在形成前述图案的衬底10上涂覆光刻胶，然后经过曝光和显影去除所述第二开口332位置处的光刻胶，对像素界定层32的被所述第二开口332暴露出的部分进行刻蚀，从而在所述像素界定层32上形成隔离槽结构322，然后去除光刻胶。示例性地，所述隔离槽结构322可以贯穿所述像素界定层32并部分地位于所述驱动结构层20中。如图6所示。
(6)形成电极绝缘层34。示例性地，形成电极绝缘层34可以包括：在形成前述图案的衬底10上形成电极绝缘薄膜，通过图案化工艺对电极绝缘薄膜进行图案化处理，形成电极绝缘层34。所述电极绝缘层34将所述第三电极层33完全覆盖，并暴露出所述像素开口321和所述隔离槽结构322(所述电极绝缘层34设置的第三开口341暴露出隔离槽结构322)。如图7所示。
(7)形成发光功能层35。示例性地，形成发光功能层35可以包括：在形成前述图案的衬底10上依次蒸镀发光功能层35的各个膜层，其中，所述 发光功能层35可以包括沿远离所述衬底10方向依次叠设的第一发光单元351、所述电荷产生层353和第二发光单元352；所述第一发光单元351包括叠设的能够发射红光的第一发光层和能够发射绿光的第二发光层，所述第二发光单元352包括能够发射蓝光的第三发光层。蒸镀过程中，所述电荷产生层353在所述隔离槽结构322处会自然断开。如图8所示。
(8)形成第二电极层36。示例性地，可以采用蒸镀工艺在形成前述图案的衬底10上形成第二电极层36。如图1a所示。
之后，在第二电极层36的远离衬底10一侧依次形成封装结构层40和彩色滤光层等膜层。
在另一些示例性实施例中，图1b示例的显示基板的制备过程中，可以在形成第三电极层33图案后，形成电极绝缘层34图案，然后在像素界定层32上形成所述隔离槽结构322。具体过程可以参考图1a示例的显示基板的制备过程。
本公开实施例还提供一种显示装置，包括前文任一实施例所述的显示基板。显示装置可以为近眼显示装置，比如AR/VR眼镜、头盔显示器、虚拟现实一体机等。
在附图中，有时为了明确起见，夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中每个部件的形状和大小不反映真实比例。此外，附图示意性地示出了一些例子，本公开的实施方式不局限于附图所示的形状或数值。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，为了区分晶体管除控制极之外的两极，直接描述了其中一极为第一极，另一极为第二极，其中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏 电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本文描述中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，包括85°以上且95°以下的角度的状态。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本文描述中，除非另有明确的规定和限定，术语“连接”、“固定连接”、“安装”、“装配”应做广义理解，例如，可以是固定连接，或是可拆卸连接，或一体地连接；术语“安装”、“连接”、“固定连接”可以是直接相连，或通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开实施例中的含义。

Claims (16)

  1. 一种显示基板，包括依次叠设于衬底上的驱动结构层和发光结构层，所述发光结构层包括第一电极层、像素界定层、发光功能层、第二电极层、第三电极层以及电极绝缘层；
    所述第一电极层包括设置在所述驱动结构层上的多个第一电极，所述像素界定层设于所述多个第一电极的远离所述衬底一侧并设有多个像素开口，每个所述像素开口将对应的一个所述第一电极的远离所述衬底的表面暴露出；所述像素界定层还设有呈网格状的隔离槽结构，所述隔离槽结构包括多个网格单元，所述隔离槽结构的每个网格单元将一个所述像素开口包围；
    所述第三电极层和所述电极绝缘层依次叠设于所述像素界定层的远离所述衬底一侧，并暴露出所述像素开口和所述隔离槽结构，且所述电极绝缘层将所述第三电极层的靠近所述像素开口的边缘部分包覆；
    所述发光功能层和所述第二电极层依次叠设于所述多个第一电极和所述电极绝缘层的远离所述衬底一侧，每个所述第一电极、所述发光功能层和所述第二电极层形成一个发光器件；所述第二电极层与所述第三电极层设置为等电位；
    所述发光功能层包括叠设的至少两个发光单元，以及位于相邻两个发光单元之间的电荷产生层，所述电荷产生层设置为在所述第一电极和所述第二电极层的电压作用下产生空穴和电子，所述电荷产生层被所述隔离槽结构隔断。
  2. 如权利要求1所述的显示基板，其中，所述第三电极层设有暴露出所述像素开口的第一开口，所述第一开口在所述衬底上的正投影包含所述像素开口在所述衬底上的正投影。
  3. 如权利要求2所述的显示基板，其中，所述电极绝缘层将所述像素开口的周向侧壁覆盖。
  4. 如权利要求1所述的显示基板，其中，所述第三电极层设有暴露出所述隔离槽结构的第二开口，所述隔离槽结构在所述衬底上的正投影包含所述第二开口在所述衬底上的正投影。
  5. 如权利要求4所述的显示基板，其中，所述电极绝缘层设有暴露出所述隔离槽结构的第三开口，所述第三开口在所述衬底上的正投影包含所述第二开口在所述衬底上的正投影；所述电极绝缘层在所述衬底上的正投影与所述隔离槽结构在所述衬底上的正投影存在交叠部分。
  6. 如权利要求1所述的显示基板，其中，所述电极绝缘层在所述衬底上的正投影包含所述第三电极层在所述衬底上的正投影。
  7. 如权利要求6所述的显示基板，其中，所述第三电极层设有暴露出所述隔离槽结构的第二开口，所述电极绝缘层设有暴露出所述隔离槽结构的第三开口，所述第二开口在所述衬底上的正投影包含所述第三开口在所述衬底上的正投影。
  8. 如权利要求7所述的显示基板，其中，所述隔离槽结构在所述衬底上的正投影包含所述第三开口在所述衬底上的正投影。
  9. 如权利要求1所述的显示基板，其中，所述第一电极在厚度方向上的侧壁为斜坡状，所述第一电极在厚度方向上的侧壁与所述第一电极的朝向所述衬底的表面的夹角为60度至80度。
  10. 如权利要求1所述的显示基板，其中，所述隔离槽结构的周向侧面相较于所述隔离槽结构的槽口内缩。
  11. 如权利要求10所述的显示基板，其中，所述隔离槽结构的底面为向靠近所述衬底的方向凹陷的弧形凹面。
  12. 如权利要求11所述的显示基板，其中，所述隔离槽结构的周向侧面为弧面并与底面之间圆滑连接。
  13. 如权利要求1所述的显示基板，其中，所述隔离槽结构贯穿所述像素界定层并部分地位于所述驱动结构层中。
  14. 如权利要求1所述的显示基板，其中，所述电极绝缘层的材料包括氮化硅、氧化硅、氮氧化硅中的任一种或多种。
  15. 如权利要求1所述的显示基板，其中，所述发光功能层包括沿远离所述衬底方向依次叠设的第一发光单元、所述电荷产生层和第二发光单元；所述第一发光单元包括叠设的能够发射红光的第一发光层和能够发射绿光的 第二发光层，所述第二发光单元包括能够发射蓝光的第三发光层。
  16. 一种显示装置，包括权利要求1至15任一项所述的显示基板。
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