WO2023201602A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023201602A1
WO2023201602A1 PCT/CN2022/088061 CN2022088061W WO2023201602A1 WO 2023201602 A1 WO2023201602 A1 WO 2023201602A1 CN 2022088061 W CN2022088061 W CN 2022088061W WO 2023201602 A1 WO2023201602 A1 WO 2023201602A1
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WIPO (PCT)
Prior art keywords
electrode
base substrate
display panel
layer
orthographic projection
Prior art date
Application number
PCT/CN2022/088061
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English (en)
French (fr)
Inventor
苏同上
成军
黄勇潮
刘军
闫梁臣
王海涛
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/088061 priority Critical patent/WO2023201602A1/zh
Priority to US18/022,189 priority patent/US20240276793A1/en
Priority to CN202280000800.6A priority patent/CN117296474A/zh
Publication of WO2023201602A1 publication Critical patent/WO2023201602A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • the larger the area of the transparent area the higher the light transmittance, and the clearer the image observed through the panel.
  • Embodiments of the present disclosure provide a display panel and a display device.
  • an embodiment of the present disclosure provides a display panel, including: a base substrate, an electrode layer, and a planarization layer located between the base substrate and the electrode layer;
  • the electrode layer includes a plurality of repeating units, each repeating unit includes at least one electrode group, each electrode group includes a plurality of electrode blocks arranged along the first direction, and each of the electrode blocks includes a plurality of electrode blocks arranged along the first direction.
  • the planarization layer has a plurality of grooves, the repeating unit has grooves on at least one side in the second direction, the grooves have first sidewalls extending along the first direction, and the connection
  • the electrode is at least partially located on the first side wall; wherein the second direction intersects the first direction;
  • the planarization layer also has a plurality of first protrusions, and an orthographic projection of the first protrusions on the base substrate covers the first side wall on the base substrate in the second direction. and at least one first protrusion is provided between the connecting electrodes of at least two adjacent electrode blocks in the same electrode group.
  • an edge of the first side wall close to the base substrate includes a first portion
  • an edge of the first side wall away from the base substrate includes a second portion
  • the first portion and the The second parts both extend along the first direction
  • the orthographic projection of the first part and the second part on the base substrate is the same as the orthographic projection of the first protrusion on the base substrate. No overlap;
  • the orthographic projection of the extension line of the second part on the base substrate passes through the orthographic projection of the first protrusion on the base substrate.
  • the display panel further includes:
  • a plurality of first pads each of the first pads is located between the base substrate and the planarization layer, and the orthographic projection of the first protrusion on the base substrate covers the first pads on the substrate Orthographic projection on the substrate.
  • the display panel further includes:
  • a thin film transistor located between the planarization layer and the base substrate;
  • the first electrode is electrically connected to the drain of the thin film transistor through a via hole on the planarization layer, and the first pad is made of the same material as the drain or gate of the thin film transistor.
  • each repeating unit includes two electrode groups arranged along the second direction, and the connecting electrodes in the two electrode groups are respectively located on two adjacent electrode groups arranged along the second direction. Dig in the trench.
  • the orthographic projection of the first protrusion on the base substrate does not overlap with the orthographic projection of the first electrode on the base substrate.
  • the trench further has a second sidewall extending along the second direction
  • the planarization layer further has at least one second protrusion
  • the second protrusion is on the base substrate
  • the orthographic projection of the second side wall covers the orthographic projection of the second side wall on the base substrate in the first direction.
  • the display panel further includes:
  • a plurality of second pads each of the second pads is located between the base substrate and the planarization layer, and the orthographic projection of the second protrusion on the base substrate covers the second pads on the substrate Orthographic projection on the substrate.
  • the display panel further includes:
  • a thin film transistor located between the planarization layer and the base substrate;
  • the second pad is made of the same material as the drain or gate of the thin film transistor.
  • the display panel further includes:
  • each of the light-emitting devices includes the first electrode, a light-emitting layer and a second electrode, the second electrode is located on a side of the first electrode away from the base substrate, the light-emitting layer Located between the first electrode and the second electrode;
  • the light-emitting layers corresponding to the plurality of first electrodes in the same electrode block emit the same color.
  • the plurality of repeating unit arrays are arranged, one of the first direction and the second direction is a row direction, and the other is a column direction;
  • the trench is provided between every two adjacent repeating units in the second direction.
  • the angle between the first side wall and the trench bottom wall is between 110° and 170°.
  • one of the first protrusions is provided for each spacing area between two adjacent electrode blocks in the same electrode group.
  • the first electrode and the connecting electrode in the same electrode block are connected into an integrated structure.
  • an embodiment of the present disclosure provides a display device, including the display panel described in the first aspect.
  • Figure 1 is a plan view of a display panel.
  • Figure 2 is a schematic structural diagram of the planarization layer.
  • FIG. 3 is a plan structural view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 4 is a partial cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic plan view of a first electrode provided by an embodiment of the present disclosure.
  • FIG. 6 is a plan structural view of another display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of forming a first electrode layer according to an embodiment of the present disclosure.
  • FIG. 8 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • each pixel is equipped with a light-emitting device and a pixel circuit used to provide driving current for the light-emitting device.
  • the pixel circuit includes multiple thin film transistors, which are among the pixel circuit and the light-emitting device.
  • a planarization layer is provided between the layers, and the light-emitting device is connected to the thin film transistor in the pixel driving circuit through a via hole on the planarization layer.
  • OLED display panels can be used as transparent display panels to provide users with a better experience.
  • a transparent display panel means that the display panel itself has a certain degree of light penetration. You can see both the image displayed on the display panel and the drawings behind the display panel.
  • transparent display panels have been widely used in on-board displays such as cars/subways, window displays such as hotels/clothing stores, and display scenarios such as AR (Augmented Reality) and VR (Virtual Reality).
  • the planarization layer is hollowed out to form trenches to improve the transparent display effect of the display panel.
  • Figure 1 is a plan structural view of a display panel.
  • the display panel includes a display area A and a transparent area B.
  • the display area A and the transparent area B are alternately arranged in the second direction X.
  • the planarization layer located in the transparent area is hollowed out to form a trench 30; a plurality of light-emitting devices are provided in the display area, and each light-emitting device includes a first electrode 231 and a second electrode arranged oppositely, and a first electrode 231 and a second electrode located between the two. luminous layer between. Only the first electrode 231 of the light emitting device is shown in the figure.
  • the plurality of light-emitting devices in the display area are divided into a plurality of repeating units 21.
  • Each repeating unit 21 includes at least one electrode group 22.
  • Each electrode group 22 includes a plurality of electrode blocks 23 arranged along the first direction Y.
  • Each electrode The block 23 includes a plurality of first electrodes 231 arranged along the first direction
  • the light-emitting layers corresponding to the plurality of first electrodes 231 in each electrode block 23 emit the same color, and adjacent first electrodes 231 are connected through connecting electrodes 232 . That is to say, the plurality of light-emitting devices corresponding to the plurality of first electrodes 231 in the same electrode block are configured to emit light of the same color, and the plurality of first electrodes 231 are connected through the connection electrodes 232 .
  • the light-emitting devices corresponding to other first electrodes 231 in the same electrode block 23 can still be used normally, thus avoiding affecting the overall display effect of the display panel. For example, when one of the light-emitting devices fails, the first electrode 231 of the light-emitting device can be disconnected from the connection electrode 232 .
  • Figure 2 is a schematic structural diagram of the planarization layer.
  • the hollowed out planarization layer has a certain thickness, resulting in the inability to form a trench side that is completely parallel to the thickness direction of the display panel.
  • the wall 20 instead forms a trench side wall 20 with a certain inclination angle.
  • the angle between the trench side wall 20 and the plane where the bottom of the trench 30 is located presents an angle of ⁇ degree.
  • the first electrode 231 is formed through a photolithography patterning process after the planarization layer is formed. Specifically, a conductive material layer 12 and a photoresist layer 11 (Photoresist, PR) are sequentially formed on the planarization layer.
  • the conductive material can be indium tin oxide (Indium Tin Oxide, ITO).
  • ITO Indium Tin Oxide
  • area I needs to retain the conductive material, and the photoresist in this area does not need to be exposed; area II is the area where the conductive material needs to be etched away, and the photoresist in this area needs to be exposed.
  • the thickness of the photoresist that needs to be removed by exposure is D; the area III also needs to be exposed to the photoresist layer 11, but because the area III is the area where the sidewall 20 of the trench is located, and it is different from the trench
  • the thickness d of the photoresist layer 11 that needs to be removed by exposure in the III region is greater than the thickness D that needs to be removed by exposure in the II region. That is to say, under the condition of a certain exposure amount, the photoresist layer 11 located on the trench sidewall 20 will be insufficiently exposed, and photoresist residue will be formed after the exposure process. Due to the residual photoresist, the conductive material layer 12 is further etched incompletely, and ultimately, conductive material residue is formed on the trench sidewall 20 .
  • the connecting electrodes 232 in the plurality of electrode blocks 23 in the same electrode group 22 are at least partially located on the side walls 20 of the trenches.
  • the connection electrodes 232 in different electrode blocks 23 are connected to each other. Since the luminescent layers corresponding to the first electrodes 231 in different electrode blocks 23 have different luminous colors, the mutual connection of the connecting electrodes 232 will cause color mixing between the electrode blocks 23 of different luminous colors, affecting the display of the display panel. Effect.
  • embodiments of the present disclosure provide a display panel that improves or avoids the connection of first electrodes of light-emitting devices with different emitting colors due to conductive material residues formed on the side walls of the trenches. , thereby improving or avoiding color mixing on the display panel and improving the display effect of the display panel.
  • FIG. 3 is a plan structural view of a display panel provided by an embodiment of the present disclosure
  • FIG. 4 is a partial cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes: a base substrate 1 , an electrode layer 2 , and a planarization layer 3 located between the base substrate 1 and the electrode layer 2 .
  • the electrode layer 2 includes a plurality of repeating units 21 , each repeating unit 21 includes at least one electrode group 22 , and each electrode group 22 includes a plurality of electrode blocks 23 arranged along the first direction Y.
  • FIG. 5 is a schematic plan view of a first electrode provided by an embodiment of the present disclosure. As shown in FIGS. 3 and 5 , each electrode block 23 includes a plurality of first electrodes 231 arranged along the first direction Y and connected to each adjacent electrode. A connecting electrode 232 between the two first electrodes 231 .
  • Figure 6 is a plan structural view of another display panel provided by an embodiment of the present disclosure.
  • the planarization layer 3 has a plurality of grooves 30, and the repeating units 21 have at least There is a trench 30 on one side.
  • the trench 30 has a first side wall 301 extending along the first direction Y, and the connecting electrode 232 is at least partially located on the first side wall 301; wherein the second direction X intersects the first direction Y.
  • the first side wall 301 extends along the first direction Y, which means that the orthographic projection of the first side wall 301 on the base substrate 1 generally tends to extend along the first direction Y.
  • the planarization layer 3 also has a plurality of first protrusions 31, and the orthographic projection of the first protrusions 31 on the base substrate 1 covers the orthographic projection of the first side wall 301 on the base substrate 1 in the second direction X, Furthermore, at least one first protrusion 31 is provided between the connecting electrodes 232 of at least two adjacent electrode blocks 23 in the same electrode group 22 .
  • the display panel provided by the embodiment of the present disclosure has a plurality of first protrusions 31 on the planarization layer 3, and the orthographic projection of the first protrusions 31 on the base substrate 1 covers the orthogonal projection of the first side wall 301 on the base substrate 1. , that is, at least part of the first protrusion 31 is formed on the first side wall 301 .
  • Figure 7 is a schematic diagram of the preparation of the first electrode layer provided by an embodiment of the present disclosure.
  • the planarization layer 3 shown in Figure 7 is cut along line AA' in Figure 6, as shown in Figure 7, and Figure 2
  • the conductive material needs to be retained in the I area, and the photoresist in this area does not need to be exposed; the II area is the area where the conductive material needs to be etched away, and the photoresist in this area needs to be exposed; the III area also needs to be exposed to light.
  • the resist is exposed.
  • the photoresist layer is a fluid gel that is formed first, it needs to be solidified to form.
  • the thickness of the photoresist layer 11 in area I is D.
  • the first convex portion 31 protrudes from other parts in the thickness direction of the display panel, it is located in area II.
  • the photoresist layer 11 is thinner than the photoresist layer 11 at other locations, that is, the thickness d1 of the photoresist layer 11 in the II region is smaller than the thickness D of the photoresist layer 11 in the I region; photolithography in the III region
  • the display panel includes multiple repeating units 21 , and the multiple repeating units 21 are arranged in an array, that is, arranged in multiple rows and multiple columns.
  • One of the first direction X and the second direction Y is the row direction, and the other is the column direction; in the second direction Y, a trench 30 is provided between every two adjacent repeating units 21 to improve the transparency of the display panel. display effect.
  • the first electrode 231 and the connecting electrode 232 in the same electrode block 23 are connected into an integrated structure. That is to say, during the preparation process of the display panel, the first electrode 231 and the connecting electrode 232 can be Synchronized formation to save display panel preparation steps.
  • the display panel further includes a plurality of light-emitting devices 4 and thin film transistors 5 .
  • the thin film transistor 5 is located between the planarization layer 3 and the base substrate 1 , and includes a gate electrode 51 , an active layer 52 , a source electrode 53 and a drain electrode 54 .
  • the above-mentioned first electrode 231 may be the anode of the light-emitting device 4 and passes through The via hole on the planarization layer 3 is electrically connected to the drain electrode 54 .
  • the active layer 52 is located between the gate electrode 51 and the base substrate 1 .
  • the material of the active layer 52 may include, for example, inorganic semiconductor materials (eg, polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials.
  • the active layer 52 includes a channel portion and a source connection portion and a drain connection portion located on both sides of the channel portion. The source connection portion is connected to the source electrode 53 of the thin film transistor 5 , and the drain connection portion is connected to the source electrode 53 of the thin film transistor 5 . Drain 54 is connected.
  • Both the source connection part and the drain connection part may be doped with impurities (for example, N-type impurities or P-type impurities) that are higher than the impurity concentration of the channel part.
  • the channel part is directly opposite to the gate electrode 51 of the thin film transistor 5. When the voltage signal loaded on the gate electrode 51 reaches a certain value, a carrier path is formed in the channel part, causing the source electrode 53 and the drain electrode 54 of the thin film transistor 5 to conduct Pass.
  • the buffer layer BFL is provided between the thin film transistor 5 and the base substrate 1 to prevent or reduce the diffusion of metal atoms and/or impurities from the base substrate 1 into the active layer 52 of the transistor.
  • the buffer layer BFL may include inorganic materials such as silicon oxide, silicon nitride, and/or silicon oxynitride, and may be formed as a multi-layer or a single layer.
  • the first gate insulating layer GI1 is provided on the side of the active layer 52 away from the base substrate 1 .
  • the material of the first gate insulating layer GI1 may include silicon compounds and metal oxides.
  • the material of the first gate insulating layer GI1 includes silicon oxynitride, silicon oxide, silicon nitride, silicon oxycarbide, silicon nitride carbide, aluminum oxide, aluminum nitride, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.
  • the first gate insulating layer GI1 may be a single layer or multiple layers.
  • the gate electrode layer is disposed on the side of the first gate insulating layer GI1 away from the base substrate 1 .
  • the gate electrode layer at least includes the gate electrode 51 of each thin film transistor.
  • Materials of the gate electrode layer may include, for example, metals, metal alloys, metal nitrides, conductive metal oxides, transparent conductive materials, and the like.
  • the gate electrode layer may include gold, gold alloys, silver, silver alloys, aluminum, aluminum alloys, aluminum nitride, tungsten, tungsten nitride, copper, copper alloys, nickel, chromium, chromium nitride, molybdenum , Molybdenum alloys, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, tin oxide, indium oxide, gallium oxide, indium tin oxide, indium zinc oxide, etc.
  • the gate electrode layer may have a single layer or multiple layers.
  • the second gate insulating layer GI2 is disposed on the side of the gate electrode layer away from the base substrate 1 .
  • the material of the second gate insulating layer GI2 may include, for example, silicon compounds and metal oxides.
  • the material of the second gate insulating layer GI2 may include silicon oxynitride, silicon oxide, silicon nitride, silicon oxycarbide, silicon nitride carbide, aluminum oxide, aluminum nitride, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.
  • the second gate insulating layer GI2 may be formed as a single layer or multiple layers.
  • the interlayer insulating layer ILD is disposed on the side of the second electrode plate of the capacitor away from the base substrate 1 .
  • the material of the interlayer insulating layer ILD may include, for example, silicon compounds, metal oxides, etc. Specifically, the silicon compounds and metal oxides listed above can be selected, which will not be described again here.
  • the source-drain conductive layer is provided on the side of the interlayer insulating layer ILD away from the base substrate 1 .
  • the first source-drain conductive layer may include a source electrode 53 and a drain electrode 54 of each transistor.
  • the source electrode 53 is electrically connected to the source electrode connection part
  • the drain electrode 54 is electrically connected to the drain electrode connection part.
  • the source-drain conductive layer may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.
  • the source-drain conductive layer may be a single layer or multiple layers made of metal, such as Mo/Al/Mo or Ti. /Al/Ti.
  • the passivation layer PVX is provided on the side of the source-drain conductive layer away from the base substrate 1.
  • the material of the passivation layer PVX may include, for example, silicon oxynitride, silicon oxide, silicon nitride, etc.
  • the planarization layer 3 is provided on the side of the passivation layer PVX away from the base substrate 1.
  • the planarization layer 3 can be made of organic insulating materials.
  • the organic insulating materials include polyimide, epoxy resin, and acrylic. , polyester, photoresist, polyacrylate, polyamide, silicone and other resin materials, etc.
  • the pixel definition layer PDL is located on the side of the planarization layer 3 away from the base substrate 1 , and includes a plurality of accommodating portions, each accommodating portion corresponding to the light-emitting device 4 one-to-one.
  • Each light-emitting device 4 includes a first electrode 231, a light-emitting layer 41 and a second electrode 42.
  • the second electrode 42 is located on the side of the first electrode 231 away from the base substrate 1.
  • the light-emitting layer 41 is located between the first electrode 231 and the second electrode. 42; wherein the light-emitting layers 41 corresponding to the multiple first electrodes 231 in the same electrode block 23 emit the same color.
  • Adjacent first electrodes 231 are connected through connection electrodes 232 .
  • the connection electrode 232 includes a first electrode strip a, a second electrode strip b, and a third electrode strip c.
  • the first electrode strip a and the third electrode strip c are respectively connected with two third electrode strips.
  • One electrode 231 is connected, and both ends of the second electrode strip b are connected to the first electrode strip a and the third electrode strip c respectively.
  • the first electrode 231 is an anode
  • the second electrode 42 is a cathode.
  • the light-emitting layer 41 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer stacked in sequence.
  • the first electrode 231 is located between the pixel definition layer PDL and the planarization layer 3 .
  • the second electrodes 42 of the plurality of light emitting devices 4 may be formed into an integrated structure.
  • the light-emitting device 4 is an OLED device, and in this case, the light-emitting layer uses an organic light-emitting material; or, the light-emitting device 4 is a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) device, and in this case, the light-emitting layer uses quantum dots. Luminescent material.
  • Each light emitting device 4 is configured to emit light of a preset color.
  • the edge of the first side wall 301 close to the base substrate 1 includes a first portion e1
  • the edge of the first side wall 301 away from the base substrate 1 includes a second portion e2
  • the first portion e1 and the second portion e2 both extend along the first direction Y, and their orthographic projections on the base substrate 1 do not overlap with the orthographic projection of the first protrusion 31 on the base substrate 1 .
  • the orthographic projection of the extension line of the second part e2 on the base substrate 1 passes through the orthographic projection of the first protrusion 31 on the base substrate 1 , that is, the first protrusion 31 can move the first side wall in the second direction X.
  • the orthographic projection of the first protrusion 31 on the base substrate 1 may be a circle, a trapezoid, a triangle, a quadrilateral, etc., and is not specifically limited in the embodiment of the present disclosure.
  • the display panel further includes a plurality of first pads 6 located between the base substrate 1 and the planarization layer 3 , and the first protrusions 31 are located on the base substrate 1
  • the orthographic projection covers the orthographic projection of the first pad 6 on the base substrate 1 . That is to say, during the manufacturing process of the display panel, the first pad 6 is formed first, and then the planarization layer 3 is formed, so that the portion of the planarization layer 3 opposite to the first pad 6 protrudes away from the first pad 6. Thus, the first convex portion 31 is formed.
  • the first spacer 6 and the source/drain electrodes in the thin film transistor 5 are made of the same material, so the first spacer 6 and the source/drain electrodes in the thin film transistor 5 can be formed in the same manufacturing process, Moreover, the source electrode and the drain electrode are closer to the planarization layer 3 , so it is more advantageous to form the first convex portion 31 .
  • the first spacer 6 may also be made of the same gate material as the thin film transistor 5, which is not limited in the embodiment of the present disclosure.
  • the orthographic projection of the extension line of the second part e2 on the base substrate 1 passes through the orthographic projection of the first protrusion 31 on the base substrate 1 , so that during the patterning process of the first electrode layer , to minimize the conductive material residue on the first protrusion 31 .
  • the angle ⁇ between the first side wall and the trench bottom wall is between 110° and 170°.
  • ⁇ can be any one of 110°, 120°, 130°, 140°, 150°, 160°, and 170°.
  • each repeating unit 21 includes two electrode groups 22 arranged along the second direction Two adjacent trenches 30. Since the first protrusion 31 is formed on the first side wall 301 of the trench 30 , it can prevent the formation of continuous conductive material residues on the first side wall 301 , further avoiding adjacent electrode blocks 23 in each electrode group 22 The connection of the connecting electrodes 232 and the cross-color phenomenon of the light-emitting layer 41 between adjacent electrode blocks 23.
  • the same electrode group 22 may include multiple electrode blocks 23 , such as three electrode blocks 23 or four electrode blocks 23 , then a first protrusion needs to be provided between each two adjacent electrode blocks 23 . 31 to avoid the connection of the connecting electrodes 232 of adjacent electrode blocks 23 and the cross-color phenomenon of the light-emitting layer 41 between the adjacent electrode blocks 23.
  • the orthographic projection of the first protrusion 31 on the base substrate 1 does not overlap with the orthographic projection of the first electrode 231 on the base substrate 1 , that is, the first electrode 231 is still disposed on the planarization layer.
  • the relatively flat area is not affected by the first convex portion 31 .
  • the trench 30 also has a second sidewall 302 extending along the second direction X, and the planarization layer 3 also has at least one second protrusion 32 .
  • the orthographic projection on the base substrate 1 covers the orthographic projection of the second side wall 302 on the base substrate 1 in the first direction Y.
  • the second side wall 302 in the trench 30 is connected to the first side walls 301 on both sides of the second direction X.
  • Each first side wall 301 is provided with a connection electrode 232, and the connection electrodes 232 on different side walls belong to Different electrode blocks 23, therefore, the second protrusion 32 is provided on the second side wall 302 to prevent the second side wall 302 from connecting the connecting electrodes 232 in the different electrode blocks 23 located on both sides of the trench 30 in the second direction X. Make a connection.
  • the display panel further includes a plurality of second spacers (not shown in the figure), each second spacer is located between the base substrate 1 and the planarization layer 3 , and the second protrusions 32 are on the lining.
  • the orthographic projection on the base substrate 1 covers the orthographic projection of the second pad on the base substrate 1 .
  • the second spacer may be made of the same material as the source or drain of the thin film transistor 5 , and may also be made of the same gate material as the thin film transistor 5 , which is not limited in the embodiments of the present disclosure.
  • the above-mentioned second cushion block and the first cushion block 6 in the embodiment of the present disclosure belong to the same inventive concept, and will not be described again here.
  • FIG. 8 is a partial plan view of a display panel provided by an embodiment of the present disclosure. In some embodiments, as shown in FIG. 8 , at a position close to the spacing area of each two adjacent electrode blocks 23 in the same electrode group 22, A first convex portion 31 is provided.
  • the position close to the spacing area between each two adjacent electrode blocks 23 in the same electrode group 22 refers to the position between the first side wall 301 and each two adjacent electrode blocks 23 in the same electrode group 22
  • the spacing areas are adjacent to each other, that is to say, the orthographic projection of the boundary line of two adjacent electrode blocks 23 on the base substrate 1 passes through the orthographic projection of the first protrusion 31 on the base substrate 1 .
  • the first protrusion 31 is used to cut off the remaining conductive material on the first side wall 301 to prevent the connecting electrodes 232 of adjacent electrode blocks 23 from being short-circuited, so that the first electrode 231 between the adjacent electrode blocks 23 has a light-emitting layer.
  • the first protrusion 31 can be disposed at any position between the connection electrode 232a and the connection electrode 232b in FIG. 8, and can cut off the remaining conductive material on the first side wall 301 between the two connection electrodes. , to avoid the connection between the two connecting electrodes, thereby avoiding the display color mixing phenomenon caused by the short circuit of the first electrodes of the light-emitting devices of different colors, thereby improving the display effect of the display panel.
  • An embodiment of the present disclosure also provides a display device, including the above display panel.
  • the above-mentioned display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. This disclosure is not limited thereto.

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  • Physics & Mathematics (AREA)
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  • Electroluminescent Light Sources (AREA)
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Abstract

一种显示面板和显示装置，显示面板包括：衬底基板（1）、电极层（2）、以及位于衬底基板（1）和电极层（2）之间的平坦化层（3）；电极层（2）包括多个重复单元（21），每一重复单元（21）包括至少一个电极组（22），每一电极组（22）包括沿第一方向（Y）排列的多个电极块（23），每个电极块（23）包括沿第一方向（Y）排列的多个第一电极（231）以及连接在每相邻两个第一电极（231）之间的连接电极（232）；平坦化层（3）上具有多个挖槽（30），重复单元（21）在第二方向（X）上至少一侧有挖槽（30），挖槽（30）具有沿第一方向（Y）延伸的第一侧壁（301），连接电极（232）至少部分位于第一侧壁（301）上；平坦化层（3）还具有多个第一凸部（31），其在衬底基板（1）上的正投影在第二方向（X）上覆盖第一侧壁（301）在衬底基板（1）上的正投影，同一个电极组（22）中至少两个相邻电极块（23）的连接电极（232）之间，设置有至少一个第一凸部（31）。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)器件是一种以有机半导体材料为基础的电致发光器件，其具有较高的光转换效率和非常低的功耗。与此同时，随着信息社会的发展，新颖的显示技术如透明显示装置，也获得了良好的用户体验，具有广阔的市场前景。
在透明显示装置中，透明区域的面积越大，透光率越高，透过面板观察到的图像也越清晰。
发明内容
本公开实施例提供一种显示面板和显示装置。
第一方面，本公开实施例提供一种显示面板，包括：衬底基板、电极层、以及位于所述衬底基板和所述电极层之间的平坦化层；
所述电极层包括多个重复单元，每一重复单元包括至少一个电极组，每一电极组包括沿第一方向排列的多个电极块，每个所述电极块包括沿所述第一方向排列的多个第一电极以及连接在每相邻两个所述第一电极之间的连接电极；
所述平坦化层上具有多个挖槽，所述重复单元在第二方向上的至少一侧有挖槽，所述挖槽具有沿所述第一方向延伸的第一侧壁，所述连接电极至少部分位于所述第一侧壁上；其中，所述第二方向与所述第一方向交叉；
所述平坦化层还具有多个第一凸部，所述第一凸部在所述衬底基板上的正投影在所述第二方向上覆盖所述第一侧壁在所述衬底基板上的正 投影，并且，同一个所述电极组中至少两个相邻的所述电极块的连接电极之间，设置有至少一个所述第一凸部。
在一些实施例中，所述第一侧壁靠近所述衬底基板的边缘包括第一部分，所述第一侧壁远离所述衬底基板的边缘包括第二部分，所述第一部分和所述第二部分均沿所述第一方向延伸，且所述第一部分和所述第二部分在所述衬底基板上的正投影与所述第一凸部在所述衬底基板上的正投影无交叠；
所述第二部分的的延长线在所述衬底基板上的正投影穿过所述第一凸部在所述衬底基板上的正投影。
在一些实施例中，所述显示面板还包括：
多个第一垫块，每一所述第一垫块位于所述衬底基板和所述平坦化层之间，第一凸部在衬底基板上的正投影覆盖第一垫块在衬底基板上的正投影。
在一些实施例中，所述显示面板还包括：
薄膜晶体管，位于所述平坦化层与所述衬底基板之间；
其中，所述第一电极通过所述平坦化层上的过孔与所述薄膜晶体管的漏极电连接，所述第一垫块与所述薄膜晶体管的漏极或栅极材料相同。
在一些实施例中，每个重复单元包括沿所述第二方向排列的两个所述电极组，所述两个电极组中的连接电极分别位于沿第二方向排列的相邻两个所述挖槽中。
在一些实施例中，所述第一凸部在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影无交叠。
在一些实施例中，所述挖槽还具有沿第二方向延伸的第二侧壁，所述平坦化层还具有至少一个第二凸部，所述第二凸部在所述衬底基板上的正投影在所述第一方向上覆盖所述第二侧壁在所述衬底基板上的正投影。
在一些实施例中，所述显示面板还包括：
多个第二垫块，每一所述第二垫块位于所述衬底基板和所述平坦化层之间，第二凸部在衬底基板上的正投影覆盖第二垫块在衬底基板上的正投影。
在一些实施例中，所述显示面板还包括：
薄膜晶体管，位于所述平坦化层与所述衬底基板之间；
所述第二垫块与所述薄膜晶体管的漏极或栅极材料相同。
在一些实施例中，所述显示面板还包括：
多个发光器件，每个所述发光器件包括所述第一电极、发光层和第二电极，所述第二电极位于所述第一电极远离所述衬底基板的一侧，所述发光层位于所述第一电极与所述第二电极之间；
其中，同一个电极块中的多个第一电极所对应的发光层的发光颜色相同。
在一些实施例中，所述多个重复单元阵列排布，所述第一方向和所述第二方向中的一个为行方向，另一个为列方向；
所述第二方向上每相邻两个所述重复单元之间，设置有所述挖槽。
在一些实施例中，所述第一侧壁与所述挖槽底壁之间的角度在110°-170°之间。
在一些实施例中，同一个所述电极组中每相邻两个所述电极块的间隔区域，对应设置有一个所述第一凸部。
在一些实施例中，同一电极块中的所述第一电极和所述连接电极连为一体结构。
第二方面，本公开实施例提供一种显示装置，包括第一方面所述的显示面板。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为一种显示面板的平面结构图。
图2为平坦化层的结构示意图。
图3为本公开实施例提供的一种显示面板的平面结构图。
图4为本公开实施例提供的一种显示面板的局部剖视图。
图5为本公开实施例提供的第一电极的平面示意图。
图6为本公开实施例提供的另一显示面板的平面结构图。
图7为本公开实施例提供的制作第一电极层时的示意图。
图8为本公开实施例提供的一种显示面板的局部平面图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，本公开实施例使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列 举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
有机发光二极管(Organic Light Emitting Diode，OLED)显示面板中，每个像素内设置有发光器件以及用于为发光器件提供驱动电流的像素电路，像素电路包括多个薄膜晶体管，像素电路与发光器件之间设置有平坦化层，发光器件通过平坦化层上的过孔与像素驱动电路中的薄膜晶体管连接。OLED显示面板可以用作透明显示面板，从而为用户提供更好的体验。透明显示面板是指显示面板本身具有一定程度的光穿透性，既可以看到显示面板上显示的图像，又可以看到显示面板后面的画图。目前，透明显示面板已经被广泛应用在汽车/地铁等车载显示、酒店/服装店等橱窗展示、AR(Augmented Reality，增强现实)以及VR(Virtual Reality，虚拟现实)等显示场景中。
由于透明显示面板的应用场景和显示效果受外接光环境的影响较大，在较差的光照条件下无法获取较佳得到显示效果。因此，通常在未设置发光器件的区域，将平坦化层进行挖空处理形成挖槽，以提高显示面板的透明显示效果。
图1为一种显示面板的平面结构图，如图1所示，显示面板包括显示区A和透明区B，示例性地，显示区A和透明区B在第二方向X上交替设置。其中位于透明区的平坦化层被挖空，形成挖槽30；显示区中设置有多个发光器件，每个发光器件均包括相对设置的第一电极231和第二电极、以及位于二者之间的发光层。图中仅示出了发光器件的第一电极231。显示区中的多个发光器件划分为多个重复单元21，每一重复单元21包括至少一个电极组22，每一电极组22包括沿第一方向Y排列 的多个电极块23，每个电极块23包括沿第一方向Y排列的多个第一电极231。
如图1所示，每一电极块23中的多个第一电极231所对应的发光层的发光颜色相同，相邻的第一电极231之间通过连接电极232连接。也就是说，同一电极块中的多个第一电极231对应的多个发光器件被配置为发射相同颜色的光线，且多个第一电极231通过连接电极232连接。当其中一个发光器件出现故障时导致显示不良时，同一电极块23内的其他第一电极231所对应的发光器件依然可以正常使用，因此可以避免影响显示面板的整体显示效果。例如，当其中一个发光器件出现故障时，可以将该发光器件的第一电极231与连接电极232断开。
图2为平坦化层的结构示意图，如图2所示，一方面由于工艺限制，另一方面所挖空的平坦化层具有一定厚度，导致无法形成与显示面板厚度方向完全平行的挖槽侧壁20，而是形成具有一定倾斜角度的挖槽侧壁20，例如，挖槽侧壁20与挖槽30的底部所在平面之间呈现θ度的夹角。
在显示面板的制备过程中，第一电极231是在平坦化层形成后，通过光刻构图工艺形成的。具体地，在平坦化层上依次形成导电材料层12和光刻胶层11(Photoresist，PR)，导电材料可以为氧化铟锡(IndiumTinOxide，ITO)，之后，对光刻胶层11进行曝光并显影，从而去除部分区域的光刻胶；之后对未被光刻胶覆盖的导电材料层进行刻蚀，形成包括第一电极的图形。在这个过程中，如图2所示，Ⅰ区域需要保留导电材料，该区域的光刻胶不需要曝光；Ⅱ区域是需要将导电材料刻蚀掉的区域，该区域的光刻胶需要曝光，在光照量一定的条件下，需要曝光去掉的光刻胶厚度为D；Ⅲ区域同样需要对光刻胶层11进行曝光，但由于Ⅲ区域为挖槽侧壁20所在区域，且其与挖槽底部所在平面之间呈现θ度的夹角，因此光刻胶在Ⅲ区域需要被曝光去掉的厚度为d＝D/cosθ。
根据上述分析，显然光刻胶层11在Ⅲ区域需要被曝光去掉的厚度d大于其在Ⅱ区域需要被曝光去掉的厚度D。也就是说，在曝光量一定的条件下，位于挖槽侧壁20上的光刻胶层11会出现曝光不充分的状态，在曝光工艺后形成光刻胶残留。由于光刻胶残留，进一步导致导电材料层12刻蚀不完全，最终在挖槽侧壁20上形成了导电材料的残留。
如图1所示，同一电极组22内的多个电极块23中的连接电极232均有至少部分位于挖槽侧壁20上，而由于挖槽侧壁20上的导电材料刻蚀不完全，使得不同电极块23中的连接电极232相互连接。而由于不同电极块23中的第一电极231所对应的发光层的发光颜色不同，因此连接电极232的相互连接会导致不同发光颜色的电极块23之间出现混色的情况，影响显示面板的显示效果。
为了解决上述技术问题中的至少一个，本公开实施例提供一种显示面板，改善或避免由于挖槽侧壁上所形成的导电材料残留而导致的不同发光颜色的发光器件的第一电极发生连接，从而改善或避免显示面板上出现混色的现象，提高显示面板的显示效果。
图3为本公开实施例提供的一种显示面板的平面结构图，图4为本公开实施例提供的一种显示面板的局部剖视图。如图3、4所示，显示面板包括：衬底基板1、电极层2、以及位于衬底基板1和电极层2之间的平坦化层3。
其中，电极层2包括多个重复单元21，每一重复单元21包括至少一个电极组22，每一电极组22包括沿第一方向Y排列的多个电极块23。图5为本公开实施例提供的第一电极的平面示意图，如图3和图5所示，每个电极块23包括沿第一方向Y排列的多个第一电极231以及连接在每相邻两个第一电极231之间的连接电极232。
图6为本公开实施例提供的另一显示面板的平面结构图，如图3和图6所示，平坦化层3上具有多个挖槽30，重复单元21在第二方向X 上的至少一侧有挖槽30，挖槽30具有沿第一方向Y延伸的第一侧壁301，连接电极232至少部分位于第一侧壁301上；其中，第二方向X与第一方向Y交叉。需要说明的是，第一侧壁301沿第一方向Y延伸，是指，第一侧壁301在衬底基板1上的正投影大致呈沿第一方向Y延伸的趋势。
平坦化层3还具有多个第一凸部31，第一凸部31在衬底基板1上的正投影在第二方向X上覆盖第一侧壁301在衬底基板1上的正投影，并且，同一个电极组22中至少两个相邻电极块23的连接电极232之间，设置有至少一个第一凸部31。
本公开实施例提供的显示面板，其平坦化层3上具有多个第一凸部31，其在衬底基板1上的正投影在覆盖第一侧壁301在衬底基板1上的正投影，即第一凸部31的至少部分形成在第一侧壁301上。图7为本公开实施例提供的制作第一电极层时的示意图，图7中所示的平坦化层3是沿图6中AA’线剖切得到的，如图7所示，与图2中相同的是，Ⅰ区域需要保留导电材料，该区域的光刻胶不需要曝光；Ⅱ区域是需要将导电材料刻蚀掉的区域，该区域的光刻胶需要曝光；Ⅲ区域同样需要对光刻胶进行曝光。在通过光刻工艺制备电极层的过程中，由于光刻胶层是先形成的具有流动性的胶状物，需要对其固化形成。在平坦化层3上涂覆光刻胶层11时，Ⅰ区域的光刻胶层11的厚度为D，由于第一凸部31在显示面板厚度方向上突出于其它部分，因此位于Ⅱ区域上的光刻胶层11相对于其它位置上的光刻胶层11较薄，即Ⅱ区域上光刻胶层11的厚度d1小于Ⅰ区域上光刻胶层11的厚度D；Ⅲ区域上光刻胶层11的厚度d2＝d1/cosθ。相比于图2中Ⅲ区域上光刻胶层11的厚度d，形成了第一凸部31之后的第一侧壁301上需要曝光掉的光刻胶层11的厚度d2薄了很多。因此，经过曝光处理后能够完全去掉，避免形成光刻胶残留，进一步在对导电材料层12进行刻蚀时也不会形成导电材料的残留，也不会出现由于导电材料层刻蚀不完全而导致不同的电极块相互连接的 情况，进而不会产生因不同颜色的发光器件的第一电极短接而导致的显示混色现象，从而提高显示面板的显示效果。
在一些实施例中，如图3所示，显示面板中包括多个重复单元21，多个重复单元21阵列排布，即排成多行多列。第一方向X和第二方向Y中的一个为行方向，另一个为列方向；在第二方向Y上每相邻两个重复单元21之间设置有挖槽30，从而提高显示面板的透明显示效果。
在一些实施例中，如图3所示，同一电极块23中第一电极231和连接电极232连为一体结构，也就是说在显示面板的制备过程中，第一电极231和连接电极232可以同步形成，以节省显示面板的制备步骤。
在一些实施例中，如图4所示，显示面板还包括多个发光器件4和薄膜晶体管5。薄膜晶体管5位于平坦化层3与衬底基板1之间，其包括栅极51、有源层52、源极53和漏极54，上述第一电极231可以为发光器件4的阳极，并通过平坦化层3上的过孔与漏极54电连接。
如图4所示，以薄膜晶体管5采用顶栅型薄膜晶体管为例，有源层52位于栅极51与衬底基板1之间。有源层52的材料可以包括例如无机半导体材料(例如，多晶硅、非晶硅等)、有机半导体材料、氧化物半导体材料。有源层52包括沟道部和位于该沟道部两侧的源极连接部和漏极连接部，源极连接部与薄膜晶体管5的源极53连接，漏极连接部与薄膜晶体管5的漏极54连接。源极连接部和漏极连接部均可以掺杂有比沟道部的杂质浓度高的杂质(例如，N型杂质或P型杂质)。沟道部与薄膜晶体管5的栅极51正对，当栅极51加载的电压信号达到一定值时，沟道部中形成载流子通路，使薄膜晶体管5的源极53和漏极54导通。
缓冲层BFL设置在薄膜晶体管5与衬底基板1之间，用于防止或减少金属原子和/或杂质从衬底基板1扩散到晶体管的有源层52中。缓冲层BFL可以包括诸如氧化硅、氮化硅和/或氮氧化硅的无机材料，并且可以形成为多层或单层。
第一栅绝缘层GI1设置在有源层52远离衬底基板1的一侧。第一栅绝缘层GI1的材料可以包括硅化合物、金属氧化物。例如，第一栅绝缘层GI1的材料包括氮氧化硅、氧化硅、氮化硅、碳氧化硅、氮碳化硅、氧化铝、氮化铝、氧化钽、氧化铪、氧化锆、氧化钛等。另外，第一栅绝缘层GI1可以为单层或多层。
栅电极层设置在第一栅绝缘层GI1远离衬底基板1的一侧。其中，栅电极层至少包括各薄膜晶体管的栅极51。栅电极层的材料可以包括例如金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等。例如，栅电极层可以包括金、金的合金、银、银的合金、铝、铝的合金、氮化铝、钨、氮化钨、铜、铜的合金、镍、铬、氮化铬、钼、钼的合金、钛、氮化钛、铂、钽、氮化钽、钕、钪、氧化锶钌、氧化锌、氧化锡、氧化铟、氧化镓、氧化铟锡、氧化铟锌等。栅电极层可以具有单层或多层。
第二栅绝缘层GI2设置在栅电极层远离衬底基板1的一侧，第二栅绝缘层GI2的材料可以包括例如硅化合物、金属氧化物。例如，第二栅绝缘层GI2的材料可以包括氮氧化硅、氧化硅、氮化硅、碳氧化硅、氮碳化硅、氧化铝、氮化铝、氧化钽、氧化铪、氧化锆、氧化钛等。第二栅绝缘层GI2可以形成为单层或多层。
层间绝缘层ILD设置在电容的第二电极板远离衬底基板1的一侧，层间绝缘层ILD的材料可以包括例如硅化合物、金属氧化物等。具体可以选择上文所列举的硅化合物和金属氧化物，这里不再赘述。
源漏导电层设置在层间绝缘层ILD远离衬底基板1的一侧。第一源漏导电层可以包括各晶体管的源极53和漏极54，源极53与源极连接部电连接，漏极54与漏极连接部电连接。源漏导电层可以包括金属、合金、金属氮化物、导电金属氧化物、透明导电材料等，例如，源漏导电层可以为金属构成的单层或多层，例如为Mo/Al/Mo或Ti/Al/Ti。
钝化层PVX设置在源漏导电层远离衬底基板1的一侧，钝化层PVX的材料可以包括例如氮氧化硅、氧化硅、氮化硅等。平坦化层3设置在钝化层PVX远离衬底基板1的一侧，平坦化层3可以采用有机绝缘材料制成，例如，该有机绝缘材料包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。
像素界定层PDL位于平坦化层3远离衬底基板1的一侧，其包括多个容纳部，每个容纳部与发光器件4一一对应。
每个发光器件4包括第一电极231、发光层41和第二电极42，第二电极42位于第一电极231远离衬底基板1的一侧，发光层41位于第一电极231与第二电极42之间；其中，同一个电极块23中的多个第一电极231所对应的发光层41的发光颜色相同。相邻的第一电极231之间通过连接电极232连接。
在一些实施例中，如图5所示，连接电极232包括第一电极条a、第二电极条b和第三电极条c，第一电极条a和第三电极条c分别与两个第一电极231连接，第二电极条b的两端分别与第一电极条a和第三电极条c连接。当被配置为发射相同颜色光线的多个发光器件4中的其中一个出现故障而导致显示不良时，可以对第一电极条a、第二电极条b和第三电极条c上的任意位置(例如图5中虚线位置)进行切割，以将故障器件去除，使得同一电极块23内的其他第一电极对应的正常发光器件依然可以正常使用，避免影响显示面板的整体显示效果。
可选地，第一电极231为阳极，第二电极42为阴极。发光层41可以包括依次叠置的：空穴注入层、空穴传输层、发光层、电子传输层和电子注入层。第一电极231位于像素界定层PDL与平坦化层3之间。多个发光器件4的第二电极42可以形成为一体结构。
可选地，发光器件4为OLED器件，此时，发光层采用有机发光材料；或者，发光器件4为QLED(Quantum Dot Light Emitting Diodes， 量子点发光二极管)器件，此时，发光层采用量子点发光材料。每个发光器件4被配置为发射预设颜色的光线。
在一些实施例中，如图6所示，第一侧壁301靠近衬底基板1的边缘包括第一部分e1，第一侧壁301远离衬底基板1的边缘包括第二部分e2，第一部分e1和第二部分e2均沿第一方向Y延伸，且二者在衬底基板1上的正投影与第一凸部31在衬底基板1上的正投影无交叠。第二部分e2的延长线在衬底基板1的正投影穿过第一凸部31在衬底基板1上的正投影，即第一凸部31在第二方向X上能够将第一侧壁301完全切断，以避免在第一凸部31和第一侧壁301之间的连接面上形成导电材料的残留，进而第一凸部31无法将第一侧壁301上的导电材料残留截断的现象。
需要说明的是，第一凸部31在衬底基板1上的正投影可以是圆形，也可以是梯形、三角形、四边形等，本公开实施例具体不做限定。
在一些实施例中，如图7所示，显示面板还包括多个第一垫块6，其位于衬底基板1和平坦化层3之间，第一凸部31在衬底基板1上的正投影覆盖第一垫块6在衬底基板1上的正投影。也就是说，在显示面板制作过程中，先形成了第一垫块6，然后形成平坦化层3，使得平坦化层3与第一垫块6相对的部分背向第一垫块6突出，从而形成第一凸部31。
在一些实施例中，第一垫块6与薄膜晶体管5中的源极/漏极材料相同，因此第一垫块6和薄膜晶体管5中的源极/漏极可以在同一制作工序中形成，并且源极和漏极更加靠近平坦化层3，因此更有利于形成第一凸部31。另外，第一垫块6也可以与薄膜晶体管5的栅极材料相同，本公开实施例对此不作限定。
其中，如图6所示，第二部分e2的延长线在衬底基板1的正投影穿过第一凸部31在衬底基板1上的正投影，从而在第一电极层的构图工艺中，尽量减少第一凸部31上的导电材料残留。
在一些实施例中，如图7所示，第一侧壁与挖槽底壁之间的角度β在110°-170°之间。可选地，β可以为110°、120°、130°、140°、150°、160°、170°中的任意一个。
在一些实施例中，如图6所示，每个重复单元21包括沿第二方向X排列的两个电极组22，两个电极组22中的连接电极232分别位于沿第二方向X排列的相邻两个挖槽30中。由于在挖槽30的第一侧壁301上形成第一凸部31，其可以防止第一侧壁301上形成连续的导电材料的残留，进一步避免了每一电极组22中相邻电极块23的连接电极232的连接，以及相邻电极块23之间的发光层41串色现象。
需要说明的是，同一电极组22中可以包括多个电极块23，例如三个电极块23或者四个电极块23，则每相邻的两个电极块23之间均需要对应设置第一凸部31，以避免相邻电极块23的连接电极232的连接，以及相邻电极块23之间的发光层41串色现象。
在一些实施例中，第一凸部31在衬底基板1上的正投影与第一电极231在衬底基板1上的正投影无交叠，即第一电极231仍设置在平坦化层的较为平坦的区域，而不受第一凸部31的影响。
在一些实施例中，如图6所示，挖槽30还具有沿第二方向X延伸的第二侧壁302，平坦化层3还具有至少一个第二凸部32，第二凸部32在衬底基板1上的正投影在第一方向Y上覆盖第二侧壁302在衬底基板1上的正投影。挖槽30中的第二侧壁302连接其第二方向X两侧的第一侧壁301，每个第一侧壁301上均设置有连接电极232，且不同侧壁上的连接电极232属于不同的电极块23，因此，在第二侧壁302上设置第二凸部32，避免第二侧壁302将位于挖槽30第二方向X上两侧的不同电极块23中的连接电极232进行连接。
在一些实施例中，显示面板还包括多个第二垫块(图中未示出)，每一第二垫块位于衬底基板1和平坦化层3之间，第二凸部32在衬底基 板1上的正投影覆盖第二垫块在衬底基板1上的正投影。
在一些实施例中，第二垫块可以与薄膜晶体管5的源极或漏极材料相同，其也可以与薄膜晶体管5的栅极材料相同，本公开实施例对此不作限定。上述第二垫块与本公开实施例中的第一垫块6属于相同发明构思，在此不作赘述。
图8为本公开实施例提供的一种显示面板的局部平面图，在一些实施例中，如图8所示，在靠近同一电极组22中每相邻两个电极块23的间隔区域的位置，设置有一个第一凸部31。
需要说明的是，靠近同一电极组22中每相邻两个电极块23的间隔区域的位置是指，第一侧壁301中，与同一电极组22中每相邻两个电极块23之间的间隔区域相邻的位置，也就是说，相邻两个电极块23的分界线在衬底基板1上的正投影穿过第一凸部31在衬底基板1上的正投影。
另外，第一凸部31用于截断第一侧壁301上导电材料的残留，以避免相邻电极块23的连接电极232短接，使得相邻电极块23之间的第一电极231发光层41之间存在串色的现象。因此，第一凸部31可以设置在图8中的连接电极232a与连接电极232b之间的任意位置上，均能够将上述两个连接电极之间的第一侧壁301上导电材料的残留截断，避免两个连接电极之间连接，进而避免因不同颜色的发光器件的第一电极短接而导致的显示混色现象，从而提高显示面板的显示效果。
本公开实施例还提供一种显示装置，包括上述显示面板。
上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开对此不作限定。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变 型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种显示面板，其中，包括：衬底基板、电极层、以及位于所述衬底基板和所述电极层之间的平坦化层；
    所述电极层包括多个重复单元，每一重复单元包括至少一个电极组，每一电极组包括沿第一方向排列的多个电极块，每个所述电极块包括沿所述第一方向排列的多个第一电极以及连接在每相邻两个所述第一电极之间的连接电极；
    所述平坦化层上具有多个挖槽，所述重复单元在第二方向上的至少一侧有挖槽，所述挖槽具有沿所述第一方向延伸的第一侧壁，所述连接电极至少部分位于所述第一侧壁上；其中，所述第二方向与所述第一方向交叉；
    所述平坦化层还具有多个第一凸部，所述第一凸部在所述衬底基板上的正投影在所述第二方向上覆盖所述第一侧壁在所述衬底基板上的正投影，并且，同一个所述电极组中至少两个相邻的所述电极块的连接电极之间，设置有所述第一凸部。
  2. 根据权利要求1所述的显示面板，其中，所述第一侧壁靠近所述衬底基板的边缘包括第一部分，所述第一侧壁远离所述衬底基板的边缘包括第二部分，所述第一部分和所述第二部分均沿所述第一方向延伸，且所述第一部分和所述第二部分在所述衬底基板上的正投影与所述第一凸部在所述衬底基板上的正投影无交叠；
    所述第二部分的延长线在所述衬底基板上的正投影穿过所述第一凸部在所述衬底基板上的正投影。
  3. 根据权利要求1或2所述的显示面板，其中，所述显示面板还包 括：
    多个第一垫块，所述第一垫块位于所述衬底基板和所述平坦化层之间，所述第一凸部在所述衬底基板上的正投影覆盖所述第一垫块在所述衬底基板上的正投影。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板还包括：
    薄膜晶体管，位于所述平坦化层与所述衬底基板之间；
    其中，所述第一电极通过所述平坦化层上的过孔与所述薄膜晶体管的漏极电连接，所述第一垫块与所述薄膜晶体管的漏极或栅极材料相同。
  5. 根据权利要求1-4中任一项所述的显示面板，其中，每个重复单元包括沿所述第二方向排列的两个所述电极组，所述两个电极组中的连接电极分别位于沿第二方向排列的相邻两个所述挖槽中。
  6. 根据权利要求1-4中任一项所述的显示面板，其中，所述第一凸部在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影无交叠。
  7. 根据权利要求1-4中任一项所述的显示面板，其中，所述挖槽还具有沿第二方向延伸的第二侧壁，所述平坦化层还具有至少一个第二凸部，所述第二凸部在所述衬底基板上的正投影在所述第一方向上覆盖所述第二侧壁在所述衬底基板上的正投影。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板还包括：
    多个第二垫块，每一所述第二垫块位于所述衬底基板和所述平坦化层之间，所述第二凸部在所述衬底基板上的正投影覆盖所述第二垫块在 所述衬底基板上的正投影。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括：
    薄膜晶体管，位于所述平坦化层与所述衬底基板之间；
    所述第二垫块与所述薄膜晶体管的漏极或栅极材料相同。
  10. 根据权利要求1-4中任一项所述的显示面板，其中，所述显示面板还包括：
    多个发光器件，每个所述发光器件包括所述第一电极、发光层和第二电极，所述第二电极位于所述第一电极远离所述衬底基板的一侧，所述发光层位于所述第一电极与所述第二电极之间；
    其中，同一个电极块中的多个第一电极所对应的发光层的发光颜色相同。
  11. 根据权利要求1-10中任一项所述的显示面板，其中，
    所述多个重复单元阵列排布，所述第一方向和所述第二方向中的一个为行方向，另一个为列方向；
    所述第二方向上每相邻两个所述重复单元之间，设置有所述挖槽。
  12. 根据权利要求1-10中任一项所述的显示面板，其中，所述第一侧壁与所述挖槽底壁之间的角度在110°-170°之间。
  13. 根据权利要求1-10中任一项所述的显示面板，其中，同一个所述电极组中每相邻两个所述电极块的间隔区域，对应设置有一个所述第一凸部。
  14. 根据权利要求1-10中任一项所述的显示面板，其中，同一电极块中的所述第一电极和所述连接电极连为一体结构。
  15. 一种显示装置，其中，包括权利要求1-14中任一项所述的显示面板。
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CN111584757A (zh) * 2020-05-27 2020-08-25 京东方科技集团股份有限公司 显示母板和显示基板的制作方法
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CN113540194A (zh) * 2021-07-12 2021-10-22 武汉华星光电半导体显示技术有限公司 一种显示面板及显示装置
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