WO2022262367A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

Info

Publication number
WO2022262367A1
WO2022262367A1 PCT/CN2022/084646 CN2022084646W WO2022262367A1 WO 2022262367 A1 WO2022262367 A1 WO 2022262367A1 CN 2022084646 W CN2022084646 W CN 2022084646W WO 2022262367 A1 WO2022262367 A1 WO 2022262367A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
contact
array substrate
display panel
Prior art date
Application number
PCT/CN2022/084646
Other languages
English (en)
French (fr)
Inventor
邢汝博
米磊
韩真真
Original Assignee
合肥维信诺科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 合肥维信诺科技有限公司 filed Critical 合肥维信诺科技有限公司
Priority to KR1020237020667A priority Critical patent/KR20230101925A/ko
Publication of WO2022262367A1 publication Critical patent/WO2022262367A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a manufacturing method thereof.
  • Organic light emitting display panel (Organic Light Emitting Diode, referred to as OLED) has many characteristics such as self-illumination, fast response, wide viewing angle and can be fabricated on a flexible substrate, and is increasingly used in high-performance display fields such as flexible display devices. middle.
  • the cathode layer is a whole-layer structure, and the cathode layer is connected to a common potential through wires.
  • the cathode layer is easy to manufacture, the wires are simple to manufacture, and the display panel is less difficult to manufacture, but the light transmittance of the cathode layer is low, resulting in a poor shooting effect of the camera module.
  • the cathode layer includes multiple cathodes.
  • the cathode layer of this structure With the cathode layer of this structure, the light transmittance of the cathode layer is better, and the shooting effect of the camera module is good, but the fabrication of the cathode layer is relatively difficult, and the cathode layer Each cathode in the layer needs to be connected with a wire, and the manufacturing of the wire is complicated, which makes it difficult to manufacture the display panel.
  • embodiments of the present application provide a display panel and a manufacturing method thereof, which are used to improve the shooting effect of the camera module and reduce the difficulty of manufacturing the display panel.
  • the first aspect of the embodiments of the present application provides a display panel, which includes: an array substrate arranged in layers, a first electrode layer, an intermediate layer, and a second electrode layer, and the first electrode layer includes electrode contacts arranged on the same layer and a plurality of first electrodes, a space is provided between two adjacent first electrodes, and a space is provided between adjacent first electrodes and the electrode contacts; the array substrate is provided with a shielding part, the shielding part is opposite to the space between the first electrode and the electrode contact, and the orthographic projection of the first electrode and the electrode contact on the array substrate is consistent with the Orthographic projections of the shielding portion on the array substrate are adjacent or at least partly overlapped; the second electrode layer is in contact with the electrode contact, the second electrode layer has a hollow area, and the second The orthographic projection of the electrode layer on the array substrate covers the first electrode, the electrode contact, and the orthographic projection of the shielding portion on the array substrate.
  • the second electrode layer is provided with a hollow area, which allows external light to enter, reduces the second electrode layer's blocking of external light, and increases the external light received by the camera module. Thereby improving the shooting effect of the camera module.
  • the shielding part in the array substrate is opposite to the space between the first electrode and the electrode contact, and the orthographic projection of the first electrode and the electrode contact on the array substrate is adjacent to the orthographic projection of the shielding part on the array substrate Or at least partially overlap, so that the first electrode, the electrode contact and the orthographic projection of the shielding part on the array substrate are integrated, and the orthographic projection of the second electrode layer on the array substrate covers the first electrode, the electrode contact, and the shielding part Orthographic projection on the array substrate, so that the second electrode layer located above the electrode contact communicates with the second electrode layer located above the first electrode, and the second electrode layer is in contact with the electrode contact, so as to realize the second The electrode layer is electrically connected to the electrode contacts, so that the display panel can emit light normally.
  • the wires connected to the first electrodes and the wires connected to the electrode contacts can be made on the same layer. , which simplifies the process, thereby reducing the difficulty of manufacturing the display panel.
  • the second aspect of the embodiments of the present application provides a method for manufacturing a display panel, which includes:
  • An array substrate is provided, and a shielding part is arranged in the array substrate;
  • a first electrode layer is formed on the array substrate, the first electrode layer includes electrode contacts and a plurality of first electrodes arranged on the same layer, and there is a space between two adjacent first electrodes, and There is a space between the adjacent first electrode and the electrode contact, the space between the first electrode and the electrode contact is exactly corresponding to the shielding part, the first electrode and the electrode contact
  • the orthographic projection of the electrode contact on the array substrate is adjacent to or at least partially coincides with the orthographic projection of the shielding portion on the array substrate;
  • the intermediate layer includes a pixel defining layer formed on the first electrode layer, the pixel defining layer is provided with a plurality of first openings corresponding to each of the first electrodes, and the A second opening corresponding to the electrode contact, the first opening is provided with a luminescent material, and the second opening exposes at least part of the electrode contact;
  • the first electrode and the electrode contact as a mask, laser etching the second electrode material layer to form a second electrode layer, the second electrode layer has a hollow area, and the The orthographic projection of the second electrode layer on the array substrate covers the first electrode, the electrode contacts, and the orthographic projection of the shielding portion on the array substrate.
  • the second electrode material layer is formed by laser etching the second electrode material layer with the shielding part, the first electrode and the electrode contact as a mask, and the second electrode layer is reduced.
  • the area of the second electrode layer makes the second electrode layer have a space for external light to pass through, which increases the amount of external light received by the camera module, thereby improving the shooting effect of the camera module.
  • the wires connected to the first electrodes and the wires connected to the electrode contacts can be made on the same layer, which simplifies the process and reduces the difficulty of manufacturing the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in an embodiment of the present application
  • Fig. 2 is a schematic diagram of the arrangement of the first electrode and electrode contacts in the embodiment of the present application
  • Fig. 3 is another schematic diagram of the arrangement of the first electrode and electrode contacts in the embodiment of the present application.
  • FIG. 4 is a flowchart of a method for manufacturing a display panel in an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of an array substrate in an embodiment of the present application.
  • FIG. 6 is a schematic structural view after forming the first electrode layer in the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a pixel defining layer formed in an embodiment of the present application.
  • FIG. 8 is a schematic structural view of the formation of the intermediate layer in the embodiment of the present application.
  • FIG. 9 is a schematic structural view after forming a second electrode material layer in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of laser etching in the embodiment of the present application.
  • the display panel in the related art has the problem that it is difficult to balance the shooting effect of the camera module and the difficulty of making the display panel.
  • the reason for this problem is that the camera module is located under the display panel.
  • the cathode layer far away from the camera module in the display panel is adopted as a whole-layer structure, the cathode layer is easy to manufacture, and the wires of the cathode layer are also easy to lead out, and the manufacturing difficulty of the display panel is relatively low.
  • the light transmittance of the cathode layer is low, and its light transmittance is usually lower than 50%, resulting in less external light passing through the display panel, resulting in insufficient external light received by the camera module.
  • the shooting effect of the module is poor.
  • the cathode layer is a block structure, that is, the cathode layer includes a plurality of cathodes, and there are intervals between two adjacent cathodes. Since there are intervals between the cathodes, these intervals form a light-transmitting area, so that the external light passing through the display panel can be increased, and the shooting effect of the camera module can be improved.
  • the production of the display panel is relatively difficult, which is mainly reflected in the following two aspects:
  • a plurality of cathodes are usually made by vacuum evaporation process, and the high-precision metal mask plate (Fine Metal Mask, FMM for short) required by this process is difficult to make.
  • the thickness of the high-precision metal mask plate is usually The diameter of the opening required for the evaporation cathode is usually 20 microns. It is difficult to make this opening on a high-precision metal mask, and the failure rate is high, resulting in high manufacturing costs for the high-precision metal mask. The manufacturing difficulty and manufacturing cost of the display panel are increased. If other methods are used to make the cathode, there is usually a problem of difficulty in aligning the cathode and anode, or the problem of damaging the luminescent material.
  • each cathode needs to be connected to the common potential of the display panel, so that a potential difference can be generated between the cathode and the anode to ensure that the luminescent material located between the cathode and the anode emits light.
  • a potential difference can be generated between the cathode and the anode to ensure that the luminescent material located between the cathode and the anode emits light.
  • it is relatively complicated to manufacture the wires connected to the cathode, which also increases the manufacturing difficulty and cost of the display panel.
  • one of the anode layer and the cathode layer includes a plurality of electrode blocks, and the other is provided with a hollow area, which allows external light to enter, reducing the exposure to external light.
  • the blocking increases the external light received by the camera module, thereby improving the shooting effect of the camera module.
  • the cathode layer or the anode layer of the entire layer structure is connected to the common potential through the electrode contacts, and the electrode contacts are arranged on the same layer as the anode layer or the cathode layer including a plurality of electrode blocks, so that the cathode layer or the anode layer of the entire layer structure
  • the number of connected wires is small, and the wires connected to the cathode layer or the anode layer and the wires connected to the electrode contacts can be manufactured together, which simplifies the manufacturing process of the wires, thus simplifying the manufacturing difficulty and reducing the manufacturing cost of the display panel .
  • the display panel provided by the embodiment of the present application includes an array substrate 100 , a first electrode layer, an intermediate layer 300 and a second electrode layer 410 arranged in layers.
  • the array substrate 100 may be a thin film transistor (Thin Film Transistor, TFT for short) array substrate.
  • the array substrate 100 includes a substrate 110 , an insulating layer 120 disposed on the substrate 110 , and a planarization layer 130 (Planarization Layer, PLN for short) disposed on the insulating layer 120 .
  • TFT Thin Film Transistor
  • the substrate 110 may be a glass substrate, a flexible plastic substrate or a quartz substrate.
  • a plurality of gate lines arranged along a first direction and a plurality of data lines arranged along a second direction are arranged on the surface of the substrate 110, and the defined area between the gate lines and the data lines is used to define a pixel unit, and the first The direction intersects the second direction.
  • the gate of the thin film transistor is connected to the gate line, the source of the thin film transistor is connected to the data line, and the drain of each thin film transistor is electrically connected to its corresponding pixel unit.
  • the thin film transistor provides the data display signal input by the data line to the pixel unit corresponding to the thin film transistor under the control of the gate line.
  • the insulating layer 120 can be a single-layer or multi-layer structure, and a connecting line is arranged in the insulating layer 120, such as a metal line penetrating through the insulating layer 120, so as to electrically connect the thin film transistor to the first electrode layer (such as the anode layer) in the pixel unit. .
  • the insulating layer 120 includes a gate insulating (Gate Insulator, referred to as GI) layer 121 located on the substrate 110, and an interlayer insulating (Inter Layer Dielectric, referred to as ILD) layer located on the gate insulating layer 121 122.
  • the gate insulating layer 121 covers the source and drain of the thin film transistor, and the gate of the thin film transistor is disposed on the gate insulating layer 121 .
  • the gate insulating layer 121 and the interlayer insulating layer 122 can be fabricated by a chemical vapor deposition (Chemical Vapor Deposition, CVD for short) process.
  • the material of the gate insulating layer 121 includes silicon oxide, and the material of the interlayer insulating layer 122 includes silicon oxide (such as SiO2), borophosphosilicate glass (BPSG), phosphosilicate hydrochloric acid glass (PSG) or silicon nitride (such as Si3N4), etc. .
  • silicon oxide such as SiO2
  • BPSG borophosphosilicate glass
  • PSG phosphosilicate hydrochloric acid glass
  • Si3N4 silicon nitride
  • the planarization layer 130 is located on the uppermost layer of the array substrate 100 , and the upper surface of the planarization layer 130 is flush, so as to form relatively flat film layers on the planarization layer 130 .
  • the material of the planarization layer 130 may be an organic material, and the planarization layer 130 may be fabricated by a coating or sputtering process.
  • a shielding portion 140 is further disposed in the array substrate 100 .
  • the shielding portion 140 is disposed on the insulating layer 120
  • the planarization layer 130 covers the insulating layer 120 and the shielding portion 140 disposed on the insulating layer 120 .
  • the shielding portion 140 is an opaque material layer, that is, the shielding portion 140 is opaque.
  • the shielding part 140 is made of metal (such as silver), or the shielding part 140 is a black material layer, such as a resin layer including carbon black.
  • the shielding portion 140 may be a separately provided structure, or may be a metal wire in the array substrate 100 , that is, the metal wire in the array substrate 100 serves as the shielding portion 140 .
  • the first electrode layer can be an anode layer
  • the second electrode layer 410 can be a cathode layer; or, the first electrode layer can be a cathode layer, and the second electrode layer 410 can be an anode layer, hereinafter referred to as the first
  • the electrode layer is an anode layer
  • the second electrode layer 410 is a cathode layer as an example for description.
  • the first electrode layer in the embodiment of the present application includes a first electrode 210 and an electrode contact 220, the first electrode 210 is an anode, and the first electrode 210 and the electrode contact 220 are arranged on the same layer, so that the first electrode 210 and the electrode Contacts 220 are made simultaneously.
  • the space between the first electrode 210 and the electrode contact 220 is opposite to the shielding portion 140 , and the orthographic projection of the first electrode 210 and the electrode contact 220 on the array substrate 100 is the same as the orthographic projection of the shielding portion 140 on the array substrate 100 .
  • the projections are contiguous or at least partially coincident. It can be understood that, the orthographic projection of the first electrode 210 , the electrode contact 220 and the shielding portion 140 on the array substrate 100 are connected into one piece.
  • the structure and material of the first electrode 210 and the electrode contact 220 can be the same, which further ensures that the first electrode 210 and the electrode contact 220 can be manufactured at the same time, reduces the manufacturing difficulty of the display panel, and improves the manufacturing efficiency of the display panel.
  • Both the first electrode 210 and the electrode contact 220 are opaque material layers.
  • the first electrode 210 and the electrode contact 220 may be a metal layer, such as a silver layer; they may also be a stack of metal-transparent materials, For example an ITO-Ag-ITO layer (indium tin oxide-silver-indium tin oxide layer).
  • an electrode contact 220 is correspondingly arranged next to each first electrode 210, that is, the number of first electrodes 210 is the same as that of the electrode contact.
  • the number of points 220 is the same, and the multiple first electrodes 210 correspond to the multiple electrode contacts 220 one by one.
  • the interval 240 between each first electrode 210 and the corresponding electrode contact 220 corresponds to one shielding portion 140 .
  • the edge of the first electrode 210 may be provided with a recess, and at least a part of the electrode contact 220 is located in the recess, so as to reduce the space occupied by the first electrode 210 and the electrode contact 220 .
  • the cross-sectional shape of the recessed portion is arc-shaped, the cross-sectional shape of the electrode contact 220 is circular, and the curvature of the recessed portion is the same as the curvature of the electrode contact 220 The same, so as to match between the first electrode 210 and the electrode contact 220 .
  • the spaces 240 between the first electrodes 210 and the electrode contacts 220 are equidistant.
  • the cross-sectional shape of the recessed portion and the cross-sectional shape of the electrode contact 220 are not limited. 220 to match the cross-sectional shape.
  • the first electrode layer includes several electrode units, each electrode unit includes an electrode contact 220, and the electrode contact 220 adjacent to There are at least two first electrodes 210, so as to reduce the number of electrode contacts 220, thereby reducing the manufacturing difficulty of the first electrode layer.
  • the number of first electrodes 210 in each electrode unit can be the same or different.
  • some electrode units include two first electrodes 210
  • some electrode units include three first electrodes 210 ; or, each electrode unit includes two first electrodes 210 .
  • each electrode unit includes three first electrodes 210 and one electrode contact 220, and the centers of the three first electrodes 210 are respectively located in three corners of a virtual triangle (shown by a dotted line in FIG. 3 ). vertices, the electrode contact 220 is located inside the virtual triangle.
  • the interval 240 between the electrode contact 220 and each first electrode 210 corresponds to one shielding portion 140, that is, the number of shielding portions 140 is equal to the number of first electrodes 210 in this electrode unit. same.
  • the distance between the edge of the electrode contact 220 and the edge of each first electrode 210 is equal, the width of each shielding portion 140 along the direction from the first electrode 210 to the electrode contact 220 is equal, and the distance between the electrode contact 220 and the first electrode 210 is equal.
  • the intervals 240 between the shielding portions 140 corresponding to each other are the same.
  • the distance 240 between the electrode contact 220 and the first electrode 210 in each electrode unit corresponds to a shielding portion 140, that is, the orthographic projection of the electrode contact 220 on the array substrate 100 is located in the shielding portion.
  • the orthographic projection of the first electrode 210 on the array substrate 100 is adjacent to or at least partially coincides with the orthographic projection of the shielding portion 140 on the array substrate 100 .
  • a first wire 250 is disposed below the first electrode 210 , the first wire 250 is located between the first electrode 210 and the array substrate 100 , and the first wire 250 electrically connects the first electrode 210 Connect the driving potential.
  • a second wire 230 is disposed below the electrode contact 220 , the second wire 230 is located between the electrode contact 220 and the array substrate 100 , and the second wire 230 electrically connects the electrode contact 220 to a common potential.
  • the first wires 250 and the second wires 230 can be arranged in the same layer, so that the first wires 250 and the second wires 230 can be manufactured at the same time, which simplifies the manufacturing steps of the display panel.
  • the intermediate layer 300 in the embodiment of the present application includes a pixel defining layer 310 (Pixel Define Layer, PDL for short), and the pixel defining layer 310 is arranged on the first electrode layer.
  • the pixel defining layer 310 can be a silicon oxide layer, The silicon nitride layer or the transparent resin layer, and the pixel defining layer 310 can be fabricated by Plasma Chemical Vapor Deposition (PCVD), inkjet printing, or spin coating (Spin Coating) and other processes.
  • the pixel defining layer 310 is provided with a plurality of first openings and second openings 311 , the plurality of first openings correspond to the plurality of first electrodes 210 one by one, and the second openings 311 correspond to the electrode contacts 220 .
  • the first opening and the second opening 311 penetrate the pixel defining layer 310, the first opening exposes the first electrode 210, and the second opening 311 exposes at least part of the electrode contact 220, for example, the second opening 311 exposes the central area of the electrode contact 220 .
  • the orthographic projection of the first opening on the first electrode layer is located in the first electrode 210 , and the distance between the edge of the orthographic projection of the first opening on the first electrode layer and the corresponding edge of the first electrode 210 is greater than 2 ⁇ m. In this way, the pixel defining layer 310 can seal the edge of the first electrode 210 to prevent structures such as burrs on the edge of the first electrode 210 from affecting the normal operation of the luminescent material 320 in the first opening.
  • the orthographic projection of the second opening 311 on the first electrode layer is located inside the electrode contact 220 or coincides with the electrode contact 220 .
  • the luminescent material 320 may include a red luminescent material R, a green luminescent material G, and a blue luminescent material B to emit light of different colors.
  • each electrode unit includes three first electrodes 210 and one electrode contact 220, in some possible examples, as shown in FIG.
  • the colors of the materials are different, that is, the first opening corresponding to one of the first electrodes 210 among the three first electrodes 210 is provided with a red luminescent material R, and the first opening corresponding to the other first electrode 210 among the three first electrodes 210 A green luminescent material G is disposed in the first opening, and a blue luminescent material B is disposed in the first opening corresponding to the last first electrode 210 among the three first electrodes 210 .
  • the three first electrodes 210 share one electrode contact 220 to reduce the number of electrode contacts 220 .
  • the centers of the three first electrodes 210 are respectively located at the three vertices of a virtual triangle, the electrode contact 220 is located in the virtual triangle, and the central area of the electrode contact 220 is exposed in the second opening 311, and the center of the second opening 311 at the center of the virtual triangle.
  • a first common layer 321 may also be disposed on the pixel defining layer 310, and the first common layer 321 includes a hole injection layer (Hole Injection Layer, referred to as HIL) and/or Hole Transport Layer (HTL for short).
  • HIL hole injection layer
  • HTL Hole Transport Layer
  • a luminescent material (not shown) is disposed on the first common layer 321 in the first opening
  • a second common layer (not shown) is disposed on the first common layer 321 and the luminescent material
  • the second common Layers include Electron Injection Layer (EIL for short) and/or Electron Transport Layer (ETL for short).
  • the second opening 311 extends into the first common layer 321 and the second common layer, that is, the second opening 311 runs through the first common layer 321 and the second common layer.
  • the second common layer exposes the electrode contact 220 so that the second electrode layer 410 can be in contact with the electrode contact 220 to realize the electrical connection between the second electrode layer 410 and the electrode contact 220 .
  • the shape of the second opening 311 located in the first common layer 321 , the second common layer and the pixel defining layer 310 may be a stepped through hole or a straight through hole.
  • the first electrode layer located in the first opening, the first common layer 321 , the luminescent material, the second common layer and the second electrode layer 410 constitute a pixel unit.
  • the second electrode layer 410 (ie, the cathode layer) is in contact with the electrode contact 220 , and the second electrode layer 410 is connected to the common potential through the electrode contact 220 and the second wire 230 .
  • the second electrode layer 410 has a hollowed-out area, and the hollowed-out area runs through the second electrode layer 410 to reduce the area of the second electrode layer 410 so that external light can pass through the second electrode layer 410 to increase the amount of external light entering, thereby improving the camera. The shooting effect of the module.
  • the gap between the hollowed out area and the first electrode 210 is directly opposite, and no electrode contact 220 is arranged in the space directly opposite to the hollowed out area, that is, the hollowed out area is not aligned with the first electrode 210 and the electrode contact 220 Yes, to ensure that the second electrode layer 410 facing the electrode contact 220 communicates with the second electrode layer 410 facing the first electrode 210 .
  • the orthographic projection of the second electrode layer 410 on the array substrate 100 covers the first electrode 210 , the electrode contact 220 , and the orthographic projection of the shielding portion 140 on the array substrate 100 , that is, the second electrode layer 410 located above the first electrode 210 It communicates with the second electrode layer 410 on the electrode contact 220 .
  • the second electrode layer 410 within the range of the orthographic projection of the first electrode 210 can be connected to a common potential through the electrode contact 220 to ensure that the display panel can work normally.
  • the orthographic projection of the second electrode layer 410 on the array substrate 100 coincides with the orthographic projection of the first electrode 210, the electrode contact 220, and the shielding portion 140 on the array substrate 100, so as to further reduce the The area of 410 increases the amount of external light entering.
  • the second electrode layer 410 includes a plurality of second electrodes, the second electrodes are cathodes, and each cathode is connected to the first electrode 210 and the electrode contact 220 in an electrode unit.
  • the cathode opposite to the first electrode 210 and the electrode contact 220 in an electrode unit has an integrated structure, that is, at least two pixel units corresponding to an electrode unit share a cathode, and the cathode is in contact with the electrode contact 220 to lower the electrode. The number of contacts 220.
  • the material of the second electrode layer 410 may include metal, such as one or more of silver, magnesium-silver alloy, and aluminum.
  • the second electrode layer 410 can be formed by laser etching using the first electrode 210 , the electrode contact 220 and the shielding portion 140 as a mask. During etching, the laser is focused on the second electrode layer 410 to avoid damage to other film layers.
  • the wavelength of the laser light is a specific value, so that the second electrode layer 410 has a higher absorption rate of the laser light of this wavelength, and the other film layers have a lower absorption rate of the laser light of this wavelength, so as to further avoid damage to other film layers.
  • the second electrode layer 410 is provided with a hollow area, which can allow external light to enter, which reduces the blocking of external light by the second electrode layer 410 and increases the external light received by the camera module. Light, thereby improving the shooting effect of the camera module.
  • the shielding part 140 in the array substrate 100 is opposite to the space between the first electrode 210 and the electrode contact 220, and the orthographic projection of the first electrode 210 and the electrode contact 220 on the array substrate 100 is the same as that of the shielding part 140 in the array.
  • the orthographic projections on the substrate 100 are adjacent or at least partly overlapped, so that the orthographic projections of the first electrode 210, the electrode contact 220 and the shielding part 140 on the array substrate 100 are integrated, and the second electrode layer 410 is on the array substrate 100.
  • the orthographic projection of the first electrode 210 , the electrode contact 220 and the shielding part 140 on the array substrate 100 covers the orthographic projection of the first electrode 210 , the electrode contact 220 and the shielding part 140 , so that the second electrode layer 410 located above the electrode contact 220 and the second electrode layer 410 located above the first electrode 210
  • the electrode layer 410 is connected, and the second electrode layer 410 is in contact with the electrode contact 220, so as to realize the electrical connection between the second electrode layer 410 and the electrode contact 220, so that the display panel can normally emit light.
  • the wires connected to the first electrode 210 and the wires connected to the electrode contact 220 can be made on the same layer, which simplifies the process and reduces the difficulty of manufacturing the display panel. , reducing the manufacturing difficulty of the display panel.
  • the embodiment of the present application also provides a method for manufacturing a display panel. As shown in FIG. 4 , the method for manufacturing a display panel includes the following steps:
  • step S101 an array substrate is provided, and a shielding portion is disposed in the array substrate.
  • the array substrate 100 may be a TFT array substrate, and the array substrate 100 includes a substrate 110 , an insulating layer 120 disposed on the substrate 110 , and a planarization layer 130 disposed on the insulating layer 120 .
  • a plurality of gate lines arranged along a first direction and a plurality of data lines arranged along a second direction are arranged on the surface of the substrate 110, and the defined area between the gate lines and the data lines is used to define a pixel unit, and the first The direction intersects the second direction.
  • the gate of the thin film transistor is connected to the gate line, the source of the thin film transistor is connected to the data line, and the drain of each thin film transistor is electrically connected to its corresponding pixel unit; during the display process, the thin film transistor is controlled by the gate line , providing the data display signal input by the data line to the pixel unit corresponding to the thin film transistor.
  • the insulating layer 120 may be a single-layer or multi-layer structure, and a connecting wire, such as a metal wire penetrating through the insulating layer 120, is provided in the insulating layer 120 to electrically connect the thin film transistor and the first electrode layer.
  • the insulating layer 120 includes a gate insulating layer 121 on the substrate 110 , and an interlayer insulating layer 122 on the gate insulating layer 121 .
  • the gate insulating layer 121 covers the source and drain of the thin film transistor, and the gate of the thin film transistor is disposed on the gate insulating layer 121 .
  • the planarization layer 130 is generally located on the uppermost layer of the array substrate 100 , and the upper surface of the planarization layer 130 is flush, so as to form relatively flat film layers on the planarization layer 130 .
  • the material of the planarization layer 130 may be an organic material, and the planarization layer 130 may be fabricated by a coating or sputtering process.
  • a shielding portion 140 is also disposed in the array substrate 100 .
  • the shielding portion 140 may be disposed on the insulating layer 120 , and the planarization layer 130 covers the insulating layer 120 and the shielding portion 140 disposed on the insulating layer 120 .
  • the shielding portion 140 is an opaque material layer, that is, the shielding portion 140 is opaque.
  • the shielding part 140 is made of metal (such as silver), or the shielding part 140 is a black material layer, such as a resin layer including carbon black.
  • the shielding portion 140 may be a separately provided structure, or may be a metal wire in the array substrate 100 , that is, the metal wire in the array substrate 100 serves as the shielding portion 140 .
  • Step S102 forming a first electrode layer on the array substrate.
  • the first electrode layer includes electrode contacts 220 and a plurality of first electrodes 210 arranged on the same layer. There is an interval between two adjacent first electrodes 210, and There is a space between the adjacent first electrode 210 and the electrode contact 220, the space between the first electrode 210 and the electrode contact 220 corresponds to the shielding part 140, the first electrode 210 and the electrode contact 220 are on the array substrate
  • the orthographic projection of and the orthographic projection of the shielding portion 140 on the array substrate are adjacent to or at least partly overlapped.
  • a plurality of first electrodes 210 and electrode contacts 220 are formed simultaneously by depositing a first electrode material on the array substrate 100 and then etching the first electrode material by a process such as laser etching.
  • the first electrode material is an opaque material, and the first electrode material may be a metal, such as silver, or a stack of metal-transparent materials, such as a stack of ITO-Ag-ITO.
  • first electrodes 210 for example, anodes
  • an interval is provided between two adjacent first electrodes 210
  • a gap is provided between adjacent electrode contacts 220 and the first electrodes 210.
  • interval, and the interval is exactly corresponding to the shielding portion 140 .
  • the orthographic projection of the first electrode 210 and the electrode contact 220 on the array substrate 100 is adjacent to or at least partially coincides with the orthographic projection of the shielding portion 140 on the array substrate 100, that is, the first electrode 210, the electrode contact 220 and the shielding portion
  • the orthographic projections of 140 on the array substrate 100 are connected into one piece.
  • an electrode contact 220 is correspondingly arranged beside each first electrode 210 , and the distance between each first electrode 210 and the corresponding electrode contact 220 is positive.
  • the edge of the first electrode 210 may be provided with a recess, and at least a partial area of the electrode contact 220 is located in the recess, so as to reduce the space occupied by the first electrode 210 and the electrode contact 220 .
  • the first electrode layer includes several electrode units, and each electrode unit includes at least two adjacent first electrodes 210 and an electrode contact 220 between these first electrodes 210 , so as to reduce the number of electrode contacts 220 and reduce the manufacturing difficulty of the first electrode layer.
  • each electrode unit includes three first electrodes 210 and one electrode contact 220, the centers of the three first electrodes 210 are respectively located at the three vertices of a virtual triangle, and the electrode contact 220 is located at The interior of the virtual triangle.
  • the distance between the electrode contact 220 and each first electrode 210 corresponds to one shielding portion 140, that is, the number of shielding portions 140 is the same as the number of first electrodes 210 in this electrode unit .
  • a first wire 250 is provided below the first electrode 210 , the first wire 250 is located between the first electrode 210 and the array substrate 100 , and the first wire 250 electrically connects the first electrode 210 to the array substrate 100 .
  • a second wire 230 is disposed below the electrode contact 220 , the second wire 230 is located between the electrode contact 220 and the array substrate 100 , and the second wire 230 electrically connects the electrode contact 220 to a common potential.
  • the first wires 250 and the second wires 230 can be arranged in the same layer, so that the first wires 250 and the second wires 230 can be manufactured at the same time, which simplifies the manufacturing steps of the display panel.
  • Step S103 forming an intermediate layer, the intermediate layer includes a pixel defining layer formed on the first electrode layer, the pixel defining layer is provided with a plurality of first openings corresponding to each first electrode 210, and a plurality of first openings corresponding to the electrode contacts 220 In the second opening, a luminescent material is disposed in the first opening, and at least part of the electrode contact 220 is exposed through the second opening.
  • a pixel-defining material layer is formed on the first electrode layer by plasma chemical vapor deposition, inkjet printing, or spin coating, and then a patterning process is performed on the pixel-defining material layer to form a first pixel-defining material layer that penetrates the pixel-defining material layer.
  • the opening 312 and the second opening 311 , the pixel defining material layer having the first opening 312 and the second opening 311 form the pixel defining layer 310 .
  • the number of first openings 312 is multiple, and the multiple first openings 312 correspond to the multiple first electrodes 210 one by one, and the first electrodes 210 are exposed in the first openings 312, and the second openings 311 and the electrode contacts 220 Correspondingly, and the second opening 311 exposes at least part of the electrode contact 220 .
  • the multiple electrode contacts 220 there are also multiple second openings 311 , and the multiple second openings 311 correspond to the multiple electrode contacts 220 one by one.
  • the orthographic projection of the first opening 312 on the first electrode layer is located in the first electrode 210, and the distance between the edge of the orthographic projection of the first opening 312 on the first electrode layer and the corresponding edge of the first electrode 210 is greater than 2 Micron.
  • the orthographic projection of the second opening 311 on the first electrode layer is located inside the electrode contact 220 or coincides with the electrode contact 220 .
  • a first common layer 321 is formed in the pixel defining layer 310, the first opening 312, and the second opening 311, and the first common layer 321 includes voids.
  • Hole injection layer and/or hole transport layer Evaporate light-emitting material on the first common layer 321 located in the first opening 312; Form a second common layer on the first common layer 321 and the light-emitting material, the second common layer
  • the layers include an electron injection layer and/or an electron transport layer; laser etching removes at least part of the first common layer 321 and the second common layer located in the second opening 311 to expose the electrode contact 220 .
  • each electrode unit includes three first electrodes 210 and one electrode contact 220, as shown in FIG. R, green luminescent material G and blue luminescent material B, and the centers of the three first electrodes 210 are respectively located at the three vertices of the virtual triangle, and the center of the second opening 311 is located at the center of the virtual triangle.
  • Step S104 forming a second electrode material layer on the intermediate layer and in the second opening 311 , the second electrode material layer is in contact with the electrode contact 220 .
  • a second electrode material layer 420 is formed on the second common layer and in the second opening 311 , as shown in FIG. 9 , the second electrode material layer 420 is a whole layer structure.
  • the second electrode material layer 420 covers the second common layer and is in contact with the electrode contact 220 , so that the second electrode material layer 420 is electrically connected to the electrode contact 220 .
  • the material of the second electrode material layer 420 may be metal, such as one or more of silver, magnesium-silver alloy, and aluminum.
  • Step S105 using the shielding part 140, the first electrode 210 and the electrode contact 220 as a mask, laser etching the second electrode material layer to form a second electrode layer 410, the second electrode layer 410 has a hollow area, and the second electrode
  • the orthographic projection of the layer 410 on the array substrate covers the first electrode 210 , the electrode contact 220 , and the orthographic projection of the shielding part 140 on the array substrate.
  • the second electrode material layer 420 is laser etched to remove the material layer 420 that is not shielded by the shielding portion 140 , the first electrode 210 and the electrode contact 220 .
  • the second electrode material layer 420, the remaining second electrode material layer 420 forms the second electrode layer 410, and the second electrode layer 410 has a hollow area.
  • the orthographic projection of the second electrode layer 410 on the array substrate 100 covers the orthographic projection of the first electrode 210, the electrode contact 220, and the shielding portion 140 on the array substrate 100, and the second electrode layer 410 in each electrode unit
  • the electrode layer 410 is a whole.
  • the hollowed out area of the second electrode layer 410 is directly opposite to the gap between the first electrode 210, and no electrode contact 220 is arranged in the space directly opposite to the hollowed out area, so as to ensure that the electrode contact 220 is directly opposite to the second electrode layer.
  • 410 communicates with the second electrode layer 410 opposite to the first electrode 210 .
  • the laser when laser etching the second electrode material layer 420, the laser is located below the array substrate 100, that is, the laser is irradiated from bottom to top.
  • the wavelength of the laser light can be set to a specific value
  • the second electrode material layer 420 has a higher absorption rate of the laser light of this wavelength
  • the other film layers have a lower absorption rate of the laser light of this wavelength, so as to further prevent other film layers from being damaged. .
  • the shielding part 140 in the embodiment of the present application is arranged in the array substrate 100, and in some other possible embodiments, the shielding part 140 can also be a shield between the first electrode layer and the second electrode layer 410.
  • Support Pad SPC
  • SPC Support Pad
  • the second electrode layer with a hollow part is formed by laser etching the second electrode material layer 420 using the shielding part 140, the first electrode 210 and the electrode contact 220 as a mask 410, reducing the area of the second electrode layer 410, so that there is a space in the second electrode layer 410 for external light to pass through, increasing the external light received by the camera module, thereby improving the shooting effect of the camera module.
  • a plurality of first electrodes 210 and electrode contacts 220 are arranged on the same layer, so that the wires connected to the first electrodes 210 and the wires connected to the electrode contacts 220 can be made on the same layer, which simplifies the process and reduces the cost of the display panel. Difficulty of preparation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供一种显示面板及其制作方法，涉及显示技术领域。显示面板的第一电极层包括同层设置的电极触点和多个第一电极，相邻两个第一电极之间设置有间隔，相邻的第一电极与电极触点之间设置有间隔；阵列基板内的遮挡部与第一电极和电极触点之间的间隔相对，第一电极和电极触点在阵列基板上的正投影与遮挡部在阵列基板上的正投影相邻接或至少部分重合；第二电极层与电极触点接触，第二电极层具有镂空区，第二电极层在阵列基板上的正投影覆盖第一电极、电极触点、遮挡部在阵列基板上的正投影。镂空区可供外界光线穿过，提高摄像头模组的拍摄效果，且电极触点与多个第一电极同层设置，降低显示面板制作难度。

Description

显示面板及其制作方法
本申请要求于2021年6月18日提交中国专利局、申请号为202110680227.5、申请名称为“显示面板及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及其制作方法。
背景技术
有机发光显示面板(Organic Light Emitting Diode，简称OLED)具有自发光、快速响应、宽视角和可制作在柔性基板上等多种特点，越来越多地被应用于高性能显示领域如柔性显示装置中。
为了提高显示面板的屏占比，通常将摄像头模组等功能器件设置在显示面板的下方。一种实现方式中，阴极层为整层结构，通过导线将阴极层连接公共电位。采用这种结构的阴极层，阴极层易于制作，导线制作简单，显示面板的制作难度较低，但阴极层的透光率较低，导致摄像头模组的拍摄效果较差。另一种实现方式中，阴极层包括多个阴极，采用这种结构的阴极层，阴极层的透光率较好，摄像头模组的拍摄效果好，但阴极层的制作难度较高，且阴极层中的每个阴极均需连接有导线，导线制作复杂，进而导致显示面板的制作难度较高。
发明内容
鉴于上述问题，本申请实施例提供一种显示面板及其制作方法，用于改善摄像头模组的拍摄效果的同时，降低显示面板的制作难度。
为了实现上述目的，本申请实施例提供如下技术方案：
本申请实施例的第一方面提供一种显示面板，其包括：层叠设置的阵列基板、第一电极层、中间层和第二电极层，所述第一电极层包括同层设置的电极触点和多个第一电极，相邻两个所述第一电极之间设置有间隔，且相邻的所述第一电极与所述电极触点之间设置有间隔；所述阵列基板内设置有遮挡部，所述遮挡部与所述第一电极和所述电极触点之间的所述间隔相对，且所述第一电极和所述电极触点在所述阵列基板上的正投影与所述遮挡部在所述阵列基板上的正投影相邻接或者至少部分重合；所述第二电极层与所述电极触点相接触，所述第二电极层具有镂空区，且所述第二电极层在所述阵列基板上的正投影覆盖所述第一电极、所述电极触点，以及所述遮挡部在所述阵列基板上的正投影。
本申请实施例提供的显示面板中，第二电极层中设置有镂空区，镂空区可供外界光线进入，降低了第二电极层对外界光线的阻挡，增加了摄像头模组接收的外界光线，从而提高摄像头模组的拍摄效果。同时，阵列基板中的遮挡部与第一电极与电极触点之间的间隔相对，且第一电极和电极触点在阵列基板上的正投影与遮挡部在阵列基板上的正投影相邻 接或者至少部分重合，使得第一电极、电极触点与遮挡部在阵列基板上的正投影连成一体，第二电极层在阵列基板上的正投影覆盖第一电极、电极触点，以及遮挡部在阵列基板上的正投影，从而使得位于电极触点上方的第二电极层与位于第一电极上方的第二电极层相连通，且第二电极层与电极触点相接触，以实现第二电极层与电极触点电连接，从而可以使显示面板正常发光，同时由于第一电极和电极触点同层设置，使得与第一电极连接的导线以及与电极触点连接的导线可以同层制作，简化了工艺，从而降低了显示面板的制作难度。
本申请实施例的第二方面提供一种显示面板的制作方法，其包括：
提供阵列基板，所述阵列基板内设置有遮挡部；
在所述阵列基板上形成第一电极层，所述第一电极层包括同层设置的电极触点和多个第一电极，相邻两个所述第一电极之间设置有间隔，且相邻的所述第一电极与所述电极触点之间设置有间隔，所述第一电极和所述电极触点之间的所述间隔与所述遮挡部正对应，所述第一电极和所述电极触点在所述阵列基板上的正投影与所述遮挡部在所述阵列基板上的正投影相邻接或者至少部分重合；
形成中间层，所述中间层包括形成在所述第一电极层上的像素限定层，所述像素限定层中设有与各所述第一电极对应的多个第一开口，以及与所述电极触点对应的第二开口，所述第一开口内设置有发光材料，所述第二开口暴露至少部分所述电极触点；
在所述中间层上和所述第二开口内形成第二电极材料层，所述第二电极材料层与所述电极触点相接触；
以所述遮挡部、所述第一电极和所述电极触点为掩膜，激光刻蚀所述第二电极材料层，形成第二电极层，所述第二电极层具有镂空区，且所述第二电极层在所述阵列基板上的正投影覆盖所述第一电极、所述电极触点，以及所述遮挡部在所述阵列基板上的正投影。
本申请实施例提供的显示面板的制作方法中，通过以遮挡部、第一电极和电极触点为掩膜激光刻蚀第二电极材料层，形成具有镂空区的第二电极层，减少了第二电极层的面积，使得第二电极层中存在供外界光线穿过的空间，增加了摄像头模组接收的外界光线量，从而提高摄像头模组的拍摄效果。同时由于第一电极和电极触点同层设置，使得与第一电极连接的导线以及与电极触点连接的导线可以同层制作，简化了工艺，从而降低了显示面板的制作难度。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中的显示面板的结构示意图；
图2为本申请实施例中的第一电极和电极触点的一种排布示意图；
图3为本申请实施例中的第一电极和电极触点的另一种排布示意图；
图4为本申请实施例中的显示面板的制作方法的流程图；
图5为本申请实施例中的阵列基板的结构示意图；
图6为本申请实施例中的形成第一电极层后的结构示意图；
图7为本申请实施例中的形成像素限定层后的结构示意图；
图8为本申请实施例中的形成中间层后的结构示意图；
图9为本申请实施例中的形成第二电极材料层后的结构示意图；
图10为本申请实施例中的激光刻蚀的示意图。
具体实施方式
正如背景技术所述，相关技术中的显示面板存在摄像头模组拍摄效果与显示面板制作难度难以兼顾的问题，经发明人研究发现，出现这种问题的原因在于，摄像头模组位于显示面板的下方，若采用显示面板中远离摄像头模组的阴极层为整层结构的方案，阴极层易于制作，阴极层的导线也便于引出，显示面板的制作难度较低。然而，该方案中，阴极层的透光率较低，其透光率通常低于50％，导致穿过显示面板的外界光线较少，从而导致摄像头模组接收不到足够的外界光线，摄像头模组的拍摄效果较差。
发明人还研究发现，若采用阴极层为分块结构的方案，即阴极层包括多个阴极，相邻的两个阴极之间设置有间隔，由于各阴极之间具有间隔，这些间隔形成透光区，从而可以增加穿过显示面板的外界光线，改善摄像头模组的拍摄效果。然而，该方案中，显示面板的制作难度较高，主要体现在以下两方面：
一个方面，多个阴极通常采用真空蒸镀工艺制作，该工艺所需的高精度金属掩膜板(Fine Metal Mask，简称为FMM)难以制作，具体地，高精度金属掩膜板的厚度通常为20微米，蒸镀阴极所需的开口直径也通常为20微米，在高精度金属掩膜板上制作该开口难度较高，失败率较高，导致高精度金属掩膜板的制作成本高，也增加了显示面板的制作难度和制作成本。如果采用其他方法制作阴极，通常存在阴极与阳极对准困难的问题，或者损伤发光材料的问题。
另一方面，每个阴极都需要连接到显示面板的公共电位上，以使阴极与阳极之间可以产生电位差，保证位于阴极与阳极之间的发光材料发光。但是，制作与阴极连接的导线较为复杂，也增加了显示面板的制作难度和制作成本。
针对上述技术问题，本申请实施例提供的显示面板中，阳极层和阴极层中一者包括多个电极块，另一者设置有镂空区，镂空区可供外界光线进入，降低了对外界光线的阻挡，增加了摄像头模组接收的外界光线，从而提高摄像头模组的拍摄效果。同时，整层结构的阴极层或阳极层通过电极触点与公共电位相连接，电极触点与包括多个电极块的阳极层或阴极层同层设置，使得整层结构的阴极层或阳极层所连接的导线数量较少，而且，与阴极层或阳极层连接的导线以及与电极触点连接的导线可以一起制作，简化了导线制作工艺， 因此，可以简化显示面板的制作难度和降低制作成本。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参考图1，本申请实施例提供的显示面板包括层叠设置的阵列基板100、第一电极层、中间层300和第二电极层410。阵列基板100可以为薄膜晶体管(Thin Film Transistor，简称TFT)阵列基板。阵列基板100包括衬底110、设置在衬底110上的绝缘层120，以及设置在绝缘层120上的平坦化层130(Planarization Layer，简称PLN)。
衬底110可以为玻璃衬底、柔性塑料衬底或石英衬底。衬底110的表面上设置有沿第一方向排列的多条栅极线，以及沿第二方向排列的多条数据线，栅极线与数据线的限定区域中用于定义像素单元，第一方向与第二方向交叉。薄膜晶体管的栅极与栅极线连接，薄膜晶体管的源极与数据线连接，每个薄膜晶体管的漏极与其对应的像素单元电连接。在显示过程中，薄膜晶体管在栅极线的控制下，将数据线输入的数据显示信号提供给与薄膜晶体管对应的像素单元中。
绝缘层120可以为单层或者多层结构，绝缘层120内设置有连接线，例如贯穿绝缘层120的金属线，以将薄膜晶体管与像素单元中的第一电极层(例如阳极层)电连接。
如图1所示，绝缘层120包括位于衬底110上的栅极绝缘(Gate Insulator，简称GI)层121，以及位于栅极绝缘层121上的层间绝缘(Inter Layer Dielectric，简称ILD)层122。栅极绝缘层121覆盖薄膜晶体管的源极与漏极，栅极绝缘层121上设置薄膜晶体管的栅极。栅极绝缘层121与层间绝缘层122可以通过化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺制作。栅极绝缘层121的材质包括氧化硅，层间绝缘层122的材质包括氧化硅(例如SiO2)、硼磷硅玻璃(BPSG)、磷硅盐酸玻璃(PSG)或者氮化硅(例如Si3N4)等。
平坦化层130位于阵列基板100的最上层，且平坦化层130的上表面齐平，以便于在平坦化层130上形成较为平整的各膜层。平坦化层130的材料可以为有机材料，平坦化层130可以采用涂布或者溅射工艺制作。
继续参照图1，阵列基板100内还设置有遮挡部140。在一些可能的示例中，遮挡部140设置在绝缘层120上，平坦化层130覆盖绝缘层120和设置在绝缘层120上的遮挡部140。
遮挡部140为不透光材料层，即遮挡部140不透光。示例性的，遮挡部140的材质为金属(例如银)，或者遮挡部140为黑色材料层，如包括炭黑的树脂层。遮挡部140可以为单独设置的结构，也可以为阵列基板100内的金属线，即阵列基板100内的金属线作为遮挡部140。
本申请实施例中，第一电极层可以为阳极层，第二电极层410可以为阴极层；或者，第一电极层可以为阴极层，第二电极层410可以为阳极层，下文以第一电极层为阳极层，第二电极层410为阴极层为例进行描述。
本申请实施例中的第一电极层包括第一电极210和电极触点220，第一电极210即为阳极，第一电极210和电极触点220同层设置，以便于第一电极210和电极触点220同时制作。第一电极210可以设置有多个，相邻两个第一电极210之间设置有间隔，相邻的电极触点220与第一电极210之间设置有间隔240，以避免电极触点220与第一电极210之间导通。
第一电极210和电极触点220之间的间隔与遮挡部140相正对，且第一电极210和电极触点220在阵列基板100上的正投影与遮挡部140在阵列基板100上的正投影相邻接或者至少部分重合。可以理解的是，第一电极210、电极触点220与遮挡部140在阵列基板100上的正投影连成一片。
第一电极210与电极触点220的结构和材质可以相同，进一步保证第一电极210与电极触点220可以同时制作，降低显示面板的制作难度，提高显示面板的制作效率。第一电极210与电极触点220均为不透光材料层，示例性的，第一电极210与电极触点220可以为金属层，例如银层；也可以为金属-透明材料的叠层，例如ITO-Ag-ITO层(氧化铟锡-银-氧化铟锡层)。
在上述实施例的基础上，在本申请的一些实施例中，参考图1和图2，每个第一电极210旁对应设置有一个电极触点220，即第一电极210的数量与电极触点220的数量相同，多个第一电极210与多个电极触点220一一对应。每个第一电极210与相对应的电极触点220之间的间隔240正对应一个遮挡部140。
如图2所示，第一电极210的边缘可以设置有凹陷部，电极触点220的至少部分区域位于凹陷部内，以减少第一电极210和电极触点220所占用的空间。示例性的，在平行于阵列基板100所在平面的方向上，凹陷部的截面形状均为圆弧形，电极触点220的截面形状为圆形，且凹陷部的曲率与电极触点220的曲率相同，以使第一电极210与电极触点220之间相适配。例如，第一电极210与电极触点220之间的间隔240等距。当然，凹陷部的截面形状与电极触点220的截面形状不是限定的，例如凹陷部的截面形状为折线形，电极 触点220的截面形状为三角形或者方形，凹陷部的截面形状与电极触点220的截面形状相适配。
在上述实施例的基础上，在本申请的另一些实施例中，所述第一电极层包括数个电极单元，每一电极单元包括一个电极触点220，以及与该电极触点220相邻的至少两个第一电极210，以降低电极触点220的数量，从而降低了第一电极层的制作难度。
每一电极单元中的第一电极210数量可以相同，也可以不同。例如，某些电极单元中包括两个第一电极210，另一些电极单元中包括三个第一电极210；或者，每一电极单元中都包括两个第一电极210。示例性的，如图3所示，每一电极单元包括三个第一电极210和一个电极触点220，三个第一电极210的中心分别位于虚拟三角形(图3中虚线所示)的三个顶点，电极触点220位于该虚拟三角形的内部。
在每一电极单元中，电极触点220与每个第一电极210之间的间隔240各正对应一个遮挡部140，即遮挡部140的数量与这一电极单元中的第一电极210的数量相同。例如，电极触点220的边缘与各第一电极210的边缘的距离相等，各遮挡部140沿第一电极210至电极触点220方向的宽度相等，与电极触点220与第一电极210之间的间隔240正对应的各遮挡部140相同。
在另一些实施方式中，每一电极单元中的电极触点220与第一电极210之间的间隔240正对应一个遮挡部140，即电极触点220在阵列基板100上的正投影位于遮挡部140在阵列基板100上的正投影的内部，第一电极210在阵列基板100上的正投影与遮挡部140在阵列基板100上的正投影相邻接或者至少部分重合。
需要说明的是，如图1所示，第一电极210的下方设置有第一导线250，第一导线250位于第一电极210和阵列基板100之间，第一导线250将第一电极210电连接驱动电位。电极触点220的下方设置有第二导线230，第二导线230位于电极触点220和阵列基板100之间，第二导线230将电极触点220电连接到公共电位。第一导线250和第二导线230可以同层设置，以使第一导线250和第二导线230同时制作，简化显示面板的制作步骤。
继续参照图1，本申请实施例中的中间层300包括像素限定层310(Pixel Define Layer，简称PDL)，像素限定层310设置在第一电极层上，像素限定层310可以为氧化硅层、氮化硅层或者透明树脂层，像素限定层310可以通过等离子化学气相沉积(Plasma Chemical Vapor Deposition，PCVD)法、喷墨打印或者旋涂(Spin Coating)等工艺制作。
像素限定层310中设有多个第一开口和第二开口311，多个第一开口与多个第一电极210一一对应，第二开口311与电极触点220相对应。当电极触点220设置有多个时，第二开口311也设置有多个，多个第二开口311与多个电极触点220一一对应。第一开口和 第二开口311贯穿像素限定层310，第一开口内暴露第一电极210，第二开口311暴露至少部分电极触点220，例如，第二开口311暴露电极触点220的中心区域。
第一开口在第一电极层上的正投影位于第一电极210之中，且第一开口在第一电极层上的正投影的边缘与对应的第一电极210的边缘的距离大于2微米。如此设置，像素限定层310可以对第一电极210封边，以避免第一电极210的边缘的毛刺等结构影响第一开口内的发光材料320的正常工作。第二开口311在第一电极层的正投影位于电极触点220的内部或者与电极触点220相重合。
发光材料320可以包括红色发光材料R、绿色发光材料G和蓝色发光材料B，以发出不同颜色的光。当每一电极单元包括三个第一电极210和一个电极触点220时，在一些可能的示例中，如图3所示，这三个第一电极210各自对应的第一开口内设置的发光材料的颜色不同，即这三个第一电极210中一个第一电极210相对应的第一开口内设置有红色发光材料R，这三个第一电极210中另一个第一电极210相对应的第一开口内设置有绿色发光材料G，这三个第一电极210中最后一个第一电极210相对应的第一开口内设置有蓝色发光材料B。通过三个第一电极210共用一个电极触点220，以减少电极触点220的数量。这三个第一电极210的中心分别位于虚拟三角形的三个顶点，电极触点220位于该虚拟三角形中，且电极触点220的中心区域暴露在第二开口311中，第二开口311的中心位于虚拟三角形的中心。
在另一些可能的示例中，如图1所示，像素限定层310上还可以设置有第一公共层321，第一公共层321包括空穴注入层(Hole Injection Layer，简称HIL)和/或空穴传输层(Hole Transport Layer，简称HTL)。位于第一开口内的第一公共层321上设置有发光材料(图中未画出)，第一公共层321和发光材料上设置有第二公共层(图中未画出)，第二公共层包括电子注入层(Electron Injection Layer，简称EIL)和/或电子传输层(Electron Transport Layer，简称ETL)。
当像素限定层310上设置有第一公共层321和第二公共层时，第二开口311延伸至第一公共层321和第二公共层中，即第二开口311贯穿第一公共层321和第二公共层，以使电极触点220暴露出来，从而使得第二电极层410可以与电极触点220相接触，以实现第二电极层410与电极触点220电连接。位于第一公共层321、第二公共层和像素限定层310中的第二开口311的形状可以为阶梯形通孔，也可以为直通孔。位于第一开口内的第一电极层、第一公共层321、发光材料、第二公共层和第二电极层410构成像素单元。
继续参照图1，第二电极层410(即阴极层)与电极触点220相接触，第二电极层410通过电极触点220以及第二导线230连接到公共电位上。第二电极层410具有镂空区，镂 空区贯穿第二电极层410，以减少第二电极层410的面积，以供外界光线穿过第二电极层410，提高外界光线的进入量，从而提高摄像头模组的拍摄效果。示例性的，镂空区与第一电极210之间的间隔正对，且与镂空区正对的间隔中不设置有电极触点220，即镂空区与第一电极210和电极触点220均不正对，以保证电极触点220正对的第二电极层410和第一电极210正对的第二电极层410连通。
第二电极层410在阵列基板100上的正投影覆盖第一电极210、电极触点220，以及遮挡部140在阵列基板100上的正投影，即位于第一电极210上方的第二电极层410与位于电极触点220上的第二电极层410相连通。在第一电极210的正投影范围内的第二电极层410可以通过电极触点220连接到公共电位，以保证显示面板可以正常工作。
示例性的，第二电极层410在阵列基板100上的正投影与第一电极210、电极触点220，以及遮挡部140在阵列基板100上的正投影相重合，以进一步减少第二电极层410的面积，提高外界光线的进入量。
在一些可能的示例中，如图3所示，第二电极层410包括多个第二电极，第二电极即为阴极，每个阴极与一个电极单元中的第一电极210和电极触点220相对应。与一个电极单元中的第一电极210和电极触点220相对的阴极为一体结构，即对应于一个电极单元的至少两个像素单元共用一个阴极，阴极与电极触点220相接触，以降低电极触点220的数量。
第二电极层410的材质可以包括金属，例如银、镁银合金、铝中的一种或者多种。第二电极层410可以通过以第一电极210、电极触点220和遮挡部140为掩膜，激光刻蚀形成。刻蚀时，激光聚焦于第二电极层410，以避免损伤其他膜层。此外，激光的波长为特定值，以使第二电极层410对该波长的激光的吸收率较高，其他膜层对该波长的激光的吸收率较低，进一步避免损伤其他膜层。
本申请实施例提供的显示面板中，第二电极层410中设置有镂空区，镂空区可供外界光线进入，降低了第二电极层410对外界光线的阻挡，增加了摄像头模组接收的外界光线，从而提高摄像头模组的拍摄效果。同时，阵列基板100中的遮挡部140与第一电极210与电极触点220之间的间隔相对，且第一电极210和电极触点220在阵列基板100上的正投影与遮挡部140在阵列基板100上的正投影相邻接或者至少部分重合，使得第一电极210、电极触点220与遮挡部140在阵列基板100上的正投影连成一体，第二电极层410在阵列基板100上的正投影覆盖第一电极210、电极触点220与遮挡部140在阵列基板100上的正投影，从而使得位于电极触点220上方的第二电极层410与位于第一电极210上方的第二电极层410相连通，且第二电极层410与电极触点220相接触，以实现第二电极层410 与电极触点220电连接，从而可以使显示面板正常发光。同时由于第一电极210和电极触点220同层设置，使得与第一电极210连接的导线以及与电极触点220连接的导线可以同层制作，简化了工艺，从而降低了显示面板的制作难度，降低了显示面板的制作难度。
本申请实施例还提供一种显示面板的制作方法，如图4所示，该显示面板的制作方法包括以下步骤：
步骤S101、提供阵列基板，阵列基板内设置有遮挡部。
参考图5，阵列基板100可以为TFT阵列基板，该阵列基板100包括衬底110、设置在衬底110上的绝缘层120，以及设置在绝缘层120上的平坦化层130。
衬底110的表面上设置有沿第一方向排列的多条栅极线，以及沿第二方向排列的多条数据线，栅极线与数据线的限定区域中用于定义像素单元，第一方向与第二方向交叉。薄膜晶体管的栅极与栅极线连接，薄膜晶体管的源极与数据线连接，每个薄膜晶体管的漏极与其对应的像素单元电连接；在显示过程中，薄膜晶体管在栅极线的控制下，将数据线输入的数据显示信号提供给与薄膜晶体管对应的像素单元中。
绝缘层120可以为单层或者多层结构，绝缘层120内设置有连接线，例如贯穿绝缘层120的金属线，以将薄膜晶体管与第一电极层电连接。示例性的，绝缘层120包括位于衬底110上的栅极绝缘层121，以及位于栅极绝缘层121上的层间绝缘层122。栅极绝缘层121覆盖薄膜晶体管的源极与漏极，栅极绝缘层121上设置有薄膜晶体管的栅极。
平坦化层130一般位于阵列基板100的最上层，平坦化层130的上表面齐平，以便于在平坦化层130上形成较为平整的各膜层。平坦化层130的材料可以为有机材料，平坦化层130可以采用涂布或者溅射工艺制作。
阵列基板100内还设置有遮挡部140。遮挡部140可以设置在绝缘层120上，平坦化层130覆盖绝缘层120和设置在绝缘层120上的遮挡部140。遮挡部140为不透光材料层，即遮挡部140不透光。示例性的，遮挡部140的材质为金属(例如银)，或者遮挡部140为黑色材料层，如包括炭黑的树脂层。遮挡部140可以为单独设置的结构，也可以为阵列基板100内的金属线，即阵列基板100内的金属线作为遮挡部140。
步骤S102、在阵列基板上形成第一电极层，第一电极层包括同层设置的电极触点220和多个第一电极210，相邻两个第一电极210之间设置有间隔，且相邻的第一电极210与电极触点220之间设置有间隔，第一电极210和电极触点220之间的间隔与遮挡部140正对应，第一电极210和电极触点220在阵列基板上的正投影与遮挡部140在阵列基板上的正投影相邻接或者至少部分重合。
参照图6，示例性的，通过在阵列基板100上沉积第一电极材料，再通过激光刻蚀等 工艺刻蚀第一电极材料，以同时形成多个第一电极210和电极触点220。第一电极材料为不透光材料，第一电极材料可以为金属，例如银；也可以为金属-透明材料的叠层，例如ITO-Ag-ITO的叠层。
如图6所示，第一电极210(例如为阳极)可以为多个，相邻两个第一电极210之间设置有间隔，相邻的电极触点220与第一电极210之间设置有间隔，且该间隔(如图6中虚线所示空间)与遮挡部140正对应。第一电极210和电极触点220在阵列基板100上的正投影与遮挡部140在阵列基板100上的正投影相邻接或者至少部分重合，即第一电极210、电极触点220与遮挡部140在阵列基板100上的正投影连成一片。
在本申请的一些实施例中，如图2所示，每个第一电极210旁对应设置有一个电极触点220，且每个第一电极210与对应的电极触点220之间的间隔正对应一个遮挡部140。第一电极210的边缘可以设置有凹陷部，电极触点220的至少部分区域位于凹陷部内，以减少第一电极210和电极触点220所占用的空间。
在本申请的另一些实施例中，第一电极层包括数个电极单元，每一电极单元包括相邻的至少两个第一电极210以及位于这些第一电极210之间的一个电极触点220，以降低电极触点220的数量，降低第一电极层的制作难度。示例性的，如图3所示，每一电极单元包括三个第一电极210和一个电极触点220，三个第一电极210的中心分别位于虚拟三角形的三个顶点，电极触点220位于虚拟三角形的内部。在每一电极单元中，电极触点220与每个第一电极210之间的间隔各正对应一个遮挡部140，即遮挡部140的数量与这一电极单元中的第一电极210的数量相同。
需要说明的是，如图6所示，第一电极210的下方设置有第一导线250，第一导线250位于第一电极210和阵列基板100之间，第一导线250将第一电极210电连接驱动电位。电极触点220的下方设置有第二导线230，第二导线230位于电极触点220和阵列基板100之间，第二导线230将电极触点220电连接到公共电位。第一导线250和第二导线230可以同层设置，以使第一导线250和第二导线230同时制作，简化显示面板的制作步骤。
步骤S103、形成中间层，中间层包括形成在第一电极层上的像素限定层，像素限定层中设有与各第一电极210对应的多个第一开口，以及与电极触点220对应的第二开口，第一开口内设置有发光材料，第二开口暴露至少部分电极触点220。
参照图7，通过等离子化学气相沉积法、喷墨打印或者旋涂等工艺在第一电极层上形成像素限定材料层，再对像素限定材料层进行图形化工艺形成贯穿像素限定材料层的第一开口312和第二开口311，具有第一开口312和第二开口311的像素限定材料层形成像素限定层310。
其中，第一开口312的数量为多个，多个第一开口312与多个第一电极210一一对应，且第一开口312内暴露第一电极210，第二开口311与电极触点220相对应，且第二开口311暴露至少部分电极触点220。当电极触点220设置有多个时，第二开口311也设置有多个，且多个第二开口311与多个电极触点220一一对应。第一开口312在第一电极层上的正投影位于第一电极210之中，且第一开口312在第一电极层上的正投影的边缘与对应的第一电极210的边缘的距离大于2微米。第二开口311在第一电极层的正投影位于电极触点220的内部或者与电极触点220相重合。
在本申请一些可能的示例中，参照图8，形成像素限定层310后，在像素限定层310、第一开口312和第二开口311内形成第一公共层321，第一公共层321包括空穴注入层和/或空穴传输层；再在位于第一开口312内的第一公共层321上蒸镀发光材料；在第一公共层321和发光材料上形成第二公共层，第二公共层包括电子注入层和/或电子传输层；激光刻蚀去除位于第二开口311内的至少部分第一公共层321和第二公共层，以暴露电极触点220。
需要说明的是，当每一电极单元包括三个第一电极210和一个电极触点220时，如图3所示，这三个第一电极210相对应的第一开口312分别对应红色发光材料R、绿色发光材料G和蓝色发光材料B，且这三个第一电极210的中心分别位于虚拟三角形的三个顶点，第二开口311的中心位于该虚拟三角形的中心。
步骤S104、在中间层上和第二开口311内形成第二电极材料层，第二电极材料层与电极触点220相接触。
示例性的，在第二公共层上和第二开口311内形成第二电极材料层420，如图9所示，第二电极材料层420为整层结构。第二电极材料层420覆盖第二公共层，且与电极触点220相接触，以使第二电极材料层420与电极触点220电连接。第二电极材料层420的材质可以为金属，例如为银、镁银合金、铝中的一种或者多种。
步骤S105、以遮挡部140、第一电极210和电极触点220为掩膜，激光刻蚀第二电极材料层，形成第二电极层410，第二电极层410具有镂空区，且第二电极层410在阵列基板上的正投影覆盖第一电极210、电极触点220，以及遮挡部140在阵列基板上的正投影。
参照图10，以遮挡部140、第一电极210和电极触点220为掩膜，激光刻蚀第二电极材料层420，去除未被遮挡部140、第一电极210和电极触点220遮挡的第二电极材料层420，保留的第二电极材料层420形成第二电极层410，第二电极层410具有镂空区。
可以理解的是，第二电极层410在阵列基板100上的正投影覆盖第一电极210、电极触点220，以及遮挡部140在阵列基板100上的正投影，每一电极单元中的第二电极层410 为一个整体。第二电极层410的镂空区与第一电极210之间的间隙正对，且与镂空区正对的间隔中不设置有电极触点220，以保证电极触点220正对的第二电极层410和第一电极210正对的第二电极层410连通。
如图10所示，激光刻蚀第二电极材料层420时，激光位于阵列基板100的下方，即激光由下向上照射，通过将激光聚焦于第二电极材料层420，可以避免其他膜层受到损伤。此外，激光的波长可以设定为特定值，第二电极材料层420对该波长的激光的吸收率较高，其他膜层对该波长的激光的吸收率较低，进一步避免其他膜层受到损伤。
需要说明的是，本申请实施例中的遮挡部140设置在阵列基板100中，在另一些可能的实施例中，遮挡部140还可以为位于第一电极层与第二电极层410之间的支撑垫(SPC)，该支撑垫不透光。如此设置，利用显示面板本身所具有的结构，无需额外制作遮挡部140。
本申请实施例提供的显示面板的制作方法中，通过以遮挡部140、第一电极210和电极触点220为掩膜激光刻蚀第二电极材料层420，形成具有镂空部的第二电极层410，减少了第二电极层410的面积，使得第二电极层410中存在供外界光线穿过的空间，增加摄像头模组接收的外界光线，从而提高摄像头模组的拍摄效果。同时，多个第一电极210和电极触点220同层设置，使得与第一电极210连接的导线以及与电极触点220连接的导线可以同层制作，简化了工艺，从而降低了显示面板的制备难度。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种显示面板，包括层叠设置的阵列基板、第一电极层、中间层和第二电极层，所述第一电极层包括同层设置的电极触点和多个第一电极，相邻两个所述第一电极之间设置有间隔，且相邻的所述第一电极与所述电极触点之间设置有间隔；
    所述阵列基板内设置有遮挡部，所述遮挡部与所述第一电极和所述电极触点之间的所述间隔相对，且所述第一电极和所述电极触点在所述阵列基板上的正投影与所述遮挡部在所述阵列基板上的正投影相邻接或者至少部分重合；
    所述第二电极层与所述电极触点相接触，所述第二电极层具有镂空区，且所述第二电极层在所述阵列基板上的正投影覆盖所述第一电极、所述电极触点，以及所述遮挡部在所述阵列基板上的正投影。
  2. 根据权利要求1所述的显示面板，其中，所述镂空区与相邻的所述第一电极之间的间隔正对应，且与所述镂空区正对的所述间隔中不设置有所述电极触点。
  3. 根据权利要求1或2所述的显示面板，其中，每个所述第一电极旁对应设置有一个所述电极触点，且每个所述第一电极与对应的所述电极触点之间的间隔，正对应一个所述遮挡部。
  4. 根据权利要求3所述的显示面板，其中，所述第一电极的边缘设置有凹陷部，所述电极触点的至少部分区域位于所述凹陷部内。
  5. 根据权利要求4所述的显示面板，其中，所述凹陷部的截面形状为圆弧形，所述电极触点的截面形状为圆形，且所述凹陷部的曲率与所述电极触点的曲率相同。
  6. 根据权利要求1或2所述的显示面板，其中，所述第一电极层包括数个电极单元，每一所述电极单元包括一个所述电极触点，以及与所述电极触点相邻的至少两个所述第一电极，且位于每一所述第一电极单元中的所述电极触点与每个所述第一电极之间的间隔各正对应一个所述遮挡部。
  7. 根据权利要求6所述的显示面板，其中，所述中间层包括设置在所述第一电极层上的像素限定层，所述像素限定层中设有与各所述第一电极对应的多个第一开口，以及与各所述电极触点对应的多个第二开口，所述第一开口中设置有发光材料，所述第二开口暴露至少部分所述电极触点。
  8. 根据权利要求7所述的显示面板，其中，所述第一开口在所述第一电极层上的正投影位于所述第一电极之中，且所述第一开口在所述第一电极层上的正投影的边缘与对应的所述第一电极的边缘的距离大于2微米。
  9. 根据权利要求7所述的显示面板，其中，所述发光材料包括红色发光材料、绿色发光材料和蓝色发光材料；
    每一所述电极单元包括三个所述第一电极和一个所述电极触点，且三个所述第一电极各自对应的所述第一开口中设置的所述发光材料的颜色不同。
  10. 根据权利要求9所述的显示面板，其中，三个所述第一电极的中心分别位于虚拟三角形的三个顶点；
    所述第二开口的中心位于所述虚拟三角形的中心。
  11. 根据权利要求1或2所述的显示面板，其中，所述阵列基板包括层叠设置的衬底、绝缘层和平坦化层；
    所述遮挡部设置在所述绝缘层和所平坦化层之间。
  12. 根据权利要求1或2所述的显示面板，其中，所述第一电极层和所述阵列基板之间还设置有第一导线和第二导线，所述第一导线和所述第二导线同层设置，所述第一导线与所述第一电极相接触，以将所述第一电极电连接驱动电位，所述第二导线与所述电极触点相接触，以将所述电极触点电连接公共电位。
  13. 根据权利要求1所述的显示面板，其中，所述第一电极、所述电极触点和所述遮挡部的材料均为不透光材料，所述第二电极层的材质包括金属。
  14. 一种显示面板的制作方法，包括：
    提供阵列基板，所述阵列基板内设置有遮挡部；
    在所述阵列基板上形成第一电极层，所述第一电极层包括同层设置的电极触点和多个第一电极，相邻两个所述第一电极之间设置有间隔，且相邻的所述第一电极与所述电极触点之间设置有间隔，所述第一电极和所述电极触点之间的所述间隔与所述遮挡部正对应，所述第一电极和所述电极触点在所述阵列基板上的正投影与所述遮挡部在所述阵列基板上的正投影相邻接或者至少部分重合；
    形成中间层，所述中间层包括形成在所述第一电极层上的像素限定层，所述像素限定层中设有与各所述第一电极对应的多个第一开口，以及与所述电极触点对应的第二开口，所述第一开口内设置有发光材料，所述第二开口暴露至少部分所述电极触点；
    在所述中间层上和所述第二开口内形成第二电极材料层，所述第二电极材料层与所述电极触点相接触；
    以所述遮挡部、所述第一电极和所述电极触点为掩膜，激光刻蚀所述第二电极材料层，形成第二电极层，所述第二电极层具有镂空区，且所述第二电极层在所述阵列基板上的正投影覆盖所述第一电极、所述电极触点，以及所述遮挡部在所述阵列基板上的正投影。
  15. 根据权利要求14所述的显示面板的制作方法，其中，所述第一电极、所述电极触点和所述遮挡部的材料均为不透光材料，所述第二电极层的材质包括金属。
  16. 根据权利要求15所述的显示面板的制作方法，其中，所述第二电极层的材质为银、镁银合金或者铝。
PCT/CN2022/084646 2021-06-18 2022-03-31 显示面板及其制作方法 WO2022262367A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020237020667A KR20230101925A (ko) 2021-06-18 2022-03-31 디스플레이 패널 및 그 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110680227.5A CN113421904B (zh) 2021-06-18 2021-06-18 显示面板及其制作方法
CN202110680227.5 2021-06-18

Publications (1)

Publication Number Publication Date
WO2022262367A1 true WO2022262367A1 (zh) 2022-12-22

Family

ID=77789321

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/084646 WO2022262367A1 (zh) 2021-06-18 2022-03-31 显示面板及其制作方法

Country Status (3)

Country Link
KR (1) KR20230101925A (zh)
CN (1) CN113421904B (zh)
WO (1) WO2022262367A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113421904B (zh) * 2021-06-18 2024-02-13 合肥维信诺科技有限公司 显示面板及其制作方法
CN114400239B (zh) * 2021-12-21 2023-04-07 昆山国显光电有限公司 显示面板、显示装置及显示面板的制备方法
CN115132749B (zh) * 2022-06-28 2023-05-02 昆山国显光电有限公司 阵列基板及显示面板
CN115295592A (zh) * 2022-08-09 2022-11-04 昆山国显光电有限公司 显示面板、显示装置及显示面板的制备方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020058420A1 (en) * 2000-11-14 2002-05-16 Joo Hyeon Lee Method for manufacturing cathode electrodes of electroluminescent display device
CN104885251A (zh) * 2012-12-28 2015-09-02 乐金显示有限公司 透明的有机发光显示装置及其制造方法
CN105552107A (zh) * 2016-02-29 2016-05-04 上海天马有机发光显示技术有限公司 一种显示面板、制作方法以及电子设备
CN106876331A (zh) * 2017-03-03 2017-06-20 武汉华星光电技术有限公司 Oled显示面板及其制备方法、显示装置
CN108470749A (zh) * 2018-03-07 2018-08-31 深圳市华星光电半导体显示技术有限公司 显示面板及其制造方法
CN110854290A (zh) * 2019-10-29 2020-02-28 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法
CN111952481A (zh) * 2020-08-25 2020-11-17 湖北长江新型显示产业创新中心有限公司 显示面板及电子设备
CN112635693A (zh) * 2021-01-05 2021-04-09 Tcl华星光电技术有限公司 一种阵列基板及其制备方法
CN113421904A (zh) * 2021-06-18 2021-09-21 合肥维信诺科技有限公司 显示面板及其制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013125436A1 (ja) * 2012-02-20 2013-08-29 株式会社カネカ 有機ｅｌ装置及び有機ｅｌ装置の製造方法
KR20160099979A (ko) * 2015-02-13 2016-08-23 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
CN205645814U (zh) * 2016-03-15 2016-10-12 上海天马微电子有限公司 一种有机发光显示面板
KR101918146B1 (ko) * 2018-04-27 2018-11-13 셀로코아이엔티 주식회사 인셀 터치표시장치 및 그 제조방법
CN209119108U (zh) * 2018-12-12 2019-07-16 武汉华星光电技术有限公司 一种oled显示器

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020058420A1 (en) * 2000-11-14 2002-05-16 Joo Hyeon Lee Method for manufacturing cathode electrodes of electroluminescent display device
CN104885251A (zh) * 2012-12-28 2015-09-02 乐金显示有限公司 透明的有机发光显示装置及其制造方法
CN105552107A (zh) * 2016-02-29 2016-05-04 上海天马有机发光显示技术有限公司 一种显示面板、制作方法以及电子设备
CN106876331A (zh) * 2017-03-03 2017-06-20 武汉华星光电技术有限公司 Oled显示面板及其制备方法、显示装置
CN108470749A (zh) * 2018-03-07 2018-08-31 深圳市华星光电半导体显示技术有限公司 显示面板及其制造方法
CN110854290A (zh) * 2019-10-29 2020-02-28 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法
CN111952481A (zh) * 2020-08-25 2020-11-17 湖北长江新型显示产业创新中心有限公司 显示面板及电子设备
CN112635693A (zh) * 2021-01-05 2021-04-09 Tcl华星光电技术有限公司 一种阵列基板及其制备方法
CN113421904A (zh) * 2021-06-18 2021-09-21 合肥维信诺科技有限公司 显示面板及其制作方法

Also Published As

Publication number Publication date
CN113421904B (zh) 2024-02-13
KR20230101925A (ko) 2023-07-06
CN113421904A (zh) 2021-09-21

Similar Documents

Publication Publication Date Title
WO2022262367A1 (zh) 显示面板及其制作方法
JP6585322B1 (ja) 有機ｅｌ表示装置及びその製造方法
CN100595943C (zh) 顶部发射型有机发光显示器件及其制造方法
US11289669B2 (en) Light-emitting device, pixel unit, manufacturing method for pixel unit and display device
WO2021254058A1 (zh) 显示基板及其制备方法、显示装置
WO2021254059A1 (zh) 显示基板及其制备方法、显示装置
US11081680B2 (en) Pixel structure, method for forming the same, and display screen
WO2020042806A1 (zh) 显示基板、显示装置及显示基板的制造方法
WO2020233284A1 (zh) 显示面板及其制作方法、显示装置
WO2022222436A1 (zh) 显示面板及其制造方法、显示装置
US20230006178A1 (en) Display panel, display apparatus, and method for manufacturing display panel
US11183111B2 (en) Pixel unit and method for manufacturing the same, and double-sided OLED display device
CN110211994B (zh) 阵列基板及其制造方法、有机发光二极管显示器
WO2022048010A1 (zh) 显示面板及其制作方法
US20230006011A1 (en) Display panel and manufacturing method therefor, and display device
CN110660839A (zh) 一种显示面板及其制备方法
WO2020239071A1 (zh) 显示基板及其制作方法、显示面板和显示装置
CN114284458B (zh) 显示基板及其制作方法、显示面板
WO2021184235A1 (zh) 一种阵列基板及其制备方法和显示面板
CN113053924A (zh) 显示基板及其制备方法、显示装置
CN110459586B (zh) 一种阵列基板和显示面板
WO2021012399A1 (zh) 显示面板、显示装置及其制作方法
WO2021017106A1 (zh) 阵列基板及采用该阵列基板的制备方法、显示装置
WO2021164132A1 (zh) 有机发光二极管显示器及其制造方法
WO2023184609A1 (zh) 有机发光二极管显示面板及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22823858

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20237020667

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE