WO2022048010A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2022048010A1
WO2022048010A1 PCT/CN2020/127815 CN2020127815W WO2022048010A1 WO 2022048010 A1 WO2022048010 A1 WO 2022048010A1 CN 2020127815 W CN2020127815 W CN 2020127815W WO 2022048010 A1 WO2022048010 A1 WO 2022048010A1
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WIPO (PCT)
Prior art keywords
anode
display panel
array substrate
layer
isolation unit
Prior art date
Application number
PCT/CN2020/127815
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English (en)
French (fr)
Inventor
唐甲
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/972,027 priority Critical patent/US20220077250A1/en
Publication of WO2022048010A1 publication Critical patent/WO2022048010A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/818—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/852—Arrangements for extracting light from the devices comprising a resonant cavity structure, e.g. Bragg reflector pair
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a manufacturing method thereof.
  • Top-emitting OLED Organic Light
  • OLED Organic Light
  • the control of the cavity length of the OLED device the cavity length generally refers to the direct distance from the reflective electrode at the bottom of the anode to the cathode. Due to the influence of the microcavity effect, the luminous efficiency of each sub-pixel (sub-pixel) and the position of the wave are not optimized, especially the position accuracy of the light beam is greatly affected, resulting in low life and efficiency of the OLED device.
  • the anode structure in top-emitting OLED devices is composed of a reflective electrode and an anode (the material is ITO) covering the reflective electrode, and the reflective electrode and the anode are made of a mask, and the anode is generally a low-thickness ITO film ( The thickness is 150A), it is difficult to adjust the cavity length depending on the thickness of the OLED organic material itself, so the thickness of the anode on the anode structure plays an important role in the adjustment of the cavity length.
  • the device efficiency is the best when the thickness of the anode is about 800A.
  • scheme one thicken the anode (ITO material) to 800A
  • scheme two add a transparent spacer (Spacer) between the anode (ITO material) and the reflective electrode, the spacer
  • the materials include silicon oxide or other transparent organic materials.
  • the anode is formed by an etching process, and the anode of ITO material is thickened (for example, thickened to more than 400A), which is easy to crystallize, which is easy to cause etching residues, especially when the anode material is deposited on the metal reflective electrode (the material is generally On Ag or Al), the crystallization is more serious, resulting in failure to etch normally;
  • exposure and development process or chemical vapor deposition (Chemical Vapor Deposition) needs to be introduced for the patterning of the gasket. Vapor Deposition, CVD) and etching process, etc., the process is complicated, which is not conducive to mass production.
  • the present application provides a display panel and a manufacturing method thereof.
  • the two adjacent first anodes can be naturally disconnected, and the thickness of the first anode can be adjusted through the thickness of the first anode.
  • the present application provides a display panel, including:
  • a plurality of reflective electrodes located on the array substrate and distributed in an array
  • isolation units a plurality of isolation units; wherein, one of the isolation units is arranged between any two adjacent reflective electrodes;
  • an anode layer comprising a first anode on each of the reflective electrodes and a second anode on a side of each of the isolation units away from the array substrate;
  • a light-emitting functional layer located on the first anode
  • each of the first anodes is separated from the adjacent second anodes by the isolation unit.
  • the width of the isolation unit gradually increases in the direction of the array substrate toward the second anode, and the upper surface of the isolation unit is on the positive side of the array substrate.
  • the projection completely covers the orthographic projection of the lower surface of the isolation unit on the array substrate.
  • the shape of the cross section of the isolation unit in the direction perpendicular to the array substrate is an inverted trapezoid.
  • the cross section includes two oblique sides arranged oppositely; the included angle between each of the oblique sides and the upper surface of the array substrate is greater than or equal to 45° and less than or equal to 45° 60°.
  • the thickness of the isolation unit is greater than the sum of the thicknesses of the reflective electrode and the first anode.
  • the thickness of the first anode is greater than or equal to 800A; the thickness of the isolation unit is greater than or equal to 1 ⁇ m.
  • the display panel further includes a pixel definition layer covering the upper surface and the side surface of each of the second anodes.
  • the pixel definition layer also partially covers the first anode and the reflective electrode to form a pixel opening, and the light-emitting functional layer is located in the pixel opening.
  • the material of the anode layer includes indium tin oxide.
  • the first anode and the second anode are made of the same material and have the same thickness.
  • the array substrate includes a base substrate, a buffer layer disposed on the base substrate, and a buffer layer disposed on the buffer layer and connected to the plurality of reflective electrodes in a one-to-one correspondence of multiple thin film transistors.
  • the present application also provides a method for manufacturing a display panel, comprising the following steps:
  • An anode layer is covered on the array substrate formed with the reflective electrodes and the isolation units, so as to form a first anode on each of the reflective electrodes and a first anode located on the side of each of the isolation units away from the array substrate a second anode; wherein the first anode is spaced apart from the second anode by the isolation unit; and
  • a light-emitting functional layer is formed on the first anode.
  • the width of the isolation unit gradually increases in the direction of the array substrate toward the second anode, and the upper surface of the isolation unit is on the array substrate.
  • the orthographic projection of the upper surface completely covers the orthographic projection of the lower surface of the isolation unit on the array substrate.
  • the shape of the cross section of the isolation unit in the direction perpendicular to the array substrate is an inverted trapezoid.
  • the cross section includes two oblique sides arranged oppositely; the included angle between each of the oblique sides and the upper surface of the array substrate is greater than or equal to 45° and less than or equal to 60°.
  • the thickness of the isolation unit is greater than the sum of the thicknesses of the reflective electrode and the first anode.
  • the thickness of the first anode is greater than or equal to 800A; the thickness of the isolation unit is greater than or equal to 1 ⁇ m.
  • the forming a light-emitting functional layer on the first anode includes the following steps:
  • pixel definition layer covering the upper surface and side surface of each of the second anodes; wherein the pixel definition layer also partially covers the first anode and the reflective electrode to form pixel openings;
  • a light-emitting functional layer is formed on the first anode located in the pixel opening.
  • the material of the anode layer includes indium tin oxide.
  • the first anode and the second anode are made of the same material and have the same thickness.
  • the present application by arranging an isolation unit between any two adjacent reflective electrodes, when the anode layer is formed on the array substrate on which the isolation unit and the reflective electrode are formed, the reflective The first anode on the electrode and the second anode on the isolation unit, and the first anode and the second anode are naturally separated by the isolation unit, so that any two adjacent first anodes are also naturally separated by the isolation unit Therefore, the present application can directly form a first anode with a large thickness and spaced apart without using an etching process when making the anode layer, which is beneficial to adjust the thickness of the OLED device in the display panel through the thickness of the first anode.
  • the embodiment of the present application avoids using an etching process to pattern an anode layer with a large thickness, thereby avoiding the problem of etching residues, It is beneficial to improve product yield; on the other hand, the embodiment of the present application avoids setting a spacer between the anode layer and the reflective electrode to adjust the cavity length of the light-emitting device, which simplifies the manufacturing process and is beneficial to improving production efficiency, that is, it is beneficial to mass production.
  • FIG. 1 is a schematic diagram of a partial cross-sectional structure of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic partial cross-sectional structure diagram of another display panel according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a method for fabricating a display panel according to an embodiment of the present application.
  • FIG. 4 a is a schematic partial cross-sectional structural diagram of an array substrate formed with reflective electrodes according to an embodiment of the present application.
  • FIG. 4b is a schematic diagram of a partial cross-sectional structure of an isolation unit formed on the basis of FIG. 4a.
  • FIG. 4c is a schematic diagram of a partial cross-sectional structure of an anode layer formed on the basis of FIG. 4b.
  • FIG. 4d is a schematic diagram of a partial cross-sectional structure of a pixel definition layer formed on the basis of FIG. 4c.
  • FIG. 4e is a schematic diagram of a partial cross-sectional structure of a light-emitting functional layer formed on the basis of FIG. 4d.
  • FIG. 4f is a partial cross-sectional structural schematic diagram of forming a cathode layer and an encapsulation layer on the basis of FIG. 4e.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • an embodiment of the present application provides a top-emitting display panel 1, the display panel 1 includes an array substrate 2, a plurality of reflective electrodes 3, a plurality of isolation units 4, an anode layer 5, a pixel definition layer 6, Light-emitting functional layer 7 and cathode layer 8 .
  • a plurality of reflective electrodes 3 are located on the array substrate 2 and are distributed in an array, and an isolation unit 4 is arranged between any two adjacent reflective electrodes 3 ;
  • the anode layer 5 includes a first The anode 9 and the second anode 10 located on the side of each isolation unit 4 away from the array substrate 2, and each first anode 9 and the adjacent second anode 10 are spaced apart by the isolation unit 4;
  • the light-emitting functional layer 7 is located on the first anode 9
  • the anode 9 is used for light-emitting display;
  • the cathode layer 8 is located on the side of the light-emitting functional layer 7 away from the first anode 9 .
  • each first anode 9 and the light-emitting functional layer 7 and the cathode layer 8 disposed on the first anode 9 constitute an OLED device
  • the cavity length of each OLED device is the distance between the reflective electrode 3 and the cathode layer 8 Spacing L.
  • the array substrate 2 includes a base substrate 11, a buffer layer 12 disposed on the base substrate 11, a plurality of thin film transistors 13 disposed on the buffer layer 12 and connected to the plurality of reflective electrodes 3 in a one-to-one correspondence, and The passivation layer 14 and the planarization layer 15 on the plurality of thin film transistors 13 .
  • Each thin film transistor 13 includes a semiconductor unit 16 (ie, a channel layer) disposed on the buffer layer 12 , a doping unit 17 (ie, an ohmic contact layer) disposed on the buffer layer 12 and located on both sides of the semiconductor unit 16 (ie, an ohmic contact layer)
  • the gate insulating unit 18 on the semiconductor unit 16, the gate 19 provided on the gate insulating unit 18, the interlayer insulating layer covering the buffer layer 12, the doping unit 17, the gate insulating unit 18 and the gate 19 20, and the source electrode 21 and the drain electrode 22 arranged on the interlayer insulating layer 20; 17 corresponds to the connection. As shown in FIG.
  • the gate electrode 19 ′, the source electrode 21 ′ and the drain electrode 22 ′ are arranged in the same layer, which can save an interlayer insulating layer;
  • the semiconductor unit 16 (ie, the channel layer) on the buffer layer 12 , the doping unit 17 (ie, the ohmic contact unit) disposed on the buffer layer 12 and located on both sides of the semiconductor unit 16 is disposed on the buffer layer 12 and the semiconductor unit 16 and the gate insulating layer 23 on the doped unit 17, the gate electrode 19', the source electrode 21' and the drain electrode 22' are arranged on the gate insulating layer 23 and are spaced apart from each other; wherein the source electrode 21' and the drain electrode are 22' are respectively located on both sides of the gate 19', the gate 19' is disposed corresponding to the semiconductor unit 16, and the source 21' and the drain 22' are respectively connected to both sides of the semiconductor unit 16 through two through holes penetrating the interlayer insulating layer 20.
  • the doping unit 17 is correspondingly connected.
  • the present application does not limit the specific type and structure of the thin film transistor 13 in the array substrate 2 , and the embodiment of the present application uses the structure of the thin film transistor 13 shown in FIG. 1 as an example to illustrate.
  • the array substrate 2 further includes a plurality of light shielding (LS) units 24 disposed between the base substrate 11 and the buffer layer 12 and corresponding to the plurality of thin film transistors 13 one-to-one.
  • the orthographic projection of each shading unit 24 on the base substrate 11 completely covers the orthographic projection of the corresponding semiconductor unit 16 in the thin film transistor 13 and the doping units 17 located on both sides of the semiconductor unit 16 on the base substrate 11 .
  • the light shielding unit 24 is used to protect the channel layer of the thin film transistor 13 from being affected by light, so as to avoid the phenomenon of light-induced leakage current.
  • the light shielding unit 24 further extends to be disposed corresponding to the source electrode 21 , and is connected to the source electrode 21 through a through hole passing through the buffer layer 12 and the interlayer insulating layer 20 (or the gate insulating layer 23 ).
  • the material of the semiconductor unit 16 includes IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide).
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • the material of the semiconductor unit 16 is not limited here.
  • the array substrate 2 includes a display area for displaying pictures and a non-display area located at the periphery of the display area (only part of the structure in the display area is shown in the drawings).
  • a plurality of thin film transistors 13 are located in the display area, corresponding to , a plurality of reflective electrodes 3 and anode layers 5 are located in the display area.
  • the material of the reflective electrode 3 includes metals or alloys such as Ag, Al, etc., which are used to reflect the light emitted by the light-emitting functional layer 7 in a direction away from the array substrate 2 to realize top emission.
  • Each reflective electrode 3 is connected to the source electrode 21 of the corresponding thin film transistor 13 through a through hole penetrating the planarization layer 15 and the passivation layer 14 .
  • the source electrode 21 and the drain electrode 22 of each thin film transistor 13 can be interchanged.
  • each reflective electrode 3 penetrates through the flat layer 15 and the passivation layer 14 The through-holes are connected to the drains of the corresponding thin film transistors 13 .
  • the material of the isolation unit 4 is an electrical insulating material; the width d of the isolation unit 4 increases gradually in the direction of the array substrate 2 toward the second anode 10 , and the orthographic projection of the upper surface of the isolation unit 4 on the array substrate 2 It completely covers the orthographic projection of the lower surface of the isolation unit 4 on the array substrate 2; it should be noted that the upper surface of the isolation unit 4 refers to the surface of the isolation unit 4 away from the side of the array substrate 2, and the lower surface of the isolation unit 4 refers to the isolation unit 4. The unit 4 is close to the surface on the side of the array substrate 2 . Also, the thickness h of the isolation unit 4 is greater than the sum of the thicknesses of the reflective electrode 3 and the first anode 9 .
  • the shape of the cross section of the isolation unit 4 in the direction perpendicular to the array substrate 2 is an inverted trapezoid; the cross section includes two oblique sides arranged oppositely;
  • the angle is ⁇ , wherein the included angle ⁇ is less than or equal to 60°, and the smaller the included angle ⁇ , the better the isolation effect of the isolation unit 4 on the anode layer 5; in one embodiment, in order to ensure the stability of the isolation unit 4 structure , the included angle ⁇ is greater than or equal to 45° and less than or equal to 60°.
  • the isolation unit 4 is an inverted trapezoid or an inverted trapezoid-like structure, and the thickness h of the isolation unit 4 is greater than the sum of the thicknesses of the reflective electrode 3 and the first anode 9 , the distance between the side surface of the isolation unit 4 and the upper surface of the reflective electrode 3 is The included angle is an acute angle, and there is a discontinuity with a height greater than the thickness of the anode layer 5 between the isolation unit 4 and the reflective electrode 3;
  • the anode layer 5 is formed by sputtering, since the angle between the side surface of the isolation unit 4 and the upper surface of the reflective electrode 3 is an acute angle, the formation of an anode layer on the side surface of the isolation unit 4 is avoided, thereby avoiding the formation of an anode layer on the side surface of the reflective electrode 3.
  • the first anode 9 and the second anode 10 located on the side of the isolation unit 4 away from the array substrate 2 are connected through the side surface of the isolation unit 4, and the disconnection between the isolation unit 4 and the reflective electrode 3 makes the first anode 9 and the
  • the distance between the two anodes 10 in the direction perpendicular to the array substrate 2 further prevents the first anode 9 on the reflective electrode 3 from being connected to the second anode 10 on the side of the isolation unit 4 away from the array substrate 2. Therefore, this application
  • the isolation structure 4 in the embodiment can naturally break the anode layer 5 into a plurality of first anodes 9 and second anodes 10 that are not connected to each other.
  • the material of the anode layer 5 includes indium tin oxide (ITO); the first anode 9 and the second anode 10 are made of the same material and have the same thickness; wherein the first anode 9 is the anode electrode of the light-emitting functional layer 7 .
  • ITO indium tin oxide
  • the first anode 9 and the second anode 10 are made of the same material and have the same thickness; wherein the first anode 9 is the anode electrode of the light-emitting functional layer 7 .
  • ITO indium tin oxide
  • the first anode 9 and the second anode 10 are made of the same material and have the same thickness; wherein the first anode 9 is the anode electrode of the light-emitting functional layer 7 .
  • any one of the first anodes 9 is connected to the orthographic projection of the adjacent second anode 10 on the array substrate 2 , or partially overlaps. Through the isolation unit 4, any two adjacent first anodes 9 are also naturally spaced apart
  • the thickness of the first anode 9 is greater than or equal to 800A (Angstrom); and the thickness h of the isolation unit 4 is greater than or equal to 1 um (micrometer).
  • the cavity length of the OLED device can be regulated by the thickness of the first anode 9 to improve the luminous efficiency, luminescence spectral accuracy and device life; that is, the thickness of the first anode 9 can be adjusted according to the cavity length of the OLED device It needs to be adjusted to avoid setting a spacer between the anode layer 5 and the reflective electrode 3 to adjust the cavity length of the light-emitting device.
  • the bottom of the isolation unit 4 is located on the flat layer 15 exposed by the two adjacent reflective electrodes 3, and the isolation unit 4 is partially covered on the two adjacent reflective electrodes 3; the first anode 9 is located on the adjacent two reflective electrodes 3.
  • the corresponding reflective electrode 3 is not connected (not in contact) with the adjacent isolation unit 4, and since the bottom width of the isolation unit 4 is smaller than the top width, each isolation unit 4 is connected to the adjacent first anode 9 and the reflective electrode.
  • An undercut opening 25 is formed between 3 .
  • the pixel definition layer 6 covers the upper surface and side surface of each second anode 10, and partially covers the first anode 9 and the reflective electrode 3 to form the pixel opening 27; the light-emitting functional layer 7 is located in the pixel opening 27 middle. It will be appreciated that the pixel definition layer 6 also fills in each of the undercut openings 25 . That is to say, the pixel definition layer 6 wraps around the outer surfaces of the second anode 10 and the isolation unit 4 , and partially covers the edges of the first anode 9 and the reflective electrode 3 , so that the pixel definition layer 6 surrounds the first anode 9 . A pixel opening 27 is formed.
  • the pixel definition layer 6 is wrapped around the outer surface of the second anode 10 to prevent the conductive second anode 10 from electrically connecting two adjacent light-emitting functional layers 7 , thereby ensuring that the display panel 1 can display normally and improving the life of the device.
  • the materials of the pixel definition layer 6 and the isolation unit 4 may be the same, which, of course, is not limited in this application.
  • the light-emitting functional layer 7 includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer that are sequentially arranged on each of the first anodes 9;
  • the light-emitting functional layer 7 can be made of an organic ink material, Evaporation type organic materials can also be used; correspondingly, they can be formed by inkjet printing technology or by evaporation technology.
  • the material of the pixel definition layer 6 is a hydrophobic material; when the light-emitting functional layer 7 in the display panel 1 is formed by an evaporation technique, the pixel definition layer The material of 6 may be a non-hydrophobic material.
  • the display panel 1 may be an RGB-OLED display panel, that is, the light-emitting layers in different light-emitting functional layers 7 may emit red light, green light and blue light respectively, so as to realize full-color display;
  • the display panel 1 may be a W-OLED display panel, that is, all the light-emitting layers in the light-emitting functional layers 7 emit white light, and the display panel 1 further includes a color filter corresponding to each OLED device, for full color display.
  • the cathode layer 8 can be laid in a whole layer to reduce the difficulty of the process; the present application does not limit the specific structure of the cathode layer 8 .
  • the display panel 1 further includes an encapsulation layer 26 located on the cathode layer 8 to prevent water and oxygen from outside from entering the OLED device, and can protect the OLED device.
  • the reflective electrode 3 can be formed
  • the first anode 9 and the second anode 10 located on the isolation unit 4, and the first anode 9 and the second anode 10 are naturally separated by the isolation unit, so that any adjacent two first anodes 9 also pass through
  • the isolation units 4 are naturally spaced apart. Therefore, the present application can directly form the first anode 9 with a large thickness and spaced apart without using an etching process when fabricating the anode layer 5, which is beneficial to pass the thickness of the first anode 9.
  • the embodiment of the present application avoids the use of an etching process for the anode layer 5 with a relatively large thickness. patterning, thereby avoiding the problem of etching residues and improving product yield; on the other hand, the embodiment of the present application avoids setting a spacer between the anode layer 5 and the reflective electrode 3 to adjust the cavity length of the light-emitting device, simplifying the Therefore, it is beneficial to improve the production efficiency, that is, it is beneficial to mass production.
  • an embodiment of the present application further provides a manufacturing method of a display panel 1 , including steps S301 to S305 .
  • Step S301 Provide an array substrate.
  • the array substrate 2 includes a base substrate 11, a buffer layer 12 disposed on the base substrate 11, a plurality of thin film transistors 13 disposed on the buffer layer 12, and a plurality of thin film transistors disposed on the buffer layer 12 Passivation layer 14 and planarization layer 15 on 13 .
  • Each thin film transistor 13 includes a semiconductor unit 16 (ie, a channel layer) disposed on the buffer layer 12 , a doping unit 17 (ie, an ohmic contact layer) disposed on the buffer layer 12 and located on both sides of the semiconductor unit 16 (ie, an ohmic contact layer)
  • the gate insulating unit 18 on the semiconductor unit 16, the gate 19 provided on the gate insulating unit 18, the interlayer insulating layer covering the buffer layer 12, the doping unit 17, the gate insulating unit 18 and the gate 19 20, and the source electrode 21 and the drain electrode 22 arranged on the interlayer insulating layer 20; 17 corresponds to the connection.
  • each thin film transistor includes a semiconductor unit (ie, a channel layer) arranged on the buffer layer.
  • the doping unit ie ohmic contact unit
  • the gate insulating layer arranged on the buffer layer, the semiconductor unit and the doped unit, arranged on the gate insulating layer and mutually
  • the gate electrode, the source electrode and the drain electrode are arranged at intervals; wherein, the source electrode and the drain electrode are respectively located on both sides of the gate electrode, the gate electrode is arranged corresponding to the semiconductor unit, and the source electrode and the drain electrode pass through two through holes penetrating the interlayer insulating layer They are respectively connected to the doping units on both sides of the semiconductor unit correspondingly.
  • the array substrate 2 further includes a plurality of shading units 24 disposed between the base substrate 11 and the buffer layer 12 and corresponding to the plurality of thin film transistors 13 one-to-one.
  • each shading unit 24 The orthographic projection of the unit 24 on the base substrate 11 completely covers the orthographic projection of the corresponding semiconductor unit 16 in the thin film transistor 13 and the doping units 17 located on both sides of the semiconductor unit 16 on the base substrate 11 .
  • the light shielding unit 24 is used to protect the channel layer of the thin film transistor 13 from being affected by light, so as to avoid the phenomenon of light-induced leakage current.
  • the light shielding unit 24 further extends to be disposed corresponding to the source electrode 21 , and is connected to the source electrode 21 through a through hole passing through the buffer layer 12 and the interlayer insulating layer 20 .
  • the material of the semiconductor unit 16 includes IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide).
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • the material of the semiconductor unit 16 is not limited here.
  • Step S302 forming a plurality of reflective electrodes distributed in an array on the array substrate.
  • step S302 includes the following steps:
  • a layer of reflective film is deposited on the array substrate by PVD (Physical Vapor Deposition) process;
  • the reflective film is patterned by a photolithography process to form a plurality of reflective electrodes distributed in an array.
  • the plurality of reflective electrodes 3 are connected to the plurality of thin film transistors 13 in the array substrate 2 in a one-to-one correspondence;
  • the source 21 of the thin film transistor 13 is connected.
  • the source electrode 21 and the drain electrode 22 of each thin film transistor 13 can be interchanged.
  • each reflective electrode 3 penetrates through the flat layer 15 and the passivation layer 14 The through-holes are connected to the drains of the corresponding thin film transistors 13 .
  • the material of the reflective electrode 3 includes metals or alloys such as Ag, Al, etc., which are used to reflect the light emitted by the light-emitting functional layer 7 in a direction away from the array substrate 2 to realize top emission.
  • Step S303 forming an isolation unit between any two adjacent reflective electrodes.
  • the material of the isolation unit is an electrical insulating material; as shown in FIG. 4b , the width d of the isolation unit 4 gradually increases in the direction of the array substrate 2 toward the reflective electrode 3 , and the upper surface of the isolation unit 4 is on the array substrate 2 .
  • the orthographic projection on the upper surface completely covers the orthographic projection of the lower surface of the isolation unit 4 on the array substrate 2; it should be noted that the upper surface of the isolation unit 4 refers to the surface of the isolation unit 4 away from the array substrate 2 side, and the lower surface of the isolation unit 4 The surface refers to the surface of the isolation unit 4 on the side close to the array substrate 2 .
  • the shape of the cross section of the isolation unit 4 in the direction perpendicular to the array substrate 2 is an inverted trapezoid; the cross section includes two oblique sides arranged oppositely;
  • the angle is ⁇ , wherein the included angle ⁇ is less than or equal to 60°, and the smaller the included angle ⁇ , the better the isolation effect of the isolation unit 4 on the anode layer 5; in one embodiment, in order to ensure the stability of the isolation unit 4 structure , the included angle ⁇ is greater than or equal to 45° and less than or equal to 60°.
  • the bottom of the isolation unit 4 is located on the flat layer 15 exposed by the two adjacent reflective electrodes 3 , and the isolation unit 4 partially covers the two adjacent reflective electrodes 3 .
  • Step S304 Covering an anode layer on the array substrate formed with the reflective electrodes and the isolation units to form a first anode on each reflective electrode and a second anode on the side of each isolation unit away from the array substrate; An anode is separated from the second anode by an isolation unit.
  • the anode layer 5 includes a first anode 9 located on each reflective electrode 3 and a second anode 10 located on the side of each isolation unit 4 away from the array substrate 2;
  • the material includes indium tin oxide (ITO); the anode layer 5 can be formed by an evaporation process or a sputtering process. It should be noted that when the anode layer 5 is formed by the evaporation process, the anode layer 5 is disconnected at the isolation unit 4 to form the first layer. An anode 9 and a second anode 10 work better.
  • the thickness h of the isolation unit 4 is greater than the sum of the thicknesses of the reflective electrode 3 and the first anode 9 . Since the isolation unit 4 is an inverted trapezoid or an inverted trapezoid-like structure, and the thickness h of the isolation unit 4 is greater than the sum of the thicknesses of the reflective electrode 3 and the first anode 9 , the distance between the side surface of the isolation unit 4 and the upper surface of the reflective electrode 3 is The included angle is an acute angle, and there is a discontinuity with a height greater than the thickness of the anode layer 5 between the isolation unit 4 and the reflective electrode 3; When the anode layer 5 is formed by sputtering, since the angle between the side surface of the isolation unit 4 and the upper surface of the reflective electrode 3 is an acute angle, the formation of an anode layer on the side surface of the isolation unit 4 is avoided, thereby avoiding the formation of an anode layer on the
  • the first anode 9 and the second anode 10 located on the side of the isolation unit 4 away from the array substrate 2 are connected through the side surface of the isolation unit 4, and the disconnection between the isolation unit 4 and the reflective electrode 3 makes the first anode 9 and the
  • the distance between the two anodes 10 in the direction perpendicular to the array substrate 2 further prevents the first anode 9 on the reflective electrode 3 from being connected to the second anode 10 on the side of the isolation unit 4 away from the array substrate 2. Therefore, this application
  • the isolation structure 4 in the embodiment can naturally disconnect the anode layer 5 into a plurality of first anodes 9 and second anodes 10 that are not connected to each other.
  • the first anode 9 and the second anode 10 are made of the same material and have the same thickness; wherein, the first anode 9 is an anode electrode of the light-emitting functional layer. It can be understood that any one of the first anodes 9 is connected to the orthographic projection of the adjacent second anode 10 on the array substrate 2 , or partially overlaps. Through the isolation unit 4, any two adjacent first anodes 9 are also naturally spaced apart. Therefore, the patterning of the anode layer 5 does not require an etching process, which avoids the problem of etching residues or difficulty in etching.
  • the thickness of the first anode 9 is greater than or equal to 800A (Angstrom); and the thickness h of the isolation unit 4 is greater than or equal to 1 um (micrometer).
  • the thickness of the first anode 9 can be adjusted according to the requirements of the cavity length of the OLED device, avoiding setting a spacer between the anode layer 5 and the reflective electrode 3 to adjust the cavity length of the light-emitting device.
  • the first anode 9 is located on the corresponding reflective electrode 3 and is not connected (not in contact) with the adjacent isolation unit 4, and since the bottom width of the isolation unit 4 is smaller than the top width, each isolation unit 4 is adjacent to the An undercut opening 25 is formed between the first anode 9 and the reflective electrode 3 .
  • the array substrate 2 includes a display area for displaying images and a non-display area located at the periphery of the display area (only part of the structure in the display area is shown in the drawings).
  • the non-display area can be Shading is performed to prevent the anode layer 5 from being formed in the non-display area, causing the metal layer in the non-display area to be short-circuited, etc.
  • the area of the non-display area is relatively large, and the shading of the non-display area will not affect the aperture ratio of the display panel 1 .
  • Step S305 forming a light-emitting functional layer on the first anode.
  • step S305 includes the following steps:
  • a pixel definition layer 6 is formed covering the upper and side surfaces of each second anode 10; wherein the pixel definition layer 6 also partially covers the first anode 9 and the reflective electrode 3 to form pixel openings 27;
  • the light-emitting functional layer 7 is formed on the first anode 9 located in the pixel opening 27 .
  • the pixel definition layer 6 is also filled in each of the undercut openings 25 . That is to say, the pixel definition layer 6 wraps around the outer surfaces of the second anode 10 and the isolation unit 4 , and partially covers the edges of the first anode 9 and the reflective electrode 3 , so that the pixel definition layer 6 surrounds the first anode 9 .
  • a pixel opening 27 is formed.
  • the pixel definition layer 6 is wrapped around the outer surface of the second anode 10 to prevent the conductive second anode 10 from electrically connecting two adjacent light-emitting functional layers 7 , thereby ensuring that the display panel 1 can display normally and improving the life of the device.
  • the light-emitting functional layer 7 includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer that are sequentially arranged on each of the first anodes 9;
  • the light-emitting functional layer 7 can be made of an organic ink material, Evaporation type organic materials can also be used; correspondingly, they can be formed by inkjet printing technology or by evaporation technology.
  • the material of the pixel definition layer 6 is a hydrophobic material; when the light-emitting functional layer 7 in the display panel 1 is formed by an evaporation technique, the pixel definition layer The material of 6 may be a non-hydrophobic material.
  • the display panel 1 may be an RGB-OLED display panel, that is, the light-emitting layers in different light-emitting functional layers 7 may emit red light, green light and blue light respectively, so as to realize full-color display;
  • the display panel 1 may be a W-OLED display panel, that is, all the light-emitting layers in the light-emitting functional layers 7 emit white light, and the display panel 1 further includes a color filter corresponding to each OLED device, for full color display.
  • the manufacturing method of the display panel 1 further includes the following steps:
  • a cathode layer 8 is formed on the array substrate 2 on which the pixel definition layer 6 and the light-emitting functional layer 7 are formed;
  • An encapsulation layer 26 is formed on the cathode layer 8 .
  • the cathode layer 8 can be laid in the whole layer to reduce the difficulty of the process; each first anode 9 and the light-emitting functional layer 7 and the cathode layer 8 disposed on the first anode 9 constitute an OLED device, and each OLED device
  • the cavity length is the distance L between the reflective electrode 3 and the cathode layer 8 .
  • the encapsulation layer 26 can prevent external water and oxygen from entering the OLED device, and can protect the OLED device.
  • the isolation unit 4 by disposing the isolation unit 4 between any two adjacent reflective electrodes 3 , when the anode layer 5 is formed on the array substrate 2 on which the isolation unit and the reflective electrode 3 are formed, the reflective electrode 3 can be formed on the anode layer 5 .
  • the first anode 9 and the second anode 10 located on the isolation unit 4, and the first anode 9 and the second anode 10 are naturally separated by the isolation unit, so that any adjacent two first anodes 9 also pass through
  • the isolation units 4 are naturally spaced apart. Therefore, the present application can directly form the first anode 9 with a large thickness and spaced apart without using an etching process when fabricating the anode layer 5, which is beneficial to pass the thickness of the first anode 9.
  • the embodiment of the present application avoids the use of an etching process for the anode layer 5 with a larger thickness. patterning, thereby avoiding the problem of etching residues and improving product yield; on the other hand, the embodiment of the present application avoids setting a spacer between the anode layer 5 and the reflective electrode 3 to adjust the cavity length of the light-emitting device, simplifying the The production process is improved, which is conducive to improving production efficiency, that is, it is conducive to mass production.
  • a display panel and a manufacturing method thereof provided by the embodiments of the present application have been described in detail above.
  • the principles and implementations of the present application are described with specific examples in this article.
  • the technical solution of the application and its core idea; those of ordinary skill in the art should understand that: it can still make modifications to the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements,
  • the essence of the corresponding technical solutions does not deviate from the scope of the technical solutions of the embodiments of the present application.

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Abstract

公开一种显示面板及其制作方法，显示面板包括阵列基板、位于阵列基板上且呈阵列分布的多个反射电极、设置在任意相邻的两个反射电极之间的隔离单元、包括位于反射电极上的第一阳极以及位于隔离单元远离阵列基板一侧的第二阳极的阳极层、以及位于第一阳极上的发光功能层；每个第一阳极与相邻的第二阳极通过隔离单元间隔开。

Description

显示面板及其制作方法 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及其制作方法。
 背景技术
顶发光OLED（Organic Light Emitting Diode，有机发光二极管）器件的发光效率及发光波长准确控制一直是OLED器件研发的难题。影响OLED器件的发光效率及发光波长准确控制的主要因素之一是：OLED器件腔长的控制（腔长一般指阳极底部的反射电极至阴极的直接距离）。由于微腔效应的影响，各子像素（sub-pixel）的发光效率及波普位置均不是最佳化，尤其对出光波普的位置精度影响较大，导致OLED器件的寿命和效率较低。
目前顶发光OLED器件中的阳极结构由反射电极和覆盖在反射电极上的阳极（材料为ITO）构成，且反射电极与阳极通过一张光罩制成，阳极一般为低膜厚的ITO膜（厚度为150A），依靠OLED有机材料的本身厚度来调节腔长比较困难，因此阳极结构上的阳极的厚度对腔长的调节有着重要作用。通过器件最佳效率的模拟可知，当阳极的厚度约为800A时器件效率最佳。
目前腔长的调节主要有两种方案：方案一，将阳极（ITO材料）加厚至800A；方案二，在阳极（ITO材料）与反射电极之间增加透明的垫片（Spacer），垫片的材料包括氧化硅或其他透明有机材料。但是，对于方案一，阳极通过刻蚀工艺形成，ITO材质的阳极加厚（例如加厚至400A以上）易结晶，易造成刻蚀残留，特别是当阳极材料沉积在金属反射电极（材料一般是Ag或Al）上时，结晶更加严重，导致无法正常刻蚀；对于方案二，对垫片图形化需要引入曝光显影制程或化学气相沉积（Chemical Vapor Deposition，CVD）和刻蚀制程等，制程复杂，不利于量产。
 技术问题
本申请提供一种显示面板及其制作方法，通过在相邻的两个反射电极之间设置隔离单元，可以自然的将相邻的两个第一阳极断开，且可以通过第一阳极的厚度来调节器件腔长，解决了厚度较大的阳极层难刻蚀的问题，同时解决了在阳极层和反射电极之间设置垫片调节器件腔长导致的工艺复杂的问题。
 技术解决方案
第一方面，本申请提供一种显示面板，包括：
阵列基板；
多个反射电极，位于所述阵列基板上且呈阵列分布；
多个隔离单元；其中，任意相邻的两个所述反射电极之间设置一所述隔离单元；
阳极层，包括位于每个所述反射电极上的第一阳极以及位于每个所述隔离单元远离所述阵列基板一侧的第二阳极；
发光功能层，位于所述第一阳极上；
其中，每个所述第一阳极与相邻的所述第二阳极通过所述隔离单元间隔开。
在本申请所提供的显示面板中，所述隔离单元的宽度在所述阵列基板朝向所述第二阳极的方向上逐渐增大，且所述隔离单元的上表面在所述阵列基板上的正投影完全覆盖所述隔离单元的下表面在所述阵列基板上的正投影。
在本申请所提供的显示面板中，所述隔离单元在垂直于所述阵列基板方向上的截面的形状为倒梯形。
在本申请所提供的显示面板中，所述截面包括相对设置的两个斜边；每个所述斜边与所述阵列基板的上表面之间的夹角大于或等于45°且小于或等于60°。
在本申请所提供的显示面板中，所述隔离单元的厚度大于所述反射电极和所述第一阳极的厚度之和。
在本申请所提供的显示面板中，所述第一阳极的厚度大于或等于800A；所述隔离单元的厚度大于或等于1um。
在本申请所提供的显示面板中，所述显示面板还包括覆盖在每个所述第二阳极的上表面和侧表面的像素定义层。
在本申请所提供的显示面板中，所述像素定义层还部分覆盖在所述第一阳极和所述反射电极上以形成像素开口，且所述发光功能层位于所述像素开口中。
在本申请所提供的显示面板中，所述阳极层的材料包括氧化铟锡。
在本申请所提供的显示面板中，所述第一阳极和所述第二阳极的材料相同且厚度相同。
在本申请所提供的显示面板中，所述阵列基板包括衬底基板、设置在所述衬底基板上缓冲层、以及设置在所述缓冲层上且与所述多个反射电极一一对应连接的多个薄膜晶体管。
第二方面，本申请还提供一种显示面板的制作方法，包括以下步骤：
提供阵列基板；
在所述阵列基板上形成呈阵列分布的多个反射电极；
在任意相邻的两个反射电极之间形成隔离单元；
在形成有所述反射电极和所述隔离单元的阵列基板上覆盖阳极层，以形成位于每个所述反射电极上的第一阳极和位于每个所述隔离单元远离所述阵列基板一侧的第二阳极；其中，所述第一阳极与所述第二阳极通过所述隔离单元间隔开；以及
在所述第一阳极上形成发光功能层。
在本申请所提供的显示面板的制作方法中，所述隔离单元的宽度在所述阵列基板朝向所述第二阳极的方向上逐渐增大，且所述隔离单元的上表面在所述阵列基板上的正投影完全覆盖所述隔离单元的下表面在所述阵列基板上的正投影。
在本申请所提供的显示面板的制作方法中，所述隔离单元在垂直于所述阵列基板方向上的截面的形状为倒梯形。
在本申请所提供的显示面板的制作方法中，所述截面包括相对设置的两个斜边；每个所述斜边与所述阵列基板的上表面之间的夹角大于或等于45°且小于或等于60°。
在本申请所提供的显示面板的制作方法中，所述隔离单元的厚度大于所述反射电极和所述第一阳极的厚度之和。
在本申请所提供的显示面板的制作方法中，所述第一阳极的厚度大于或等于800A；所述隔离单元的厚度大于或等于1um。
在本申请所提供的显示面板的制作方法中，所述在所述第一阳极上形成发光功能层，包括以下步骤：
形成覆盖在每个所述第二阳极的上表面和侧表面的像素定义层；其中，所述像素定义层还部分覆盖在所述第一阳极和所述反射电极上以形成像素开口；
在位于所述像素开口中所述第一阳极上形成发光功能层。
在本申请所提供的显示面板的制作方法中，所述阳极层的材料包括氧化铟锡。
在本申请所提供的显示面板的制作方法中，所述第一阳极和所述第二阳极的材料相同且厚度相同。
 有益效果
本申请提供的显示面板及其制作方法中，通过在任意相邻的两个反射电极之间设置隔离单元，使得在形成有隔离单元和反射电极的阵列基板上形成阳极层时，可以形成位于反射电极上的第一阳极和位于隔离单元上的第二阳极，且第一阳极和第二阳极通过隔离单元自然的间隔开，从而使得任意相邻的两个第一阳极也通过隔离单元自然的间隔开了，因此，本申请在制作阳极层时不需要采用刻蚀工艺就可以直接形成厚度较大且间隔设置的第一阳极，有利于通过第一阳极的厚度来调节显示面板中的OLED器件的腔长，以改善发光效率、发光光谱精度和器件寿命；由此可知，一方面，本申请实施例避免了厚度较大的阳极层采用刻蚀工艺进行图案化，从而避免了刻蚀残留问题，有利于提高产品良率；另一方面，本申请实施例避免了在阳极层和反射电极之间设置垫片来调节发光器件的腔长，简化了制作工艺，有利于提高生产效率，即有利于量产化。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的一种显示面板的部分截面结构示意图。
图2为本申请实施例提供的另一种显示面板的部分截面结构示意图。
图3为本申请实施例提供的一种显示面板的制作方法的流程示意图。
图4a为本申请实施例提供的形成有反射电极的阵列基板的部分截面结构示意图。
图4b为在图4a基础上形成隔离单元的部分截面结构示意图。
图4c为在图4b基础上形成阳极层的部分截面结构示意图。
图4d为在图4c基础上形成像素定义层的部分截面结构示意图。
图4e为在图4d基础上形成发光功能层的部分截面结构示意图。
图4f为在图4e基础上形成阴极层和封装层的部分截面结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
如图1所示，本申请实施例提供了一种顶发光的显示面板1，显示面板1包括阵列基板2、多个反射电极3、多个隔离单元4、阳极层5、像素定义层6、发光功能层7和阴极层8。其中，多个反射电极3位于阵列基板2上且呈阵列分布，且任意相邻的两个反射电极3之间设置有一个隔离单元4；阳极层5包括位于每个反射电极3上的第一阳极9以及位于每个隔离单元4远离阵列基板2一侧的第二阳极10，且每个第一阳极9与相邻的第二阳极10通过隔离单元4间隔开；发光功能层7位于第一阳极9上，用于发光显示；阴极层8位于发光功能层7远离第一阳极9的一侧。
具体的，每个第一阳极9和设置在该第一阳极9上的发光功能层7和阴极层8构成一个OLED器件，每个OLED器件的腔长为反射电极3与阴极层8之间的间距L。
具体的，阵列基板2包括衬底基板11、设置在衬底基板11上的缓冲层12、设置在缓冲层12上且与多个反射电极3一一对应连接的多个薄膜晶体管13、以及设置在多个薄膜晶体管13上的钝化层14和平坦层15。每个薄膜晶体管13包括设置在缓冲层12上的半导体单元16（即沟道层），设置在缓冲层12上且位于半导体单元16两侧的掺杂单元17（即欧姆接触层），设置在半导体单元16上的栅极绝缘单元18，设置在栅极绝缘单元18上的栅极19，覆盖在缓冲层12、掺杂单元17、栅极绝缘单元18和栅极19上的层间绝缘层20，以及设置在层间绝缘层20上的源极21和漏极22；源极21和漏极22通过贯穿层间绝缘层20的两个通孔分别与半导体单元16两侧的掺杂单元17对应连接。如图2所示，在另一实施例中，栅极19’、源极21’和漏极22’同层设置，可以节省一层层间绝缘层；具体的，每个薄膜晶体管13包括设置在缓冲层12上的半导体单元16（即沟道层），设置在缓冲层12上且位于半导体单元16两侧的掺杂单元17（即欧姆接触单元），设置在缓冲层12、半导体单元16以及掺杂单元17上的栅极绝缘层23，设置在栅极绝缘层23上且相互间隔设置的栅极19’、源极21’和漏极22’；其中，源极21’和漏极22’分别位于栅极19’的两侧，栅极19’对应半导体单元16设置，源极21’和漏极22’通过贯穿层间绝缘层20的两个通孔分别与半导体单元16两侧的掺杂单元17对应连接。
需要说明的是，本申请对阵列基板2中的薄膜晶体管13的具体类型和结构不做限制，本申请实施例以图1所示的薄膜晶体管13结构为例说明。
如图1所示，阵列基板2还包括设置在衬底基板11和缓冲层12之间且与多个薄膜晶体管13一一对应设置的多个遮光（Light Shielding，LS）单元24，具体的，每个遮光单元24在衬底基板11上的正投影完全覆盖对应的薄膜晶体管13中的半导体单元16和位于该半导体单元16两侧的掺杂单元17在衬底基板11上的正投影。遮光单元24用于保护薄膜晶体管13的沟道层不受到光照影响，避免光生漏电流现象。在另一实施例中，遮光单元24还延伸至与源极21对应设置，并通过贯穿缓冲层12和层间绝缘层20（或者栅极绝缘层23）的通孔与源极21连接。
具体的，半导体单元16的材料包括IGZO（Indium Gallium Zinc Oxide，氧化铟镓锌），当然，此处对半导体单元16的材料不做限制。
具体的，阵列基板2包括用于显示画面的显示区和位于显示区外围的非显示区（附图中仅示出显示区内的部分结构），多个薄膜晶体管13位于显示区内，对应的，多个反射电极3和阳极层5均位于显示区内。
具体的，反射电极3的材料包括Ag、Al等金属或合金，用于将发光功能层7发出的光向远离阵列基板2的方向反射，以实现顶发光。每个反射电极3通过贯穿平坦层15和钝化层14的通孔与对应的薄膜晶体管13的源极21连接。需要说明的是，本实施例中，每个薄膜晶体管13的源极21和漏极22可以互换，例如，在一实施例中，每个反射电极3通过贯穿平坦层15和钝化层14的通孔与对应的薄膜晶体管13的漏极连接。
具体的，隔离单元4的材料为电绝缘材料；隔离单元4的宽度d在阵列基板2朝向第二阳极10的方向上逐渐增大，且隔离单元4的上表面在阵列基板2上的正投影完全覆盖隔离单元4的下表面在阵列基板2上的正投影；需要说明的是，隔离单元4的上表面是指隔离单元4远离阵列基板2侧的表面，隔离单元4的下表面是指隔离单元4靠近阵列基板2侧的表面。并且，隔离单元4的厚度h大于反射电极3和第一阳极9的厚度之和。在一实施例中，隔离单元4在垂直于阵列基板2方向上的截面的形状为倒梯形；截面包括相对设置的两个斜边；每个斜边与阵列基板2的上表面之间的夹角为α，其中，夹角α小于或等于60°，且夹角α越小，隔离单元4对阳极层5的隔离效果越好；在一实施例中，为了保证隔离单元4结构的稳定性，夹角α大于或等于45°且小于或等于60°。
由于隔离单元4为倒梯形或类倒梯形结构，且隔离单元4的厚度h大于反射电极3和第一阳极9的厚度之和，使得隔离单元4的侧面与反射电极3的上表面之间的夹角为锐角，且隔离单元4与反射电极3之间存在高度大于阳极层5的厚度的断差；当在形成有反射电极3和隔离单元4的阵列基板2的显示区整层蒸镀或溅射形成阳极层5时，由于隔离单元4的侧面与反射电极3的上表面之间的夹角为锐角，避免了隔离单元4的侧面上形成有阳极层，从而避免了位于反射电极3上的第一阳极9与位于隔离单元4远离阵列基板2一侧的第二阳极10通过隔离单元4的侧面连接，并且，隔离单元4与反射电极3之间的断差使得第一阳极9与第二阳极10在垂直于阵列基板2的方向上存在间距，进一步避免了位于反射电极3上的第一阳极9与位于隔离单元4远离阵列基板2一侧的第二阳极10连接，因此，本申请实施例中的隔离结构4可以使阳极层5自然的被断开成多个相互不连接的第一阳极9和第二阳极10。
具体的，阳极层5的材料包括氧化铟锡（ITO）；第一阳极9和第二阳极10的材料相同且厚度相同；其中，第一阳极9为发光功能层7的阳极电极。可以理解的是，任意一个第一阳极9和相邻设置的第二阳极10在阵列基板2上的正投影相连接，或者部分重叠。通过隔离单元4，任意相邻的两个第一阳极9也自然间隔设置，因此，阳极层5的图案化不需要采用刻蚀工艺，避免了刻蚀残留以及刻蚀困难的问题。
在一实施例中，第一阳极9的厚度大于或等于800A（埃）；且隔离单元4的厚度h大于或等于1um（微米）。本实施例中，可以通过第一阳极9的厚度来调控OLED器件的腔长，以改善发光效率、发光光谱精度和器件寿命；也就是说，第一阳极9的厚度可以根据OLED器件的腔长需求进行调整，避免在阳极层5和反射电极3之间设置垫片来调节发光器件的腔长。
在一实施例中，隔离单元4的底部位于被相邻的两个反射电极3裸露的平坦层15上，且隔离单元4部分覆盖在相邻的两个反射电极3上；第一阳极9位于对应的反射电极3上且与相邻的隔离单元4不连接（不接触），且由于隔离单元4的底部宽度小于顶部宽度，使得每个隔离单元4与相邻的第一阳极9和反射电极3之间形成有底切（undercut）开口25。
具体的，像素定义层6覆盖在每个第二阳极10的上表面和侧表面上，且部分覆盖在第一阳极9和反射电极3上以形成像素开口27；发光功能层7位于像素开口27中。可以理解的，像素定义层6还填充在每个底切开口25中。也就是说，像素定义层6包裹在第二阳极10和隔离单元4的外表面，且部分覆盖在第一阳极9和反射电极3的边缘上，使得像素定义层6在第一阳极9上围成像素开口27。像素定义层6包裹在第二阳极10的外表面可以避免导电性的第二阳极10将相邻的两个发光功能层7电连通，从而保证显示面板1可以正常显示，提高了器件寿命。
在一实施例中，像素定义层6和隔离单元4的材料可以相同，当然，本申请对此不作限制。
具体的，发光功能层7包括依次设置在每个第一阳极9上的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层；发光功能层7可以采用有机墨水材料，也可以采用蒸镀型有机材料；对应的，可以通过喷墨打印技术形成，也可以通过蒸镀技术形成。当显示面板1中的发光功能层7采用喷墨打印技术形成时，像素定义层6的材料为疏水性的材料；当显示面板1中的发光功能层7采用蒸镀技术形成时，像素定义层6的材料可以是非疏水性的材料。
在一实施例中，显示面板1可以为RGB-OLED显示面板，也就是说，不同的发光功能层7中的发光层可以分别发红光、绿光和蓝光，以实现全彩色显示；在另一实施例中，显示面板1可以为W-OLED显示面板，也就是说，所有发光功能层7中的发光层发白光，且显示面板1还包括对应每个OLED器件设置的彩色滤光片，以实现全彩色显示。
具体的，阴极层8可以整层铺设，以减小工艺难度；本申请对阴极层8的具体结构不做限制。
具体的，显示面板1还包括位于阴极层8上的封装层26，避免外界的水氧进入OLED器件，且可以对OLED器件起到保护作用。
本实施例中，通过在任意相邻的两个反射电极3之间设置隔离单元4，使得在形成有隔离单元和反射电极3的阵列基板2上形成阳极层5时，可以形成位于反射电极3上的第一阳极9和位于隔离单元4上的第二阳极10，且第一阳极9和第二阳极10通过隔离单元自然的间隔开，从而使得任意相邻的两个第一阳极9也通过隔离单元4自然的间隔开了，因此，本申请在制作阳极层5时不需要采用刻蚀工艺就可以直接形成厚度较大且间隔设置的第一阳极9，有利于通过第一阳极9的厚度来调节显示面板1中的OLED器件的腔长，以改善发光效率、发光光谱精度和器件寿命；由此可知，一方面，本申请实施例避免了厚度较大的阳极层5采用刻蚀工艺进行图案化，从而避免了刻蚀残留问题，有利于提高产品良率；另一方面，本申请实施例避免了在阳极层5和反射电极3之间设置垫片来调节发光器件的腔长，简化了制作工艺，有利于提高生产效率，即有利于量产化。
如图3、图4a至图4f所示，本申请实施例还提供了一种显示面板1的制作方法，包括步骤S301至步骤S305。
步骤S301：提供阵列基板。
具体的，如图4a所示，阵列基板2包括衬底基板11、设置在衬底基板11上的缓冲层12、设置在缓冲层12上的多个薄膜晶体管13、以及设置在多个薄膜晶体管13上的钝化层14和平坦层15。每个薄膜晶体管13包括设置在缓冲层12上的半导体单元16（即沟道层），设置在缓冲层12上且位于半导体单元16两侧的掺杂单元17（即欧姆接触层），设置在半导体单元16上的栅极绝缘单元18，设置在栅极绝缘单元18上的栅极19，覆盖在缓冲层12、掺杂单元17、栅极绝缘单元18和栅极19上的层间绝缘层20，以及设置在层间绝缘层20上的源极21和漏极22；源极21和漏极22通过贯穿层间绝缘层20的两个通孔分别与半导体单元16两侧的掺杂单元17对应连接。
在另一实施例中，栅极、源极和漏极同层设置，可以节省一层层间绝缘层；具体的，每个薄膜晶体管包括设置在缓冲层上的半导体单元（即沟道层），设置在缓冲层上且位于半导体单元两侧的掺杂单元（即欧姆接触单元），设置在缓冲层、半导体单元以及掺杂单元上的栅极绝缘层，设置在栅极绝缘层上且相互间隔设置的栅极、源极和漏极；其中，源极和漏极分别位于栅极的两侧，栅极对应半导体单元设置，源极和漏极通过贯穿层间绝缘层的两个通孔分别与半导体单元两侧的掺杂单元对应连接。
具体的，如图4a所示，阵列基板2还包括设置在衬底基板11和缓冲层12之间且与多个薄膜晶体管13一一对应设置的多个遮光单元24，具体的，每个遮光单元24在衬底基板11上的正投影完全覆盖对应的薄膜晶体管13中的半导体单元16和位于该半导体单元16两侧的掺杂单元17在衬底基板11上的正投影。遮光单元24用于保护薄膜晶体管13的沟道层不受到光照影响，避免光生漏电流现象。在另一实施例中，遮光单元24还延伸至与源极21对应设置，并通过贯穿缓冲层12和层间绝缘层20的通孔与源极21连接。
具体的，半导体单元16的材料包括IGZO（Indium Gallium Zinc Oxide，氧化铟镓锌），当然，此处对半导体单元16的材料不做限制。
步骤S302：在阵列基板上形成呈阵列分布的多个反射电极。
具体的，步骤S302包括以下步骤：
采用PVD（物理气相沉积）工艺在阵列基板上沉积一层反射膜；
采用光刻（Photo etch）工艺对反射膜进行图形化处理，以形成呈阵列分布的多个反射电极。
具体的，如图4a所示，多个反射电极3与阵列基板2中的多个薄膜晶体管13一一对应连接；每个反射电极3通过贯穿平坦层15和钝化层14的通孔与对应的薄膜晶体管13的源极21连接。需要说明的是，本实施例中，每个薄膜晶体管13的源极21和漏极22可以互换，例如，在一实施例中，每个反射电极3通过贯穿平坦层15和钝化层14的通孔与对应的薄膜晶体管13的漏极连接。
具体的，反射电极3的材料包括Ag、Al等金属或合金，用于将发光功能层7发出的光向远离阵列基板2的方向反射，以实现顶发光。
步骤S303：在任意相邻的两个反射电极之间形成隔离单元。
具体的，隔离单元的材料为电绝缘材料；如图4b所示，隔离单元4的宽度d在阵列基板2朝向反射电极3的方向上逐渐增大，且隔离单元4的上表面在阵列基板2上的正投影完全覆盖隔离单元4的下表面在阵列基板2上的正投影；需要说明的是，隔离单元4的上表面是指隔离单元4远离阵列基板2侧的表面，隔离单元4的下表面是指隔离单元4靠近阵列基板2侧的表面。在一实施例中，隔离单元4在垂直于阵列基板2方向上的截面的形状为倒梯形；截面包括相对设置的两个斜边；每个斜边与阵列基板2的上表面之间的夹角为α，其中，夹角α小于或等于60°，且夹角α越小，隔离单元4对阳极层5的隔离效果越好；在一实施例中，为了保证隔离单元4结构的稳定性，夹角α大于或等于45°且小于或等于60°。
具体的，隔离单元4的底部位于被相邻的两个反射电极3裸露的平坦层15上，且隔离单元4部分覆盖在相邻的两个反射电极3上。
步骤S304：在形成有反射电极和隔离单元的阵列基板上覆盖阳极层，以形成位于每个反射电极上的第一阳极和位于每个隔离单元远离阵列基板一侧的第二阳极；其中，第一阳极与第二阳极通过隔离单元间隔开。
具体的，如图4c所示，阳极层5包括位于每个反射电极3上的第一阳极9和位于每个隔离单元4远离阵列基板2一侧的第二阳极10；其中，阳极层5的材料包括氧化铟锡（ITO）；可以采用蒸镀工艺或溅射工艺形成阳极层5，需要说明的是，采用蒸镀工艺形成阳极层5时，阳极层5在隔离单元4处断开形成第一阳极9和第二阳极10的效果更好。
为了保证第一阳极9和第二阳极10的隔离效果，隔离单元4的厚度h大于反射电极3和第一阳极9的厚度之和。由于隔离单元4为倒梯形或类倒梯形结构，且隔离单元4的厚度h大于反射电极3和第一阳极9的厚度之和，使得隔离单元4的侧面与反射电极3的上表面之间的夹角为锐角，且隔离单元4与反射电极3之间存在高度大于阳极层5的厚度的断差；当在形成有反射电极3和隔离单元4的阵列基板2的显示区整层蒸镀或溅射形成阳极层5时，由于隔离单元4的侧面与反射电极3的上表面之间的夹角为锐角，避免了隔离单元4的侧面上形成有阳极层，从而避免了位于反射电极3上的第一阳极9与位于隔离单元4远离阵列基板2一侧的第二阳极10通过隔离单元4的侧面连接，并且，隔离单元4与反射电极3之间的断差使得第一阳极9与第二阳极10在垂直于阵列基板2的方向上存在间距，进一步避免了位于反射电极3上的第一阳极9与位于隔离单元4远离阵列基板2一侧的第二阳极10连接，因此，本申请实施例中的隔离结构4可以使阳极层5自然的被断开成多个相互不连接的第一阳极9和第二阳极10。
具体的，第一阳极9和第二阳极10的材料相同且厚度相同；其中，第一阳极9为发光功能层的阳极电极。可以理解的是，任意一个第一阳极9和相邻设置的第二阳极10在阵列基板2上的正投影相连接，或者部分重叠。通过隔离单元4，任意相邻的两个第一阳极9也自然间隔设置，因此，阳极层5的图案化不需要采用刻蚀工艺，避免了刻蚀残留或者刻蚀困难的问题。
在一实施例中，第一阳极9的厚度大于或等于800A（埃）；且隔离单元4的厚度h大于或等于1um（微米）。本实施例中，第一阳极9的厚度可以根据OLED器件的腔长需求进行调整，避免在阳极层5和反射电极3之间设置垫片来调节发光器件的腔长。
具体的，第一阳极9位于对应的反射电极3上且与相邻的隔离单元4不连接（不接触），且由于隔离单元4的底部宽度小于顶部宽度，使得每个隔离单元4与相邻的第一阳极9和反射电极3之间形成有底切（undercut）开口25。
具体的，阵列基板2包括用于显示画面的显示区和位于显示区外围的非显示区（附图中仅示出显示区内的部分结构），在形成阳极层5时，可以对非显示区进行遮挡，避免阳极层5形成在非显示区，造成非显示区的金属层短接等，非显示区的面积比较大，对非显示区的遮挡不会影响显示面板1的开口率。
步骤S305：在第一阳极上形成发光功能层。
具体的，步骤S305包括以下步骤：
如图4d所示，形成覆盖在每个第二阳极10的上表面和侧表面的像素定义层6；其中，像素定义层6还部分覆盖在第一阳极9和反射电极3上以形成像素开口27；
如图4e所示，在位于像素开口27中第一阳极9上形成发光功能层7。
具体的，像素定义层6还填充在每个底切开口25中。也就是说，像素定义层6包裹在第二阳极10和隔离单元4的外表面，且部分覆盖在第一阳极9和反射电极3的边缘上，使得像素定义层6在第一阳极9上围成像素开口27。像素定义层6包裹在第二阳极10的外表面可以避免导电性的第二阳极10将相邻的两个发光功能层7电连通，从而保证显示面板1可以正常显示，提高了器件寿命。
具体的，发光功能层7包括依次设置在每个第一阳极9上的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层；发光功能层7可以采用有机墨水材料，也可以采用蒸镀型有机材料；对应的，可以通过喷墨打印技术形成，也可以通过蒸镀技术形成。当显示面板1中的发光功能层7采用喷墨打印技术形成时，像素定义层6的材料为疏水性的材料；当显示面板1中的发光功能层7采用蒸镀技术形成时，像素定义层6的材料可以是非疏水性的材料。
在一实施例中，显示面板1可以为RGB-OLED显示面板，也就是说，不同的发光功能层7中的发光层可以分别发红光、绿光和蓝光，以实现全彩色显示；在另一实施例中，显示面板1可以为W-OLED显示面板，也就是说，所有发光功能层7中的发光层发白光，且显示面板1还包括对应每个OLED器件设置的彩色滤光片，以实现全彩色显示。
如图4f所示，显示面板1的制作方法还包括以下步骤：
在形成有像素定义层6和发光功能层7的阵列基板2上形成一层阴极层8；
在阴极层8上形成封装层26。
具体的，阴极层8可以整层铺设，以减小工艺难度；每个第一阳极9和设置在该第一阳极9上的发光功能层7和阴极层8构成一个OLED器件，每个OLED器件的腔长为反射电极3与阴极层8之间的间距L。封装层26可以避免外界的水氧进入OLED器件，且可以对OLED器件起到保护作用。
本实施例中，通过在任意相邻的两个反射电极3之间设置隔离单元4，使得在形成有隔离单元和反射电极3的阵列基板2上形成阳极层5时，可以形成位于反射电极3上的第一阳极9和位于隔离单元4上的第二阳极10，且第一阳极9和第二阳极10通过隔离单元自然的间隔开，从而使得任意相邻的两个第一阳极9也通过隔离单元4自然的间隔开了，因此，本申请在制作阳极层5时不需要采用刻蚀工艺就可以直接形成厚度较大且间隔设置的第一阳极9，有利于通过第一阳极9的厚度来调节显示面板1中的OLED器件的腔长，以改善发光效率、发光光谱精度和器件寿命；由此可知，一方面，本申请实施例避免了厚度较大的阳极层5采用刻蚀工艺进行图案化，从而避免了刻蚀残留问题，有利于提高产品良率；另一方面，本申请实施例避免了在阳极层5和反射电极3之间设置垫片来调节发光器件的腔长，简化了制作工艺，有利于提高生产效率，即有利于量产化。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板及其制作方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，包括：
    阵列基板；
    多个反射电极，位于所述阵列基板上且呈阵列分布；
    多个隔离单元；其中，任意相邻的两个所述反射电极之间设置一所述隔离单元；
    阳极层，包括位于每个所述反射电极上的第一阳极以及位于每个所述隔离单元远离所述阵列基板一侧的第二阳极；
    发光功能层，位于所述第一阳极上；
    其中，每个所述第一阳极与相邻的所述第二阳极通过所述隔离单元间隔开。
  2. 如权利要求1所述的显示面板，其中，所述隔离单元的宽度在所述阵列基板朝向所述第二阳极的方向上逐渐增大，且所述隔离单元的上表面在所述阵列基板上的正投影完全覆盖所述隔离单元的下表面在所述阵列基板上的正投影。
  3. 如权利要求2所述的显示面板，其中，所述隔离单元在垂直于所述阵列基板方向上的截面的形状为倒梯形。
  4. 如权利要求3所述的显示面板，其中，所述截面包括相对设置的两个斜边；每个所述斜边与所述阵列基板的上表面之间的夹角大于或等于45°且小于或等于60°。
  5. 如权利要求1所述的显示面板，其中，所述隔离单元的厚度大于所述反射电极和所述第一阳极的厚度之和。
  6. 如权利要求5所述的显示面板，其中，所述第一阳极的厚度大于或等于800A；所述隔离单元的厚度大于或等于1um。
  7. 如权利要求1所述的显示面板，其中，所述显示面板还包括覆盖在每个所述第二阳极的上表面和侧表面的像素定义层。
  8. 如权利要求7所述的显示面板，其中，所述像素定义层还部分覆盖在所述第一阳极和所述反射电极上以形成像素开口，且所述发光功能层位于所述像素开口中。
  9. 如权利要求1所述的显示面板，其中，所述阳极层的材料包括氧化铟锡。
  10. 如权利要求1所述的显示面板，其中，所述第一阳极和所述第二阳极的材料相同且厚度相同。
  11. 如权利要求1所述的显示面板，其中，所述阵列基板包括衬底基板、设置在所述衬底基板上缓冲层、以及设置在所述缓冲层上且与所述多个反射电极一一对应连接的多个薄膜晶体管。
  12. 一种显示面板的制作方法，包括以下步骤：
    提供阵列基板；
    在所述阵列基板上形成呈阵列分布的多个反射电极；
    在任意相邻的两个反射电极之间形成隔离单元；
    在形成有所述反射电极和所述隔离单元的阵列基板上覆盖阳极层，以形成位于每个所述反射电极上的第一阳极和位于每个所述隔离单元远离所述阵列基板一侧的第二阳极；其中，所述第一阳极与所述第二阳极通过所述隔离单元间隔开；以及
    在所述第一阳极上形成发光功能层。
  13. 如权利要求12所述的显示面板的制作方法，其中，所述隔离单元的宽度在所述阵列基板朝向所述第二阳极的方向上逐渐增大，且所述隔离单元的上表面在所述阵列基板上的正投影完全覆盖所述隔离单元的下表面在所述阵列基板上的正投影。
  14. 如权利要求13所述的显示面板的制作方法，其中，所述隔离单元在垂直于所述阵列基板方向上的截面的形状为倒梯形。
  15. 如权利要求14所述的显示面板的制作方法，其中，所述截面包括相对设置的两个斜边；每个所述斜边与所述阵列基板的上表面之间的夹角大于或等于45°且小于或等于60°。
  16. 如权利要求12所述的显示面板的制作方法，其中，所述隔离单元的厚度大于所述反射电极和所述第一阳极的厚度之和。
  17. 如权利要求16所述的显示面板的制作方法，其中，所述第一阳极的厚度大于或等于800A；所述隔离单元的厚度大于或等于1um。
  18. 如权利要求12所述的显示面板的制作方法，其中，所述在所述第一阳极上形成发光功能层，包括以下步骤：
    形成覆盖在每个所述第二阳极的上表面和侧表面的像素定义层；其中，所述像素定义层还部分覆盖在所述第一阳极和所述反射电极上以形成像素开口；
    在位于所述像素开口中所述第一阳极上形成发光功能层。
  19. 如权利要求12所述的显示面板的制作方法，其中，所述阳极层的材料包括氧化铟锡。
  20. 如权利要求12所述的显示面板的制作方法，其中，所述第一阳极和所述第二阳极的材料相同且厚度相同。
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CN111900194A (zh) * 2020-09-04 2020-11-06 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制作方法
CN112635526B (zh) * 2020-12-14 2022-10-04 昆山国显光电有限公司 一种显示面板及显示装置
CN112670247B (zh) * 2020-12-23 2024-02-02 武汉天马微电子有限公司 一种显示面板的制备方法、显示面板及显示装置
CN112635691B (zh) * 2020-12-31 2022-07-12 Tcl华星光电技术有限公司 阵列基板及阵列基板的制作方法
CN113871431A (zh) * 2021-09-17 2021-12-31 深圳市华星光电半导体显示技术有限公司 显示面板和移动终端
CN114388599A (zh) * 2021-12-16 2022-04-22 深圳市华星光电半导体显示技术有限公司 一种显示背板及移动终端
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