WO2020177666A1 - 像素单元及其制造方法、显示基板 - Google Patents

像素单元及其制造方法、显示基板 Download PDF

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Publication number
WO2020177666A1
WO2020177666A1 PCT/CN2020/077439 CN2020077439W WO2020177666A1 WO 2020177666 A1 WO2020177666 A1 WO 2020177666A1 CN 2020077439 W CN2020077439 W CN 2020077439W WO 2020177666 A1 WO2020177666 A1 WO 2020177666A1
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Prior art keywords
dielectric layer
layer
light
sub
active layer
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PCT/CN2020/077439
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English (en)
French (fr)
Inventor
刘军
闫梁臣
周斌
苏同上
刘宁
宋威
刘融
冯波
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2020177666A1 publication Critical patent/WO2020177666A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers

Definitions

  • At least one embodiment of the present disclosure relates to a pixel unit, a manufacturing method thereof, and a display substrate.
  • thin film transistors are used as driving elements of display panels.
  • the active layer in the thin film transistor will generate photo-generated carriers after being irradiated by light, which causes the leakage current of the thin film transistor to increase, thereby affecting the quality of the display screen of the display panel, such as crosstalk, afterimages, and the like.
  • At least one embodiment of the present disclosure provides a pixel unit including a dielectric layer, a switching element, and a first light-shielding structure.
  • the switching element includes an active layer and is located on the dielectric layer, the first light-shielding structure is at least partly the same layer as the dielectric layer, and the orthographic projection of the first light-shielding structure on the surface where the active layer is located is located on the dielectric layer.
  • the source layer is outside the orthographic projection on the surface where the active layer is located.
  • the dielectric layer is disposed on at least two opposite sides of the same layer of the first light shielding structure as the dielectric layer.
  • At least a part of the sidewall of the dielectric layer in the same layer as the first light shielding structure and facing the first light shielding structure is formed as a convex-concave structure.
  • the dielectric layer on a surface parallel to the dielectric layer, is provided with an opening or groove surrounding the switching element, and the sidewall of the opening or groove It is formed as the convex-concave structure.
  • the dielectric layer is a stack composed of at least two sub-dielectric layers.
  • the openings in the adjacent sub-dielectric layers are connected or the openings of one of the adjacent sub-dielectric layers are connected with the grooves of the other, and Orthographic projections of the openings in the adjacent sub-dielectric layers or the openings of one of the adjacent sub-dielectric layers and the other groove on the surface where the active layer is located at least partially do not overlap.
  • the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the first sub-dielectric layer is located between the second sub-dielectric layer and the Between the active layers, a first opening is provided in the first sub-dielectric layer, a second opening or a second groove is provided in the second sub-dielectric layer, and the first opening and the second opening are either The second grooves are connected, and the orthographic projection of the first opening on the surface where the active layer is located is within the orthographic projection of the second opening or the second groove on the surface where the active layer is located.
  • the dielectric layer includes at least three of the sub-dielectric layers, and the openings or grooves of the sub-dielectric layers on both sides are in the active layer.
  • the projection of the orthographic projection on the surface where the opening of the sub-dielectric layer is located in the middle is within the orthographic projection of the surface where the active layer is located.
  • the first light-shielding structure includes a first part and a second part, the first part is in the same layer as the dielectric layer, and the second part is the same layer as the dielectric layer.
  • the layers are located on different floors.
  • the distance from an end of the second portion that faces away from the dielectric layer to the surface where the dielectric layer is located is greater than or equal to that of the active layer away from the dielectric layer. The distance from the surface of the layer to the surface of the dielectric layer.
  • the pixel unit provided by at least one embodiment of the present disclosure further includes a black matrix
  • the pixel unit includes a display area and a non-display area located around the display area
  • the black matrix and the first shading structure are located in the In the non-display area
  • the black matrix and the second part are on the same layer and have an integrated structure.
  • the pixel unit provided by at least one embodiment of the present disclosure further includes a second light-shielding structure located on a side of the dielectric layer away from the active layer, and the active layer is located on the active layer.
  • the orthographic projection on the surface where the layer is located coincides with the orthographic projection of the second light shielding structure on the surface where the active layer is located, or the orthographic projection of the active layer on the surface where the active layer is located is located on the first
  • the two light-shielding structures are within the orthographic projection on the surface where the active layer is located.
  • the orthographic projection of the second light shielding structure on the surface where the active layer is located is located on the surface of the first light shielding structure on the surface where the active layer is located. The inside of the orthographic projection.
  • the pixel unit provided in at least one embodiment of the present disclosure further includes a light-emitting device, the light-emitting device is located on the side of the switching element away from the dielectric layer, and the light-emitting device includes sequentially stacked on the switching element.
  • the first electrode layer, the light-emitting function layer and the second electrode layer on the upper side, one of the first electrode layer and the second electrode layer is a reflective electrode layer.
  • At least one embodiment of the present disclosure provides a display substrate including the pixel unit described in any of the above embodiments.
  • At least one embodiment of the present disclosure provides a method for manufacturing a pixel unit, including: forming a dielectric layer; forming a switching element including an active layer on the dielectric layer; forming a first light shield at least part of the same layer as the dielectric layer Structure; wherein the orthographic projection of the first light shielding structure on the surface where the active layer is located is outside the orthographic projection of the active layer on the surface where the active layer is located.
  • forming the dielectric layer includes: patterning the dielectric layer to form at least a portion of the sidewall of the uneven structure in the dielectric layer.
  • the dielectric layer is patterned to form an opening or a groove in the dielectric layer, and the sidewall of the opening or the groove is formed as the convex-concave structure .
  • Forming the first light-shielding structure includes depositing a light-shielding material layer on the dielectric layer to fill the openings or grooves, and patterning the light-shielding material layer to form the first light-shielding structure; wherein the dielectric layer surrounds The switching element.
  • the dielectric layer is formed as a stack composed of at least two sub-dielectric layers.
  • the dielectric layer is a stack composed of at least two sub-dielectric layers, and forming the dielectric layer includes: forming a second sub-dielectric layer, and Forming a first sub-dielectric layer on the second sub-dielectric layer; patterning the first sub-dielectric layer and the second sub-dielectric layer to form a first opening in the first sub-dielectric layer; After the first opening is formed in the first sub-dielectric layer, using the first sub-dielectric layer as a mask, the second sub-dielectric layer is etched using an atmosphere to form the second sub-dielectric layer A second opening or a second groove; wherein the materials forming the first sub-dielectric layer and the second sub-dielectric layer are different, and the etching ratio of the atmosphere to the material of the second sub-dielectric layer is greater than that of the The etching ratio of the material of the first sub-dielectric layer
  • the first light-shielding structure is located around the active layer and is at least partially in the same layer as the dielectric layer.
  • the first light-shielding structure can block at least part of the light from the side surface of the active layer, thereby reducing the increase in leakage current caused by the photo-generated carriers generated by the light irradiating the active layer, and improving the stability of the switching element .
  • FIG. 1 is a cross-sectional view of a partial structure of a pixel unit provided by some embodiments of the present disclosure
  • 2A is a cross-sectional view of a partial structure of another pixel unit provided by some embodiments of the present disclosure
  • FIG. 2B is a plan view of a structure of the pixel unit shown in FIG. 2A;
  • FIG. 2C is a plan view of another structure of the pixel unit shown in FIG. 2A;
  • FIG. 3 is a cross-sectional view of a partial structure of another pixel unit provided by some embodiments of the present disclosure.
  • FIG. 4 is a cross-sectional view of a partial structure of another pixel unit provided by some embodiments of the present disclosure.
  • 5A is a cross-sectional view of a partial structure of another pixel unit provided by some embodiments of the present disclosure.
  • 5B is a cross-sectional view of a partial structure of another pixel unit provided by some embodiments of the present disclosure.
  • FIG. 6 is a cross-sectional view of a partial structure of another pixel unit provided by some embodiments of the present disclosure.
  • FIG. 7 is a cross-sectional view of another pixel unit provided by some embodiments of the present disclosure.
  • FIG. 8A is a cross-sectional view of another pixel unit provided by some embodiments of the present disclosure.
  • FIG. 8B is a plan view of the pixel unit shown in FIG. 8A;
  • FIG. 9 is a plan view of a display substrate provided by some embodiments of the present disclosure.
  • 10A to 10F are process diagrams of a method for manufacturing a pixel unit provided by some embodiments of the disclosure.
  • OLED display panels have the advantages of high contrast and self-luminescence, and thus have a good development prospect.
  • the OLED display panel needs to be provided with a switching element such as a thin film transistor (TFT) to realize a control circuit, so as to control functions such as light emission of the OLED display panel.
  • TFT thin film transistor
  • a light blocking structure is arranged above and/or below the TFT to prevent light in this direction from irradiating the active layer in the thin film transistor.
  • the OLED display panel The arrangement of the signal lines, etc.
  • the light blocking structure arranged above and/or below the TFT cannot block the light, resulting in Leakage current is generated in the active layer due to photo-generated carriers, and the performance of the thin film transistor is unstable, resulting in poor display of the OLED display panel.
  • At least one embodiment of the present disclosure provides a pixel unit, a manufacturing method thereof, and a display substrate.
  • the pixel unit includes a dielectric layer, a switching element and a first light shielding structure.
  • the switching element includes an active layer and is located on the dielectric layer.
  • the first light-shielding structure is at least partially in the same layer as the dielectric layer.
  • the orthographic projection of the first light-shielding structure on the surface of the active layer is located on the surface of the active layer. Outside the orthographic projection.
  • the first light-shielding structure is located around the active layer and is at least partially in the same layer as the dielectric layer.
  • the first light-shielding structure can be At least part of the shielding is performed, thereby reducing the increase in leakage current caused by the photogenerated carriers generated by the light irradiating the active layer, and improving the stability of the switching element.
  • FIG. 1 is a cross-sectional view of a partial structure of a pixel unit provided by some embodiments of the present disclosure, which shows a partial structure of a region where a switching element of the pixel unit is located.
  • the pixel unit includes a dielectric layer 100, a switching element (not shown, see the switching element 200 in FIG. 2A), and a first light shielding structure 300.
  • the switching element includes an active layer 210 and is located on the dielectric layer 100. At least part of the first light shielding structure 300 is in the same layer as the dielectric layer 100.
  • the orthographic projection of the first light shielding structure 300 on the surface where the active layer 210 is located is located on the active layer 210 Outside the orthographic projection on the surface where the active layer 210 is located.
  • the surface where the active layer 210 is located is, for example, the plane where the upper surface or the lower surface of the active layer 210 in FIG. 1 is located.
  • a part of the first light-shielding structure 300 is in the same layer as the dielectric layer 100, and the other part protrudes outside the dielectric layer 100, thereby shielding light from the side of the pixel unit to the active layer 210 (FIG. 1 The dotted line " ⁇ ").
  • the part of the first light shielding structure 300 that is in the same layer as the dielectric layer 100 can shield the light S1 along the dielectric layer 100 to the side surface of the active layer 210, and the part of the first light shielding structure 300 protruding beyond the dielectric layer 100
  • the light S2 irradiated from outside the dielectric layer 100 to the side surface of the active layer 210 can be blocked.
  • the material of the active layer 210 may include amorphous silicon, polysilicon, or metal oxides such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), and gallium zinc oxide (GZO).
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • GZO gallium zinc oxide
  • the type and material of the dielectric layer 100 can be set according to the type of the switching element, and the type of the switching element can be selected as required.
  • the switching element may be a thin film transistor
  • the thin film transistor may be a top gate type thin film transistor, a bottom gate type thin film transistor, a double gate type thin film transistor, or the like.
  • the switching element in the pixel unit is a top-gate thin film transistor.
  • the switching element 200 in the pixel unit includes an active layer 210, a gate electrode 220, and a source-drain electrode layer (including a drain electrode 231 and a source electrode 232), and the active layer 210 is located on the gate electrode 220.
  • a gate insulating layer 240 is provided between the dielectric layer 100 and the active layer 210 and the gate electrode 220.
  • the switching element 200 includes an interlayer dielectric layer 250 covering the gate electrode 220, the drain electrode 231 and the source electrode 232 are located on the surface of the interlayer dielectric layer 250 away from the gate electrode 220, and the interlayer dielectric layer 250 is provided with via holes.
  • the drain electrode 231 and the source electrode 232 are respectively connected to both ends of the active layer 210 through the via hole.
  • the pixel unit includes a base substrate 10 to support various structures of the pixel unit.
  • the dielectric layer 100 may be a buffer layer.
  • the material of the buffer layer may include silicon oxide, silicon nitride, silicon oxynitride, etc. These materials have high density and can prevent ions in the base substrate 10 from invading the active layer 210.
  • the switching element in the pixel unit is a top-gate thin film transistor.
  • the switching element in the pixel unit includes an active layer, a gate electrode, and a source-drain electrode layer, and the dielectric layer is located between the gate electrode and the active layer.
  • the switching element includes an interlayer dielectric layer covering the active layer, the source and drain electrode layers are located on the surface of the interlayer dielectric layer away from the active layer, and the interlayer dielectric layer is provided with via holes, and the drain electrode of the source and drain electrode layers The and source electrodes are respectively connected to both ends of the active layer through the via hole.
  • the dielectric layer may be a gate insulating layer to separate the active layer and the gate electrode.
  • the material of the gate insulating layer may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or other suitable materials.
  • the dielectric layer is disposed on at least two opposite sides of the portion of the first light-shielding structure in the same layer as the dielectric layer.
  • the dielectric layer may be disposed on the side facing the active layer and the side away from the active layer of the light shielding structure.
  • the first light shielding structure 300 has the dielectric layer 100 on at least two sides of the same layer as the dielectric layer 100. In this way, the portion of the first light shielding structure 300 that is the same layer as the dielectric layer 100 is sandwiched in the dielectric layer 100.
  • the sidewall of the portion of the first light shielding structure 300 that is in the same layer as the dielectric layer 100 is in contact with the sidewall of the dielectric layer 100 facing the first light shielding structure 300.
  • the planar shape of the portion of the first light-shielding structure that is in the same layer as the dielectric layer is a closed ring, such as a "mouth" shape.
  • dielectric layers are provided on opposite sides of the portion of the first light shielding structure that is in the same layer as the dielectric layer. Exemplarily, as shown in FIGS.
  • the orthographic projection of the portion of the first light shielding structure 300 that is the same layer as the dielectric layer 100 on the surface where the active layer 210 is located is a closed ring shape, so that the first light shielding can be enhanced
  • the shielding area of the structure 300 to the side surface of the active layer 210 along the dielectric layer 100 further reduces the risk of the active layer 210 being irradiated by light.
  • the planar shape of the portion of the first light shielding structure that is in the same layer as the dielectric layer is a line segment shape.
  • the first light-shielding structure 300 (not shown in FIG. 2C) includes a plurality of sub-light-shielding structures whose planar shape is a line segment, such as a first light-shielding structure 3001, a second light-shielding structure 3002, and a The three sub-shielding structures 3003 and the fourth sub-shielding structure 3004.
  • the first light-shielding structure 3001, the second light-shielding structure 3002, the third light-shielding structure 3003, and the fourth light-shielding structure 3004 are distributed around the active layer 210 to shield the active layer 210 from light.
  • the first light shielding structure 300 in a direction parallel to the surface where the active layer 210 is located, the first light shielding structure 300 is provided with a dielectric layer 100 on all side surfaces of the same layer as the dielectric layer 100.
  • the number of sub-light-shielding structures included in the first light-shielding structure can be set as required.
  • the sub-light-shielding structure can be provided on the side of the active layer 210 that is most affected by light.
  • the first light-shielding structure is It has a small design volume while shielding the active layer of the switching element from light.
  • the amount of material used to form the first light-shielding structure is reduced to reduce costs, and the adverse effect of the first light-shielding structure on the manufacturing process of the switching element is reduced,
  • the structure of the pixel unit is simplified, and the difficulty of the manufacturing process of the pixel unit is reduced.
  • planar shape of the portion of the first light shielding structure that is in the same layer as the dielectric layer can be selected according to needs, and is not limited to the above-mentioned closed ring shape and line segment shape.
  • planar shape of the part of the first light shielding structure at the same layer as the dielectric layer as a closed loop as shown in FIGS. 2A and 2B as an example, the technical solution in at least one embodiment of the present disclosure will be described below.
  • the dielectric layer in a direction parallel to the surface of the dielectric layer, the dielectric layer is provided with a recessed structure surrounding the switching element, and a portion of the first light shielding structure in the same layer as the dielectric layer is filled In the recessed structure.
  • a recess structure 101 is formed in the dielectric layer 100, and a part of the first light shielding structure 300 fills the recess structure 101.
  • the recessed structure may be set as an opening as shown in FIG. 2A, that is, the dielectric layer 100 is disconnected at the recessed structure 101, and the first light shielding structure 300 penetrates the dielectric layer 100.
  • the first light-shielding structure 300 can enhance the shielding of the light emitted to the side surface of the active layer 210 along the dielectric layer 100, and further reduce the risk of the active layer 210 being irradiated by light.
  • the recessed structure may be configured as a groove, and the depth of the groove is greater than zero and less than the thickness of the dielectric layer.
  • the shape of the recessed structure can be set as needed.
  • the sidewalls of the recessed structure can be set as a flat surface, a curved surface, or a surface with a concave-convex shape.
  • the sidewalls of the recessed structure are also the sidewalls of the dielectric layer in the same layer as the first shading structure and facing the first shading structure.
  • the dielectric layer may be a single-layer structure or may be a stack of multiple sub-dielectric layers.
  • the sidewall of the dielectric layer that is the same layer as the first light-shielding structure and faces the first light-shielding structure may be composed of the sidewall of one sub-dielectric layer or may be composed of The sidewalls of a plurality of sub-dielectric layers are formed.
  • the first light-shielding structure is related to the structure (for example, sidewalls) of the dielectric layer. In the following, the first light-shielding structure will be described in conjunction with different arrangements of the sidewalls of the dielectric layer.
  • the sidewall 1011 of the recessed structure 101 is substantially flat.
  • the surface where the sidewall 1011 is located is substantially perpendicular to the surface where the active layer 210 is located.
  • At least a portion of the sidewall of the dielectric layer that is the same layer as the first light-shielding structure and faces the first light-shielding structure is formed as a convex-concave structure.
  • the sidewall 1011a of the recessed structure 101a of the dielectric layer 100a is formed as a concave-convex structure 1012a, so that the sidewall 1011a of the recessed structure 101a has a concave-convex shape.
  • the recessed structure 101a is an opening, and all of the sidewalls 1011a of the opening are formed as a concave-convex structure 1012a.
  • the sidewall 1011a of the concave-convex structure 1012a makes the width of each part of the concave structure 101a different, and the sidewall 1011a formed with the concave-convex structure 1012a can make the first light-shielding structure in Extending in the direction parallel to the surface where the active layer 210 is located, the first light shielding structure 300a increases the shielding area of the light obliquely irradiating the active layer 210 from the side of the dielectric layer 100a away from the active layer 210, and further reduces the active layer. 210 Risk of exposure to light.
  • the portion of the concave-convex structure with a larger width is located The bottom of the recessed structure (see the recessed structure 101a in FIG. 3) or the middle of the recessed structure (see the recessed structure 101c in FIG. 5A).
  • the first light-shielding structure extends toward the active layer to improve the light-shielding effect of the first light-shielding structure on the active layer, it is possible to prevent the first light-shielding structure from being too close to the active layer to cause the substance of the first light-shielding structure (For example, hydrogen) invades the active layer.
  • the above design makes it difficult to separate the first light-shielding structure and the dielectric layer, and increases the stability of the first light-shielding structure.
  • the manner in which the recess structure is formed in the dielectric layer and the sidewall of the recess structure is formed to have a concave-convex structure is not limited, and can be designed according to the actual process.
  • the dielectric layer is a stack of at least two sub-dielectric layers. In this way, in the process of manufacturing each sub-dielectric layer, different sub-dielectric layers may be subjected to a patterning process respectively, so that the sidewall of the recessed structure is formed with a concave-convex structure, which reduces the difficulty of the manufacturing process.
  • the openings in the adjacent sub-dielectric layers are connected or the openings of one of the adjacent sub-dielectric layers are connected to the grooves of the other, and the adjacent sub-dielectric layers Orthographic projections of the openings in or the openings of one of the adjacent sub-dielectric layers and the other grooves on the surface where the active layer is located at least partially do not overlap.
  • the orthographic projection of the opening or groove of one of the adjacent sub-dielectric layers on the surface of the active layer is at least partially located on the other opening or groove of the adjacent sub-dielectric layer on the surface of the active layer. Outside the orthographic projection.
  • sub-recess structures openings or grooves
  • the wall may be formed to have an uneven structure.
  • the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer.
  • the first sub-dielectric layer is located between the second sub-dielectric layer and the active layer.
  • the dielectric layer is provided with a first opening
  • the second sub-dielectric layer is provided with a second opening or a second groove
  • the first opening and the second opening or the second groove are connected
  • the first opening is on the surface where the active layer is located.
  • the orthographic projection of is located within the orthographic projection of the second opening or the second groove on the surface where the active layer is located.
  • the dielectric layer 100b includes a first sub-dielectric layer 110b and a second sub-dielectric layer 120b, and the first sub-dielectric layer 110b is located between the active layer 210 and the second sub-dielectric layer 120b.
  • a first opening 111b is provided in the first sub-dielectric layer 110b
  • a second opening 121b is provided in the second sub-dielectric layer 120b, the first opening 111b and the second opening 121b are connected, and the first opening 111b is located in the active layer 210
  • the orthographic projection on the surface (or the base substrate 10) is within the orthographic projection of the second opening 121b on the surface (or the base substrate 10) where the active layer 210 is located.
  • the first opening 111b and the second opening 121b make the sidewall 1011b of the dielectric layer 100b a concave-convex structure, and the portion of the first light-shielding structure 300b located at the second opening 121b may extend toward the active layer 210 to improve the first light-shielding structure.
  • the light-shielding effect of the structure 300b on the active layer 210, and the portion of the first light-shielding structure 300b located in the first opening 111b and the active layer 210 are kept at a certain distance to avoid the distance between the first light-shielding structure 300b and the active layer 210 Too close causes the substance (such as hydrogen, etc.) of the first light shielding structure 300b to invade the active layer 210.
  • the first opening 111b is formed in the first sub-dielectric layer 110b, and the method of forming the second opening 121b in the second sub-dielectric layer 120b can refer to the relevant description in the embodiment shown in FIGS. 10A to 10B, and will not be repeated here.
  • the dielectric layer includes at least three sub-dielectric layers, and the projections of the orthographic projections of the openings or grooves of the sub-dielectric layers on both sides on the active layer are located in the middle.
  • the opening of the sub-dielectric layer is within the orthographic projection of the surface where the active layer is located.
  • the dielectric layer 100c includes a third sub-dielectric layer 130c, a second sub-dielectric layer 120c, and a first sub-dielectric layer 110c that are sequentially stacked on the base substrate 10.
  • the active layer 210 is located On the first sub-dielectric layer 110c.
  • the first sub-dielectric layer 110c is provided with a first opening 111c
  • the second sub-dielectric layer 120c is provided with a second opening 121c
  • the third sub-dielectric layer 120c is provided with a third opening 131c
  • the first opening 111c and the second opening 121c and the third opening 131c are connected
  • the orthographic projection of the first opening 111c and the third opening 131c on the surface of the active layer 210 (or the base substrate 10) is located on the surface of the second opening 121c on the surface of the active layer 210 (or Within the orthographic projection on the base substrate 10).
  • the first opening 111c, the second opening 121c, and the third opening 131c make the sidewall 1011c of the dielectric layer 100c formed into a concave-convex structure, and the portion of the first light shielding structure 300c located at the second opening 121c may extend toward the active layer 210,
  • the active layer 210 is too close to cause the substance (such as hydrogen, etc.) of the first light shielding structure 300 c to invade the active layer 210.
  • the structure of the dielectric layer 100c as shown in FIG. 5A may be deformed, so that the orthographic projection of the first opening 111c and the second opening 121c on the base substrate 10 is located on the third The opening 131c is within the orthographic projection of the base substrate 10, or the orthographic projection of the first opening 111c on the base substrate 10 is within the orthographic projection of the second opening 121c and the third opening 131c on the base substrate 10. .
  • the first light-shielding structure includes a first part and a second part.
  • the first part and the dielectric layer are in the same layer, and the second part and the dielectric layer are in different layers.
  • the first light shielding structure 300c includes a first portion 310c in the same layer as the dielectric layer 100c and a second portion 320c protruding outside the dielectric layer 100c.
  • the thickness of the second part 320c affects the light shielding effect of the first light shielding structure 300c on the active layer 210.
  • the greater the thickness of the second portion 320c the better the light shielding effect of the first light shielding structure 300c.
  • the thickness of the second portion 320c can be determined according to the actual process.
  • the design thickness of the second portion 320c can be made as large as possible without affecting the performance of the switching elements in the pixel unit.
  • the orthographic projection of the first portion 310c of the first light-shielding structure 300c on the base substrate 10 may be located within the orthographic projection of the second portion 320c of the first light-shielding structure 300c on the base substrate 10.
  • Figure 2A the orthographic projection of the second portion 320c of the first light-shielding structure 300c on the base substrate 10 may be located within the orthographic projection of the first portion 310c of the first light-shielding structure 300c on the base substrate 10.
  • the first portion 310c of the first light-shielding structure 300c extends in the direction of the active layer 210, which can further increase the shielding area of the first light-shielding structure 300c to prevent light from being emitted from the side of the active layer 210 Into the active layer 210, thereby reducing the risk of the active layer 210 being irradiated by light.
  • the side of the first portion 310c of the first light shielding structure 300c close to the active layer 210 may extend toward the active layer 210, while the side of the first portion 310c away from the active layer 210 does not have The extension structure, as shown in FIG. 5B, at this time, the orthographic projection of the first portion 310c of the first light-shielding structure 300c on the base substrate 10 and the orthographic projection of the second portion 320c of the first light-shielding structure 300c on the base substrate 10 Partially overlapped.
  • the embodiment of the present disclosure does not limit the specific form of the first light shielding structure 300c, as long as the effect of shielding the active layer 210 can be achieved.
  • the distance from the end of the second part facing away from the dielectric layer to the surface (or the base substrate) where the dielectric layer is located is greater than or equal to the surface of the active layer facing away from the dielectric layer to The distance between the surface of the dielectric layer (or the base substrate).
  • the height L2 of the second portion 320c is greater than the height L1 of the active layer 210. In this way, the shielding area of the first light shielding structure 300c to the dielectric layer 300c can be increased, and the active layer 210 can be further reduced. Risk of light exposure.
  • the pixel unit provided by at least one embodiment of the present disclosure further includes a second light-shielding structure, the second light-shielding structure is located on the side of the dielectric layer away from the active layer, and the orthographic projection of the active layer on the surface of the active layer and the second The orthographic projections of the light shielding structure on the surface where the active layer is located overlap, or the orthographic projection of the active layer on the surface where the active layer is located is within the orthographic projection of the second light shielding structure on the surface where the active layer is located.
  • a second light shielding structure 400 is provided between the base substrate 10 and the dielectric layer 100c. The second light shielding structure 400 can shield the light emitted from the side of the base substrate 10 to the active layer 210.
  • the switching element is a top-gate thin film transistor as shown in FIG. 6, and the second light-shielding structure 400 may be provided separately.
  • the second light-shielding structure 400 is a light-shielding metal and is not combined with other conductive structures such as The signal wires are connected.
  • the switching element is a bottom-gate or double-gate thin film transistor, and the second light-shielding structure may be configured as a gate electrode.
  • the second light-shielding structure may include a metal material, and may form a single-layer or multi-layer structure, for example, a single-layer molybdenum or molybdenum-niobium alloy, a single-layer aluminum structure, a single-layer molybdenum structure, or two layers of molybdenum sandwiched by one The structure of layered aluminum.
  • the orthographic projection of the second light-shielding structure on the surface where the active layer is located is inside the orthographic projection of the first light-shielding structure on the surface where the active layer is located.
  • the inner side here refers to the side of the orthographic projection of the first light shielding structure on the surface where the active layer is located closer to the orthographic projection of the active layer on the surface where the active layer is located.
  • the first light-shielding structure 300 c and the second light-shielding structure 400 cooperate to block the light emitted from the side of the base substrate 10 to the active layer 210.
  • FIG. 6 the first light-shielding structure 300 c and the second light-shielding structure 400 cooperate to block the light emitted from the side of the base substrate 10 to the active layer 210.
  • the dielectric layer 100c is arranged such that the portion of the first light shielding structure 300c contacting the second sub-dielectric layer 120c can extend toward the active layer 210. In this way, the first light shielding structure 300c and the second The gap of the light shielding structure 400 improves the light shielding effect of the first light shielding structure 300c and the second light shielding structure 400 on light.
  • the pixel unit provided in at least one embodiment of the present disclosure further includes a light-emitting device, the light-emitting device is located on the side of the switching element away from the dielectric layer, and the light-emitting device may include a first electrode layer sequentially stacked on the switching element and a light-emitting function. Layer and second electrode layer.
  • the pixel unit includes a light emitting device 500.
  • the light emitting device 500 includes a first electrode layer 510, a light emitting function layer 520, and a second electrode layer 530, and the light emitting function layer 520 is sandwiched between the first electrode layer 510.
  • the first electrode layer 510 is electrically connected to the drain electrode 231 of the switching element.
  • the pixel unit includes a passivation layer 260, the passivation layer 260 is located between the switching element (such as the drain electrode 231) and the light emitting device 500, the passivation layer 260 is formed with an opening, the first electrode layer 510 and the drain electrode 231 is connected through the opening.
  • a flat layer may be provided between the passivation layer and the light emitting device to improve the flatness of the first electrode layer, thereby improving the light emitting performance of the light emitting device.
  • the passivation layer when configured to have a planarization effect, there may be no need to provide a planarization layer between the passivation layer and the light emitting device, which simplifies the structure of the pixel unit and reduces the design thickness of the pixel unit , It is beneficial to the light and thin design of the pixel unit and the products including the pixel unit (for example, display substrate, display panel).
  • one of the first electrode layer and the second electrode layer is provided as a reflective electrode layer.
  • the other of the first electrode layer and the second electrode layer may be a transparent electrode layer or a semi-transparent electrode layer.
  • the display mode of the pixel unit can be implemented as top emission or bottom emission.
  • the display mode of the pixel unit is top emission; when the second electrode layer 520 is configured as a reflective electrode, the display mode of the pixel unit is For the bottom launch.
  • the first electrode layer is the anode of the light-emitting device
  • the second electrode layer is the cathode of the light-emitting device.
  • the anode as the connection layer of the forward voltage of the light-emitting device, has good conductivity and a higher work function value.
  • the anode may be formed of a conductive material with a high work function
  • the electrode material of the anode may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), zinc oxide (ZnO ), indium oxide (In 2 O 3 ), aluminum oxide zinc (AZO), carbon nanotubes, etc.
  • the cathode is used as the connection layer for the negative voltage of the light-emitting device, which has good conductivity and low work function value.
  • the cathode can Use metal materials with low work function values, such as lithium, magnesium, calcium, strontium, aluminum, indium, etc., or alloys of the above metal materials with low work function values and copper, gold, and silver.
  • metal materials with low work function values such as lithium, magnesium, calcium, strontium, aluminum, indium, etc.
  • alloys of the above metal materials with low work function values and copper, gold, and silver such as copper, gold, and silver.
  • the cathode formed of the above metal material if the cathode needs to be configured to transmit light, the thickness of the cathode needs to be designed to transmit light.
  • the anode when the first electrode layer (anode) of the light-emitting device is set as a reflective electrode, the anode may be designed as a stack of multiple film layers, and part of the film layers may be made of transparent conductive Material is formed (such as ITO, IZO, etc.), and another part of the film layer is made of opaque conductive materials (such as metals such as chromium and silver).
  • transparent conductive Material such as ITO, IZO, etc.
  • opaque conductive materials such as metals such as chromium and silver
  • transparency may mean that the transmittance of light is 75% to 100%
  • translucency may mean that the transmittance of light is 25% to 75%
  • the light-emitting function layer includes an organic light-emitting layer.
  • the light-emitting functional layer may further include one or a combination of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • an anode, a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, and a cathode are sequentially stacked.
  • an electron blocking layer and a hole blocking layer may also be provided in the organic light emitting functional layer, the electron blocking layer is located between the anode and the organic light emitting layer, and the hole blocking layer is located between the cathode and the organic light emitting layer, but is not limited thereto.
  • the light-emitting color of the light-emitting device is not limited.
  • the material of the organic light-emitting layer of the light-emitting functional layer can be selected according to the required light-emitting color.
  • the organic light emitting layer can emit red light, green light, blue light, yellow light, white light or other colors of light depending on the organic light-emitting material used.
  • the light-emitting functional layers of the light-emitting devices of multiple pixel units are integrated to emit light of the same color, such as white light, blue light, yellow light or other colors of light.
  • a pixel defining layer 501 is provided in the pixel unit, and the pixel defining layer 501 separates the light-emitting function layers of the light-emitting devices in different pixel units so that different pixel units emit light.
  • the device can be set to emit light of different colors.
  • the pixel unit provided by at least one embodiment of the present disclosure further includes a black matrix
  • the pixel unit includes a display area and a non-display area located around the display area
  • the black matrix and the first light shielding structure are located in the non-display area.
  • the black matrix is used to limit the display area and the non-display area, prevent light leakage, and avoid interference of light emitted between adjacent pixels.
  • the black matrix in a case where the first light-shielding structure includes a first portion that is the same layer as the dielectric layer and a second portion protruding outside the dielectric layer, the black matrix may be set to be the same as the second portion.
  • Layer and integrated structure Exemplarily, as shown in FIGS. 8A and 8B, the pixel unit is configured to have a bottom emission display function, and the black matrix 600 and the first light shielding structure 300c (the second part of the first light shielding structure 300c) are an integrated structure. In this way, in the process of manufacturing the first light-shielding structure 300c, the black matrix 600 is manufactured simultaneously, which simplifies the manufacturing process of the pixel unit and reduces the cost.
  • the black matrix 600, the first light-shielding structure 300c, and the switching element 200 are located in the non-display area 1100 of the pixel unit, and are used to define the display area 1200 of the pixel unit.
  • the light emitting device 500 is at least partially located in the display area 1200.
  • a second light-shielding structure 400 is provided in the area where the switch element 200 is located.
  • the black matrix 600, the first light-shielding structure 300c, and the second light-shielding structure 400 cooperate to prevent non-display of the pixel unit. Area leaks light.
  • the display substrate may include the pixel unit in any of the foregoing embodiments.
  • the display substrate is composed of a plurality of pixel units arranged in an array (pixel units 1000a, 1000b, 1000c, 1000d, etc. in FIG. 9), and the structure of the pixel unit can refer to the relevant description in the foregoing embodiment , I won’t repeat it here.
  • the display panel includes multiple rows and multiple columns of pixel units.
  • every four pixel units may be a group, for example, in each row of pixel units (along the X axis direction), the pixel units 1000a, 1000b, 1000c, and 1000d in each group may be red sub-pixels R and green sub-pixels, respectively G, blue sub-pixel B and white sub-pixel W.
  • the embodiments of the present disclosure do not limit the number and types of pixel units in each group.
  • each group may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B but not the white sub-pixel W.
  • each The pixel unit may include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, a yellow sub-pixel Y, and so on.
  • the display substrate may be a rigid substrate; or the display substrate may also be a flexible substrate, so that the display substrate can be applied to the field of flexible display.
  • the base substrate may be a glass plate, a quartz plate, a metal plate, or a resin-based plate.
  • the material of the base substrate may include an organic material, for example, the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, or polyethersulfone. , Polyethylene terephthalate and polyethylene naphthalate and other resin materials.
  • the display substrate may be used in the field of micro OLED display.
  • the base substrate may be a silicon wafer.
  • the material of the silicon wafer may be single crystal silicon, and the planar shape of the silicon wafer may be circular or other shapes.
  • the display substrate may further include an encapsulation layer, the encapsulation layer is located on a side of the light-emitting device away from the base substrate, and the encapsulation layer at least covers the light-emitting device.
  • the encapsulation layer can encapsulate the display substrate to prevent external water, oxygen, etc. from intruding into the interior of the display substrate, thereby protecting components (such as light-emitting devices) inside the display substrate.
  • the encapsulation layer may be a single-layer structure or a composite structure of at least two layers.
  • the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that are sequentially disposed on the light emitting device.
  • the materials of the first encapsulation layer and the third encapsulation layer may include inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc.
  • the inorganic materials are highly dense and can prevent the intrusion of water, oxygen, etc.; for example, the first The material of the second encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, such as polymer resin to flatten the surface of the display substrate, and can relieve the first encapsulation layer and the third encapsulation layer.
  • the stress of the encapsulation layer can also include water-absorbing materials such as desiccant to absorb substances such as water and oxygen that have penetrated into the interior.
  • At least one embodiment of the present disclosure provides a display panel including the display substrate in any of the foregoing embodiments.
  • a packaging cover plate may be provided, and the switching elements and light emitting devices in the display substrate are located between the packaging cover plate and the base substrate of the display substrate, so that the packaging cover plate The above components can be protected.
  • a touch substrate may be provided on the display side of the display substrate to enable the display panel to obtain a touch display function.
  • a polarizing layer may be provided on the display side of the display substrate.
  • the polarizing layer may include a polarizer, a retardation film (for example, a quarter wave plate), etc.
  • a color film may be provided on the display side of the display substrate.
  • the color film can absorb light from the external environment, thereby reducing the adverse effects of ambient light on the display image of the display panel, and improving the display effect of the display panel.
  • a light splitting element such as a light splitting grating, etc.
  • the display panel can have a three-dimensional display function.
  • the display panel can be any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, or a navigator.
  • a display function such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, or a navigator.
  • At least one embodiment of the present disclosure provides a method for manufacturing a pixel unit, including: forming a dielectric layer; forming a switching element including an active layer on the dielectric layer; forming a first light-shielding structure at least part of the same layer as the dielectric layer; wherein, The orthographic projection of the first light shielding structure on the surface where the active layer is located is outside the orthographic projection of the active layer on the surface where the active layer is located.
  • the first light-shielding structure is located around the active layer and is at least partially in the same layer as the dielectric layer.
  • the first light shielding structure can shield at least part of the light, thereby reducing the increase in leakage current caused by the photogenerated carriers generated by the light irradiating the active layer, and improving the stability of the switching element.
  • forming the dielectric layer includes: patterning the dielectric layer to form at least a portion of the sidewall of the uneven structure in the dielectric layer.
  • the sidewall formed with the concave-convex structure can make the first light shielding structure extend in the direction parallel to the surface where the active layer is located. , Increasing the shielding area of the first light shielding structure to light obliquely irradiating the active layer from the side of the dielectric layer away from the active layer, further reducing the risk of the active layer being irradiated by light.
  • patterning the dielectric layer to form an opening or groove in the dielectric layer, and forming the sidewall of the opening or groove as a convex-concave structure, and forming the first light-shielding structure includes: A light-shielding material layer is deposited on the dielectric layer to fill the opening or groove, and the light-shielding material layer is patterned to form a first light-shielding structure; wherein the dielectric layer surrounds the switching element.
  • the dielectric layer is formed as a stack of at least two sub-dielectric layers.
  • the different sub-dielectric layers can be patterned separately, so that the sidewalls of the recessed structure are formed to have a concave-convex structure, which can reduce manufacturing The difficulty of the process.
  • the dielectric layer is a stack composed of at least two sub-dielectric layers, and forming the dielectric layer includes: forming a second sub-dielectric layer, and A first sub-dielectric layer is formed on the layer; the first sub-dielectric layer and the second sub-dielectric layer are patterned to form a first opening in the first sub-dielectric layer; after the first opening is formed in the first sub-dielectric layer, Using the first sub-dielectric layer as a mask, the second sub-dielectric layer is etched using an atmosphere to form a second opening or a second groove in the second sub-dielectric layer; wherein the first sub-dielectric layer and the second sub-dielectric layer are formed The etching ratio of the atmosphere to the material of the second sub-dielectric layer is greater than the etching ratio of the material of the first sub-dielectric layer.
  • the part of the first light-shielding structure that is in the same layer as the second sub-dielectric layer can extend toward the active layer to improve the light-shielding effect of the first light-shielding structure on the active layer.
  • it is prevented that the part of the first light-shielding structure in the same layer as the first sub-dielectric layer is too close to the active layer, causing the substance (such as hydrogen, etc.) of the first light-shielding structure to invade the active layer.
  • the above method makes it difficult to separate the first light-shielding structure from the dielectric layer, and increases the stability of the first light-shielding structure.
  • the structure of the pixel unit obtained according to the above-mentioned manufacturing method can refer to the related content in the foregoing embodiment (for example, the embodiment shown in FIG. 1 to FIG. 8B), which is not repeated here.
  • the manufacturing process of the pixel unit may include the following processes as shown in FIGS. 10A to 10F and FIG. 6.
  • a base substrate 10 is provided and a light-shielding material film is deposited on the base substrate, a patterning process is performed on the light-shielding material film to form a second light-shielding structure 400, and then three light-shielding structures are sequentially deposited on the second light-shielding structure 400.
  • An insulating material film is used to form a third sub-dielectric layer 130c, a second sub-dielectric layer 120c, and a first sub-dielectric layer 110c that cover the second light-shielding structure 400 and are sequentially stacked on the base substrate 10.
  • the patterning process may be a photolithography patterning process, which may include, for example, coating a photoresist layer on the structure layer to be patterned, and exposing the photoresist layer using a mask, The exposed photoresist layer is developed to obtain a photoresist pattern, the structure layer is etched using the photoresist pattern, and then the photoresist pattern is optionally removed.
  • a photolithography patterning process may include, for example, coating a photoresist layer on the structure layer to be patterned, and exposing the photoresist layer using a mask, The exposed photoresist layer is developed to obtain a photoresist pattern, the structure layer is etched using the photoresist pattern, and then the photoresist pattern is optionally removed.
  • the material forming the second light-shielding structure 400 may be metal, such as molybdenum or molybdenum-niobium alloy, and the thickness may be 0.1-0.2um.
  • a mixed acid for example, including at least two of hydrochloric acid, nitric acid, sulfuric acid, hydrofluoric acid, or other types of acids
  • hydrochloric acid for example, including at least two of hydrochloric acid, nitric acid, sulfuric acid, hydrofluoric acid, or other types of acids
  • the material of the third sub-dielectric layer 130c is silicon oxide
  • the material of the second sub-dielectric layer 120c is silicon nitride
  • the material of the first sub-dielectric layer 110c is silicon oxide.
  • the thickness of the third sub-dielectric layer 130c may be 0.2-0.25um
  • the thickness of the second sub-dielectric layer 120c may be 0.07-0.1um
  • the thickness of the first sub-dielectric layer 110c may be 0.2-0.25um.
  • the dielectric layer 100c can make the subsequently formed first light-shielding structure have a better light-shielding effect, and the separation distance between the first light-shielding structure and the active layer meets the requirements, the substance of the first light-shielding structure (such as hydrogen, etc.) It is difficult to penetrate the active layer.
  • a photoresist is deposited on the dielectric layer 100c, and the photoresist is developed to form a photoresist pattern 1.
  • the photoresist pattern 1 includes an opening 2 exposing the dielectric layer 100c.
  • the thickness of the photoresist pattern may be 2.0um ⁇ 2.2um.
  • the width of the portion of the photoresist pattern 1 located between the openings 2 can be designed according to the size of the switching element.
  • the width of the portion of the photoresist pattern 1 located between the openings 2 can be 6um-10um.
  • the photoresist may not be subjected to a hard Bake process. In this case, the photoresist pattern 1 will form an internal recessed shape, that is, the photoresist
  • the glue pattern 1 shrinks inwardly in the middle part of the direction perpendicular to the surface of the base substrate 10.
  • the first sub-dielectric layer 110c is patterned (eg, dry-etched) using the photoresist pattern 1 as a mask to form a first opening 111c corresponding to the opening 2 in the first sub-dielectric layer 110c.
  • the material of the second sub-dielectric layer 120c is silicon nitride
  • the material of the first sub-dielectric layer 110c is silicon oxide.
  • the atmosphere for etching the first sub-dielectric layer 110c can be made of tetrafluoroethylene. Carbon (CF 4 ) and oxygen (O 2 ) are mixed.
  • this atmosphere has a larger etching selection ratio to silicon oxide, so that this atmosphere is only used to etch the first sub-dielectric layer 110c .
  • the flow rate of CF 4 can be 2000-2500 sccm, and the flow rate of O 2 can be 1000-1500 sccm, with high source power and high bias power.
  • the photoresist pattern 1 is formed to have an internal recessed shape as shown in FIG. 10C, the lateral oxygen ashing is slower.
  • the sidewall of the first opening 111c and the surface of the base substrate 100 are basically vertical.
  • the second sub-dielectric layer 120c is patterned (for example, dry etching) using the photoresist pattern 1 and the first sub-dielectric layer 110c as a mask, so as to form the second sub-dielectric layer 120c and the first sub-dielectric layer 120c.
  • the opening 111c corresponds to the second opening 121c.
  • the material of the third sub-dielectric layer 130c is silicon oxide
  • the material of the second sub-dielectric layer 120c is silicon nitride
  • the material of the first sub-dielectric layer 110c is silicon oxide.
  • the atmosphere can be changed from four to four. Carbon fluoride (SF 6 ) and oxygen (O 2 ) are mixed.
  • this atmosphere has a greater etching selection ratio to silicon nitride, so that this atmosphere is only used to etch the second sub-dielectric layer 120c.
  • the flow rate of SF 6 can be 2000-2500 sccm
  • the flow rate of O 2 can be 600-800 sccm
  • high source power and low bias power because SF 6 contains a lot of fluorine, it is an isotropic etching gas
  • the etching rate of this atmosphere to silicon oxide is very slow (silicon oxide needs to rely on the bias power bombardment to open the Si-O bond to be easier to etch), while the etching rate of silicon nitride Higher (Si-N bond energy is small, and active SF groups can directly react with it).
  • the second opening 121c has a larger width than the first opening 111c, that is, the orthographic projection of the first opening 111c on the base substrate 10 is within the orthographic projection of the second opening 121c
  • the third sub-dielectric layer 130c is patterned (for example, dry-etched) using the photoresist pattern 1 and the first sub-dielectric layer 110c as a mask, so as to form the third sub-dielectric layer 130c and the first sub-dielectric layer 130c.
  • the opening 1 corresponds to the third opening 131c.
  • the material of the second sub-dielectric layer 120c is silicon nitride
  • the material of the third sub-dielectric layer 130c is silicon oxide.
  • the atmosphere for etching the third sub-dielectric layer 130c can be made of tetrafluoroethylene. Carbon (CF 4 ) and oxygen (O 2 ) are mixed.
  • this atmosphere has a greater etching selection ratio to silicon oxide, so that this atmosphere is only used to etch the third sub-dielectric layer 130c .
  • the flow rate of CF 4 can be 2000-2500 sccm
  • the flow rate of O 2 can be 1000-1500 sccm, with high source power and high bias power.
  • the photoresist pattern 1 is formed to have an internal recessed shape as shown in FIG. 10E, the lateral oxygen ashing is slower.
  • the sidewall of the third opening 131c and the surface of the base substrate 100 are basically Vertically, the third opening 131c corresponds to the first opening 111c and has approximately the same size, that is, the orthographic projection of the third opening 131c and the first opening 111c on the base substrate 10 are substantially coincident.
  • the remaining photoresist pattern 1 can be removed by wet stripping.
  • the first opening 111c, the second opening 121c, and the third opening 131c constitute a recessed structure 101c, and the sidewall 1011c of the recessed structure 101c is a surface with a concave-convex structure.
  • a light-shielding material is applied (such as coating, inkjet printing or other methods) on the dielectric layer 100c, and the light-shielding material fills the recess structure 101c, and the film layer formed by the light-shielding material is patterned to form a first light-shielding Structure 300c.
  • the light-shielding material used to form the first light-shielding structure 300c may be BM (Black Matrix) glue.
  • the BM glue has certain fluidity, so that it can fill the recessed structure 101c (for example, the first opening 111c, the second opening 121c, and the third opening 131c).
  • the BM glue is post-baked.
  • the thickness of the BM can be 0.8um to 1.1um.
  • the thickness of the portion of the first light shielding structure 300c in the same layer as the dielectric layer 100c (the first portion in the foregoing embodiment) may be 0.6 to 0.8um, and the portion of the first light shielding structure 300c protruding beyond the dielectric layer 100c ( The thickness of the second part) in the foregoing embodiment may be 0.2-0.3um.
  • the film layer formed by the BM glue may be patterned to form the first light-shielding structure 300c and the black matrix as shown in FIG. 8A 600.
  • a manufacturing process of a switching element is performed on the dielectric layer 100c, and the process may include the following processes.
  • a semiconductor material is deposited on the dielectric layer 100c to perform a patterning process (such as photolithography, wet etching) to form the active layer 210.
  • the semiconductor material may be indium tin oxide (IGZO), and the thickness may be 0.05-0.1um.
  • a gate insulating material film is deposited on the active layer 210, the material may be silicon oxide, and the thickness may be 0.1um ⁇ 0.2um.
  • a conductive material film layer is deposited on the gate insulating material film and a patterning process is performed to form the gate electrode 220.
  • the material of the gate electrode may be metal such as copper, and the thickness may be 0.4-0.5um.
  • the thickness of the photoresist used can be 2.0-2.2um
  • the photoresist can be a positive photoresist
  • the photoresist is formed after the mask is completed.
  • the side surface of the resist pattern may be an inclined surface, for example, the inclination angle of the inclined surface may be 60-70°.
  • the conductive material film layer is first wet-etched to form a gate electrode.
  • the gate electrode material includes copper
  • the copper wet-etching can be performed with H 2 O 2 solution.
  • dry etching equipment is used to dry-etch the gate insulating material film through the above-mentioned photoresist pattern and gate electrode 220 to form the gate insulating layer 240.
  • a high content of CF 4 and a low content of CF 4 can be used.
  • O 2 mixed gas for dry engraving, the flow of CF 4 can be 2000-2500 sccm, and the flow of O 2 can be 1000-1500 sccm.
  • the portions of the active layer 210 that are not covered by the gate electrode 220 and the gate insulating layer 240 may be subjected to a conductive treatment.
  • a conductive treatment ammonia (NH 3 ) or helium (He) can be used.
  • the remaining photoresist may be removed by wet stripping, and then a thin film of insulating material may be deposited on the base substrate 10 to form
  • the interlayer dielectric layer 250 the material of the interlayer dielectric layer 250 may be silicon oxide, silicon nitride, silicon oxynitride, etc., and the thickness may be 0.45 to 0.6um.
  • a via hole exposing the active layer 210 is formed in the interlayer dielectric layer 250, and then a conductive material film layer is deposited on the interlayer dielectric layer 250, and the conductive material film layer passes through the via hole of the interlayer dielectric layer 250 and the active layer.
  • the layer 210 is connected, and the conductive material film layer is patterned to form a source and drain electrode layer (drain electrode 231 and source electrode 232).
  • the drain electrode 231 and the source electrode 232 are connected to each other through different vias formed in the interlayer dielectric layer 250.
  • the source layer 210 is connected.
  • the material for forming the source and drain electrode layers can be metals such as copper and aluminum, and the thickness can be 0.5-0.7um.
  • an insulating material can be deposited on the base substrate to form a passivation layer (PVX), the material can be silicon oxide, silicon nitride, silicon oxynitride, etc., and the thickness can be 0.3-0.5um .
  • PVX passivation layer
  • the material can be silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the thickness can be 0.3-0.5um .
  • a manufacturing process of the light emitting device may be performed on the passivation layer.
  • the manufacturing process of the passivation layer and the light-emitting device can refer to the conventional manufacturing process, and the structure of the formed passivation layer and the light-emitting device can refer to the related description in the embodiment shown in FIG. 7, which will not be repeated here.

Abstract

一种像素单元及其制造方法、显示基板。该像素单元包括电介质层(100)、开关元件(200)和第一遮光结构(300)。开关元件(200)包括有源层(210)且位于所述电介质层(100)上，第一遮光结构(300)至少部分与电介质(100)层同层，所述第一遮光结构(300)在所述有源层(210)所在面上的正投影位于所述有源层(210)在所述有源层(210)所在面上的正投影之外。该第一遮光结构(300)设置在所述有源层(210)的周围，可以对沿所述电介质层(100)射向所述有源层(210)的侧表面的光进行遮挡，从而减少因光照射有源层(210)产生的光生载流子导致的漏电流增加，提高开关元件(200)的稳定性。

Description

像素单元及其制造方法、显示基板
本申请要求于2019年03月07日递交的中国专利申请第201910172155.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种像素单元及其制造方法、显示基板。
背景技术
通常，薄膜晶体管被用作显示面板的驱动元件。薄膜晶体管中的有源层受到光照射后会产生光生载流子，导致薄膜晶体管的漏电流增加，从而影响显示面板的显示画面的质量，例如会产生串扰、残像等现象。
发明内容
本公开至少一个实施例提供一种像素单元，该像素单元包括电介质层、开关元件和第一遮光结构。开关元件包括有源层且位于所述电介质层上，第一遮光结构至少部分与所述电介质层同层，所述第一遮光结构在所述有源层所在面上的正投影位于所述有源层在所述有源层所在面上的正投影之外。
例如，在本公开至少一实施例提供的像素单元中，所述电介质层设置在所述第一遮光结构的与所述电介质层同层的部分的至少相对的两侧。
例如，在本公开至少一实施例提供的像素单元中，所述电介质层的与所述第一遮光结构同层且面向所述第一遮光结构的侧壁的至少一部分形成为凸凹结构。
例如，在本公开至少一实施例提供的像素单元中，在平行于所述电介质层的面上，所述电介质层设置有围绕所述开关元件的开口或槽，所述开口或槽的侧壁形成为所述凸凹结构。
例如，在本公开至少一实施例提供的像素单元中，所述电介质层为由至少两个子电介质层构成的叠层。
例如，在本公开至少一实施例提供的像素单元中，相邻的所述子电介质 层中的所述开口连通或者相邻的所述子电介质层之一的开口与另一个的槽连通，以及相邻的所述子电介质层中的所述开口或者相邻的所述子电介质层之一的开口与另一个的槽在所述有源层所在面上的正投影至少部分不交叠。
例如，在本公开至少一实施例提供的像素单元中，所述电介质层包括第一子电介质层和第二子电介质层，所述第一子电介质层位于所述第二子电介质层和所述有源层之间，所述第一子电介质层中设置有第一开口，所述第二子电介质层中设置有第二开口或者第二槽，所述第一开口和所述第二开口或者第二槽连通，并且所述第一开口在所述有源层所在面上的正投影位于所述第二开口或者第二槽在所述有源层所在面上的正投影之内。
例如，在本公开至少一实施例提供的像素单元中，所述电介质层包括至少三个所述子电介质层，位于两侧的所述子电介质层的所述开口或槽在所述有源层所在面上的正投影的投影位于中间的所述子电介质层的开口在所述有源层所在面上的正投影之内。
例如，在本公开至少一实施例提供的像素单元中，所述第一遮光结构包括第一部分和第二部分，所述第一部分与所述电介质层同层，所述第二部分与所述电介质层位于不同层。
例如，在本公开至少一实施例提供的像素单元中，所述第二部分的背离所述电介质层的一端至所述电介质层所在面的距离大于或等于所述有源层的背离所述电介质层的表面至所述电介质层所在面的距离。
例如，本公开至少一实施例提供的像素单元还包括黑矩阵，所述像素单元包括显示区和位于所述显示区周围的非显示区，所述黑矩阵和所述第一遮光结构位于所述非显示区，所述黑矩阵与所述第二部分同层且为一体化结构。
例如，本公开至少一实施例提供的像素单元还包括第二遮光结构，所述第二遮光结构位于所述电介质层背离所述有源层的一侧，所述有源层在所述有源层所在面上的正投影与所述第二遮光结构在所述有源层所在面上的正投影重合，或者所述有源层在所述有源层所在面上的正投影位于所述第二遮光结构在所述有源层所在面上的正投影之内。
例如，在本公开至少一实施例提供的像素单元中，所述第二遮光结构在所述有源层所在面上的正投影位于所述第一遮光结构在所述有源层所在面上的正投影的内侧。
例如，在本公开至少一实施例提供的像素单元还包括发光器件，所述发光器件位于所述开关元件的背离所述电介质层的一侧，所述发光器件包括依次叠置在所述开关元件上的第一电极层、发光功能层和第二电极层，所述第一电极层和所述第二电极层之一为反射电极层。
本公开至少一实施例提供一种显示基板，包括上述任一实施例中所述的像素单元。
本公开至少一实施例提供一种像素单元的制造方法，包括：形成电介质层；在所述电介质层上形成包括有源层的开关元件；形成至少部分与所述电介质层同层的第一遮光结构；其中，所述第一遮光结构在所述有源层所在面上的正投影位于所述有源层在所述有源层所在面上的正投影之外。
例如，在本公开至少一实施例提供的像素单元的制造方法中，形成所述电介质层包括：对所述电介质层进行构图以在所述电介质层中形成至少一部分为凹凸结构的侧壁。
例如，在本公开至少一实施例提供的像素单元的制造方法中，对所述电介质层构图以在所述电介质层中形成开口或槽，所述开口或槽的侧壁形成为所述凸凹结构，形成所述第一遮光结构包括：在所述电介质层上沉积遮光材料层以填充所述开口或槽，构图所述遮光材料层以形成所述第一遮光结构；其中，所述电介质层围绕所述开关元件。
例如，在本公开至少一实施例提供的像素单元的制造方法中，所述电介质层形成为由至少两个子电介质层构成的叠层。
例如，在本公开至少一实施例提供的像素单元的制造方法中，所述电介质层为由至少两个子电介质层构成的叠层，形成所述电介质层包括：形成第二子电介质层，并在所述第二子电介质层上形成第一子电介质层；对所述第一子电介质层和所述第二子电介质层进行构图，以在所述第一子电介质层中形成第一开口；在所述第一子电介质层中形成所述第一开口后，以所述第一子电介质层为掩模，利用气氛刻蚀所述第二子电介质层以在所述第二子电介质层中形成第二开口或第二槽；其中，形成所述第一子电介质层和所述第二子电介质层的材料不同，所述气氛对所述第二子电介质层的材料的刻蚀比大于对所述第一子电介质层的材料的刻蚀比。
在本公开至少一个实施例提供的像素单元及其制造方法、显示基板中，第一遮光结构位于有源层周围且至少部分与电介质层同层，因此至少对于沿 着电介质层且从有源层的侧面射向有源层的光线，第一遮光结构可以对该光线的至少部分进行遮挡，从而减少因光照射有源层产生的光生载流子导致的漏电流增加，提高开关元件的稳定性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种像素单元的部分结构的截面图；
图2A为本公开一些实施例提供的另一种像素单元的部分结构的截面图；
图2B为图2A所示像素单元的一种结构的平面图；
图2C为图2A所示像素单元的另一种结构的平面图；
图3为本公开一些实施例提供的另一种像素单元的部分结构的截面图；
图4为本公开一些实施例提供的另一种像素单元的部分结构的截面图；
图5A为本公开一些实施例提供的另一种像素单元的部分结构的截面图；
图5B为本公开一些实施例提供的另一种像素单元的部分结构的截面图；
图6为本公开一些实施例提供的另一种像素单元的部分结构的截面图；
图7为本公开一些实施例提供的另一种像素单元的截面图；
图8A为本公开一些实施例提供的另一种像素单元的截面图；
图8B为图8A所示像素单元的平面图；
图9为本公开一些实施例提供的一种显示基板的平面图；以及
图10A～图10F为本公开一些实施例提供的一种像素单元的制造方法的过程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描 述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
大尺寸有机发光二极管(Organic Light-Emitting Diode,OLED)显示面板具有高对比度、自发光等优势，从而具有很好的发展前景。OLED显示面板中需要设置开关元件例如薄膜晶体管(Thin Film Transistor，TFT)等以实现控制电路，从而对OLED显示面板的发光等功能进行控制。在沿着OLED显示面板的显示侧至非显示侧的方向上，TFT的上方和/或下方会设置挡光结构以防止该方向上的光照射薄膜晶体管中的有源层，但是OLED显示面板中的信号线等的排布非常密集，光线在显示面板中被信号线等反射后可能射向有源层的侧表面，而TFT的上方和/或下方设置的挡光结构无法遮挡该光线，导致有源层中因光生载流子而产生漏电流，薄膜晶体管性能不稳定，导致OLED显示面板显示不良。
本公开至少一个实施例提供一种像素单元及其制造方法、显示基板。该像素单元包括电介质层、开关元件和第一遮光结构。开关元件包括有源层且位于电介质层上，第一遮光结构至少部分与电介质层同层，第一遮光结构在有源层所在面上的正投影位于有源层在有源层所在面上的正投影之外。该第一遮光结构位于有源层周围且至少部分与电介质层同层，因此至少对于沿着电介质层且从有源层的侧面射向有源层的光线，第一遮光结构可以对该光线的至少部分进行遮挡，从而减少因光照射有源层产生的光生载流子导致的漏电流增加，提高开关元件的稳定性。
下面，结合附图对根据本公开至少一个实施例中的像素单元及其制造方法、显示基板进行说明。
图1为本公开一些实施例提供的一种像素单元的部分结构的截面图，其示出像素单元的开关元件所在区域的部分结构。
例如，在本公开至少一个实施例中，如图1所示，像素单元包括电介质层100、开关元件(未示出，可以参见图2A中的开关元件200)和第一遮光结构300。开关元件包括有源层210且位于电介质层100上，第一遮光结构300的至少部分与电介质层100同层，第一遮光结构300在有源层210所在面上的正投影位于有源层210在有源层210所在面上的正投影之外。有源层210所在面例如为图1中有源层210的上表面或下表面所在的平面。例如，如图1所示，第一遮光结构300的一部分与电介质层100同层，另一部分突出于电介质层100之外，从而遮挡从像素单元的侧面射向有源层210的光线(图1中的虚线“→”)。例如，第一遮光结构300的与电介质层100同层的部分可以遮挡沿着电介质层100射向有源层210侧表面的光线S1，第一遮光结构300的突出于电介质层100之外的部分可以遮挡从电介质层100之外射向有源层210的侧表面的光线S2。
例如，有源层210的材料可以包括非晶硅、多晶硅，或者氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物等。
在本公开至少一个实施例中，电介质层100的类型及材料可以根据开关元件的类型进行设置，开关元件的类型可以根据需要进行选择。例如，开关元件可以为薄膜晶体管，薄膜晶体管可以为顶栅型薄膜晶体管、底栅型薄膜晶体管、双栅型薄膜晶体管等。
例如，在本公开一些实施例中，像素单元中的开关元件为顶栅型薄膜晶体管。示例性的，如图2A所示，像素单元中的开关元件200包括有源层210、栅电极220和源漏电极层(包括漏电极231和源电极232)，有源层210位于栅电极220和电介质层100之间，有源层210和栅电极220之间设置有栅绝缘层240。例如，开关元件200包括覆盖栅电极220的层间介质层250，漏电极231和源电极232位于层间介质层250的背离栅电极220的表面上，并且层间介质层250中设置过孔，漏电极231和源电极232通过该过孔分别连接有源层210的两端。例如，像素单元包括衬底基板10，以对像素单元的各个结构进行支撑。
例如，在像素单元中的开关元件为顶栅型薄膜晶体管的情况下，电介质 层100可以为缓冲层。缓冲层的材料可以包括氧化硅、氮化硅、氧氮化硅等，这些材料的致密性高，可以防止衬底基板10中的离子侵入有源层210。
例如，在本公开另一些实施例中，像素单元中的开关元件为顶栅型薄膜晶体管。例如，像素单元中的开关元件包括有源层、栅电极和源漏电极层，电介质层位于栅电极和有源层之间。例如，开关元件包括覆盖有源层的层间介质层，源漏电极层位于层间介质层的背离有源层的表面上，并且层间介质层中设置过孔，源漏电极层的漏电极和源电极通过该过孔分别连接有源层的两端。在该情况下，电介质层可以为栅绝缘层，以间隔有源层和栅电极。栅绝缘层的材料可以包括氮化硅、氧化硅、氧氮化硅、氧化铝、氮化铝或其他适合的材料等。
下面，以开关元件为顶栅型薄膜晶体管为例，对本公开下述至少一个实施例中的技术方案进行说明。
例如，在本公开至少一实施例提供的像素单元中，电介质层设置在第一遮光结构的与电介质层同层的部分的至少相对的两侧。
例如，在平行于衬底基板所在面(或者有源层所在面)的方向上，电介质层可以设置在遮光结构的朝向有源层的一侧和背离有源层的一侧。
示例性的，如图2A所示，沿着X轴方向上，第一遮光结构300的与电介质层100同层的部分的至少两侧具有电介质层100。如此，第一遮光结构300的与电介质层100同层的部分夹置在电介质层100中。例如，在本公开至少一个实施例中，如图2A所示，第一遮光结构300的与电介质层100同层的部分的侧壁与电介质层100的面向第一遮光结构300的侧壁接触。
例如，在本公开一些实施例中，第一遮光结构的与电介质层同层的部分的平面形状为闭合的环形，例如“口”字形。在平行于有源层所在面的方向上，第一遮光结构的与电介质层同层的部分的相对的两侧设置电介质层。示例性的，如图2A和图2B所示，第一遮光结构300的与电介质层100同层的部分在有源层210所在面上的正投影为闭合的环形，如此，可以加强第一遮光结构300对沿电介质层100射向有源层210的侧表面的光的遮挡面积，进一步降低有源层210被光照射的风险。
例如，在本公开另一些实施例中，第一遮光结构的与电介质层同层的部分的平面形状为线段形。如图2A和图2C所示，第一遮光结构300(图2C中未示出)包括多个平面形状为线段形的子遮光结构例如第一子遮光结构 3001、第二子遮光结构3002、第三子遮光结构3003和第四子遮光结构3004。第一子遮光结构3001、第二子遮光结构3002、第三子遮光结构3003和第四子遮光结构3004分布在有源层210的周围以对有源层210进行遮光。例如，如图2A和图2C所示，在平行于有源层210所在面的方向上，第一遮光结构300的与电介质层100同层的所有侧表面处都设置有电介质层100。需要说明的是，第一遮光结构包括的子遮光结构的数量可以根据需要进行设置，例如，可以在有源层210的受光照影响最大的一侧设置子遮光结构，如此，第一遮光结构在起到对开关元件的有源层遮光的同时具有较小的设计体积，形成第一遮光结构的材料的使用量减少以降低成本，降低因设置第一遮光结构对开关元件制造工艺的不良影响，并且简化像素单元的结构，降低像素单元制造工艺的难度。
第一遮光结构的与电介质层同层的部分的平面形状可以根据需要进行选择，不限于上述的闭合环形和线段形。下面，以第一遮光结构的与电介质层同层的部分的平面形状为如图2A和图2B所示的闭合环形为例，对本公开下述至少一个实施例中的技术方案进行说明。
例如，在本公开至少一实施例提供的像素单元中，在平行于电介质层所在面的方向上，电介质层设置有围绕开关元件的凹陷结构，第一遮光结构的与电介质层同层的部分填充在该凹陷结构中。示例性的，如图2A所示，电介质层100中形成有凹陷结构101，第一遮光结构300的一部分填充该凹陷结构101。
例如，在一些实施例中，凹陷结构可以设置为如图2A所示的开口，即，电介质层100在该凹陷结构101处断开，第一遮光结构300贯穿电介质层100。如此，可以加强第一遮光结构300对沿电介质层100射向有源层210的侧表面的光的遮挡，进一步降低有源层210被光照射的风险。例如，在另一些实施例中，凹陷结构可以设置为槽，槽的深度大于零且小于电介质层的厚度。
在本公开至少一个实施例中，凹陷结构(开口或槽)的形状可以根据需要进行设置。例如，凹陷结构的侧壁可以设置为平面、曲面或者具有凹凸形状的表面等。需要说明的是，凹陷结构的侧壁也为电介质层的与第一遮光结构同层且面向第一遮光结构的侧壁。例如，在本公开一些实施例提供的像素单元中，电介质层可以为单层结构也可以为多个子电介质层构成的叠层。例 如，在电介质层为多个子电介质层构成的叠层的情况下，电介质层的与第一遮光结构同层且面向第一遮光结构的侧壁可以由一个子电介质层的侧壁构成或者可以由多个子电介质层的侧壁构成。第一遮光结构与电介质层的结构(例如侧壁)相关，下面，结合电介质层的侧壁的不同设置方式，对第一遮光结构进行说明。
例如，在一些实施例中，如图2A所示，凹陷结构101的侧壁1011基本为平面。例如，侧壁1011所在面基本垂直于有源层210所在面。如此，在形成第一遮光结构300时，在第一遮光结构300能够填充凹陷结构101的情况下，形成第一遮光结构300的材料的流动性要求低或者不需要该材料具有流动性，使得第一遮光结构300填充凹陷结构101的工艺难度低。
例如，在本公开另一些实施例提供的像素单元中，电介质层的与第一遮光结构同层且面向第一遮光结构的侧壁的至少一部分形成为凸凹结构。
示例性的，如图3所示，电介质层100a的凹陷结构101a的侧壁1011a形成为凹凸结构1012a，以使得凹陷结构101a的侧壁1011a为具有凹凸形状的表面。例如，凹陷结构101a为开口，该开口的侧壁1011a的全部都形成为凹凸结构1012a。如此，在垂直于有源层210所在面的方向上，凹凸结构1012a的侧壁1011a使得凹陷结构101a的各部分的宽度不同，利用形成有凹凸结构1012a的侧壁1011a可以使得第一遮光结构在平行于有源层210所在面的方向上延伸，增加第一遮光结构300a对从电介质层100a的背离有源层210的一侧斜射向有源层210的光的遮挡面积，进一步降低有源层210被光照射的风险。
例如，在本公开至少一个实施例中，在电介质层的凹陷结构的侧壁形成为具有凹凸结构的情况下，在垂直于有源层所在面的方向上，凹凸结构的宽度较大的部分位于凹陷结构的底部(参见图3中的凹陷结构101a)或者位于凹陷结构的中部(参见图5A中的凹陷结构101c)。如此，可以在使得第一遮光结构在向有源层延伸以提高第一遮光结构对有源层的遮光效果的同时，防止第一遮光结构与有源层距离太近导致第一遮光结构的物质(例如氢等)侵入有源层。此外，上述设计使得第一遮光结构和电介质层不易分离，增加第一遮光结构的稳固性。
在本公开至少一个实施例中，对电介质层中形成凹陷结构且将凹陷结构的侧壁形成为具有凹凸结构的方式不做限制，可以根据实际工艺进行设计。 例如，在本公开至少一实施例提供的像素单元中，电介质层为由至少两个子电介质层构成的叠层。如此，在制造各个子电介质层的过程中，可以对不同的子电介质层分别进行构图工艺，从而使得凹陷结构的侧壁形成为具有凹凸结构，降低制造工艺的难度。
例如，在本公开至少一实施例提供的像素单元中，相邻的子电介质层中的开口连通或者相邻的子电介质层之一的开口与另一个的槽连通，以及相邻的子电介质层中的开口或者相邻的子电介质层之一的开口与另一个的槽在有源层所在面上的正投影至少部分不交叠。例如，相邻的子电介质层中的一个的开口或槽在有源层所在面上的正投影至少部分位于相邻的子电介质层中的另一个的开口或槽在有源层所在面上的正投影之外。如此，不同的子电介质层中，分别形成在平行于有源层所在面的方向上宽度不等的子凹陷结构(开口或者槽)，相应地，不同大小的子凹陷结构构成的凹陷结构的侧壁可以形成为具有凹凸结构。
下面，结合电介质层中子电介质层的不同数量，对凹陷结构的几种设置方式进行说明。
例如，在本公开一些实施例提供的像素单元中，电介质层包括第一子电介质层和第二子电介质层，第一子电介质层位于第二子电介质层和有源层之间，第一子电介质层中设置有第一开口，第二子电介质层中设置有第二开口或者第二槽，第一开口和第二开口或者第二槽连通，并且第一开口在在有源层所在面上的正投影位于第二开口或者第二槽在有源层所在面上的正投影之内。
示例性的，如图4所示，电介质层100b包括第一子电介质层110b和第二子电介质层120b，第一子电介质层110b位于有源层210和第二子电介质层120b之间。第一子电介质层110b中设置有第一开口111b，第二子电介质层120b中设置有第二开口121b，第一开口111b和第二开口121b连通，并且第一开口111b在有源层210所在面(或者衬底基板10)上的正投影位于第二开口121b在有源层210所在面(或者衬底基板10)上的正投影之内。如此，第一开口111b和第二开口121b使得电介质层100b的侧壁1011b形成为凹凸结构，第一遮光结构300b的位于第二开口121b的部分可以向有源层210延伸，以提高第一遮光结构300b对有源层210的遮光效果，而且第一遮光结构300b的位于第一开口111b的部分与有源层210之间保持一定的 间隔距离，以免第一遮光结构300b与有源层210距离太近导致第一遮光结构300b的物质(例如氢等)侵入有源层210。
在第一子电介质层110b中形成第一开口111b，第二子电介质层120b中形成第二开口121b的方法可以参见图10A～图10B所示实施例中的相关说明，在此不做赘述。
例如，在本公开至少一实施例提供的像素单元中，电介质层包括至少三个子电介质层，位于两侧的子电介质层的开口或槽在有源层所在面上的正投影的投影位于中间的子电介质层的开口在有源层所在面上的正投影之内。
示例性的，如图5A所示，电介质层100c包括依次叠置在衬底基板10上的第三子电介质层130c、第二子电介质层120c和第一子电介质层110c，有源层210位于第一子电介质层110c的上。第一子电介质层110c中设置有第一开口111c，第二子电介质层120c中设置有第二开口121c，第三子电介质层120c中设置有第三开口131c，第一开口111c、第二开口121c和第三开口131c连通，并且第一开口111c和第三开口131c在有源层210所在面(或者衬底基板10)上的正投影位于第二开口121c在有源层210所在面(或者衬底基板10)上的正投影之内。如此，第一开口111c、第二开口121c和第三开口131c使得电介质层100c的侧壁1011c形成为凹凸结构，第一遮光结构300c的位于第二开口121c的部分可以向有源层210延伸，以提高第一遮光结构300c对有源层210的遮光效果，而且第一遮光结构300c的位于第一开口111c的部分与有源层210之间保持一定的间隔距离，以免第一遮光结构300c与有源层210距离太近导致第一遮光结构300c的物质(例如氢等)侵入有源层210。
例如，在本公开另一些实施例中，可以对如图5A所示的电介质层100c的结构进行变形，以使得第一开口111c和第二开口121c在衬底基板10上的正投影位于第三开口131c在衬底基板10上的正投影之内，或者使得第一开口111c在衬底基板10上的正投影位于第二开口121c和第三开口131c在衬底基板10上的正投影之内。
例如，在本公开至少一实施例提供的像素单元中，第一遮光结构包括第一部分和第二部分，第一部分与电介质层同层，第二部分与电介质层位于不同层。示例性的，如图5A所示，第一遮光结构300c包括与电介质层100c同层的第一部分310c和突出于电介质层100c之外的第二部分320c。第二部 分320c的厚度影响第一遮光结构300c对有源层210的遮光效果。例如，第二部分320c的厚度越大，第一遮光结构300c的遮光效果越好。第二部分320c的厚度可以根据实际工艺进行确定，例如，可以在不影响像素单元中的开关元件等的性能的情况下，使得第二部分320c的设计厚度尽量大。
例如，在一些实施例中，第一遮光结构300c的第一部分310c在衬底基板10上的正投影可以位于第一遮光结构300c的第二部分320c在衬底基板10上的正投影内，参考图2A。在另一些实施例中，第一遮光结构300c的第二部分320c在衬底基板10上的正投影可以位于第一遮光结构300c的第一部分310c在衬底基板10上的正投影内，参考图4-图8A，此时，第一遮光结构300c的第一部分310c向有源层210的方向延伸，由此可以进一步提高第一遮光结构300c的遮挡面积，避免光从有源层210的侧面射入有源层210，从而降低有源层210被光照射的风险。
例如，在一些示例中，也可以是第一遮光结构300c的第一部分310c的靠近有源层210的一侧向有源层210延伸，而第一部分310c的远离有源层210的一侧不具有延伸结构，如图5B所示，此时，第一遮光结构300c的第一部分310c在衬底基板10上的正投影与第一遮光结构300c的第二部分320c在衬底基板10上的正投影部分重叠。本公开的实施例对第一遮光结构300c的具体形式不做限定，只要可以达到为有源层210遮光的效果即可。
例如，在本公开至少一实施例提供的像素单元中，第二部分的背离电介质层的一端至电介质层所在面(或者衬底基板)的距离大于或等于有源层的背离电介质层的表面至电介质层所在面(或者衬底基板)的距离。示例性的，如图5A所示，第二部分320c的高度L2大于有源层210的高度L1，如此，可以增加第一遮光结构300c对电介质层300c的遮挡面积，进一步降低有源层210被光照射的风险。
例如，本公开至少一实施例提供的像素单元还包括第二遮光结构，第二遮光结构位于电介质层背离有源层的一侧，有源层在有源层所在面上的正投影与第二遮光结构在有源层所在面上的正投影重合，或者有源层在有源层所在面上的正投影位于第二遮光结构在有源层所在面上的正投影之内。示例性的，如图6所示，衬底基板10和电介质层100c之间设置有第二遮光结构400。第二遮光结构400可以遮挡从衬底基板10所在一侧射向有源层210的光线。
例如，在本公开一些实施例中，开关元件为如图6所示的顶栅型薄膜晶 体管，第二遮光结构400可以单独设置，例如第二遮光结构400为遮光金属且不与其它导电结构例如信号线等相连。例如，在本公开另一些实施例中，开关元件为底栅型或双栅型薄膜晶体管，第二遮光结构可以设置为栅电极。
例如，第二遮光结构可以包括金属材料，可以形成单层或多层结构，例如，形成为单层的钼或钼铌合金、单层铝结构、单层钼结构或者由两层钼夹设一层铝的结构。
例如，在本公开至少一实施例提供的像素单元中，第二遮光结构在有源层所在面上的正投影位于第一遮光结构在有源层所在面上的正投影的内侧。这里的内侧是指，第一遮光结构在有源层所在面上的正投影的更靠近有源层在有源层所在面上的正投影的一侧。如此，如图6所示，第一遮光结构300c和第二遮光结构400配合可以遮挡从衬底基板10所在侧射向有源层210的光线。例如，如图6所示，电介质层100c设置为使得第一遮光结构300c的与第二子电介质层120c接触的部分可以向有源层210延伸，如此，可以缩小第一遮光结构300c和第二遮光结构400的间隙，提高第一遮光结构300c和第二遮光结构400对光线的遮光效果。
例如，在本公开至少一实施例提供的像素单元还包括发光器件，发光器件位于开关元件的背离电介质层的一侧，发光器件可以包括依次叠置在开关元件上的第一电极层、发光功能层和第二电极层。示例性的，如图7所示，像素单元包括发光器件500，发光器件500包括第一电极层510、发光功能层520和第二电极层530，发光功能层520夹置在第一电极层510和第二电极层530之间，第一电极层510与开关元件的漏电极231电连接。例如，像素单元包括钝化层260，钝化层260位于开关元件(例如其中的漏电极231)和发光器件500之间，钝化层260中形成有开孔，第一电极层510与漏电极231通过该开孔连接。
例如，在一些实施例中，可以在钝化层和发光器件之间设置平坦层，以提高第一电极层的平坦度，从而提高发光器件的发光性能。例如，在另一些实施例中，在钝化层设置为具有平坦化作用的情况下，钝化层和发光器件之间可以不需要设置平坦层，简化像素单元的结构并降低像素单元的设计厚度，有利于像素单元以及包括该像素单元的产品(例如显示基板、显示面板)的轻薄化设计。
例如，在本公开至少一个实施例中，第一电极层和第二电极层之一设置 为反射电极层。例如，第一电极层和第二电极层之另一可以设置为透明电极层或者半透明电极层。如此，像素单元的显示方式可以实现为顶发射或者底发射。例如，如图7所示，在第一电极层510设置为反射电极的情况下，像素单元的显示方式为顶发射；在第二电极层520设置为反射电极的情况下，像素单元的显示方式为底发射。
例如，在本公开至少一个实施中，第一电极层为发光器件的阳极，第二电极层为发光器件的阴极。阳极作为发光器件正向电压的连接层，具有较好的导电性能以及较高的功函数值。例如，阳极可由具有高功函数的导电材料形成，阳极的电极材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In 2O 3)、氧化铝锌(AZO)和碳纳米管等；阴极作为发光器件负向电压的连接层，具有较好的导电性能和较低的功函数值，阴极可以采用低功函数值的金属材料，比如锂、镁、钙、锶、铝、铟等，或上述低功函数值的金属材料与铜、金、银的合金制成。此外，对于上述金属材料形成的阴极，在阴极需要设置为透光的情况下，需要该阴极的厚度设计为能够透光。
例如，在本公开至少一个实施例中，在发光器件的第一电极层(阳极)设置为反射电极的情况下，阳极可以设计为多个膜层构成的叠层，部分膜层可以由透明导电材料形成(例如ITO、IZO等)，另一部分膜层为不透明的导电材料(例如铬、银等金属)。
例如，在本公开至少一个实施例中，透明可以表示光的透过率为75％～100％，半透明可以表示光的透过率为25％～75％。
例如，在本公开至少一个实施例提供中，发光功能层包括有机发光层。例如，发光功能层还可以包括空穴注入层、空穴传输层、电子传输层和电子注入层等中的一种或组合。例如，在发光器件中，阳极、空穴注入层、空穴传输层、有机发光层、电子传输层、电子注入层和阴极依次叠置。例如，有机发光功能层中还可以设置电子阻挡层和空穴阻挡层，电子阻挡层位于阳极和有机发光层之间，空穴阻挡层位于阴极和有机发光层之间，但不限于此。
例如，在本公开至少一个实施例中，对发光器件的发光颜色不做限制。例如，在发光器件中，发光功能层的有机发光层的材料可以根据需求的发光颜色进行选择。例如，有机发光层根据所使用的有机发光材料的不同，可以发射红光、绿光、蓝光、黄光、白光或者其它颜色的光。例如，在一些实施 例中，多个像素单元的发光器件的发光功能层设置为一体化以发出同一颜色的光线，例如白光、蓝光、黄光或者其它颜色的光线。例如，在另一些实施例中，如图7所示，像素单元中设置有像素界定层501，像素界定层501将不同像素单元中的发光器件的发光功能层间隔，以使得不同像素单元的发光器件可以设置为分别发出不同颜色的光线。
例如，本公开至少一实施例提供的像素单元还包括黑矩阵，像素单元包括显示区和位于显示区周围的非显示区，黑矩阵和第一遮光结构位于非显示区。黑矩阵用于限定显示区和非显示区，防止漏光，避免相邻像素之间发出的光线相互干扰。
例如，在本公开至少一个实施例中，在第一遮光结构包括与电介质层同层的第一部分和突出于电介质层之外的第二部分的情况下，黑矩阵可以设置为与第二部分同层且为一体化结构。示例性的，如图8A和图8B所示，像素单元设置为具有底发射式的显示功能，黑矩阵600与第一遮光结构300c(第一遮光结构300c的第二部分)为一体化结构，如此，在制造第一遮光结构300c的过程中，同步制造黑矩阵600，简化像素单元的制造工艺，降低成本。此外，如图8A和图8B所示，黑矩阵600与第一遮光结构300c、开关元件200位于像素单元的非显示区1100，并用于限定像素单元的显示区1200。例如，发光器件500至少部分位于显示区1200中。例如，如图8A所示，在开关元件200所在的区域，设置有第二遮光结构400，如此，黑矩阵600、第一遮光结构300c和第二遮光结构400配合，可以防止像素单元的非显示区漏光。
本公开至少一实施例提供一种显示基板，该显示基板可以包括上述任一实施例中的像素单元。例如，如图9所示，显示基板由多个阵列排布的像素单元(图9中的像素单元1000a、1000b、1000c、1000d等)构成，像素单元的结构可以参见前述实施例中的相关说明，在此不做赘述。
例如，显示面板包括多行多列的像素单元。例如，每四个像素单元可以为一组，例如，每行(沿X轴方向)的像素单元中，每组的像素单元1000a、1000b、1000c、1000d可以分别为红色子像素R、绿色子像素G、蓝色子像素B和白色子像素W。本公开的实施例不限制每个组的像素单元的数量和类型，例如每组可以包括红色子像素R、绿色子像素G、蓝色子像素B而不包括白色子像素W，又例如每个像素单元可以包括红色子像素R、绿色子像 素G、蓝色子像素B以及黄色子像素Y等。
例如，在本公开至少一个实施例中，显示基板可以为刚性基板；或者显示基板也可以为柔性基板，从而使得显示基板可以应用于柔性显示领域。例如，在显示基板为刚性基板的情况下，衬底基板可以为玻璃板、石英板、金属板或树脂类板件等。例如，在显示基板为柔性基板的情况下，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。
例如，在本公开至少一个实施例中，显示基板可以用于微型OLED显示领域中，相应地，衬底基板可以为硅晶圆。例如，该硅晶圆的材料可以为单晶硅，并且该硅晶圆的平面形状可以为圆形也可以为其它形状。
例如，在本公开至少一个实施例中，显示基板还可以包括封装层，封装层位于发光器件的背离衬底基板的一侧，封装层至少覆盖发光器件。封装层可以对显示基板进行封装，防止外界水、氧等侵入显示基板内部，从而对显示基板内部的构件(例如发光器件)进行保护。
例如，封装层可以为单层结构也可以为至少两层的复合结构。例如，封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。例如，封装层可以包括依次设置在发光器件上的第一封装层、第二封装层和第三封装层。例如，第一封装层和第三封装层的材料可以包括无机材料，例如氮化硅、氧化硅、氮氧化硅等，无机材料的致密性高，可以防止水、氧等的侵入；例如，第二封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一封装层和第三封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
本公开至少一个实施例提供一种显示面板，该显示面板包括前述任一实施例中的显示基板。例如，在本公开至少一个实施例提供的显示面板中，可以设置封装盖板，显示基板中的开关元件、发光器件等位于封装盖板和显示基板的衬底基板之间，以使得封装盖板可以对上述元件进行保护。例如，在本公开至少一个实施例提供的显示面板中，可以在显示基板的显示侧设置触控基板以使得显示面板获得触控显示功能。
例如，在本公开至少一个实施例提供的显示面板中，显示基板的显示侧 可以设置偏光层，该偏光层可以包括偏振片、延迟片(例如1/4波片)等结构，如此，由外界环境射入显示基板中的光线不会从显示基板中出射，从而消除环境光对显示面板的显示图像的不良影响，提高显示面板的显示效果。
例如，在本公开至少一个实施例提供的显示面板中，显示基板的显示侧可以设置彩膜。彩膜可以吸收外界环境的光线，从而降低环境光对显示面板的显示图像的不良影响，提高显示面板的显示效果。例如，在本公开至少一个实施例提供的显示面板中，显示面板的显示侧可以设置分光元件(例如分光光栅等)，使得显示面板可以具有三维显示功能。
例如，该显示面板可以为电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
需要说明的是，为表示清楚，并没有叙述上述的显示基板以及包括该显示基板的显示面板的全部结构。为实现显示基板以及显示面板的必要功能，本领域技术人员可以根据具体应用场景进行设置其他结构，本公开的实施例对此不作限制。
本公开至少一实施例提供一种像素单元的制造方法，包括：形成电介质层；在电介质层上形成包括有源层的开关元件；形成至少部分与电介质层同层的第一遮光结构；其中，第一遮光结构在有源层所在面上的正投影位于有源层在有源层所在面上的正投影之外。在利用该方法制造的像素单元中，第一遮光结构位于有源层周围且至少部分与电介质层同层，因此至少对于沿着电介质层且从有源层的侧面射向有源层的光线，第一遮光结构可以对该光线的至少部分进行遮挡，从而减少因光照射有源层产生的光生载流子导致的漏电流增加，提高开关元件的稳定性。
例如，在本公开至少一实施例提供的像素单元的制造方法中，形成电介质层包括：对电介质层进行构图以在电介质层中形成至少一部分为凹凸结构的侧壁。如此，在利用该方法制造的像素单元中，在垂直于有源层所在面的方向上，利用形成有凹凸结构的侧壁可以使得第一遮光结构在平行于有源层所在面的方向上延伸，增加第一遮光结构对从电介质层的背离有源层的一侧斜射向有源层的光的遮挡面积，进一步降低有源层被光照射的风险。
例如，在本公开至少一实施例提供的像素单元的制造方法中，对电介质层构图以在电介质层中形成开口或槽，开口或槽的侧壁形成为凸凹结构，形成第一遮光结构包括：在电介质层上沉积遮光材料层以填充开口或槽，构图 遮光材料层以形成第一遮光结构；其中，电介质层围绕开关元件。
例如，在本公开至少一实施例提供的像素单元的制造方法中，电介质层形成为由至少两个子电介质层构成的叠层。如此，在利用该方法制造的像素单元中，在制造各个子电介质层的过程中，可以对不同的子电介质层分别进行构图工艺，从而使得凹陷结构的侧壁形成为具有凹凸结构，可以降低制造工艺的难度。
例如，在本公开至少一实施例提供的像素单元的制造方法中，电介质层为由至少两个子电介质层构成的叠层，形成电介质层包括：形成第二子电介质层，并在第二子电介质层上形成第一子电介质层；对第一子电介质层和第二子电介质层进行构图，以在第一子电介质层中形成第一开口；在第一子电介质层中形成第一开口后，以第一子电介质层为掩模，利用气氛刻蚀第二子电介质层以在第二子电介质层中形成第二开口或第二槽；其中，形成第一子电介质层和第二子电介质层的材料不同，气氛对第二子电介质层的材料的刻蚀比大于对第一子电介质层的材料的刻蚀比。如此，在利用该方法制造的像素单元中，可以在使得第一遮光结构的与第二子电介质层同层的部分在向有源层延伸以提高第一遮光结构对有源层的遮光效果的同时，防止第一遮光结构的与第一子电介质层同层的部分与有源层距离太近导致第一遮光结构的物质(例如氢等)侵入有源层。此外，上述方法使得第一遮光结构和电介质层不易分离，增加第一遮光结构的稳固性。
需要说明的是，根据上述制造方法获得的像素单元的结构可以参考前述实施例(例如图1～图8B所示的实施例)中的相关内容，在此不作赘述。
下面，以制造如图6所示的像素单元为例，像素单元的制造过程可以包括如图10A～图10F以及图6所示的下述过程。
如图10A所示，提供衬底基板10并在衬底基板上沉积遮光材料薄膜，对该遮光材料薄膜进行构图工艺以形成第二遮光结构400，然后在第二遮光结构400上依次沉积三个绝缘材料薄膜，以形成覆盖第二遮光结构400并在衬底基板10上依次叠置的第三子电介质层130c、第二子电介质层120c和第一子电介质层110c。
例如，在本公开至少一个实施例中，构图工艺可以为光刻构图工艺，例如可以包括：在需要被构图的结构层上涂覆光刻胶层，使用掩模板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图 案对结构层进行蚀刻，然后可选地去除光刻胶图案。
例如，形成第二遮光结构400的材料可以为金属，例如钼或钼铌合金等，厚度可以为0.1～0.2um。例如，在光刻构图工艺以形成第二遮光结构400时，可以利用混酸(例如包括盐酸、硝酸、硫酸、氢氟酸或其它类型酸的至少之二)进行湿刻。
例如，第三子电介质层130c的材料为氧化硅、第二子电介质层120c的材料为氮化硅，第一子电介质层110c的材料为氧化硅。例如，第三子电介质层130c的厚度可以为0.2～0.25um，第二子电介质层120c的厚度可以为0.07～0.1um，第一子电介质层110c的厚度可以为0.2～0.25um。在上述范围内，电介质层100c可以使得后续形成的第一遮光结构具有较好的遮光效果，并且第一遮光结构与有源层的间隔距离满足要求，第一遮光结构的物质(例如氢等)难以侵入有源层。
如图10B所示，在电介质层100c上沉积光刻胶，对该光刻胶进行显影后形成光刻胶图案1。光刻胶图案1包括暴露电介质层100c的开口2。例如，光刻胶图案的厚度可以为2.0um～2.2um。光刻胶图案1的位于开口2之间的部分的宽度可以根据开关元件的尺寸进行设计，例如，光刻胶图案1的位于开口2之间的部分的宽度可以为6um～10um。例如，在对光刻胶利用掩膜进行构图的工艺中，可以不对光刻胶进行后烘(Hard Bake)工艺，在该情况下，光刻胶图案1会形成内部凹陷形状，即，光刻胶图案1在垂直于衬底基板10所在面的方向上的中间部分向内收缩。
如图10C所示，以光刻胶图案1为掩模对第一子电介质层110c进行构图(例如干刻)，以在第一子电介质层110c中形成与开口2对应的第一开口111c。例如，第二子电介质层120c的材料为氮化硅，第一子电介质层110c的材料为氧化硅，在该构图工艺过程中，用于刻蚀第一子电介质层110c的气氛可以由四氟化碳(CF 4)和氧气(O 2)混合而成，相对于氮化硅，该气氛对氧化硅的刻蚀选择比更大，从而使得该气氛只用于刻蚀第一子电介质层110c。例如，CF 4的流量可以为2000～2500sccm，O 2的流量可以为1000～1500sccm，高源功率和高偏置功率进行。例如，在光刻胶图案1形成为具有如图10C所示的内部凹陷形状的情况下，横向氧气灰化较慢，干刻后，第一开口111c的侧壁与衬底基板100所在面基本垂直。
如图10D所示，以光刻胶图案1和第一子电介质层110c为掩模对第二 子电介质层120c进行构图(例如干刻)，以在第二子电介质层120c中形成与第一开口111c对应的第二开口121c。例如，第三子电介质层130c的材料为氧化硅，第二子电介质层120c的材料为氮化硅，第一子电介质层110c的材料为氧化硅，在该构图工艺过程中，气氛可以由四氟化碳(SF 6)和氧气(O 2)混合而成，相对于氧化硅，该气氛对氮化硅的刻蚀选择比更大，从而使得该气氛只用于刻蚀第二子电介质层120c。例如，SF 6的流量可以为2000～2500sccm，O 2的流量可以为600～800sccm，高源功率和低偏置功率进行，由于SF 6含氟量多，为一种各向同性的刻蚀气体，在低偏置功率的条件下，该气氛对氧化硅的刻蚀速率很慢(氧化硅需要依靠偏置功率轰击打开Si-O键才更易刻蚀)，而对氮化硅的刻蚀速率较高(Si-N键能小，活性SF基团可直接与之反应)。如此，第二开口121c比第一开口111c的宽度大，即，第一开口111c在衬底基板10上的正投影位于第二开口121c在衬底基板10上的正投影之内。
如图10E所示，以光刻胶图案1和第一子电介质层110c为掩模对第三子电介质层130c进行构图(例如干刻)，以在第三子电介质层130c中形成与第一开口1对应的第三开口131c。例如，第二子电介质层120c的材料为氮化硅，第三子电介质层130c的材料为氧化硅，在该构图工艺过程中，用于刻蚀第三子电介质层130c的气氛可以由四氟化碳(CF 4)和氧气(O 2)混合而成，相对于氮化硅，该气氛对氧化硅的刻蚀选择比更大，从而使得该气氛只用于刻蚀第三子电介质层130c。例如，CF 4的流量可以为2000～2500sccm，O 2的流量可以为1000～1500sccm，高源功率和高偏置功率进行。例如，在光刻胶图案1形成为具有如图10E所示的内部凹陷形状的情况下，横向氧气灰化较慢，干刻后，第三开口131c的侧壁与衬底基板100所在面基本垂直，第三开口131c与第一开口111c对应且尺寸大致相同，即，第三开口131c与第一开口111c在衬底基板10上的正投影基本重合。例如，形成第三开口131c后，可以利用湿法剥离去除残留的光刻胶图案1。第一开口111c、第二开口121c和第三开口131c构成凹陷结构101c，该凹陷结构101c的侧壁1011c为具有凹凸结构的面。
如图10F所示，在电介质层100c上施加(例如涂覆、喷墨打印或其它方式)遮光材料，遮光材料填充凹陷结构101c，对该遮光材料形成的膜层进行构图工艺以形成第一遮光结构300c。例如，用于形成第一遮光结构300c 的遮光材料可以为BM(Black Matrix，黑矩阵)胶。BM胶具有一定的流动性，从而可以填充凹陷结构101c(例如第一开口111c、第二开口121c和第三开口131c)，在BM胶填充凹陷结构101c后，对BM胶进行后烘处理。例如，BM的厚度可以为0.8um～1.1um。例如，第一遮光结构300c的与电介质层100c同层的部分(前述实施例中的第一部分)的厚度可以为0.6～0.8um，第一遮光结构300c的突出于电介质层100c之外的部分(前述实施例中的第二部分)的厚度可以为0.2～0.3um。
需要说明的是，在如图10F所示的形成第一遮光结构300c的过程中，可以对BM胶形成的膜层进行构图工艺，以形成如图8A所示的第一遮光结构300c和黑矩阵600。
如图6所示，在电介质层100c上进行开关元件的制造工艺，该工艺可以包括如下过程。
在电介质层100c上沉积半导体材料以进行构图工艺(例如光刻、湿刻)以形成有源层210，半导体材料可以为氧化铟锡(IGZO)，厚度可以为0.05～0.1um。
在有源层210上沉积一层栅绝缘材料薄膜，材料可以为氧化硅，厚度可以为0.1um～0.2um。
在栅绝缘材料薄膜沉积导电材料膜层并进行构图工艺以形成栅电极220，例如，该栅电极的材料可以为金属例如铜等，厚度可以为0.4～0.5um。
例如，在通过构图工艺形成栅电极的过程中，利用的光刻胶的厚度可以为2.0～2.2um，光刻胶可以为正性光刻胶，该光刻胶在掩膜完成后形成的光刻胶图案的侧面可以为斜面，例如，该斜面的倾角可以为60～70°。利用该光刻胶图案作为掩模先对导电材料膜层进行湿刻以形成栅电极，例如，在栅电极材料包括铜的情况下，铜湿刻可用H 2O 2药液进行。
湿刻完成后利用干刻设备，通过上述的光刻胶图案和栅电极220对栅绝缘材料薄膜干刻，以形成栅绝缘层240，示例性的，可采用含量高的CF 4和含量低的O 2混合气体进行干刻，CF 4流量可为2000～2500sccm，O 2流量1000～1500sccm。
例如，形成栅电极220和栅绝缘层240之后，可以对有源层210的未被栅电极220和栅绝缘层240覆盖的部分进行导体化处理。例如，在该导体化处理的工艺中，可以利用氨气(NH 3)或者氦气(He)进行。
例如，形成栅电极220和栅绝缘层240之后，或者对有源层210完成导体化处理之后，可以利用湿法剥离去除残留的光刻胶，然后在衬底基板10上沉积绝缘材料薄膜以形成层间介质层250(Inter Layer Dielectric，ILD)，层间介质层250的材料可为氧化硅、氮化硅、氧氮化硅等，厚度可以为0.45～0.6um。
例如，在层间介质层250中形成暴露有源层210的过孔，然后在该层间介质层250沉积导电材料膜层，该导电材料膜层通过层间介质层250的过孔与有源层210连接，对该导电材料膜层构图以形成源漏电极层(漏电极231和源电极232)，漏电极231和源电极232通过形成在层间介质层250中的不同过孔分别与有源层210连接。例如，形成源漏电极层的材料可以为铜、铝等金属，厚度可以为0.5～0.7um。
例如，在形成源漏电极层之后，可以在衬底基板沉积绝缘材料以形成钝化层(PVX)，材料可以为氧化硅、氮化硅、氧氮化硅等，厚度可以为0.3～0.5um。例如，形成钝化层之后，可以在钝化层上进行发光器件的制造工艺。钝化层以及发光器件的制造工艺可以参见常规制造工艺，形成的钝化层以及发光器件的结构可以参见图7所示实施例中的相关说明，在此不做赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种像素单元，包括：
    电介质层；
    开关元件，包括有源层且位于所述电介质层上；以及
    第一遮光结构，至少部分与所述电介质层同层；
    其中，所述第一遮光结构在所述有源层所在面上的正投影位于所述有源层在所述有源层所在面上的正投影之外。
  2. 根据权利要求1所述的像素单元，其中，
    所述电介质层设置在所述第一遮光结构的与所述电介质层同层的部分的至少相对的两侧。
  3. 根据权利要求2所述的像素单元，其中，
    所述电介质层的与所述第一遮光结构同层且面向所述第一遮光结构的侧壁的至少一部分形成为凸凹结构。
  4. 根据权利要求3所述的像素单元，其中，
    在平行于所述电介质层的面上，所述电介质层设置有围绕所述开关元件的开口或槽，所述开口或槽的侧壁形成为所述凸凹结构。
  5. 根据权利要求1-4任一所述的像素单元，其中，
    所述电介质层为由至少两个子电介质层构成的叠层。
  6. 根据权利要求5所述的像素单元，其中，
    相邻的所述子电介质层中的所述开口连通或者相邻的所述子电介质层之一的开口与另一个的槽连通，以及
    相邻的所述子电介质层中的所述开口或者相邻的所述子电介质层之一的开口与另一个的槽在所述有源层所在面上的正投影至少部分不交叠。
  7. 根据权利要求6所述的像素单元，其中，
    所述电介质层包括第一子电介质层和第二子电介质层，所述第一子电介质层位于所述第二子电介质层和所述有源层之间，所述第一子电介质层中设置有第一开口，所述第二子电介质层中设置有第二开口或者第二槽，
    所述第一开口和所述第二开口或者第二槽连通，并且所述第一开口在所述有源层所在面上的正投影位于所述第二开口或者第二槽在所述有源层所在面上的正投影之内。
  8. 根据权利要求6所述的像素单元，其中，
    所述电介质层包括至少三个所述子电介质层，位于两侧的所述子电介质层的所述开口或槽在所述有源层所在面上的正投影的投影位于中间的所述子电介质层的开口在所述有源层所在面上的正投影之内。
  9. 根据权利要求1-8任一所述的像素单元，其中，
    所述第一遮光结构包括第一部分和第二部分，所述第一部分与所述电介质层同层，所述第二部分与所述电介质层位于不同层。
  10. 根据权利要求9所述的像素单元，其中，
    所述第二部分的背离所述电介质层的一端至所述电介质层所在面的距离大于或等于所述有源层的背离所述电介质层的表面至所述电介质层所在面的距离。
  11. 根据权利要求9或10所述的像素单元，还包括黑矩阵，其中，
    所述像素单元包括显示区和位于所述显示区周围的非显示区，所述黑矩阵和所述第一遮光结构位于所述非显示区，
    所述黑矩阵与所述第二部分同层且为一体化结构。
  12. 根据权利要求1-8任一所述的像素单元，还包括：
    第二遮光结构，位于所述电介质层背离所述有源层的一侧；
    其中，所述有源层在所述有源层所在面上的正投影与所述第二遮光结构在所述有源层所在面上的正投影重合，或者
    所述有源层在所述有源层所在面上的正投影位于所述第二遮光结构在所述有源层所在面上的正投影之内。
  13. 根据权利要求12所述的像素单元，其中，
    所述第二遮光结构在所述有源层所在面上的正投影位于所述第一遮光结构在所述有源层所在面上的正投影的内侧。
  14. 根据权利要求1-8任一所述的像素单元，还包括：
    发光器件，位于所述开关元件的背离所述电介质层的一侧；
    其中，所述发光器件包括依次叠置在所述开关元件上的第一电极层、发光功能层和第二电极层，
    所述第一电极层和所述第二电极层之一为反射电极层。
  15. 一种显示基板，包括阵列排布的多个如权利要求1-14任一所述的像素单元。
  16. 一种像素单元的制造方法，包括：
    形成电介质层；
    在所述电介质层上形成包括有源层的开关元件；
    形成至少部分与所述电介质层同层的第一遮光结构；
    其中，所述第一遮光结构在所述有源层所在面上的正投影位于所述有源层在所述有源层所在面上的正投影之外。
  17. 根据权利要求16所述的制造方法，其中，形成所述电介质层包括：
    对所述电介质层进行构图以在所述电介质层中形成至少一部分为凹凸结构的侧壁。
  18. 根据权利要求17所述的制造方法，其中，对所述电介质层构图以在所述电介质层中形成开口或槽，所述开口或槽的侧壁形成为所述凸凹结构，形成所述第一遮光结构包括：
    在所述电介质层上沉积遮光材料层以填充所述开口或槽，构图所述遮光材料层以形成所述第一遮光结构；
    其中，所述电介质层围绕所述开关元件。
  19. 根据权利要求18所述的制造方法，其中，
    所述电介质层形成为由至少两个子电介质层构成的叠层。
  20. 根据权利要求19所述的制造方法，其中，所述电介质层为由至少两个子电介质层构成的叠层，形成所述电介质层包括：
    形成第二子电介质层，并在所述第二子电介质层上形成第一子电介质层；
    对所述第一子电介质层和所述第二子电介质层进行构图，以在所述第一子电介质层中形成第一开口；
    在所述第一子电介质层中形成所述第一开口后，以所述第一子电介质层为掩模，利用气氛刻蚀所述第二子电介质层以在所述第二子电介质层中形成第二开口或第二槽；
    其中，形成所述第一子电介质层和所述第二子电介质层的材料不同，所述气氛对所述第二子电介质层的材料的刻蚀比大于对所述第一子电介质层的材料的刻蚀比。
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CN107369693A (zh) * 2017-08-04 2017-11-21 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN109920823A (zh) * 2019-03-07 2019-06-21 合肥鑫晟光电科技有限公司 像素单元及其制造方法、显示基板

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