WO2022151681A1 - 显示基板及其制作方法和显示装置 - Google Patents

显示基板及其制作方法和显示装置 Download PDF

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Publication number
WO2022151681A1
WO2022151681A1 PCT/CN2021/105278 CN2021105278W WO2022151681A1 WO 2022151681 A1 WO2022151681 A1 WO 2022151681A1 CN 2021105278 W CN2021105278 W CN 2021105278W WO 2022151681 A1 WO2022151681 A1 WO 2022151681A1
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Prior art keywords
base substrate
sub
layer
orthographic projection
display substrate
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PCT/CN2021/105278
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English (en)
French (fr)
Inventor
许程
许晨
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020217033420A priority Critical patent/KR20230129069A/ko
Priority to US17/604,931 priority patent/US20230108752A1/en
Priority to JP2021558710A priority patent/JP2024502388A/ja
Priority to AU2021240181A priority patent/AU2021240181B2/en
Priority to EP21773272.6A priority patent/EP4071822A4/en
Publication of WO2022151681A1 publication Critical patent/WO2022151681A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
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    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
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    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.
  • AMOLED active matrix organic light emitting diode display
  • AMOLED active matrix organic light emitting diode display devices
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • the display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate, wherein each of the sub-pixels includes: a conductive light-shielding structure located on the base substrate; a buffer layer located on the conductive light-shielding structure a side away from the base substrate; a semiconductor layer, located on a side of the buffer layer away from the conductive light-shielding structure; an interlayer insulating layer, located at a side of the semiconductor layer away from the buffer layer; and a conductive layer , which is located on the side of the interlayer insulating layer away from the semiconductor layer, and includes a conductive structure, the conductive light-shielding structure includes a first main body portion and a first recessed portion, and the display substrate further includes a first contact hole, so The first contact hole passes through the interlayer insulating layer and the buffer layer, the conductive structure is electrically
  • the display substrate increases the contact area between the first drain electrode and the conductive light-shielding structure, making the contact more sufficient, thereby reducing the contact resistance and improving the first drain electrode and the conductive light-shielding structure.
  • the electrical connection effect of the structure is not limited.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate and a plurality of sub-pixels located on the base substrate, wherein each of the sub-pixels includes: a conductive light-shielding structure located on the base substrate
  • the buffer layer is located on the side of the conductive light-shielding structure away from the base substrate
  • the semiconductor layer is located on the side of the buffer layer away from the conductive light-shielding structure
  • the interlayer insulating layer is located in the semiconductor layer away from all the one side of the buffer layer
  • a conductive layer which is located on the side of the interlayer insulating layer away from the semiconductor layer, and includes a conductive structure
  • the conductive light-shielding structure includes a first main body portion and a first recessed portion
  • the display substrate further includes a first contact hole, the first contact hole passes through the interlayer insulating layer and the buffer layer, and the conductive structure is electrically connected to the first recess through the first contact hole, The area
  • the buffer layer includes: a first buffer portion, and a side of the first buffer portion away from the base substrate is disposed in contact with the conductive layer, and the first buffer portion is disposed in contact with the conductive layer.
  • a side of the first buffer part close to the base substrate is arranged in contact with the conductive light-shielding structure; and a second buffer part, the side of the second buffer part away from the base substrate is insulated from the interlayer.
  • the layers are arranged in contact with each other, and a side of the second buffer portion close to the base substrate is arranged in contact with the conductive light-shielding structure.
  • the first contact hole includes sidewalls, and the sidewalls at least include: a first sub-sidewall located on the interlayer insulating layer; and a second sub-side
  • the wall is located in the buffer layer, the angle between the first sub-sidewall and the base substrate forms a first gradient angle, and the angle between the second sub-sidewall and the base substrate forms a second gradient
  • the first gradient angle is smaller than the second gradient angle; the contact portion of the second sub-sidewall and the first buffer portion is located between the first buffer portion and the second buffer portion.
  • the sidewalls of the first contact holes further include: third sub-sidewalls located in the first buffer portion, the third sub-sidewalls and The included angle of the base substrate constitutes a third slope angle, and the first slope angle, the second slope angle and the third slope angle are different.
  • the ratio of the length of the first buffer portion to the average thickness of the first buffer portion is greater than that of the first buffer portion.
  • the ratio of the projected length of the sub-sidewall on the base substrate to the average thickness of the interlayer insulating layer is greater than that of the first buffer portion.
  • the thickness ratio is greater than the ratio of the projected length of the second sub-sidewall on the base substrate to the average thickness of the buffer layer.
  • the second gradient angle is greater than the third gradient angle
  • the first gradient angle is greater than the third gradient angle
  • the dimension L of the orthographic projection of the first recessed portion on the base substrate in a direction parallel to the base substrate satisfies the following formula:
  • A is the maximum thickness of the first buffer portion
  • B is the maximum thickness of the second buffer portion
  • C is the maximum thickness of the interlayer insulating layer
  • ⁇ is the first slope angle
  • ⁇ is the The second slope angle
  • ⁇ is the third slope angle
  • D is the maximum dimension of the orthographic projection of the first contact hole on the base substrate in a direction parallel to the base substrate.
  • the first recessed portion includes a first edge portion, and in a direction from the edge of the first recessed portion to the center of the first recessed portion, the The thickness of the first edge portion in a direction perpendicular to the base substrate gradually decreases.
  • the first concave portion includes a first edge portion, and in a direction perpendicular to the base substrate, the first edge portion is close to the surface of the conductive layer
  • the fourth slope angle of is continuously changing.
  • the surface of the first recessed portion close to the conductive structure is a continuous arc surface, or a combined surface formed by combining at least one continuous arc surface and at least one flat surface.
  • the first concave portion includes a first edge portion, and a fourth slope angle ⁇ on a surface of the first edge portion close to the conductive layer satisfies the following formula:
  • Lmax is the maximum aperture of the orthographic projection of the first recessed portion on the base substrate
  • H is the average thickness of the first main body portion
  • k is a constant greater than 1 and less than or equal to 2.
  • k 2
  • the range of the fourth slope angle is 1- ⁇ /18.
  • the first concave portion includes a first edge portion, and a fourth slope angle ⁇ on a surface of the first edge portion close to the conductive layer is smaller than the first edge portion.
  • A is the maximum thickness of the first buffer portion
  • B is the maximum thickness of the second buffer portion
  • C is the maximum thickness of the interlayer insulating layer
  • ⁇ is the first slope angle
  • ⁇ is the The second slope angle
  • ⁇ is the third slope angle
  • D is the maximum dimension of the orthographic projection of the first contact hole on the base substrate in a direction parallel to the base substrate.
  • the display substrate provided by an embodiment of the present disclosure further includes: a flat layer located on a side of the conductive layer away from the semiconductor layer, and the flat layer includes an anode hole; and an anode located on the flat layer away from all one side of the semiconductor layer, and includes a light emitting part, a driving part and an extension part connecting the light emitting part and the driving part, the driving part is at least partially located in the anode hole, at least one of the sub- In the pixel, the orthographic projection of the first contact hole on the base substrate and the orthographic projection of the driving part on the base substrate at least partially overlap, and the display substrate further includes: a power line located on the base substrate.
  • the power supply line and the sensing line are arranged in a first direction, and both the power supply line and the sensing line intersect with the first direction extending in the second direction;
  • the plurality of sub-pixels include a first sub-pixel pair and a second sub-pixel pair, and the first sub-pixel pair includes two of the sub-pixels, which are located on both sides of the power supply line, respectively.
  • the second sub-pixel pair includes two sub-pixels, which are respectively located on both sides of the sensing line; the first sub-pixel pair and the second sub-pixel pair are alternately arranged in the first direction, In two of the sub-pixels in the second sub-pixel pair, the anode hole and the first concave portion are orthographically projected on the base substrate to have a first overlapping area, and the first overlapping area is The area of the stack area is smaller than the orthographic projection area of the first contact hole on the base substrate.
  • the anode further includes a concave structure at an edge position of the anode hole, and a concave direction of the concave structure faces the conductive light-shielding structure.
  • the size of the orthographic projection of the first recessed portion on the base substrate in a direction parallel to the base substrate ranges from 5 to 10 microns.
  • an orthographic projection of the first contact hole on the base substrate at least partially overlaps with an orthographic projection of the first recessed portion on the base substrate .
  • each of the sub-pixels includes a pixel driving circuit
  • the pixel driving circuit includes a first thin film transistor
  • the conductive structure is a first drain of the first thin film transistor. pole.
  • the first thin film transistor further includes: a first active layer located in the semiconductor layer and including a first channel region and a first channel region located in the first channel The first source region and the first drain region on both sides of the region; the first source electrode is located in the conductive layer, and the display substrate further includes a first via hole and a second via hole, the first via hole and The second via hole is located in the interlayer insulating layer, the first source electrode is connected to the first source region through the first via hole, and the first drain electrode is connected to the first source region through the second via hole.
  • the via hole is connected to the first drain region.
  • the conductive light-shielding structure further includes: a first insulating portion, an orthographic projection of the first insulating portion on the base substrate and the first via hole
  • the orthographic projection on the base substrate at least partially overlaps
  • the orthographic projection of the first insulating portion on the base substrate and the orthographic projection of the first source region on the base substrate at least partially overlap overlapping.
  • the first insulating portion includes a first hollow portion, and the first hollow portion is filled with the material of the buffer layer.
  • the first hollow portion includes a first hollow ring, and the inner part of the first hollow ring and the outer side of the first hollow ring are both the conductive light shielding material of the structure.
  • the first insulating portion is an oxide portion.
  • the display substrate provided by an embodiment of the present disclosure further includes: a gate insulating layer located between the semiconductor layer and the interlayer insulating layer; a gate layer located between the gate insulating layer and the interlayer between insulating layers; a passivation layer, located on the side of the conductive layer away from the base substrate; a color filter layer, located on the side of the passivation layer away from the conductive layer, and including at least three different colors and an anode layer, the flat layer is located on the side of the color filter layer away from the passivation layer, the anode layer is located on the side of the flat layer away from the color filter layer, the An anode is located in the anode layer.
  • the display substrate provided by an embodiment of the present disclosure further includes: a power supply connection line, which is provided in the same layer as the conductive light-shielding structure, the power supply connection line includes a second main body part and a plurality of power supply recessed parts, and the power supply recessed parts
  • the average thickness in the direction perpendicular to the base substrate is smaller than the average thickness of the second body part in the direction perpendicular to the base substrate, and the power supply recess is close to the surface of the conductive layer.
  • the area is larger than the area of the orthographic projection of the power supply recessed portion on the base substrate, and the orthographic projection of at least one of the plurality of power supply recessed portions on the base substrate is the same as that of all the color filter layers.
  • the orthographic projections of the filter on the base substrate at least partially overlap.
  • the power supply recessed portion includes a second edge portion, and in a direction from the edge of the power supply recessed portion to the center of the power supply recessed portion, the second edge portion is The thickness of the edge portion in the direction perpendicular to the base substrate decreases continuously and gradually.
  • the power supply recess includes a second edge portion, and in a direction perpendicular to the base substrate, the second edge portion is close to the surface of the conductive layer.
  • the fifth slope angle is continuously changed.
  • the display substrate further includes a power supply contact hole, the power supply contact hole is located in the interlayer insulating layer and the buffer layer, and the power supply contact hole is located in the The orthographic projection on the base substrate at least partially overlaps the orthographic projection of the power supply recess on the base substrate.
  • the buffer layer includes: a third buffer portion located in the power contact hole, and a side of the third buffer portion away from the base substrate is connected to The power supply connection line is arranged in contact, and the side of the third buffer portion close to the base substrate is arranged in contact with the conductive light-shielding structure; and a fourth buffer portion is located in the third buffer portion away from the power supply
  • the sidewall of the power contact hole includes: a fourth sub-sidewall, located in the interlayer insulating layer; and a fifth sub-sidewall, located in the fourth buffer portion, the first The angle between the four sub-sidewalls and the base substrate forms a sixth gradient angle, the angle between the fifth sub-sidewall and the base substrate forms a seventh gradient angle, and the sixth gradient angle is smaller than the A seventh slope angle; the contact portion of the fifth sub-sidewall and the third buffer portion is located between the third buffer portion and the fourth buffer portion.
  • the side wall of the power contact hole further includes: a sixth sub-side wall located in the third buffer portion, the sixth sub-side wall and the lining
  • the included angle of the base substrate constitutes an eighth slope angle, and the sixth slope angle, the seventh slope angle and the eighth slope angle are different.
  • the seventh slope angle is smaller than the second slope angle.
  • the eighth slope angle is greater than the third slope angle.
  • the display substrate provided by an embodiment of the present disclosure further includes: a sensing connection line disposed in the same layer as the conductive light-shielding structure, the sensing connection line including a third main body part and a plurality of sensing concave parts, the The average thickness of the sensing concave portion in the direction perpendicular to the base substrate is smaller than the average thickness of the third main body portion in the direction perpendicular to the base substrate, and the sensing concave portion is close to the base substrate.
  • the area of the surface of the conductive layer is larger than the area of the orthographic projection of the sensing concave portion on the base substrate, and the orthographic projection of at least one of the plurality of sensing concave portions on the base substrate is the same as the orthographic projection of the sensing concave portion on the base substrate.
  • the orthographic projections of the filters in the color filter layer on the base substrate at least partially overlap.
  • the sensing recessed portion includes a third edge portion, and in the direction from the edge of the sensing recessed portion to the center of the sensing recessed portion, the The thickness of the third edge portion in the direction perpendicular to the base substrate decreases continuously and gradually.
  • the sensing concave portion includes a third edge portion, and in a direction perpendicular to the base substrate, the third edge portion is close to the surface of the conductive layer
  • the ninth slope angle of is continuously changing.
  • the display substrate further includes a sensing contact hole, the sensing contact hole is located in the interlayer insulating layer and the buffer layer, and the sensing contact hole is located in the interlayer insulating layer and the buffer layer.
  • the orthographic projection on the base substrate at least partially overlaps the orthographic projection of the sensing recess on the base substrate.
  • the buffer layer includes: a fifth buffer part, located in the sensing contact hole, and a side of the fifth buffer part away from the base substrate the fifth buffer part is arranged in contact with the sensing connection line, and the side of the fifth buffer part close to the base substrate is arranged in contact with the conductive light-shielding structure; and the sixth buffer part is located in the fifth buffer part away from the One side of the center of the sensing recessed portion, the sidewall of the sensing contact hole includes: a seventh sub-sidewall, located in the interlayer insulating layer; and an eighth sub-sidewall, located in the sixth buffer portion ;
  • the angle between the seventh sub-sidewall and the base substrate forms a tenth gradient angle
  • the angle between the eighth sub-sidewall and the base substrate forms an eleventh gradient angle
  • the tenth gradient angle The slope angle is smaller than the eleventh slope angle
  • the contact portion of the eighth sub-side wall and the fifth buffer portion is located between the fifth buffer portion and the sixth buffer
  • the buffer layer further includes: a ninth sub-sidewall located in the fifth buffer part, and a sandwich between the ninth sub-sidewall and the base substrate
  • the angle constitutes a twelfth slope angle, and the tenth slope angle, the eleventh slope angle and the twelfth slope angle are different.
  • the eleventh gradient angle is smaller than the second gradient angle.
  • the twelfth slope angle is greater than the third slope angle.
  • each of the sub-pixels includes a driving area and a light emitting area
  • the conductive light shielding structure is located in the driving area
  • the driving portion of the anode is located in the driving area
  • the light emitting part of the anode is located in the light emitting area.
  • the display substrate provided by an embodiment of the present disclosure further includes: a first gate line located on the gate layer and extending along a first direction; a second gate line located on the gate layer and extending along the first direction extending in one direction; and a data line located on the conductive layer and extending along the second direction, the power supply line extending along the second direction, the sensing line extending along the second direction, so
  • the plurality of sub-pixels are arranged in an array along the first direction and the second direction to form a plurality of sub-pixel rows arranged along the second direction and a plurality of sub-pixel columns arranged along the first direction, and in each of the In a sub-pixel row, the first grid line is located between the driving area and the light-emitting area, the second grid line is located between two adjacent sub-pixel rows, and the power supply line is located in the phase. Between two adjacent sub-pixel columns, the sensing line is located between two adjacent sub-pixel columns, and the data line is located between two adjacent sub-pixel columns.
  • each of the sub-pixels includes a pixel driving circuit
  • the pixel driving circuit includes a first thin film transistor
  • the first thin film transistor includes a first gate, a first source electrode and a first drain electrode
  • the conductive structure is the first drain electrode of the first thin film transistor
  • the pixel driving circuit further includes a second thin film transistor and a third thin film transistor
  • the second thin film transistor includes a second thin film transistor a gate electrode, a second source electrode and a second drain electrode
  • the third thin film transistor includes a third gate electrode, a third source electrode and a third drain electrode
  • the semiconductor layer further includes a conductor block
  • the first thin film transistor The first source of the transistor is connected to the power line
  • the second source of the second thin film transistor is connected to the data line
  • the second gate of the second thin film transistor is connected to the first A gate line is connected
  • the second drain of the second thin film transistor is connected to the first gate of the first thin film transistor and the conductor block, respectively, the third
  • the first source electrode of the first thin film transistor is connected to the power supply line through a first connection part
  • the second thin film transistor of the second thin film transistor The source electrode is connected to the data line through a second connection part
  • the first connection part is arranged on the same layer as the power supply line
  • the second connection part is arranged on the same layer as the data line.
  • the direction from the first source electrode to the first drain electrode intersects with the extending direction of the first connection portion
  • the direction from the second source electrode to the first drain electrode intersects with the extending direction of the first connection portion.
  • the direction of the second drain intersects with the extending direction of the second connection portion.
  • the plurality of sub-pixels at least include first-color sub-pixels, second-color sub-pixels, third-color sub-pixels, and fourth-color sub-pixels, and in each of the sub-pixels pixel row, the first color sub-pixel, the second color sub-pixel, the third color sub-pixel and the fourth color sub-pixel are arranged in sequence along the first direction and form a sub-pixel group, so The power line is located between the second color subpixel and the third color subpixel in the subpixel group.
  • the display substrate further includes a power supply connection line, which is provided in the same layer as the conductive light-shielding structure.
  • the display substrate further includes a second contact hole, a third contact hole and a fourth contact hole, the second contact hole, the third contact hole and the The fourth contact hole is located in the interlayer insulating layer and the buffer layer.
  • the power supply line is connected to the power supply connection line through the second contact hole
  • the second color The first source electrode of the sub-pixel is connected to the same layer as the power supply line
  • the first source electrode of the third color sub-pixel is connected to the same layer of the power supply line
  • all the first color sub-pixels are connected to the same layer.
  • the first source electrode is connected to the power supply connection line through the third contact hole
  • the first source electrode of the fourth color sub-pixel is connected to the power supply connection line through the fourth contact hole.
  • the power connection line includes a second main body part, a second recessed part, a third recessed part and a fourth recessed part, and the second recessed part is located on the substrate
  • the orthographic projection on the base substrate at least partially overlaps with the orthographic projection of the second contact hole on the base substrate, and the orthographic projection of the third recessed portion on the base substrate and the third contact hole
  • the orthographic projection on the base substrate at least partially overlaps, and the orthographic projection of the fourth recessed portion on the base substrate at least partially overlaps the orthographic projection of the fourth contact hole on the base substrate , the thicknesses of the second concave portion, the third concave portion and the fourth concave portion in a direction perpendicular to the base substrate are all smaller than the thickness of the second main portion in a direction perpendicular to the base substrate
  • the thickness of the second recessed portion in the direction of The area of the surface of the base substrate is greater than the area of the orthographic projection of the third recessed portion on
  • the orthographic projection of at least one of the second recessed portion, the third recessed portion, and the fourth recessed portion on the base substrate is the same as the The orthographic projections of the filters in the color filter layer on the base substrate at least partially overlap.
  • the second color sub-pixel includes a first color filter
  • the third color sub-pixel includes a second color filter
  • the fourth color sub-pixel includes a second color filter.
  • the pixel includes a third color filter
  • the orthographic projection of at least one of the first color filter and the second color filter on the base substrate is the same as the first color filter.
  • the orthographic projections of the two concave portions on the base substrate at least partially overlap, and the orthographic projection of the third color filter on the base substrate and the orthographic projection of the fourth concave portion on the base substrate The orthographic projections overlap at least partially.
  • the sensing line is located between two adjacent sub-pixel groups in the first direction, and the two adjacent sub-pixel groups in the first direction
  • the sub-pixel group includes a first sub-pixel group and a second sub-pixel group
  • the display substrate further includes a sensing connection line, a fifth contact hole, a sixth contact hole, a seventh contact hole, an eighth contact hole, and a sixth contact hole.
  • the sensing connection line and the conductive light-shielding structure are arranged in the same layer, the fifth contact hole, the sixth contact hole, the seventh contact hole, the eighth contact hole and the ninth contact hole Located in the interlayer insulating layer and the buffer layer, in the two adjacent sub-pixel groups, the sensing line is connected to the sensing connection line through the fifth contact hole, so The third source electrode of the third color subpixel in the first subpixel group is connected to the sensing connection line through the sixth contact hole, and the third color subpixel in the first subpixel group is connected to the sensing connection line.
  • the third source electrodes of the four-color sub-pixels are connected to the sensing connection line through the seventh contact hole, and the third source electrodes of the first-color sub-pixels in the first sub-pixel group
  • the eighth contact hole is connected to the sensing connection line
  • the third source electrode of the second color sub-pixel in the second sub-pixel group is connected to the sense connection through the ninth contact hole.
  • the sensing connection line includes a third main body portion, a fifth recessed portion, a sixth recessed portion, a seventh recessed portion, an eighth recessed portion, and a ninth recessed portion
  • the orthographic projection of the fifth concave portion on the base substrate at least partially overlaps with the orthographic projection of the fifth contact hole on the base substrate
  • the sixth concave portion is on the base substrate
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the sixth contact hole on the base substrate, and the orthographic projection of the seventh recessed portion on the base substrate is where the seventh contact hole is located.
  • the orthographic projection on the base substrate at least partially overlaps, and the orthographic projection of the eighth concave portion on the base substrate at least partially overlaps the orthographic projection of the eighth contact hole on the base substrate, so
  • the orthographic projection of the ninth recessed portion on the base substrate at least partially overlaps with the orthographic projection of the ninth contact hole on the base substrate, and the fifth recessed portion, the sixth recessed portion,
  • the thicknesses of the seventh recessed portion, the eighth recessed portion and the ninth recessed portion in the direction perpendicular to the base substrate are all smaller than the thickness of the third main body portion in the direction perpendicular to the base substrate , the area of the surface of the fifth recessed portion close to the sensing line is larger than the area of the orthographic projection of the fifth recessed portion on the base substrate, and the sixth recessed portion is far from the surface of the base substrate
  • the area of the sixth recessed portion is larger than the orthographic projection area of the sixth recessed portion on the base substrate, and the area of the surface of the seventh recessed portion away
  • the orthographic projection of at least one of the filters on the base substrate at least partially overlaps the orthographic projection of the filter in the color filter layer on the base substrate.
  • the sensing connection line in the second direction, is located on a side of the second gate line away from the first gate line, and the first gate line
  • the orthographic projection of the second color filter in the sub-pixel group on the base substrate is where the sixth concave portion of the first sub-pixel group adjacent in the second direction is located.
  • the orthographic projections on the base substrate at least partially overlap, and the orthographic projections of the third color filters in the first sub-pixel group on the base substrate are adjacent to the second direction.
  • the orthographic projection of the seventh recessed portion on the base substrate at least partially overlaps, and the orthographic projection of the first color filter in the second sub-pixel group on the base substrate is the same as the orthographic projection of the first color filter in the second sub-pixel group on the base substrate.
  • the orthographic projections of the adjacent ninth recesses in the second direction on the base substrate at least partially overlap.
  • the orthographic projection of the first color filter on the base substrate and the power connection line on the substrate The orthographic projection on the base substrate at least partially overlaps, and the orthographic projection of the second color filter on the base substrate is respectively the orthographic projection of the power connection line on the base substrate and the first
  • the orthographic projection of the grid line on the base substrate at least partially overlaps, and the orthographic projection of the third color filter on the base substrate and the orthographic projection of the power connection line on the base substrate at least partially overlap.
  • the orthographic projection of the first color filter on the base substrate and the sensing connection line on the The orthographic projections on the base substrate at least partially overlap, and the orthographic projections of the second color filter on the base substrate respectively at least partially overlap the orthographic projections of the sensing connection lines on the base substrate , the orthographic projection of the third color filter on the base substrate at least partially overlaps the orthographic projection of the sensing connection line on the base substrate.
  • the data line includes a first data line, a second data line, a third data line and a fourth data line, and in the sub-pixel group, the first data line A data line and the second data line are located between the first color sub-pixel and the second color sub-pixel, the first data line and the second source electrode of the first color sub-pixel
  • the second data line is connected to the second source of the second color sub-pixel
  • the third data line and the fourth data line are located between the third color sub-pixel and the first
  • the third data line is connected to the second source of the third-color sub-pixel
  • the fourth data line is connected to the second source of the fourth-color sub-pixel extremely connected.
  • the orthographic projection of the first color filter on the base substrate and the second data line on the The orthographic projections on the base substrate at least partially overlap, and the orthographic projections of the second color filter on the base substrate respectively at least partially overlap the orthographic projections of the third data lines on the base substrate , the orthographic projection of the third color filter on the base substrate and the orthographic projection of the fourth data line on the base substrate at least partially overlap.
  • the first thin film transistor further includes: a first active layer located in the semiconductor layer and including a first channel region and a first channel region located in the first channel the first source region and the first drain region on both sides of the region; the first gate is located in the gate layer, and the orthographic projection of the first gate on the base substrate is the same as the first gate The orthographic projection of the channel region on the base substrate at least partially overlaps; the first source electrode and the first drain electrode are both located on the conductive layer, and the display substrate further includes a first via hole and a second via hole a via hole, the first via hole and the second via hole are located in the interlayer insulating layer, the first source electrode is connected to the first source region through the first via hole, so The first drain is connected to the first drain region through the second via hole.
  • the orthographic projection of the first channel region on the base substrate falls into the orthographic projection of the first body portion on the base substrate.
  • the display substrate further includes: a fourth via hole located in the interlayer insulating layer, and the second drain electrode communicates with the second drain hole through the fourth via hole
  • the conductive blocks are connected to each other, and the conductive light-shielding structure further includes: a second insulating part, the orthographic projection of the second insulating part on the base substrate and the orthographic projection of the fourth via hole on the base substrate The projections overlap at least partially.
  • the second insulating portion includes a second hollow portion, and the second hollow portion is filled with the material of the buffer layer.
  • the second hollow portion includes a second hollow ring, and the inner part of the second hollow ring and the outer side of the second hollow ring are both the conductive light shielding material of the structure.
  • the second insulating portion is an oxide portion.
  • the orthographic shapes of the first via hole and the fourth via hole on the base substrate are both anisotropic patterns, and include The long side.
  • the long side of the first via hole of the second color subpixel and the long side of the third color subpixel all extend along the first direction
  • the long sides of the first via holes of the first color sub-pixels and the long sides of the fourth color sub-pixels all extend along the second direction.
  • the long side of the fourth via hole of the second color sub-pixel and the long side of the third color sub-pixel all extend along the second direction
  • the long sides of the fourth via holes of the first color sub-pixels and the long sides of the fourth color sub-pixels all extend along the first direction.
  • the center of the fourth via hole of the first color sub-pixel, the first color sub-pixel of the second color The centers of the four via holes, the center of the fourth via hole of the third-color sub-pixel, and the center of the fourth via hole of the fourth-color sub-pixel are staggered in the second direction, so The center of the fourth via hole of the first color subpixel and the center of the fourth via hole of the fourth color subpixel are located on a first virtual straight line, and the second color subpixel The centers of the four via holes and the center of the fourth via hole of the third color sub-pixel are located on a second virtual straight line parallel to the first virtual straight line.
  • the material of the conductive light-shielding structure is selected from one or more of molybdenum and titanium, and the material of the conductive layer is selected from one of copper, molybdenum and titanium or more.
  • the conductive layer includes a first sub-metal layer and a second sub-metal layer stacked in a direction perpendicular to the base substrate, and the first sub-metal layer
  • the material of the layer is copper
  • the material of the second sub-metal layer is molybdenum-titanium alloy.
  • the material of the gate layer is selected from one or more of copper, molybdenum, and titanium.
  • the thickness of the conductive light-shielding structure in a direction perpendicular to the substrate is 90-120 nanometers, and the conductive layer is perpendicular to the substrate.
  • the thickness in the direction of the substrate is in the range of 200-600 nm.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate described in any one of the above.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, which includes: forming a conductive light-shielding material layer on a base substrate; patterning the conductive light-shielding material layer to form a conductive light-shielding structure; A buffer layer is formed on the side of the light-shielding structure away from the base substrate; a semiconductor layer is formed on the side of the buffer layer away from the conductive light-shielding structure; an interlayer insulation is formed on the side of the semiconductor layer away from the buffer layer forming a first contact hole in the interlayer insulating layer and the buffer layer; forming a conductive layer on the side of the interlayer insulating layer away from the semiconductor layer; the conductive layer includes a conductive structure, the The conductive light-shielding structure includes a first main body part and a first recessed part, the average thickness of the first recessed part in the direction perpendicular to the base substrate is smaller than the average thickness of the first main body part in the direction
  • forming a first contact hole in the interlayer insulating layer and the buffer layer includes: forming a first buffer portion and a first buffer portion in the buffer layer. Two buffer parts, one side of the first buffer part away from the base substrate is in contact with the conductive layer, and one side of the first buffer part close to the base substrate is in contact with the conductive light-shielding structure A side of the second buffer part away from the base substrate is arranged in contact with the interlayer insulating layer, and a side of the second buffer part close to the base substrate is in contact with the conductive light-shielding structure set up.
  • the first contact hole includes sidewalls, and the sidewalls at least include: a first sub-sidewall located in the interlayer insulating layer; Two sub-sidewalls are located in the buffer layer, the angle between the first sub-sidewall and the base substrate forms a first slope angle, and the angle between the second sub-sidewall and the base substrate forms a first slope angle a second slope angle, the first slope angle is smaller than the second slope angle; the contact parts of the second sub-sidewall and the first buffer part are located in the first buffer part and the second buffer part between.
  • the sidewall of the first contact hole further includes: a third sub-sidewall located in the first buffer part, the third sub-sidewall
  • the included angle between the side wall and the base substrate forms a third slope angle, and the first slope angle, the second slope angle and the third slope angle are different.
  • the method for fabricating a display substrate further includes: forming a flat layer on a side of the conductive layer away from the interlayer insulating layer, the flat layer including an anode hole; and forming a flat layer on the flat layer
  • An anode layer is formed on the side away from the conductive layer to form a plurality of sub-pixels on the base substrate, each of the sub-pixels includes an anode, and the anode includes a light extraction part, a driving part, and a connection between the light extraction part and the an extension part connected to a driving part, the driving part is at least partially located in the anode hole, and in at least one of the sub-pixels, the first contact hole is orthographically projected on the base substrate to the driving part
  • the orthographic projection on the base substrate at least partially overlaps
  • the display substrate further includes: a power line located on the conductive layer; and a sensing line located on the conductive layer; the power line and the sensing Lines are arranged in
  • the conductive layer further includes a first source electrode and a first drain electrode, and the conductive structure is the first drain electrode.
  • the semiconductor layer includes a first active layer
  • the first active layer includes a first channel region and is located in the first channel region the first source region and the first drain region on both sides
  • the manufacturing method further includes: forming a first contact hole in the interlayer insulating layer and the buffer layer at the same time as forming a first contact hole in the interlayer insulating layer a first via hole and a second via hole, the first source electrode is connected to the first source region through the first via hole, and the first drain electrode is connected to the first source region through the second via hole A drain region is connected.
  • the interlayer insulating layer and the buffer layer are patterned simultaneously by using the same etching process to form the first via hole and the first contact hole.
  • the interlayer insulating layer and the buffer layer are patterned using a halftone mask process to form the first via hole and the first contact hole.
  • the interlayer insulating layer and the buffer layer are patterned using a halftone mask process to form the first via hole and the first contact
  • the hole includes: forming a first photoresist on a side of the interlayer insulating layer away from the base substrate; exposing and developing the first photoresist by using a first halftone mask to form a first photoresist including a first halftone mask.
  • the orthographic projection on the base substrate overlaps with the orthographic projection of the first photoresist completely removed portion on the base substrate, and the orthographic projection of the first via on the base substrate is the same as the orthographic projection of the first via hole on the base substrate.
  • the orthographic projections of the first photoresist partially removed portion on the base substrate overlap.
  • the conductive light-shielding structure further includes a first insulating portion, and an orthographic projection of the first insulating portion on the base substrate is the same as the first insulating portion.
  • the orthographic projection of the via hole on the base substrate at least partially overlaps, and the orthographic projection of the first insulating portion on the base substrate and the orthographic projection of the first source region on the base substrate at least partially overlap.
  • the first insulating portion includes a first hollow portion, the first hollow portion is filled with the material of the buffer layer, and the conductive light-shielding material
  • Patterning the layer to form the conductive light-shielding structure includes: patterning the conductive light-shielding material layer through the same patterning process to form the first main body portion, the first recessed portion and the first hollow portion .
  • patterning the conductive light-shielding material layer to form a conductive light-shielding structure includes: forming on a side of the conductive light-shielding structure away from the base substrate photoresist; exposing and developing the photoresist using a second halftone mask to form a second photoresist complete removal portion, a second photoresist partial removal portion and a second photoresist retention portion the third photoresist pattern; using the third photoresist pattern as a mask to etch the conductive light-shielding material layer to remove the conductive light-shielding material layer corresponding to the completely removed portion of the second photoresist; performing ashing treatment on the third photoresist pattern, removing the second photoresist partially removed portion and thinning the second photoresist retaining portion to form a fourth photoresist pattern; and using the The fourth photoresist pattern is a mask to etch the
  • the first recessed portion includes a first edge portion, in a direction from the edge of the first recessed portion to the center of the first recessed portion , the thickness of the first edge portion in a direction perpendicular to the base substrate gradually decreases.
  • the first concave portion includes a first edge portion, and in a direction perpendicular to the base substrate, the first edge portion is close to the conductive
  • the fourth slope angle of the surface of the layer is continuously variable.
  • the surface of the first recessed portion close to the conductive structure is a continuous arc surface, or a combination of at least a continuous arc surface and at least a flat surface. noodle.
  • the first concave portion includes a first edge portion, and a fourth slope angle ⁇ on a surface of the first edge portion close to the conductive layer satisfies The following formula:
  • Lmax is the maximum aperture of the orthographic projection of the first recessed portion on the base substrate
  • H is the average thickness of the first main body portion
  • k is a constant greater than 1 and less than or equal to 2.
  • k 2
  • the range of the fourth slope angle is 1- ⁇ /18.
  • the size of the orthographic projection of the first recess on the base substrate in a direction parallel to the base substrate is 5- 10 microns.
  • FIG. 1 is a schematic cross-sectional view of a display substrate using a top-gate oxide thin film transistor
  • 2A is a schematic cross-sectional view of another display substrate
  • 2B is a schematic cross-sectional view showing a contact hole in a substrate
  • FIG. 3 is a schematic cross-sectional view of a via hole in a display substrate
  • FIG. 4 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • 5A is a schematic cross-sectional view of a display substrate along line AA' in FIG. 4 according to an embodiment of the disclosure
  • 5B is a schematic cross-sectional view of a display substrate according to an embodiment of the disclosure along the line BB' in FIG. 4;
  • 5C is a schematic diagram of a light converging effect of a recessed portion in a display substrate according to an embodiment of the disclosure
  • 5D is a schematic diagram of an anode hole in a display substrate according to an embodiment of the disclosure.
  • FIG. 6A is a schematic cross-sectional view of a first recess in a display substrate according to an embodiment of the disclosure
  • 6B is a schematic cross-sectional view of a first recess in a display substrate according to an embodiment of the disclosure
  • FIG. 7A is a schematic plan view of a pixel driving circuit in a display substrate according to an embodiment of the disclosure.
  • FIG. 7B is a schematic plan view of a pixel driving circuit in a display substrate according to an embodiment of the disclosure.
  • FIG. 8 is an equivalent circuit diagram of a pixel driving circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 9 is a timing diagram of signals on each signal line in a pixel driving circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 10A is a schematic plan view of a conductive light-shielding structure in a display substrate according to an embodiment of the disclosure
  • FIG. 10B is a schematic plan view of another conductive light-shielding structure in a display substrate according to an embodiment of the present disclosure
  • FIG. 10C is a schematic plan view of another conductive light-shielding structure in a display substrate according to an embodiment of the present disclosure
  • 11A is a schematic plan view of another display substrate provided by an embodiment of the disclosure.
  • 11B is a schematic diagram of the light condensing effect of a power supply recessed portion or a sensing recessed portion in a display substrate according to an embodiment of the disclosure
  • 11C is a schematic cross-sectional view of a power supply recess in a display substrate in a direction perpendicular to the base substrate according to an embodiment of the disclosure
  • 11D is a schematic cross-sectional view of a sensing recess in a display substrate in a direction perpendicular to the base substrate according to an embodiment of the disclosure
  • FIG. 12 is a schematic plan view of another display substrate provided by an embodiment of the disclosure.
  • FIG. 13 is a schematic cross-sectional view of a first drain electrode in a display substrate according to an embodiment of the disclosure
  • FIG. 14 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • FIG. 15 is a flowchart of a method for fabricating a display substrate according to an embodiment of the disclosure.
  • a thin film transistor (TFT) in a common liquid crystal display panel uses an amorphous silicon material as its active layer, but this thin film transistor is difficult to meet the driving needs of a self-luminous display device that requires high mobility current drive. Therefore, active matrix organic light emitting diode display devices (AMOLEDs) generally need to employ thin film transistors with high carrier mobility.
  • a small-sized active matrix organic light emitting diode display device can use low temperature polysilicon (LTPS) as the thin film transistor of the active layer, while a large-sized active matrix organic light emitting diode display device can use oxide (Oxide) as the active layer. layer of thin-film transistors.
  • LTPS low temperature polysilicon
  • Oxide oxide
  • top-gate thin-film transistors have the characteristics of short channels, and their on-state current Ion can be effectively increased, thereby significantly improving the display effect and reducing the Reduce power consumption.
  • the overlapping area between the gate and the source and drain of the top-gate thin film transistor is small, so the generated parasitic capacitance is also small; therefore, the top-gate thin film transistor may have defects such as short circuit between the gate and the source and drain. Sex is also less.
  • FIG. 1 is a schematic cross-sectional view of a display substrate using a top-gate oxide thin film transistor.
  • the display substrate 10 includes a base substrate 11 , a light shielding layer 12 , a buffer layer 13 , an active layer 14 , a gate insulating layer 15 , a gate electrode 16 , an interlayer insulating layer 17 and a conductive layer 18 .
  • the manufacturing process of the display substrate 10 may include: forming a light shielding layer 12 on the base substrate 11 ; forming a buffer layer 13 on the side of the light shielding layer 12 away from the base substrate 11 ; forming a buffer layer 13 on the side of the buffer layer 13 away from the base substrate 11 forming an oxide semiconductor layer; patterning the oxide semiconductor layer to form the active layer 14, and completing the conductive doping process in the non-channel region; forming a gate on the side of the active layer 14 away from the base substrate 11 Insulating layer 15; forming gate 16 on the side of gate insulating layer 15 away from active layer 14; An interlayer insulating layer 17 is formed on the side of the gate electrode 16 away from the base substrate 11 ; the display substrate on which the interlayer insulating layer 17 is formed is etched to form a via hole H1 and a via hole H2 in the interlayer insulating layer 17 at the same time can be etched synchronously with H1 and H2 to form contact holes CNT in the interlayer insulating layer 17 and the
  • a hole-type contact hole CNT in the interlayer insulating layer 17 and the buffer layer 13 forming a conductive layer 18 on the side of the interlayer insulating layer 17 away from the base substrate 11, and the conductive layer 18 includes a source S and a drain D, the source S is connected to the source region of the active layer 14 through the first via hole H1, the drain D is connected to the drain region of the active layer 14 through the second via hole H2, and is also connected to the light shielding through the contact hole CNT Layer 12 is connected.
  • FIG. 2A is a schematic cross-sectional view of another display substrate. As shown in FIG. 1 , since the drain D is connected to the drain region of the active layer 14 through the second via hole H2 and is also connected to the light shielding layer 12 through the contact hole CNT, the light shielding layer 12 and the drain D may have the same In addition, the drain D is also electrically connected to the anode 25 .
  • FIG. 2A is a schematic cross-sectional view of another display substrate. As shown in FIG.
  • the anode 25 , the drain D and the light shielding layer 12 have the same potential, so the anode 25 , the drain D and the light shielding layer 12 can be the same as the electrode in the conductive layer 18 (not necessarily the above-mentioned drain D , which can form interlayer capacitors for the drains of other thin film transistors in the pixel driving circuit) and the conductive block 19 of the active layer.
  • FIG. 2B is a schematic cross-sectional view showing a contact hole in a substrate. As shown in FIG. 2B , the contact holes in different film layers have different slope angles, resulting in a smaller contact area between the drain electrode and the light shielding layer. In the case shown in FIG.
  • FIG. 3 shows a schematic cross-sectional view of a via hole in an array substrate.
  • the active layer itself is designed to be thin, and some parts may be easily missing or The risk of being etched away, so that the vias pass directly through the active and buffer layers and come into contact with the light shielding layer.
  • the source electrode and the drain electrode of the thin film transistor are electrically connected through the light shielding layer, so that the bright spot is defective when the source electrode is supplied with voltage.
  • the display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate, each sub-pixel includes: a conductive light-shielding structure, located on the base substrate; a buffer layer, located on the side of the conductive light-shielding structure away from the base substrate; a semiconductor layer , is located on the side of the buffer layer away from the conductive light-shielding structure; the interlayer insulating layer is located on the side of the semiconductor layer away from the buffer layer; and the conductive layer is located on the side of the interlayer insulating layer away from the semiconductor layer, and includes a conductive structure, conductive shading
  • the structure includes a first main body part and a first recessed part, the average thickness of the first recessed part in the direction perpendicular to the base substrate is smaller than the average thickness of the first main body part in the direction perpendicular to the base substrate, and the display substrate
  • the display substrate increases the contact area between the first drain electrode and the conductive light-shielding structure, making the contact more sufficient, thereby reducing the contact resistance and improving the first drain electrode and the conductive light-shielding structure.
  • the electrical connection effect of the structure is not limited.
  • FIG. 4 is a schematic plan view of a display substrate according to an embodiment of the disclosure
  • FIG. 5A is a schematic cross-sectional view of a display substrate according to an embodiment of the disclosure along the line AA' in FIG. 4
  • FIG. 5B is an embodiment of the disclosure 4 is a schematic cross-sectional view of a display substrate provided by an example
  • FIG. 5C is a schematic diagram of a light converging effect of a recess in a display substrate provided by an embodiment of the disclosure
  • FIG. 5D is an embodiment of the disclosure.
  • a schematic diagram of an anode hole in a display substrate is provided. It should be noted that FIG. 4 is a plan view from the anode layer of the display substrate to the base substrate of the display substrate.
  • the display substrate 100 includes a base substrate 110 and a plurality of sub-pixels 300 located on the base substrate 110; each sub-pixel 300 includes a conductive light-shielding structure 122, a buffer layer 130, a semiconductor layer 140, a layer The insulating layer 170 and the conductive layer 180 are formed.
  • the conductive light-shielding structure 122 is located on the base substrate 110; the buffer layer 130 is located on the side of the conductive light-shielding structure 122 away from the base substrate 110; the semiconductor layer 140 is located at the side of the buffer layer 130 away from the conductive light-shielding structure 122; The semiconductor layer 140 is on the side away from the buffer layer 130 ; the conductive layer 180 is located on the side of the interlayer insulating layer 170 away from the semiconductor layer 140 .
  • the buffer layer 130 can insulate the conductive light-shielding structure 122 from the semiconductor layer 140 ; on the other hand, the buffer layer 130 can also cover defects or burrs on the base substrate 110 , thereby improving the performance of the buffer layer 130 The quality of the formed semiconductor layer 120 .
  • the conductive light-shielding structure 122 includes a first main body part 1220 and a first recessed part 1224 , and the average thickness of the first recessed part 1224 in a direction perpendicular to the base substrate 110 is smaller than that of the first main body part 1220 The average thickness in the direction perpendicular to the base substrate 110 .
  • the display substrate 100 further includes a first contact hole 251 , the first contact hole 251 passes through the interlayer insulating layer 170 and the buffer layer 130 , the conductive structure 181 is connected to the first recessed portion 1224 through the first contact hole 251 , and the first recessed portion 1224
  • the area of the surface close to the conductive layer 180 is larger than the area of the orthographic projection of the first concave portion 1224 on the base substrate 110 .
  • the conductive light-shielding structure includes a first main body portion and a first recessed portion, and the conductive structure is connected to the first recessed portion through a first contact hole. Since the first concave portion is recessed into the conductive light-shielding structure, the area of the surface of the first concave portion close to the first drain electrode is larger than the orthographic projection area of the first concave portion on the base substrate.
  • the display substrate can increase the contact area between the first drain electrode and the conductive light-shielding structure, and make the contact more sufficient, thereby reducing the contact resistance, improving the electrical connection effect between the first drain electrode and the conductive light-shielding structure, and effectively improving the The charging and discharging efficiency of the capacitor formed by the conductive structure.
  • each sub-pixel 300 further includes: a planarization layer 210 located on the side of the conductive layer 180 away from the semiconductor layer 140 and including an anode hole 263; and an anode 225 located on the planarization layer
  • the side of 210 away from the semiconductor layer 140 includes a light-exiting part 225A, a driving part 225B and an extension part 225C connecting the light-extracting part 225A and the driving part 225B.
  • the orthographic projection of the first contact hole 251 on the base substrate 110 at least partially overlaps with the orthographic projection of the driving portion 225B on the base substrate 110 .
  • the driving part 225B of the anode 225 can be disposed above the first contact hole 251 so that the driving part 225 is located above the first recessed part 1224 , so that the light-shielding performance of the first recessed part 1224 can be reduced due to the thinning of the first recessed part 1224 At this time, the driving part 225B of the anode 225 can block the light passing through the first recessed part 1224 .
  • the driving part 225 of the anode 225 by arranging the driving part 225 of the anode 225, the area of the anode 225 can also be increased, thereby increasing the capacitance value of the interlayer capacitor formed by the anode.
  • the display substrate 100 further includes: a power supply line 186 located in the conductive layer 180 ; and a sensing line 187 located in the conductive layer 180 ;
  • the plurality of sub-pixels 300 includes a first sub-pixel pair 360A and a second sub-pixel pair 360B, the first sub-pixel pair 360A includes two sub-pixels 300, which are located on both sides of the power line 186, respectively, and the second sub-pixel pair 360B includes two sub-pixels 300, which are located on the two sides of the sensing line 187, respectively.
  • the first sub-pixel pair 360A and the second sub-pixel pair 360B are alternately arranged, and in the two sub-pixels 300 in the second sub-pixel pair 360B, the anode hole 263 and the first recessed portion 1224 are orthographically projected on the base substrate 110 There is a first overlapping region 410 , and the area of the first overlapping region 410 is smaller than the area of the orthographic projection of the first contact hole 251 on the base substrate 110 .
  • the power supply lines 186 and the sensing lines 187 are arranged in a first direction, and both the power supply lines 186 and the sensing lines 187 extend in a second direction intersecting with the first direction.
  • the anode hole 263 and the first concave portion 1224 have the first overlapping region 410 . Therefore, when the first concave portion 1224 is thinned, the light is shielded.
  • the anode 225 at the position of the anode hole 263 has a curved interface, so that the light can be concentrated, thereby preventing the light passing through the first recess 1224 from affecting the normal display.
  • the anode 225 further includes a concave structure 2258 at the edge position of the anode hole 263 , and the concave direction of the concave structure 2258 faces the conductive light shielding structure 122 . Therefore, when the light-shielding performance of the first recessed portion 1224 is reduced due to the thinning, the recessed structure has at least two inclined surfaces, so that the light passing through the first recessed portion can be reflected. In addition, since the concave structure itself is a microstructure, the concave structure can also scatter the light passing through the first concave portion, thereby further preventing the light passing through the first concave portion 1224 from affecting normal display. It should be noted that the above-mentioned edge position of the anode hole refers to the boundary between the anode hole and the surface of the flat layer away from the semiconductor layer.
  • the above-mentioned conductive structure 181 may be the first drain electrode 1841 in the conductive layer 180 , and the first drain electrode 1841 may be the drain electrode of the first thin film transistor in the pixel driving circuit of the sub-pixel 300 .
  • the material of the conductive light-shielding structure 122 may be selected from one or more of molybdenum and titanium; the material of the conductive layer 180 may be selected from one or more of copper, molybdenum, and titanium.
  • the conductive layer 180 may be a multi-layer structure with a copper layer on top and a molybdenum-titanium mixture on the bottom. At this time, the molybdenum-titanium mixture on the lower layer can prevent the diffusion of the copper material on the upper layer and avoid affecting the electrical connection properties of the signal lines.
  • the embodiments of the present disclosure include, but are not limited to, the conductive light-shielding structure and the first drain electrode can also be made of other materials.
  • the thickness of the conductive light-shielding structure in the direction perpendicular to the base substrate is in the range of 90-120 nm, and the thickness of the conductive layer in the direction perpendicular to the base substrate is in the range of 200-600 nm.
  • the material of the semiconductor layer may be an oxide semiconductor, such as indium gallium zinc oxide (IGZO). Therefore, the thin film transistor in the pixel driving circuit of the array substrate has high carrier mobility.
  • IGZO indium gallium zinc oxide
  • the interlayer insulating layer may be made of one material or two different materials, deposited using processes at different temperatures.
  • the material of the interlayer insulating layer can be selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the buffer layer may also be selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride. It should be noted that the buffer layer and the interlayer insulating layer usually use different materials, even if the elements in the buffer layer and the interlayer insulating layer have the same composition, the proportions of these elements are also different.
  • the total thickness of the interlayer insulating layer ranges from 350 to 600 nanometers.
  • the total thickness of the interlayer insulating layer may be 400 nanometers.
  • the first recessed portion 1224 includes a first edge portion 12240 , in a direction from the edge of the first recessed portion 1224 to the center of the first recessed portion 1224 , the first edge
  • the thickness of the portion 12240 in the direction perpendicular to the base substrate 110 gradually decreases continuously. Since the average thickness of the first concave portion 1224 in the direction perpendicular to the base substrate is smaller than the average thickness of the first main body portion in the direction perpendicular to the base substrate, the light-shielding performance of the first concave portion may be affected.
  • the conductive structure at the position of the first recessed portion is far away from the
  • the surface of the base substrate is a convex surface, and the convex surface has the function of converging light; when there is light that can penetrate the first concave portion, the convex surface can condense the light, thereby preventing uncontrolled reflection of part of the ambient light inside the substrate , to avoid ambient light from affecting the normal display of the display substrate.
  • the above-mentioned “center of the first recessed portion” is the center of the plane shape of the orthographic projection of the first recessed portion on the base substrate; when the orthographic projection of the first recessed portion on the base substrate is a regular shape , the center can be the geometric center of the plane shape, and when the orthographic projection of the first recess on the substrate is an irregular shape, the center can also be the center of the largest straight line between two points on the plane shape ;
  • the above-mentioned “edge of the first recessed portion” may be the edge of the orthographic projection of the first recessed portion on the base substrate.
  • the surface of the conductive structure 181 at the position of the first concave portion 1224 away from the base substrate 110 is a convex surface, and the convex surface has the function of converging light; when there is light that can penetrate the first concave portion, the The convex surface can condense light, thereby preventing uncontrolled reflection of part of the ambient light inside the substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the first recessed portion 1224 in the direction perpendicular to the base substrate 110 , at least the first recessed portion 1224 is close to the edge portion, for example, the first edge portion 12240 described above is close to the conductive layer 180 .
  • the fourth slope angle of the surface is continuously changing. Therefore, even if light can penetrate the first recessed portion, the first recessed portion can make the conductive structure located at the position of the first recessed portion away from the convex surface of the base substrate to play a role of light gathering, thereby preventing the light from penetrating the entire
  • the display substrate affects the display effect of the light emitting area.
  • the surface of the first concave portion 1224 close to the conductive structure, such as the first drain electrode 1841 is a continuous arc surface or a combination of at least a continuous arc surface and at least a flat surface. Combination face.
  • the continuous curved surface or the combined surface formed by at least one continuous curved surface and at least one flat surface can play the role of light gathering, so that even if light can penetrate the first concave part, the first concave part can also prevent the light from passing through. It is observed by the user through the entire display substrate.
  • the embodiments of the present disclosure include, but are not limited to, the surface of the first concave portion close to the first drain can also be a curved surface.
  • the orthographic projection of the first contact hole 251 on the base substrate 110 at least partially overlaps the orthographic projection of the first recess 1224 on the base substrate 110 .
  • the conductive structures 181 in the conductive layer 180 such as the first drain electrode 1841 , can be connected to the first recessed portion 1224 through the first contact hole 251 .
  • the projected shape of the entire first recess 1224 on the base substrate 110 may be isotropic, such as a circle; or anisotropic, such as a square, a rectangle, a
  • anisotropic such as a square, a rectangle, a
  • the oval shape, the racetrack shape, etc. are not limited in this embodiment of the present disclosure.
  • FIG. 6A is a schematic cross-sectional view of a first recessed portion in a display substrate provided by an embodiment of the disclosure
  • FIG. 6B is a cross-sectional schematic view of a first recessed portion in a display substrate provided by an embodiment of the disclosure.
  • the first recessed portion 1224 includes a first edge portion 1224, and the fourth slope angle ⁇ of the first edge portion 12240 close to the surface of the conductive layer 180 satisfies the following formula:
  • Lmax is the maximum aperture of the orthographic projection of the first recessed portion on the base substrate
  • H is the average thickness of the first main body portion
  • k is a constant greater than 1 and less than or equal to 2.
  • the slope angle ⁇ of each position on the surface of the first recess 1224 close to the first drain electrode 1841 ranges from 1- ⁇ /18.
  • the slope angle ⁇ of each position on the surface of the first recessed portion 1224 close to the first drain electrode 1841 may range from 1- ⁇ /36.
  • the orthographic projection of the first recess 1224 on the base substrate 110 in a direction parallel to the base substrate 110 has a size in the range of 5-10 microns. That is, the width of the first recessed portion 1224 has a size range of 5-10 microns.
  • the size of the orthographic projection of the first concave portion 1224 on the base substrate 110 in a direction parallel to the base substrate 110 is 7.8 ⁇ m.
  • the buffer layer 130 includes: a first buffer part 131 , a side of the first buffer part 131 away from the base substrate 110 is disposed in contact with the conductive layer 180 , and the first buffer part 131 is arranged in contact with the conductive light-shielding structure 122 on the side close to the base substrate 110; and a second buffer portion 132, the side of the second buffer portion 132 away from the base substrate 110 is arranged in contact with the interlayer insulating layer 170, and the second buffer portion 132 is arranged in contact with the interlayer insulating layer 170.
  • a side of the portion 132 close to the base substrate 110 is disposed in contact with the conductive light-shielding structure 122 .
  • the first buffer portion 131 can play the role of supporting part of the conductive structure, and prevent the conductive structure from being disconnected due to a large drop or a large slope angle. bad. Therefore, the display substrate has a high yield.
  • the first buffer portion 131 is located in the first contact hole 251 and is disposed in contact with the conductive light shielding structure 122 ; the second buffer portion 132 is located on the side of the first buffer portion 131 away from the center of the first recessed portion 1224 .
  • the sidewalls of the first contact hole 251 at least include: a first sub-sidewall 2512 located in the interlayer insulating layer 170 ; and a second sub-sidewall 2514 located in the buffer layer 130, the included angle between the first sub-sidewall 2512 and the base substrate 110 constitutes a first slope angle ⁇ , the included angle between the second sub-sidewall 2514 and the base substrate 110 constitutes a second slope angle ⁇ , and the first slope angle ⁇ is less than The second slope angle ⁇ ; the contact portion of the second sub-sidewall 2514 and the first buffer portion 131 is located between the first buffer portion 131 and the second buffer portion 132 .
  • the etching efficiency of the etchant for them is also different, which easily leads to the formation of the slope angle of the first sub-sidewall and the second sub-side.
  • the slope angles of the walls are different. It should be noted that, due to process conditions and other reasons, the above-mentioned sub-sidewalls may not actually be smooth planes, so the slope angle formed by each of the above-mentioned sub-sidewalls and the base substrate can be set at equal intervals on the section of each sub-sidewall. The angle between the connecting line of several points and the base substrate.
  • the sidewalls of the first contact holes 251 further include: third sub-sidewalls 2516 located in the first buffer portion 131 , the third sub-sidewalls 2516 and the base substrate 110
  • the included angle constitutes a third gradient angle, and the first gradient angle ⁇ , the second gradient angle ⁇ and the third gradient angle ⁇ are different.
  • the second gradient angle ⁇ is greater than the third gradient angle ⁇
  • the first gradient angle ⁇ is greater than the third gradient angle ⁇
  • the ratio of the length of the first buffer part 131 to the average thickness of the first buffer part 131 is greater than that of the first sub-sidewall 2512 The ratio of the projected length on the base substrate 110 to the average thickness of the interlayer insulating layer 170 .
  • the sidewall of the first contact hole 251 includes a first subsidewall 2512 located in the interlayer insulating layer 170 , a second subsidewall 2514 located in the first buffer portion 131 , and The third sub-sidewall 2516 located in the second buffer portion 132; the first sub-sidewall 2512 and the second sub-sidewall 2514 are connected, the second sub-sidewall 2514 and the third sub-sidewall 2516 are connected, and the first The first slope angle ⁇ of the sub-sidewall 2512 , the second slope angle ⁇ of the second sub-sidewall 2514 , and the third slope angle ⁇ of the third sub-sidewall 2516 are different.
  • the etching efficiency of the etchant for them is also different, which easily leads to the formation of the slope angle of the first sub-sidewall and the second sub-side.
  • the slope angles of the walls are different.
  • the above-mentioned buffer layer can be formed by deposition at different temperatures, so that the inside of the buffer layer has different densities, so that the above-mentioned first buffer portion and second buffer portion can be formed.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned first buffer portion and second buffer portion can be fabricated by other suitable methods.
  • the first slope angle ⁇ of the first subsidewall 2512 is smaller than the second slope angle ⁇ of the second subsidewall 2514 , which has a second slope
  • the angle ⁇ is greater than the third slope angle ⁇ of the third sub-sidewall 2516
  • the first slope angle ⁇ of the first sub-sidewall 2512 is greater than the third slope angle ⁇ of the third sub-sidewall 2516 . That is, the second gradient angle ⁇ is greater than the first gradient angle ⁇ , and the first gradient angle ⁇ is greater than the third gradient angle ⁇ .
  • the fourth slope angle ⁇ is smaller than the third slope angle ⁇ of the third sub-sidewall.
  • the range of the first slope angle ⁇ of the first sub-sidewall 2512 is 45-75 degrees; the range of the second slope angle ⁇ of the second sub-sidewall 2514 is 75-90 degrees ; The range of the third slope angle ⁇ of the third sub-sidewall 2516 is 3-15 degrees.
  • the orthographic projection of the third sub-sidewall 2516 on the base substrate 110 in a direction parallel to the base substrate 110 has a size in the range of 0.2-1 ⁇ m.
  • the dimension of the orthographic projection of the third sub-sidewall 2516 on the base substrate 110 in a direction parallel to the base substrate 110 is 0.5 microns.
  • the dimension L of the orthographic projection of the first recessed portion 1224 on the base substrate 110 in a direction parallel to the base substrate 110 satisfies the following formula:
  • A is the maximum thickness of the first buffer portion
  • B is the maximum thickness of the second buffer portion
  • C is the maximum thickness of the interlayer insulating layer
  • ⁇ is the first slope angle
  • ⁇ is the second slope angle
  • ⁇ is the third slope angle
  • D is the maximum dimension of the orthographic projection of the first contact hole on the base substrate in a direction parallel to the base substrate.
  • the dimension L of the orthographic projection of the first recessed portion 1224 on the base substrate 110 in a direction parallel to the base substrate 110 satisfies the formula: 8(Acot ⁇ +Bcot ⁇ +Ccot ⁇ ) ⁇ L ⁇ D.
  • the first recessed portion 1224 includes a first edge portion 12240
  • the fourth slope angle ⁇ on the surface of the first edge portion 12240 close to the conductive layer 180 is smaller than the third sub-sidewall
  • the third slope angle of 2516 and satisfy (Acot ⁇ +Bcot ⁇ +Ccot ⁇ +L/2tan ⁇ ) ⁇ D/2
  • A is the maximum thickness of the first buffer
  • B is the maximum thickness of the second buffer
  • C is the interlayer insulation
  • ⁇ is the first slope angle
  • ⁇ is the second slope angle
  • ⁇ is the third slope angle
  • D is the orthographic projection of the first contact hole on the base substrate in the direction parallel to the base substrate biggest size.
  • the display substrate 100 further includes a gate insulating layer 150 and a gate electrode layer 160; the gate insulating layer 150 is located on the side of the semiconductor layer 140 away from the base substrate 110; The electrode layer 160 is located between the gate insulating layer 150 and the interlayer insulating layer 170 . Therefore, the pixel driving circuit of the display substrate 100 adopts the top-gate thin film transistor, which can have the characteristics of short channel, and the on-state current Ion can be effectively improved, thereby significantly improving the display effect and reducing the power consumption.
  • the display substrate 100 further includes a passivation layer 190 , a color filter layer 200 , a flat layer 210 and an anode layer 220 ;
  • the passivation layer 190 is located on the conductive layer 180 away from the base substrate One side of 110;
  • the color filter layer 200 is located on the side of the passivation layer 190 away from the conductive layer 180, and includes at least three filters 350 of different colors;
  • the anode layer 220 is located on the side of the flat layer 210 away from the color filter layer 200 .
  • FIG. 7A is a schematic plan view of a pixel driving circuit in a display substrate according to an embodiment of the disclosure
  • FIG. 7B is a schematic plan view of a pixel driving circuit in a display substrate according to an embodiment of the disclosure.
  • FIG. 4 As shown in FIG. 4 , FIG. 5A , FIG. 5B , FIG. 7A and FIG.
  • each sub-pixel 300 includes a pixel driving circuit 320
  • the pixel driving circuit 320 includes a first thin film transistor T1
  • the first thin film transistor T1 further includes a first active
  • the first active layer 141 is located in the semiconductor layer 140, and includes the first channel region 141C and the first channel region 141C
  • the first source region 141S and the first drain region 141D on both sides;
  • the first gate 161 is located in the gate layer 160, and the orthographic projection of the first gate 161 on the base substrate 110 and the first channel region 141C are The orthographic projections on the base substrate 110 at least partially overlap, and both the first source electrode 1821 and the first drain electrode 1841 are located on the conductive layer 180 .
  • the material of the gate layer 160 may be selected from one or more of copper, molybdenum, and titanium.
  • the gate layer 160 can also be a multi-layer structure with the copper layer on top and the molybdenum-titanium mixture on the bottom. At this time, the molybdenum-titanium mixture on the lower layer can prevent the diffusion of the copper material on the upper layer and avoid affecting the electrical connection properties of the signal lines.
  • the embodiments of the present disclosure include, but are not limited to, the first gate and the second gate may also be made of other materials.
  • the gate layer may adopt a single-layer structure or a multi-layer structure, which is not limited in this embodiment of the present disclosure.
  • the display substrate 100 further includes a first via hole 261 and a second via hole 262 ; the first via hole 261 and the second via hole 262 are located in the interlayer insulating layer 170 , the first source electrode 1821 is connected to the first source region 141S through the first via hole 261 , and the first drain electrode 1841 is connected to the first drain region 141D through the second via hole 262 . Therefore, the above-mentioned first gate electrode, the first active layer, the first source electrode and the first drain electrode can constitute the above-mentioned first thin film transistor.
  • the first thin film transistor may be a top-gate thin film transistor, which has the characteristics of a short channel, and its on-state current Ion can be effectively increased, thereby significantly improving the display effect and reducing power consumption.
  • the second thin film transistor T2 further includes a second active layer 142 , a second gate electrode 162 , a second source electrode 1822 and a second drain electrode 1842 ;
  • the two active layers 142 are located on the semiconductor layer 140 and include a second channel region 142C, a second source region 142S and a second drain region 142D on both sides of the second channel region 142C;
  • the second gate 162 is located on the gate In the electrode layer 160, the orthographic projection of the second gate electrode 162 on the base substrate 110 at least partially overlaps with the orthographic projection of the second channel region 142C on the base substrate 110, the second source electrode 1822 and the second drain electrode 1842 are both.
  • the second source electrode 1822 is connected to the second source region 142S through the via hole H3 in the interlayer insulating layer 170
  • the second drain electrode 1842 is connected to the second drain region 142D through the via hole H4 in the interlayer insulating layer 170 . Therefore, the above-mentioned second gate electrode, the second active layer, the second source electrode and the second drain electrode can constitute the above-mentioned second thin film transistor.
  • the second thin film transistor may be a top-gate thin film transistor, which has the characteristics of a short channel, and its on-state current Ion can be effectively increased, thereby significantly improving the display effect and reducing power consumption.
  • the third thin film transistor T3 further includes a third active layer 143 , a third gate electrode 163 , a third source electrode 1823 and a third drain electrode 1843 ;
  • the three active layers 143 are located on the semiconductor layer 140 and include a third channel region 143C, a third source region 143S and a third drain region 143D on both sides of the third channel region 143C;
  • the third gate 163 is located on the gate In the electrode layer 160, the orthographic projection of the third gate electrode 163 on the base substrate 110 at least partially overlaps with the orthographic projection of the third channel region 143C on the base substrate 110, and the third source electrode 1823 and the third drain electrode 1843 are both.
  • the third source electrode 1823 is connected to the third source region 143S through the via hole H5 in the interlayer insulating layer 170
  • the third drain electrode 1843 is connected to the third drain region 143D through the via hole H6 in the interlayer insulating layer 170 . Therefore, the above-mentioned third gate electrode, the third active layer, the third source electrode and the third drain electrode can constitute the above-mentioned third thin film transistor.
  • the third thin film transistor may be a top-gate thin film transistor, which has the characteristics of a short channel, and its on-state current Ion can be effectively increased, thereby significantly improving the display effect and reducing power consumption.
  • the anode hole 263 may penetrate the passivation layer 190 and the planarization layer 210 described above, and the anode 225 passes through the passivation layer 190 and the planarization layer 210.
  • the anode hole 263 therein is connected to the first drain electrode 1841 .
  • the display substrate can apply a driving current to the anode through the first thin film transistor, so as to drive the light-emitting layer corresponding to the anode to perform light-emitting display.
  • the first via hole 261 , the second via hole 262 , the first contact hole 251 and the anode hole 263 are arranged in sequence.
  • the shape of the orthographic projection of the first via hole 261 , the second via hole 262 , the first contact hole 251 and the anode hole 263 on the base substrate 110 may be an isotropic shape, such as a circle, or It is an anisotropic shape, for example, a rectangle, an ellipse, a racetrack shape, etc.; the embodiment of the present disclosure is not limited herein.
  • the specific shapes of the orthographic projections of the first via hole, the second via hole, the first contact hole and the third via hole on the base substrate can be adjusted according to the local actual space constraints of the layout of the display substrate. The extension direction of the long or short side of the hole.
  • the pixel driving circuit 320 further includes a second thin film transistor T2 and a third thin film transistor T3;
  • the second thin film transistor T2 includes a second gate electrode 162 , a second source electrode 1822 and a second drain electrode 1842
  • the third thin film transistor T3 includes a third gate electrode 163 , a third source electrode 1823 and a third drain electrode 1843 .
  • the semiconductor layer 140 also includes a conductorization block 147 .
  • FIG. 8 is an equivalent circuit diagram of a pixel driving circuit in a display substrate according to an embodiment of the present disclosure.
  • the first source electrode 1821 of the first thin film transistor T1 can be connected to the power line 186
  • the second source electrode 1822 of the second thin film transistor T2 is connected to the data line 185
  • the second thin film transistor T2 can be connected to the data line 185 .
  • the second gate 162 of the transistor T2 is connected to the first gate line 165; for example, the overlapping portion of the first gate line 165 and the second channel region 142C of the second active layer 142 of the second thin film transistor T2 is the second gate line 165
  • the gate 162; the second drain 1842 of the second thin film transistor T2 is connected to the first gate 161 of the first thin film transistor T1 and the conductor block 147 respectively; the third gate 163 of the third thin film transistor T3 is connected to the second gate
  • the line 166 is connected; the third source 1823 of the third thin film transistor T3 is connected to the sensing line 187; the third drain 1843 of the third thin film transistor T3 is connected to the first drain 1841 of the first thin film transistor T1.
  • the anode 225, the conductive light shielding structure 122, the second drain electrode 1842 and the conductorization block 147 between the anode 225 and the conductive light shielding structure 122 form an interlayer capacitance, ie, the storage capacitance Cst of the pixel driving circuit.
  • the conductive light-shielding structure 122 and the anode 225 have the same potential (when the first thin film transistor is turned on, the conductive light-shielding structure and the anode are electrically connected through the third via hole) as one pole of the storage capacitor, and the conductor block 147 is the storage capacitor. the other pole.
  • the conductorization block 147 is located in the semiconductor layer 140; the conductorization block 147 may be connected to the active layer of the first thin film transistor T1, the active layer of the second thin film transistor T2, and the The active layers of the three thin film transistors T3 are not connected, that is to say, the conductor block 147 is a conductor independent from the active layer of the first thin film transistor T1, the active layer of the second thin film transistor T2 and the third thin film transistor T3 The processed semiconductor block.
  • the embodiments of the present disclosure include, but are not limited to, the conductive block can also be connected to the active layer of the first thin film transistor, the active layer of the second thin film transistor, and the active layer of the third thin film transistor, but with these active layers There are semiconducting spaces between layers that are not conductive.
  • the portion where the second gate line 166 overlaps with the third channel region 143C of the third active layer 143 of the third thin film transistor T3 is the third gate 163 . Therefore, the display substrate can set a part of the third thin film transistor T3 outside the position where the first main body part 1220 is located, that is, the orthographic projection of a part of the third thin film transistor T3 on the base substrate 110 is located in the first main body part 1220 is outside the orthographic projection on the base substrate 110 . Therefore, the display substrate can utilize the space on both sides of the second gate line 166, thereby optimizing the distribution of transistors and improving the utilization rate of space. For example, as shown in FIGS.
  • the third A portion of the thin film transistor T3 may also be located on a side of the second gate line 166 away from the first body portion 1220 .
  • the second drain 1842 and the first gate 161 may be connected to the drain region of the second active layer 142 through the same via hole, thereby reducing the second drain 1842 shields the area of the first gate electrode 161, thereby reducing the risk of short circuit due to breakdown of the ILD layer caused by the inheritance of the film-forming topography in the actual process.
  • the second drain 1842 and the first gate 161 can be connected to the drain region of the second active layer 142 through the same via hole, which can also reduce the number of via holes on the second active layer 142 and improve the product yield. .
  • FIG. 9 is a timing diagram of signals on various signal lines in a pixel driving circuit in a display substrate according to an embodiment of the present disclosure.
  • the operation flow of the pixel driving circuit of the present disclosure will be described with reference to the equivalent circuit diagram shown in FIG. 8 and the timing diagram shown in FIG. 9 .
  • the first gate The line 165 and the second gate line 166 are both turn-on signals, the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the data signal DT is transmitted to the first gate 161 and the first gate 161 of the first thin film transistor T1 through the second thin film transistor T2.
  • the first pole of the storage capacitor Cst is the above-mentioned conductorization block 147; at this time, the reset signal writes the reset signal to the anode 225 through the sensing line 187 and the third thin film transistor T3; the first thin film transistor T1 is turned on and the anode 225 Charge to the working voltage; in the light-emitting stage, both the first gate line 165 and the second gate line 166 are off signals.
  • the voltage across the storage capacitor Cst remains unchanged, and the first thin film transistor T1 works in a saturated state and the current remains unchanged; at this time, the driving current on the power line 186 flows to the anode 225 through the first thin film transistor T1, thereby driving the corresponding light-emitting layer to emit light.
  • the work flow of the pixel driving circuit may further include an external compensation step process; in the external compensation process, the signals on the first gate line 165 and the second gate line 166 are both turn-on signals, and the second gate line 166 is a turn-on signal.
  • the thin film transistor T2 and the third thin film transistor T3 are both turned on, and the data signal DT is transmitted to the first gate 161 of the first thin film transistor T1 through the second thin film transistor T2; at this time, the analog-to-digital converter can pass the sensing line 187 and
  • the third thin film transistor T3 writes a reset signal to the node S, the first transistor T1 is turned on and charges the node S until the first thin film transistor is turned off, and the digital-to-analog converter samples the voltage on the sensing line 187 to obtain the first Threshold voltage of thin film transistor T1.
  • the external compensation process can be performed when the display device is turned off.
  • the orthographic projection of the first channel region 141C on the base substrate 110 falls into the orthographic projection of the first body portion 1220 on the base substrate 110 projection. Therefore, the first body portion 1220 can shield the first channel region 141C from light, thereby stabilizing the first thin film transistor, thereby improving display quality and service life.
  • the orthographic projection of the pixel driving circuit 320 on the base substrate 110 and the orthographic projection of the conductive light shielding structure 122 on the base substrate 110 at least partially overlap, so that the Various transistors or storage capacitors in the entire pixel driving circuit 320 can be protected from ambient light irradiation, so that the stability of the pixel driving circuit 320 can be improved.
  • the above-mentioned conductive light-shielding structure 122 may further include a first insulating portion 1221 ; the orthographic projection of the first insulating portion 1221 on the base substrate 110 and the first via hole 261
  • the orthographic projection on the base substrate 110 at least partially overlaps, and the orthographic projection of the first insulating portion 1221 on the base substrate 110 at least partially overlaps with the orthographic projection of the first source region 141S on the base substrate 110 .
  • the above-mentioned first insulating part is a part of the conductive light-shielding structure, and relative to other parts of the conductive light-shielding structure, the first insulating part is insulated from other parts.
  • the display substrate when the semiconductor layer itself is thin and the first source region is partially missing, when the etchant is etched down from the first source region to the first insulating portion, the first insulating The insulating part is insulated from other parts of the conductive light shielding structure, and even if the first source electrode is connected to the first insulating part through the first via hole, it will not cause the first source electrode to be electrically connected to other parts of the conductive light shielding structure. Therefore, the display substrate can reduce the process risk and improve the yield.
  • the first insulating portion 1221 includes a first hollow portion 1221A, and the first hollow portion 1221A is filled with the material of the buffer layer 130 . Therefore, the first insulating portion 1221 can be insulated from other parts of the conductive light shielding structure 122 through the first hollow portion 1221A. It should be noted that, the first insulating portion 1221 itself may be the first hollow portion 1221A, that is, the first insulating portion 1221 may be the removed portion of the conductive light-shielding structure 122 .
  • the first hollow portion 1221A may be a first hollow ring, that is, the first hollow portion may be an annular hollow portion.
  • Both the inner portion 1221B of the first hollow ring 1221A and the outer side of the first hollow ring 1221A are made of the conductive light-shielding structure 122 . Therefore, the first insulating portion 1221 can be insulated from other parts of the conductive light shielding structure 122 by providing the first hollow ring 1221A.
  • FIG. 10C is a schematic plan view of another conductive light-shielding structure in a display substrate according to an embodiment of the disclosure.
  • the first insulating portion 1221 is an oxidized portion. That is, a part of the conductive light shielding structure 122 may be oxidized through an oxidation process to form the above-mentioned first insulating portion 1221 .
  • FIG. 11A is a schematic plan view of another display substrate according to an embodiment of the disclosure.
  • each sub-pixel 300 includes a driving region 310 and a light emitting region 330 ; the conductive light shielding structure 122 is located in the driving region 310 .
  • the conductive light shielding structure 122 is arranged in the driving area 310 to prevent ambient light from affecting the pixel driving on the one hand.
  • the thin film transistors in the circuit can also prevent ambient light from passing through the driving area and affecting the normal display of the display substrate.
  • the light emitting direction of the display substrate can be the direction from the anode layer to the base substrate, that is, the display substrate adopts the bottom emission mode, or the direction from the base substrate to the anode layer, that is, the display substrate adopts the top emission mode. launch mode.
  • the display substrate 100 further includes a first gate line 165 , a second gate line 166 , a data line 185 , a power supply line 186 and a sensing line 187 ; the first gate line 165 and the second gate line 165
  • the gate lines 166 are all located on the gate layer 160 and all extend along the first direction; the data lines 185 , the power supply lines 186 and the sensing lines 187 are all located on the conductive layer 180 and all extend along the second direction.
  • the plurality of sub-pixels 300 are arrayed along the first direction and the second direction to form a plurality of sub-pixel rows 370 arranged along the second direction and a plurality of sub-pixel columns 380 arranged along the first direction.
  • the first gate line 165 is located between the driving region 310 and the light-emitting region 330, and the second gate line 166 is located between two adjacent sub-pixel rows 370; the power supply line 186, the sensing line 187 and the The data lines 185 are all located between two adjacent sub-pixel columns 380 .
  • the above-mentioned first direction may be the row direction of the sub-pixel array, and the above-mentioned second direction may be the column direction of the sub-pixel array.
  • the first source electrode 1821 of the first thin film transistor T1 is connected to the power line 186 through the first connection part 1868
  • the second source electrode 1822 of the second thin film transistor T2 is connected through the second connection part 1858 is connected to the data line 185
  • the first connection portion 1868A is provided on the same layer as the power line 186
  • the second connection portion 1858 is provided on the same layer as the data line 185 .
  • the direction from the first source electrode 1821 to the first drain electrode 1841 intersects with the extension direction of the first connection part 1868
  • the second source electrode The direction from 1822 to the second drain electrode 1842 (ie, the extending direction of the second channel region) intersects the extending direction of the second connection portion 1858 .
  • the direction from the third source electrode 1823 to the third drain electrode 1843 intersects the extending direction of the second gate line 166 . Therefore, on the one hand, the overlapping portion of the second gate line 166 and the third channel region 143C of the third active layer 143 of the third thin film transistor T3 can be used as the third gate 163, so that the second gate can be used.
  • the space on both sides of the line 166 is optimized, and the distribution of the transistors is optimized and the utilization rate of the space is improved; Therefore, the voltage drop on the second gate line 166 can also be reduced, and the electrical performance of the second gate line 166 can be improved.
  • the direction from the first source electrode 1821 to the first drain electrode 1841 is substantially parallel to the extending direction of the power supply line 186
  • the direction of the drain 1842 is substantially parallel to the extending direction of the data line 185 .
  • substantially parallel includes the case where it is completely parallel, and also includes the case where the included angle between the two directions is less than 10 degrees.
  • the direction from the third source electrode 1823 to the third drain electrode 1843 is substantially parallel to the extending direction of the sensing line 187 .
  • the display substrate 100 includes the above-mentioned power supply lines 186 and power supply connecting lines 1865 ; the power supply lines 186 are located on the conductive layer 180 ; That is, the power connection line 1865 and the conductive light shielding structure 122 can be formed by the same film layer and the same patterning process.
  • the power supply connection line 1865 includes a second main body portion 1865A and a plurality of power supply recessed portions 1865K, and the average thickness of the power supply recessed portions 1865K in a direction perpendicular to the base substrate 110 is smaller than that of the second main body portion 1865A.
  • the average thickness of the main body portion 1865A in the direction perpendicular to the base substrate 110 and the area of the surface of the power source recessed portion 1865K close to the conductive layer 180 is greater than the orthographic projection area of the power source recessed portion 1865K on the base substrate 110 .
  • the power supply connection line 1865 includes a second main body portion 1865A and a plurality of power supply recessed portions 1865K, and the plurality of power supply recessed portions 1865K can be used to connect the power supply line 186 with the pixel driving circuits of the plurality of sub-pixels 300 320 are electrically connected. Since the power supply recesses 1865K are recessed into the power supply connecting lines 1865 , the area of the surface of each power supply recess 1865K close to the conductive layer 180 is larger than the orthographic projection area of the power supply recesses 1865K on the base substrate 110 , thereby increasing the contact area of the electrical connection. , the contact is more sufficient, the contact resistance can be reduced, the electrical connection effect can be improved, and problems such as voltage drop (IR drop) can be effectively avoided.
  • IR drop voltage drop
  • FIG. 11B is a schematic diagram of the light condensing effect of a power supply recessed portion or a sensing recessed portion in a display substrate according to an embodiment of the disclosure.
  • the orthographic projection of at least one of the plurality of power supply recesses 1865K on the base substrate 110 and the orthographic projection of the filter 350 in the color filter layer 200 on the base substrate 110 are at least Partially overlapping.
  • the power supply recessed portion Similar to the first recessed portion, the power supply recessed portion also has the function of concentrating light, and since the power supply recessed portion can at least partially overlap with the optical filter, the ambient light can be concentrated to the corresponding optical filter, thereby effectively preventing The display caused by ambient light is not uniform, so as to avoid affecting the look and feel.
  • FIG. 11C is a schematic cross-sectional view of a power supply recess in a display substrate provided in an embodiment of the disclosure along a direction perpendicular to the base substrate.
  • the slope angle of the surface of the power supply recess 1865K near the conductive layer 180 may be the same as the slope angle of the surface of the first recess 1865K near the conductive layer.
  • the embodiments of the present disclosure include, but are not limited to, the slope angle of the surface of the power supply recessed portion close to the conductive layer and the slope angle of the surface of the first recessed portion close to the conductive layer may also be different.
  • the power recess 1865K includes a second edge 18650; in a direction from the edge of the power recess 1865K to the center of the power recess 1865K, the first The thickness of the two edge portions 18650 in the direction perpendicular to the base substrate 110 is continuously and gradually decreased. Since the average thickness of the portion of the power supply recess near the edge in the direction perpendicular to the base substrate is smaller than the average thickness of the first body portion in the direction perpendicular to the base substrate, the light shielding performance of the power recess may be affected.
  • the thickness in the direction perpendicular to the base substrate is continuously and gradually reduced, so that at the position of the power supply recessed portion
  • the surface of the conductive part (such as a part of the power line) away from the base substrate is a convex surface, and the convex surface has the function of converging light; Uncontrolled reflection of part of the ambient light inside the substrate prevents ambient light from affecting the normal display of the display substrate.
  • the surface of the conductive part (such as a part of the power supply line) at the position of the power supply recess 1865K away from the base substrate 110 is a convex surface, and the convex surface has the function of converging light; when light can penetrate the power supply
  • the concave part the convex surface can act on the convergence of light, thereby preventing uncontrolled reflection of part of the ambient light inside the substrate, and preventing the ambient light from affecting the normal display of the display substrate.
  • the portion of the power supply recessed portion 1865K close to the edge such as the conductive layer of the second edge portion 18650 described above
  • the fifth slope angle of the surface of 180 is continuously variable. Therefore, even if light can penetrate the recessed portion of the power supply, the recessed portion of the power supply can make the conductive portion located at the recessed portion of the power supply away from the convex surface of the base substrate to play a role of light gathering, thereby preventing the light from penetrating the entire display substrate and affecting the The display effect of the light-emitting area.
  • the display substrate 100 further includes a power contact hole 551 located in the interlayer insulating layer 170 and the buffer layer 130 , for example, the power contact hole 551 penetrates the interlayer insulating layer 170 and the buffer layer Layer 130.
  • the orthographic projection of the power supply contact hole 551 on the base substrate 110 at least partially overlaps the orthographic projection of the power supply recess 1865K on the base substrate 110 .
  • the buffer layer 130 includes: a third buffer part 133 located within the power contact hole 551 ; The side of the third buffer portion close to the base substrate is in contact with the conductive light-shielding structure; and the fourth buffer portion 134 is located on the side of the third buffer portion 133 away from the center of the power recessed portion 1865K. Therefore, when the above-mentioned conductive layer (eg, the portion corresponding to the power line) is deposited in the power contact hole 551, the third buffer portion 133 can play the role of supporting part of the conductive structure, preventing the conductive structure from being too large due to a drop or a slope angle. Defective disconnection caused by excessive size. Therefore, the display substrate has a high yield.
  • the sidewalls of the power contact hole 551 include a fourth subsidewall 5512 in the interlayer insulating layer 170 , a fifth subsidewall 5514 in the fourth buffer layer 134 , and a fourth subsidewall 5514 in the interlayer insulating layer 170 .
  • the angle between the sidewall 5512 and the base substrate 110 forms a sixth gradient angle ⁇ '
  • the angle between the fifth sub-sidewall 5514 and the base substrate 110 forms a seventh gradient angle ⁇ '
  • the sixth sub-sidewall 5516 and the substrate The eighth gradient angle ⁇ ' formed by the included angle of the substrate 110 .
  • the sixth, seventh, and eighth slope angles are different.
  • the contact portion of the fifth sub-sidewall 5514 and the third buffer portion 133 is located between the third buffer portion 133 and the fourth buffer portion 134 .
  • the etching efficiency of the etchant for them is also different, which easily leads to the slope angle of the formed fourth sub-sidewall, the fifth sub-side The slope angle of the wall is different from the slope angle of the sixth sub-side wall.
  • the above-mentioned buffer layer can be formed by deposition at different temperatures, so that the inside of the buffer layer has different densities, so that the above-mentioned third buffer portion and fourth buffer portion can be formed.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned third buffer portion and fourth buffer portion may be fabricated by other suitable methods.
  • the sixth slope angle ⁇ ' is less than the seventh slope angle ⁇ ', the seventh slope angle ⁇ ' is greater than the eighth slope angle ⁇ ', and the sixth slope angle ⁇ ' is greater than the eighth slope angle theta'. That is, the seventh gradient angle ⁇ ' is greater than the sixth gradient angle ⁇ ', and the sixth gradient angle ⁇ ' is greater than the eighth gradient angle ⁇ '.
  • the fourth gradient angle ⁇ is smaller than the eighth gradient angle ⁇ '.
  • the angles of the sidewalls in the power contact holes corresponding to the power recesses and the first contact holes corresponding to the first recesses may be different.
  • the seventh slope angle ⁇ ' in the power contact hole is smaller than the third slope angle ⁇ of the first contact hole. Therefore, since the sixth slope angle in the power contact hole is smaller, the fifth sub-side wall is made gentler, so that defects such as wire breakage can be better prevented.
  • the embodiments of the present disclosure include, but are not limited to, the seventh slope angle ⁇ ' in the power contact hole may also be greater than or equal to the second slope angle ⁇ of the first contact hole.
  • the eighth slope angle ⁇ ' in the power contact hole is larger than the third slope angle ⁇ of the first contact hole, so that the size of the third buffer portion can be reduced and the effect of electrical connection with the power source recess can be increased.
  • the embodiments of the present disclosure include, but are not limited to, the eighth slope angle in the power contact hole may also be smaller than the fourth slope angle of the first contact hole.
  • the display substrate 100 includes the above-mentioned sensing lines 187 and sensing connecting lines 1875 ; the sensing lines 187 are located on the conductive layer 180 , and the sensing connecting lines 1875 are on the same layer as the conductive light-shielding structure 122 In other words, the power connection line 1865 and the conductive light-shielding structure 122 can be formed by using the same film layer through the same patterning process.
  • the sensing connection line 1875 includes a third main body portion 1875A and a plurality of sensing recessed portions 1875K, and the sensing recessed portions 1875K have an average thickness in a direction perpendicular to the base substrate 110 .
  • the area of the surface of the sensing recess 1875K close to the conductive layer 180 is larger than the orthographic projection area of the sensing recess 1875K on the base substrate 110 less than the average thickness of the third main body 1875A in the direction perpendicular to the base substrate 110 .
  • the sensing connection line 1875 includes a third main body portion 1875A and a plurality of sensing recessed portions 1875K, which can be used to electrically connect the sensing line 187 to the pixel driving circuits 320 of the plurality of sub-pixels 300 .
  • Sexual connection Since the sensing recesses 1875K are recessed into the sensing connection lines 1875 , the area of each sensing recess 1875K close to the surface of the conductive layer 180 is larger than the orthographic projection area of the sensing recess 1875K on the base substrate 110 , thereby enabling electrical connection The contact area is increased and the contact is more sufficient, which can reduce the contact resistance, improve the electrical connection effect and effectively avoid problems such as IR drop.
  • the orthographic projection of at least one of the plurality of sensing recesses 1875K on the base substrate 110 and the filter 350 in the color filter layer 200 on the base substrate overlap at least partially.
  • the power supply recessed portion Similar to the first recessed portion, the power supply recessed portion also has the function of concentrating light, and since the power supply recessed portion can at least partially overlap with the optical filter, the ambient light can be concentrated to the corresponding optical filter, thereby effectively preventing The display caused by ambient light is not uniform, so as to avoid affecting the look and feel.
  • FIG. 11D is a schematic cross-sectional view of a sensing recess in a display substrate in a direction perpendicular to the base substrate according to an embodiment of the disclosure.
  • the slope angle of the surface of the sensing recess 1875K near the conductive layer 180 may be the same as the slope angle of the surface of the first recess 1875K near the conductive layer.
  • the embodiments of the present disclosure include, but are not limited to, the slope angle of the surface of the sensing recessed portion close to the conductive layer and the slope angle of the surface of the first recessed portion close to the conductive layer may also be different.
  • the sensing recess 1875K includes a third edge portion 18750 ; in a direction from the edge of the sensing recess 1875K to the center of the sensing recess 1875K
  • the thickness of the third edge portion 18750 in the direction perpendicular to the base substrate 110 is continuously and gradually decreased. Since the average thickness of the portion of the sensing recess near the edge in the direction perpendicular to the base substrate is smaller than the average thickness of the first main body portion in the direction perpendicular to the base substrate, the light-shielding performance of the sensing recess may be affected. influences.
  • the conductive portion at the position of the sensing recess (for example, The surface of a part of the sensing line) away from the base substrate is a convex surface, and the convex surface has the function of converging light; when there is light that can penetrate the sensing recess, the convex surface can condense the light, thereby preventing part of the ambient light from Uncontrolled reflection inside the substrate prevents ambient light from affecting the normal display of the display substrate.
  • the surface of the conductive portion eg, a portion of the sensing line
  • the convex surface has the function of converging light
  • the ninth slope angle of the third edge portion 18750 close to the surface of the conductive layer 180 in the direction perpendicular to the base substrate 110 is continuously changing. Therefore, even if light can penetrate the sensing recess, the sensing recess can make the conductive portion located at the position of the sensing recess away from the convex surface of the base substrate to play a role of light gathering, thereby preventing the light from penetrating the entire
  • the display substrate affects the display effect of the light emitting area.
  • the display substrate 100 further includes a sensing contact hole 552 located in the interlayer insulating layer 170 and the buffer layer 130 , for example, the sensing contact hole 552 penetrates through the interlayer insulating layer 170 and buffer layer 130.
  • the orthographic projection of the sensing contact hole 552 on the base substrate 110 at least partially overlaps the orthographic projection of the sensing recess 1875K on the base substrate 110 .
  • the buffer layer 130 includes: a fifth buffer part 135 located within the sensing contact hole 552 and disposed in contact with the sensing connection line 1875; and a sixth buffer part 136 located in the first One side of the fifth buffer portion 135 away from the center of the sensing recessed portion 1875K. Therefore, when the above-mentioned conductive layer (for example, the portion corresponding to the sensing line) is deposited in the sensing contact hole 552, the fifth buffer portion 135 can play the role of supporting part of the conductive structure, preventing the conductive structure from being too large due to a drop or Poor wire breakage caused by too large slope angle. Therefore, the display substrate has a high yield.
  • the side of the fifth buffer portion 135 away from the base substrate 110 is disposed in contact with the sensing connection line 1875 , and the side of the fifth buffer portion 135 close to the base substrate 110 is electrically shielded from light. Structure 122 is in contact.
  • the sidewalls of the sensing contact hole 552 include a seventh subsidewall 5522 in the interlayer insulating layer 170 , an eighth subsidewall 5524 in the sixth buffer layer 136 , and The ninth subsidewall 5526 located in the fifth buffer portion 135; the seventh subsidewall 5522 and the eighth subsidewall 5524 are connected, the eighth subsidewall 5524 and the ninth subsidewall 5526 are connected, and the seventh
  • the angle between the sub-sidewall 5522 and the base substrate 110 forms a tenth gradient angle ⁇ "
  • the angle between the eighth sub-sidewall 5524 and the base substrate 110 forms an eleventh gradient angle ⁇
  • the ninth sub-sidewall 5526 and the base substrate 110 form an eleventh gradient angle ⁇ ".
  • the included angle of the base substrate 110 constitutes a twelfth slope angle ⁇ "; the tenth slope angle, the eleventh slope angle and the twelfth slope angle are different.
  • the etching efficiency of the etchant is also different, so that the slope angle of the seventh sub-sidewall, the slope angle of the eighth sub-side wall and the ninth sub-side wall are easily different.
  • the above-mentioned buffer layer can be formed by deposition at different temperatures, so that the inside of the buffer layer has different densities, so that the above-mentioned fifth buffer portion and sixth buffer portion can be formed.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned fifth buffer portion and sixth buffer portion may be fabricated by other suitable methods.
  • the tenth slope angle ⁇ " is less than the eleventh slope angle ⁇ "
  • the eleventh slope angle ⁇ " is greater than the twelfth slope angle ⁇
  • the tenth slope angle ⁇ " is greater than the twelfth slope angle ⁇ ".
  • Twelve slope angles ⁇ " That is, the eleventh gradient angle ⁇ " is greater than the tenth gradient angle ⁇ "
  • the tenth gradient angle ⁇ " is greater than the twelfth gradient angle ⁇ ".
  • the embodiments of the present disclosure include but are not limited to this.
  • the fourth gradient angle ⁇ is smaller than the twelfth gradient angle ⁇ ".
  • the sensing contact holes corresponding to the sensing recesses and the sidewalls in the first contact holes corresponding to the first recesses The angle can be different.
  • the eleventh slope angle ⁇ ′′ in the sensing contact hole is smaller than the third slope angle ⁇ of the first contact hole.
  • the eleventh slope angle in the sensing contact hole is smaller, the eighth sub-side The wall is smoother, so that defects such as wire breakage can be better prevented.
  • embodiments of the present disclosure include, but are not limited to, the eleventh gradient angle ⁇ ′′ in the sensing contact hole may also be greater than or equal to the first contact hole The third slope angle ⁇ .
  • the twelfth slope angle ⁇ " in the sensing contact hole is greater than the third slope angle ⁇ of the first contact hole, so that the size of the fifth buffer portion can be reduced and the electrical contact with the sensing recessed portion can be increased. Connection effect.
  • the embodiments of the present disclosure include, but are not limited to, the twelfth slope angle in the sensing contact hole may also be smaller than the third slope angle of the first contact hole.
  • the plurality of subpixels 300 includes a first color subpixel 300A, a second color subpixel 300B, a third color subpixel 300C, and a fourth color subpixel 300D; in each subpixel row 370 , the first color sub-pixel 300A, the second color sub-pixel 300B, the third color sub-pixel 300C and the fourth color sub-pixel 300D are sequentially arranged along the first direction to form a sub-pixel group 390, and the power line 186 is located in the sub-pixel group 390 between the second color sub-pixel 300B and the third color sub-pixel 300C.
  • the display substrate 100 further includes a power supply connection line 1865 , and the power supply connection line 1865 is provided in the same layer as the conductive light-shielding structure 122 ; the power supply line 186 can pass through the contact holes passing through the interlayer insulating layer and the buffer layer. Connect to the power connection line 1865.
  • the display substrate 100 further includes a second contact hole 252 , a third contact hole 253 and a fourth contact hole 254 , the second contact hole 252 , the third contact hole 253 and the fourth contact hole 254 is located in the interlayer insulating layer 170 and the buffer layer 130; in the sub-pixel group 390, the power supply line 186 is connected to the power supply connection line 1865 through the second contact hole 252, and the first source 1821 of the second color sub-pixel 300B is connected to the power supply line 186 are connected to the same layer, and the first source electrode 1821 of the third color sub-pixel 300C is connected to the same layer of the power line 186 .
  • the above-mentioned connection on the same layer means that the first source electrode and the power supply line are directly connected through a connecting line provided on the same layer.
  • the first source electrode 1821 of the first color sub-pixel 300A is connected to the power connection line 1865 through the third contact hole 253
  • the first source electrode 1821 of the fourth color sub-pixel 300D is connected to the power supply connection line 1865 through the third contact hole 253
  • the four contact holes 254 are connected to the power connection lines 1865 .
  • the power connection line 1865 includes a second main body portion 1865A, a second recessed portion 1865B, a third recessed portion 1865C and a fourth recessed portion 1865D; the second recessed portion 1865B is in the base substrate 110
  • the orthographic projection of the second contact hole 252 on the base substrate 110 at least partially overlaps, and the thickness of the second concave portion 1865B in the direction perpendicular to the base substrate 110 is smaller than that of the second main portion 1865A in the direction perpendicular to the base substrate 110.
  • the area of the surface of the second concave portion 1865B close to the power supply line 186 is larger than the area of the orthographic projection of the second concave portion 1865B on the base substrate 110 .
  • the power line 186 can be connected to the second recessed portion 1865B of the power connection line 1865 through the second contact hole 252 . Since the second concave portion 1865B is a concave structure, the area of the surface of the second concave portion close to the power line is larger than the area of the orthographic projection of the second concave portion on the base substrate. Therefore, the display substrate can increase the contact area between the power supply line and the power supply connecting line, and make the contact more sufficient, thereby reducing the contact resistance and improving the electrical connection effect between the power supply line and the power supply connecting line.
  • At least a portion of the second concave portion close to the edge has a thickness in a direction perpendicular to the base substrate that continuously and gradually decreases. Since the average thickness of the second recessed portion in the direction perpendicular to the base substrate is smaller than the thickness of the second main body portion in the direction perpendicular to the base substrate, the light-shielding performance of the second recessed portion may be affected.
  • the second concave portion can also function as light Convergence, thereby preventing ambient light from penetrating the entire display substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the surface of the second concave portion close to the power line is an arc surface or a bent surface.
  • the orthographic projection of the third recess 1865C on the base substrate 110 at least partially overlaps the orthographic projection of the third contact hole 253 on the base substrate 110 , the third recess 1865C is at The thickness in the direction perpendicular to the base substrate 110 is smaller than the thickness of the second main body portion 1865A in the direction perpendicular to the base substrate 110 , and the area of the surface of the third recessed portion 1865C away from the base substrate 110 is larger than that of the third recessed portion The area of the orthographic projection of 1865C on the base substrate 110.
  • the first source electrode 1821 of the first color sub-pixel 300A can be connected to the third recessed portion 1865C of the power connection line 1865 through the third contact hole 253;
  • the first source electrode of the first color sub-pixel is connected to the third recessed portion. Since the third recessed portion is a recessed structure, the area of the surface of the third recessed portion away from the base substrate is larger than the area of the orthographic projection of the third recessed portion on the base substrate. Therefore, the display substrate can increase the contact area between the first source electrode of the first color sub-pixel and the power supply connection line, and the contact is more sufficient, thereby reducing the contact resistance and improving the first source electrode of the first color sub-pixel and the power supply.
  • the electrical connection effect of the connecting line is provided.
  • the thickness of at least a portion of the third recessed portion close to the edge in the direction perpendicular to the base substrate decreases continuously and gradually. Since the average thickness of the third recessed portion in the direction perpendicular to the base substrate is smaller than the thickness of the second main body portion in the direction perpendicular to the base substrate, the light shielding performance of the third recessed portion may be affected.
  • the third concave portion can also function as light Convergence, thereby preventing ambient light from penetrating the entire display substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the surface of the third recessed portion close to the power line can also be an arc surface or a bent surface.
  • the orthographic projection of the fourth recess 1865D on the base substrate 110 at least partially overlaps the orthographic projection of the fourth contact hole 254 on the base substrate 110 , and the fourth recess 1865D is at The thickness in the direction perpendicular to the base substrate 110 is smaller than the thickness of the second main body portion 1865A in the direction perpendicular to the base substrate 110 , and the area of the surface of the fourth recessed portion 1865D away from the base substrate 110 is larger than that of the fourth recessed portion The area of the orthographic projection of 1865D on the base substrate 110.
  • the first source electrode 1821 of the fourth color sub-pixel 300D can be connected to the fourth recessed portion 1865D of the power connection line 1865 through the fourth contact hole 254;
  • the first source electrode of the fourth color sub-pixel is connected to the fourth recessed portion. Since the fourth recessed portion is a recessed structure, the area of the surface of the fourth recessed portion away from the base substrate is larger than the area of the orthographic projection of the fourth recessed portion on the base substrate. Therefore, the display substrate can increase the contact area between the first source electrode of the fourth color sub-pixel and the power supply connection line, and make the contact more sufficient, thereby reducing the contact resistance and improving the first source electrode of the fourth color sub-pixel and the power supply.
  • the electrical connection effect of the connecting line is a recessed structure, the area of the surface of the fourth recessed portion away from the base substrate. Therefore, the display substrate can increase the contact area between the first source electrode of the fourth color sub-pixel and the power supply connection line, and make the contact more sufficient, thereby reducing the contact resistance and improving
  • the fourth concave portion close to the edge has a thickness in a direction perpendicular to the base substrate that decreases continuously and gradually. Since the average thickness of the fourth recessed portion in the direction perpendicular to the base substrate is smaller than the thickness of the second body portion in the direction perpendicular to the base substrate, the light-shielding performance of the fourth recessed portion may be affected.
  • the fourth concave portion can also function as light Convergence, thereby preventing ambient light from penetrating the entire display substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the surface of the fourth concave portion close to the power line can also be an arc surface or a bent surface.
  • the orthographic projection of at least one of the second recessed portion 1865B, the third recessed portion 1865C and the fourth recessed portion 1865D on the base substrate 110 and the filter in the color filter layer 200 are at least partially overlapped, so as to effectively prevent uneven display caused by ambient light and avoid affecting the appearance.
  • the second color sub-pixel 300B includes a first color filter 351 so as to emit light of the first color; the third color sub-pixel 300C includes a second color filter 352 , Therefore, the second color light can be emitted; the fourth color sub-pixel 300D includes the third color filter 353, so that the third color light can be emitted.
  • the first color sub-pixel 300D may not be provided with a filter so as to emit white light.
  • the display substrate can realize full-color display, and due to the use of white photonic pixels, the brightness and contrast of the display substrate are increased.
  • the first color may be red (R), the second color may be green (G), and the third color may be blue (B).
  • R red
  • G green
  • B blue
  • the embodiments of the present disclosure include, but are not limited to, the above three colors can also be other colors.
  • the display substrate 100 may further include a pixel-defining layer 370 , and the pixel-defining layer 370 may include a plurality of openings 375 , and a filter 350 may be disposed in the plurality of openings 375 .
  • the plurality of openings 375 include a first opening 3751, a second opening 3752 and a third opening 3753; the first color filter 351 is disposed at least partially in the first opening 3751; the second color filter 352 is at least partially disposed in the second opening 3752 ; the third color filter 353 is disposed at least partially in the third opening 3753 .
  • the shortest distance J3 between the outer edge of the third color filter 353 and the third opening 3753 is greater than the shortest distance J2 between the outer edge of the first color filter 351 and the first opening 3751, and the outer edge of the third color filter 353
  • the shortest distance J3 from the third opening 3753 is also greater than the shortest distance J1 from the outer edge of the second color filter 352 to the second opening 3752 .
  • the embodiments of the present disclosure include but are not limited to this. According to different product requirements, the shortest distance between the outer edge of the second color filter and the second opening may also be greater than the outer edge of the first color filter and the first opening.
  • the shortest distance between the outer edge of the third color filter and the third opening, or the shortest distance between the outer edge of the first color filter and the first opening may also be greater than the outer edge of the second color filter The shortest distance from the second opening and the shortest distance from the outer edge of the third color filter to the third opening.
  • most of the first color filter 351 is disposed in the light-emitting area 330 of the first color sub-pixel 300A; most of the second color filter 352 is disposed in the second color sub-pixel 300B
  • the third color filter 353 is mostly disposed in the light exit area 330 of the third color sub-pixel 300C.
  • the orthographic projection of at least one of the first color filter 351 and the second color filter 352 on the base substrate 110 and the second depression The orthographic projection of the portion 1865B on the base substrate 110 at least partially overlaps, and the orthographic projection of the third color filter 351 on the base substrate 110 at least partially overlaps the orthographic projection of the fourth recessed portion 1865D on the base substrate 110 . Therefore, even if the light-shielding performance of the second concave portion or the fourth concave portion is affected due to its thin thickness, the first color filter and the second color filter can further shield the second concave portion from light.
  • the third color filter can further shield the fourth recessed portion from light, thereby preventing ambient light from penetrating the entire display substrate and preventing ambient light from affecting the normal display of the display substrate.
  • the second concave portion when the thickness of the second concave portion in the direction perpendicular to the base substrate gradually decreases continuously from the edge of the second concave portion to the center of the second concave portion, even if there is light passing through the second concave portion, the second concave portion will The recessed portion can concentrate light on at least one of the first color filter and the second color filter, thereby effectively preventing ambient light from penetrating the entire display substrate.
  • the fourth concave portion When the thickness of the fourth concave portion in the direction perpendicular to the base substrate decreases continuously and gradually from the edge of the fourth concave portion to the center of the fourth concave portion, even if light passes through the fourth concave portion, the fourth concave portion may The light is concentrated on the third color filter, which can effectively prevent uneven display caused by ambient light and avoid affecting the look and feel.
  • the overlapping area between the orthographic projection of the third color filter 351 on the base substrate 110 and the orthographic projection of the fourth recess 1865D on the base substrate 110 is larger than that of the first color filter
  • the overlapping area between the orthographic projection of the sheet 351 or the second color filter 352 on the base substrate 110 and the orthographic projection of the second recess 1865B on the base substrate 110 is larger than that of the first color filter.
  • the sensing line 187 is located between two sub-pixel groups 390 adjacent in the first direction, and the two sub-pixel groups 390 adjacent in the first direction include the first sub-pixel group 391 and second sub-pixel group 392.
  • the display substrate 100 further includes a sensing connection line 1875, a fifth contact hole 255, a sixth contact hole 256, a seventh contact hole 257, an eighth contact hole 258 and a ninth contact hole 259; the sensing connection line 1875 and the conductive light-shielding structure 122 are arranged in the same layer, and the fifth contact hole 255 , the sixth contact hole 256 , the seventh contact hole 257 , the eighth contact hole 258 and the ninth contact hole 259 are located in the interlayer insulating layer 170 and the buffer layer 130 .
  • the sensing line 187 is connected to the sensing connection line 1875 through the fifth contact hole 255 .
  • FIG. 11A does not completely show the entire second sub-pixel group, and the composition of the second sub-pixel group may refer to the composition of the first sub-pixel group.
  • the third source electrode 1843 of the third color subpixel 300C in the first subpixel group 391 is connected to the sensing connection line 1875 through the sixth contact hole 256 , and the first subpixel group
  • the third source electrode 1843 of the fourth color sub-pixel 300D in 391 is connected to the sensing connection line 1875 through the seventh contact hole 257 .
  • the third source electrode 1843 of the first color subpixel 300A in the second subpixel group 392 is connected to the sensing connection line 1875 through the eighth contact hole 358
  • the third source electrode 1843 of the second color subpixel 300B in the second subpixel group 392 The three source electrodes 1843 are connected to the sensing connection line 1875 through the ninth contact hole 359 .
  • each sensing line can drive four sub-pixels at the same time, so that the wiring density can be reduced.
  • the arrangement space of the pixel driving circuits of each sub-pixel is approximately the same, so that the arrangement of the pixel driving circuits of each sub-pixel can be simplified. cloth.
  • the sensing connection line 1875 includes a third body portion 1875A, a fifth recessed portion 1875B, a sixth recessed portion 1875C, a seventh recessed portion 1875D, an eighth recessed portion 1875E, and a ninth recessed portion.
  • the thickness of the fifth recessed portion 1875B in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body portion 1875A in the direction perpendicular to the base substrate 110 ; the fifth The area of the surface of the recessed portion 155 close to the sensing line 187 is larger than the area of the orthographic projection of the fifth recessed portion 1875B on the base substrate 110 .
  • the sensing line 187 can be connected to the fifth recess 1875B of the sensing connecting line 1875 through the fifth contact hole 255 .
  • the display substrate can increase the contact area between the sensing line and the sensing connecting line, and make the contact more sufficient, thereby reducing the contact resistance and improving the electrical connection effect between the sensing line and the sensing connecting line.
  • the thickness of the fifth recessed portion in the direction perpendicular to the base substrate continuously and gradually decreases. Since the average thickness of the fifth recessed portion in the direction perpendicular to the base substrate is smaller than the thickness of the third main body portion in the direction perpendicular to the base substrate, the light-shielding performance of the fifth recessed portion may be affected.
  • the fifth recessed portion can also function as light Convergence, thereby preventing ambient light from penetrating the entire display substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the surface of the fifth concave portion close to the power line is an arc surface or a bent surface.
  • the thickness of the sixth recessed portion 1875C in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body portion 1875A in the direction perpendicular to the base substrate 110 , the sixth The area of the surface of the recessed portion 1875C away from the base substrate 110 is larger than the area of the orthographic projection of the sixth recessed portion 1875C on the base substrate 110 .
  • the third source electrodes 1843 of the third color sub-pixels 300C in the first sub-pixel group 391 are connected to the sixth recesses 1875C of the sensing connection lines 1875 through the sixth contact holes 356 .
  • the display substrate can increase the contact area between the third source electrode of the third color sub-pixel in the first sub-pixel group and the sensing connection line, and the contact is more sufficient, which can reduce the contact resistance and improve the first sub-pixel.
  • the electrical connection effect of the third source electrode of the third color sub-pixel in the group and the sensing connection line is more sufficient, which can reduce the contact resistance and improve the first sub-pixel.
  • the thickness of the sixth recessed portion in the direction perpendicular to the base substrate continuously and gradually decreases. Since the average thickness of the sixth recessed portion in the direction perpendicular to the base substrate is smaller than the thickness of the third main body portion in the direction perpendicular to the base substrate, the light shielding performance of the sixth recessed portion may be affected.
  • the sixth concave portion can also function as light Convergence, thereby preventing ambient light from penetrating the entire display substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the surface of the sixth recessed portion close to the power line is an arc surface or a bent surface.
  • the thickness of the seventh recessed portion 1875D in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body portion 1875A in the direction perpendicular to the base substrate 110 , the seventh The area of the surface of the recessed portion 1875D away from the base substrate 110 is larger than the area of the orthographic projection of the seventh recessed portion 1875D on the base substrate 110 .
  • the third source electrodes 1843 of the fourth color sub-pixels 300D in the first sub-pixel group 391 are connected to the seventh concave portion 1875D of the sensing connection line 1875 through the seventh contact hole 357 .
  • the display substrate can increase the contact area between the third source electrode of the fourth color sub-pixel in the first sub-pixel group and the sensing connection line, and the contact is more sufficient, which can reduce the contact resistance and improve the first sub-pixel.
  • the electrical connection effect of the third source electrode of the fourth color sub-pixel in the group and the sensing connection line is more sufficient, which can reduce the contact resistance and improve the first sub-pixel.
  • the thickness of the seventh recessed portion in the direction perpendicular to the base substrate continuously and gradually decreases. Since the average thickness of the seventh recessed portion in the direction perpendicular to the base substrate is smaller than the thickness of the third main body portion in the direction perpendicular to the base substrate, the light shielding performance of the seventh recessed portion may be affected.
  • the seventh recessed portion can also serve as light Convergence, thereby preventing ambient light from penetrating the entire display substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the surface of the seventh concave portion close to the power line is an arc surface or a bent surface.
  • the thickness of the eighth recessed portion 1875E in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body portion 1875A in the direction perpendicular to the base substrate 110 , the eighth The area of the surface of the recessed portion 1875E away from the base substrate 110 is larger than the area of the orthographic projection of the eighth recessed portion 1875E on the base substrate 110 .
  • the third source electrodes 1843 of the first color sub-pixels 300A in the second sub-pixel group 392 are connected to the eighth recesses 1875E of the sensing connection lines 1875 through the eighth contact holes 358 .
  • the eighth concave portion 1875E is a concave structure
  • the area of the surface of the eighth concave portion 1865E away from the base substrate 110 is larger than the area of the orthographic projection of the eighth concave portion 1865E on the base substrate 110 . Therefore, the display substrate can increase the contact area between the third source electrode of the first color sub-pixel in the second sub-pixel group and the sensing connection line, and the contact is more sufficient, which can reduce the contact resistance and improve the second sub-pixel.
  • the thickness of the eighth concave portion in a direction perpendicular to the base substrate continuously decreases gradually from the edge of the eighth concave portion to the center of the eighth concave portion. Since the average thickness of the eighth recessed portion in the direction perpendicular to the base substrate is smaller than the thickness of the third main body portion in the direction perpendicular to the base substrate, the light-shielding performance of the eighth recessed portion may be affected.
  • the eighth concave portion can also function as light Convergence, thereby preventing ambient light from penetrating the entire display substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the surface of the eighth concave portion close to the power line is an arc surface or a bent surface.
  • the thickness of the ninth recessed portion 1875F in the direction perpendicular to the base substrate 110 is smaller than the thickness of the third main body portion 1875A in the direction perpendicular to the base substrate 110 , the ninth The area of the surface of the recessed portion 1875F away from the base substrate 110 is larger than the area of the orthographic projection of the ninth recessed portion 1875F on the base substrate 110 .
  • the third source electrodes 1843 of the second color sub-pixels 300B in the second sub-pixel group 392 are connected to the ninth concave portion 1875F of the sensing connection line 1875 through the ninth contact hole 359 .
  • the ninth concave portion 1875F is a concave structure
  • the area of the surface of the ninth concave portion 1865F away from the base substrate 110 is larger than the area of the orthographic projection of the ninth concave portion 1865F on the base substrate 110 . Therefore, the display substrate can increase the contact area between the third source electrode of the second color sub-pixel in the second sub-pixel group and the sensing connection line, and the contact is more sufficient, which can reduce the contact resistance and improve the second sub-pixel.
  • the thickness of the ninth recessed portion in the direction perpendicular to the base substrate continuously and gradually decreases. Since the average thickness of the ninth recessed portion in the direction perpendicular to the base substrate is smaller than the thickness of the third main body portion in the direction perpendicular to the base substrate, the light shielding performance of the ninth recessed portion may be affected.
  • the ninth recessed portion can also serve as light Convergence, thereby preventing ambient light from penetrating the entire display substrate, and preventing ambient light from affecting the normal display of the display substrate.
  • the surface of the ninth concave portion close to the power cord is an arc surface or a bent surface.
  • At least one of the fifth recessed portion 1875B, the sixth recessed portion 1875C, the seventh recessed portion 1875D, the eighth recessed portion 1875E, and the ninth recessed portion 1875F is in the base substrate 110
  • the orthographic projection on the CF layer 200 overlaps at least partially with the orthographic projection of the filter 350 in the color filter layer 200 on the base substrate 110 , which can effectively prevent uneven display caused by ambient light and avoid affecting the look and feel.
  • the sensing connection line 1875 is located on the side of the second gate line 162 away from the first gate line 161 , and the second color filter in the first sub-pixel group 391
  • the orthographic projection of the light sheet 352 on the base substrate 110 at least partially overlaps the orthographic projection of the sixth recess 1875C of the first sub-pixel group 391 adjacent in the second direction on the base substrate 110 .
  • the second color filter in the first sub-pixel group can further shield the sixth concave portion, thereby preventing the The ambient light penetrates the entire display substrate and prevents the ambient light from affecting the normal display of the display substrate.
  • the sixth recessed portion when the thickness of the sixth recessed portion in the direction perpendicular to the base substrate continuously gradually decreases from the edge of the sixth recessed portion to the center of the sixth recessed portion, even if light passes through the sixth recessed portion, the sixth recessed portion is The recessed portion can condense light onto the above-mentioned second color filter, thereby effectively preventing ambient light from penetrating the entire display substrate.
  • the orthographic projection of the third color filter 353 in the first sub-pixel group 391 on the base substrate 110 is the first sub-pixel group 391 adjacent in the second direction.
  • the orthographic projections of the seventh recess 1875D on the base substrate 110 at least partially overlap. Therefore, even if the light-shielding performance of the seventh concave portion is affected due to its thin thickness, the third color filter in the first sub-pixel group can further shield the seventh concave portion, thereby preventing the The ambient light penetrates the entire display substrate and prevents the ambient light from affecting the normal display of the display substrate.
  • the seventh concave portion in the direction perpendicular to the base substrate continuously gradually decreases from the edge of the seventh concave portion to the center of the seventh concave portion, even if light passes through the seventh concave portion, the seventh The recessed portion can condense light onto the above-mentioned third color filter, thereby effectively preventing ambient light from penetrating the entire display substrate.
  • the orthographic projection of the first color filter 351 in the second sub-pixel group 392 on the base substrate 110 is at the position of the ninth recess 1875F adjacent in the second direction.
  • the orthographic projections on the base substrate 110 overlap at least partially. Therefore, even if the light-shielding performance of the ninth concave portion is affected due to its thin thickness, the first color filter in the second sub-pixel group can further shield the ninth concave portion, thereby preventing the The ambient light penetrates the entire display substrate and prevents the ambient light from affecting the normal display of the display substrate.
  • the ninth recess when the thickness of the ninth recess in the direction perpendicular to the base substrate continuously gradually decreases from the edge of the ninth recess to the center of the ninth recess, even if light passes through the ninth recess, the ninth recess is The recessed portion can condense light onto the above-mentioned first color filter, thereby effectively preventing ambient light from penetrating the entire display substrate.
  • the overlapping area between the orthographic projection of the third color filter 351 on the base substrate 110 and the orthographic projection of the sensing recess 1875K on the base substrate 110 is larger than that of the first color filter
  • the overlapping area between the orthographic projection of the sheet 351 or the second color filter 352 on the base substrate 110 and the orthographic projection of the sensing recess 1875K on the base substrate 110 is larger than that of the first color filter.
  • the orthographic projection of the first color filter 351 on the base substrate 110 and the orthographic projection of the power connection line 1865 on the base substrate 110 are at least partially overlapping, so that the capacitance values of various capacitors in the pixel driving circuit can be adjusted, thereby achieving better electrical performance.
  • the orthographic projection of the second color filter 352 on the base substrate 110 at least partially overlaps with the orthographic projection of the power connection line 1865 on the base substrate 110 and the orthographic projection of the first grid line 161 on the base substrate 110, respectively, Therefore, the capacitance values of various capacitors in the pixel driving circuit can also be adjusted, thereby achieving better electrical performance.
  • the orthographic projection of the third color filter 353 on the base substrate 110 at least partially overlaps with the orthographic projection of the power supply connection line 1865 on the base substrate 110, so that the capacitance values of various capacitors in the pixel driving circuit can also be adjusted, and further achieve better electrical properties.
  • the orthographic projection of the first color filter 351 on the base substrate 110 and the orthographic projection of the sensing connection line 1875 on the base substrate 110 are at least at least Partially overlapping, the orthographic projection of the second color filter 352 on the base substrate 110 and the orthographic projection of the sensing connection line 1875 on the base substrate 110 at least partially overlap, respectively, and the third color filter 353 is on the base substrate.
  • the orthographic projection on 110 at least partially overlaps the orthographic projection of sensing connection line 1875 on base substrate 110 .
  • the display substrate can adjust the capacitance values of various capacitors in the pixel driving circuit by adjusting the overlapping relationship between the optical filter and the sensing connection line, thereby achieving better electrical performance.
  • the data line 185 includes a first data line 185A, a second data line 185B, a third data line 185C, and a fourth data line 185D; in the sub-pixel group 390, the first data line 185A and the second data line 185B are located between the first color sub-pixel 300A and the second color sub-pixel 300B, and the first data line 185A is located on the side of the second data line 185B away from the second color sub-pixel 300B; the first data line 185A is connected to the second source electrode 1842 of the first color sub-pixel 300A, the second data line 185B is connected to the second source electrode 1842 of the second color sub-pixel 300B, and the third data line 185C and the fourth data line 185D are located in the third Between
  • the orthographic projection of the first color filter 351 on the base substrate 110 and the orthographic projection of the second data line 185A on the base substrate 110 are at least at least Partially overlapping, the orthographic projection of the second color filter 352 on the base substrate 110 and the orthographic projection of the third data line 185C on the base substrate 110 at least partially overlap, the third color filter 353 on the base substrate 110
  • the orthographic projection of the fourth data line 185D on the base substrate 110 at least partially overlaps.
  • the display substrate 100 further includes: a fourth via hole 264 located in the interlayer insulating layer 170 , and the second drain electrode 1842 is connected to the conductorization block 147 through the fourth via hole 264 .
  • the conductive light shielding structure 122 further includes: a second insulating portion 1222, the orthographic projection of the second insulating portion 1222 on the base substrate 110 and the orthographic projection of the fourth via hole 264 on the base substrate 110 at least partially overlap.
  • the above-mentioned second insulating portion is a part of the conductive light-shielding structure, and relative to other parts of the conductive light-shielding structure, the second insulating portion is insulated from other parts.
  • the display substrate when the semiconductor layer itself is thin and the second drain region is partially missing, when the etchant is etched down from the second drain region to the second insulating portion, due to the second insulating portion The insulating portion is insulated from other portions of the conductive light shielding structure, and even if the second drain electrode is connected to the second insulating portion through the third via hole, the second drain electrode is not electrically connected to other portions of the conductive light shielding structure. Therefore, the display substrate can reduce the process risk and improve the yield.
  • the second insulating portion 1222 includes a second hollow portion 1222A, and the second hollow portion 1222A is filled with the material of the buffer layer 130 . Therefore, the second insulating portion 1222 can be insulated from other parts of the conductive light-shielding structure 122 through the second hollow portion 1222A. It should be noted that, the second insulating portion 1222 itself may be the second hollow portion 1222A, that is, the second insulating portion 1222 may be the portion from which the conductive light shielding structure 122 is removed.
  • the second hollow portion 1222A may be a second hollow ring, that is, the second hollow portion may be an annular hollow portion.
  • the inner part of the second hollow ring 1222A and the outer side of the second hollow ring 1222A are both made of the material of the conductive light-shielding structure 122 . Therefore, the second insulating portion 1222 can be insulated from other parts of the conductive light shielding structure 122 by providing the second hollow ring 1222A.
  • the second insulating portion 1222 is an oxide portion. That is, a portion of the conductive light shielding structure 122 may be oxidized through an oxidation process to form the above-mentioned second insulating portion 1222 .
  • the orthographic shapes of the first via hole 261 and the fourth via hole 264 on the base substrate 110 are both anisotropic patterns and include long sides.
  • the direction of the first drain 1841 is the second direction, by aligning the long side or extension direction of the first via hole 261 of the second color sub-pixel 300B and the long side of the first via hole 261 of the third color sub-pixel 300C along the Extending in the first direction can make the size of the first via hole 261 of the second color sub-pixel 300B and the first via hole 261 of the third color sub-pixel 300C larger in the first direction, so that the current flowing through is larger. Large cross-sectional area, thereby reducing contact resistance.
  • the long side of the fourth via hole 264 of the second color subpixel 300B and the long side of the fourth via hole 264 of the third color subpixel 300C are both Extending in the second direction, the long side of the fourth via hole 264 of the first color sub-pixel 300A and the long side of the fourth via hole 264 of the fourth color sub-pixel 300D both extend in the first direction.
  • FIG. 12 is a schematic plan view of another display substrate provided by an embodiment of the disclosure.
  • the sub-pixels of different colors can use thin film transistors with different aspect ratios, the positions of the fourth via holes of the sub-pixels of different colors can be different. For example, as shown in FIG.
  • the center of the fourth via hole 264 of the first color sub-pixel 300A, the center of the fourth via hole 264 of the second color sub-pixel 300B, and the third color sub-pixel are offset in the second direction; the center of the fourth via hole 264 of the first color sub-pixel 300A and the fourth color
  • the center of the fourth via hole 264 of the sub-pixel 300D is located on the first virtual straight line 401, the center of the fourth via hole 264 of the second color sub-pixel 300B and the center of the fourth via hole 264 of the third color sub-pixel 300C are located on the same On the second virtual straight line 402 that is parallel to the first virtual straight line.
  • ambient light can be prevented from passing through the fourth via hole of the first color subpixel 300A, the fourth via hole of the second color subpixel 300B, the fourth via hole of the third color subpixel 300C, and the fourth color subpixel
  • the regular bright lines formed by the reflection of the fourth via hole of 300D can improve the display quality.
  • the conductive layer 180 or the first drain electrode 1841 includes a first sub-metal layer 1841A and a second sub-metal layer 1841B stacked in a direction perpendicular to the base substrate 110 ; the material of the first sub-metal layer 1841A It is copper, and the material of the second sub-metal layer 1841B is molybdenum-titanium alloy.
  • FIG. 14 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • the display device 500 includes the above-mentioned display substrate 100 .
  • the display device has beneficial technical effects corresponding to the technical effects of the display substrate it includes.
  • the conductive structure is connected to the first recessed portion through the first contact hole. Since the first concave portion is recessed into the conductive light-shielding structure, the area of the surface of the first concave portion close to the conductive layer is larger than the orthographic projection area of the first concave portion on the base substrate.
  • the contact area of the conductive structure such as the first drain electrode and the conductive light-shielding structure is increased, and the contact is more sufficient, which can reduce the contact resistance, improve the electrical connection effect between the conductive structure and the conductive light-shielding structure, and can effectively improve the conductive structure.
  • the charge-discharge efficiency of the formed capacitor is increased, and the contact is more sufficient, which can reduce the contact resistance, improve the electrical connection effect between the conductive structure and the conductive light-shielding structure, and can effectively improve the conductive structure.
  • the display device may be an electronic product such as a TV, a tablet computer, a notebook computer, an electronic picture frame, a navigator, and a smart phone.
  • FIG. 15 is a flowchart of a method for fabricating a display substrate according to an embodiment of the disclosure. As shown in FIG. 15 , the manufacturing method of the display substrate includes the following steps S101-S107.
  • Step S101 forming a conductive light-shielding material layer on the base substrate.
  • the base substrate can be a transparent substrate made of inorganic materials such as glass and substrate.
  • the base substrate can also be a transparent substrate made of organic materials such as polyimide, polycarbonate, and polyethylene terephthalate.
  • the base substrate can be a flexible substrate such as a polyimide substrate.
  • the embodiments of the present disclosure include, but are not limited to, the rigid substrate as the base substrate.
  • the material of the conductive light-shielding material layer may be selected from one or more of molybdenum and titanium.
  • the embodiments of the present disclosure include, but are not limited to, the materials of the conductive light-shielding material layer can also be made of other materials.
  • a film-forming process such as sputtering process, vapor deposition process, etc. can be used to form the conductive light-shielding material layer on the base substrate.
  • Step S102 patterning the conductive light-shielding material layer to form a conductive light-shielding structure.
  • the process of patterning the conductive light-shielding material layer may include exposure, development, etching process, and the like.
  • a photoresist can be coated on the conductive light-shielding material layer first, then a photoresist pattern can be formed on the conductive light-shielding material layer through exposure and development processes, and then the conductive light-shielding material can be etched by using the photoresist pattern, and finally The photoresist pattern is peeled off to form a conductive light-shielding structure.
  • Step S103 forming a buffer layer on the side of the conductive light-shielding structure away from the base substrate.
  • the material of the buffer layer may be at least one of silicon nitride, silicon oxide and silicon oxynitride.
  • the thickness of the buffer layer may range from 380-420 nanometers.
  • the embodiments of the present disclosure include but are not limited to this, and the thickness of the buffer layer can be set according to actual requirements.
  • Step S104 forming a semiconductor layer on the side of the buffer layer away from the conductive light-shielding structure.
  • the material of the semiconductor layer may be an oxide semiconductor, such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • a vapor deposition process may be used to form the semiconductor layer on the side of the buffer layer away from the conductive light shielding structure.
  • the embodiments of the present disclosure include, but are not limited to, other suitable processes to form the semiconductor layer.
  • the thickness of the semiconductor layer may range from 35-45 nanometers, such as 40 nanometers.
  • the embodiments of the present disclosure include but are not limited thereto, and the thickness of the semiconductor layer can be set according to actual requirements.
  • Step S105 forming an interlayer insulating layer on the side of the semiconductor layer away from the buffer layer.
  • the material of the interlayer insulating layer can be selected from at least one of silicon nitride, silicon oxide and silicon oxynitride.
  • the embodiments of the present disclosure include but are not limited to this, and the material of the interlayer insulating layer may also be other materials.
  • the material of the interlayer insulating layer and the material of the buffer layer can be the same or different. Even if the materials of the interlayer insulating layer and the buffer layer are the same, different process temperatures can be used for the interlayer insulating layer and the buffer layer to form a film. The layer densities are also different, resulting in different slope angles at which the interlayer insulating layer and the buffer layer are etched.
  • the thickness of the interlayer insulating layer may range from 350 to 600 nanometers, such as 400 nanometers.
  • the embodiments of the present disclosure include but are not limited to this, and the thickness of the interlayer insulating layer can be set according to actual requirements.
  • Step S106 forming a first contact hole in the interlayer insulating layer and the buffer layer.
  • an etching process (eg, a wet etching process) may be used to form the first contact hole in the interlayer insulating layer and the buffer layer.
  • Step S107 forming a conductive layer on the side of the interlayer insulating layer away from the semiconductor layer, the conductive layer includes a conductive structure, such as a first drain electrode, the conductive light-shielding structure includes a first main body portion and a first recessed portion, and the first recessed portion is vertical.
  • the average thickness in the direction of the base substrate is smaller than the average thickness of the first main body part in the direction perpendicular to the base substrate, the first contact hole passes through the interlayer insulating layer and the buffer layer, and the conductive structure passes through the first contact hole and is connected to the buffer layer.
  • the first concave portion is connected, and the area of the surface of the first concave portion close to the conductive layer is larger than the area of the orthographic projection of the first concave portion on the base substrate.
  • the conductive light-shielding structure includes a first main body portion and a first recessed portion, and the first drain electrode is connected to the first recessed portion through a first contact hole. Since the first concave portion is recessed into the conductive light-shielding structure, the area of the surface of the first concave portion close to the first drain electrode is larger than the orthographic projection area of the first concave portion on the base substrate.
  • the display substrate manufactured by the display substrate manufacturing method can increase the contact area between the first drain electrode and the conductive light-shielding structure, and make the contact more sufficient, thereby reducing the contact resistance and improving the electrical connection effect between the first drain electrode and the conductive light-shielding structure. And the charging and discharging efficiency of the capacitor formed by the conductive structure can be effectively improved.
  • the material of the conductive layer may be selected from one or more of copper, molybdenum and titanium.
  • the embodiments of the present disclosure include, but are not limited to, the conductive layer can also be made of other materials.
  • the conductive light-shielding structure has a thickness in a range of 90-120 nanometers in a direction perpendicular to the base substrate, and a thickness of the conductive layer in a direction perpendicular to the base substrate in a range of 200-600 nanometers.
  • forming the first contact hole in the interlayer insulating layer and the buffer layer includes: forming a first buffer part and a second buffer part in the buffer layer, the first buffer part being away from the One side of the base substrate is arranged in contact with the conductive layer, the side of the first buffer portion close to the substrate substrate is arranged in contact with the conductive light-shielding structure, and the side of the second buffer portion away from the substrate substrate is arranged in contact with the interlayer insulating layer, And the side of the second buffer portion close to the base substrate is arranged in contact with the conductive light-shielding structure.
  • the first buffer portion can play the role of supporting part of the conductive structure, and prevent the conductive structure from being broken due to a large drop or a large slope angle. Therefore, the display substrate has a high yield.
  • the first contact hole includes sidewalls, and the sidewalls include at least: a first sub-sidewall located in the interlayer insulating layer; and a second sub-sidewall located in the buffer layer, wherein the first sub-sidewall and the liner
  • the included angle of the bottom substrate constitutes a first slope angle
  • the included angle of the second sub-sidewall and the base substrate constitutes a second slope angle
  • the first slope angle is smaller than the second slope angle
  • the contact portion is located between the first buffer portion and the second buffer portion.
  • the sidewall of the first contact hole further includes: a third sub-sidewall located in the first buffer portion, and an included angle between the third sub-sidewall and the base substrate forms a third slope angle, the first slope angle, The second slope angle and the third slope angle are different.
  • the manufacturing method of the display substrate further includes: forming a flat layer on a side of the conductive layer, such as the source-drain metal layer, away from the interlayer insulating layer, the flat layer includes an anode hole;
  • An anode layer is formed on one side to form a plurality of sub-pixels on the base substrate, each sub-pixel includes an anode, the anode includes a light extraction part, a driving part and an extension part connecting the light extraction part and the driving part, and the driving part is at least partially located in the anode hole
  • the orthographic projection of the first contact hole on the base substrate at least partially overlaps with the orthographic projection of the driving portion on the base substrate
  • the display substrate further comprises: a power supply line located in the conductive layer; and a sensing line , located in the conductive layer; the power supply lines and the sensing lines are arranged in a first direction, and both the power supply lines and the sensing lines extend in a second direction intersecting with the first direction
  • the anode hole and the first concave portion are orthographically projected on the base substrate to have a first overlapping area, and the first overlapping area is The area is smaller than the orthographic projection area of the first contact hole on the base substrate. Therefore, in the two sub-pixels in the second sub-pixel pair, there is a first overlapping area between the anode hole and the first concave portion. Therefore, when the light-shielding performance of the first concave portion is reduced due to thinning, the anode hole and the first concave portion have a first overlapping area.
  • the anode at the position has a curved interface, so that light can be concentrated, so as to prevent the light passing through the first recessed portion from affecting normal display.
  • the anode further includes a concave structure at the edge of the anode hole, and the concave direction of the concave structure faces the conductive light-shielding structure. Therefore, when the light-shielding performance of the first concave portion is reduced due to the thinning, the concave structure has at least two inclined surfaces, so that the light transmitted through the first concave portion can be reflected. In addition, since the concave structure itself is a microstructure, the concave structure can also scatter the light passing through the first concave portion, thereby further preventing the light passing through the first concave portion from affecting normal display. It should be noted that the above-mentioned edge position of the anode hole refers to the boundary between the anode hole and the surface of the flat layer away from the semiconductor layer.
  • the conductive layer further includes a first source electrode and a first drain electrode, and the conductive structure is the first drain electrode.
  • the conductive layer further includes a first source electrode
  • the semiconductor layer includes a first active layer
  • the first active layer includes a first channel region and first source regions located on both sides of the first channel region and The first drain region
  • the method for fabricating the display substrate further includes: forming a first contact hole in the interlayer insulating layer and the buffer layer, and forming a first via hole and a second via hole in the interlayer insulating layer; the first source The electrode is connected with the first source region through the first via hole, and the first drain electrode is connected with the first drain region through the second via hole.
  • the interlayer insulating layer and the buffer layer are simultaneously patterned using the same etching process to form the first via hole and the first contact hole.
  • the display substrate fabricated by the manufacturing method can increase the contact area between the first drain electrode and the conductive light-shielding structure, and make the contact more sufficient, thereby reducing the contact resistance and improving the electrical connection effect between the first drain electrode and the conductive light-shielding structure.
  • the interlayer insulating layer and the buffer layer are also patterned using a halftone mask process to form the first via hole and the first contact hole.
  • patterning the interlayer insulating layer and the buffer layer using a halftone mask process to form the first via hole and the first contact hole includes: forming a first photoresist on a side of the interlayer insulating layer away from the base substrate; using The first halftone mask exposes and develops the first photoresist to form a first photoresist including a first photoresist complete removal portion, a first photoresist partial removal portion, and a first photoresist retention portion Glue pattern; using the first photoresist pattern as a mask to etch the interlayer insulating layer to remove the interlayer insulating layer corresponding to the completely removed portion of the first photoresist; performing ashing treatment on the first photoresist pattern , removing the first photoresist part removal part and thinning the first photoresist retaining part to form a second photoresist pattern; and using the second photoresist pattern as a mask to etch the buffer layer, the first contact
  • the conductive light-shielding structure further includes a first insulating portion, an orthographic projection of the first insulating portion on the base substrate at least partially overlaps with an orthographic projection of the first via hole on the base substrate, and the first insulating portion is on the base substrate.
  • the orthographic projection on the base substrate at least partially overlaps the orthographic projection of the first source region on the base substrate.
  • the above-mentioned first insulating part is a part of the conductive light-shielding structure, and relative to other parts of the conductive light-shielding structure, the first insulating part is insulated from other parts.
  • the display substrate can reduce the process risk and improve the yield.
  • the first insulating portion 1221 includes a first hollow portion 1221A, and the first hollow portion 1221A is filled with the material of the buffer layer 130 . Therefore, the first insulating portion 1221 can be insulated from other parts of the conductive light shielding structure 122 through the first hollow portion 1221A. It should be noted that, the first insulating portion 1221 itself may be the first hollow portion 1221A, that is, the first insulating portion 1221 may be the removed portion of the conductive light-shielding structure 122 .
  • the first hollow portion 1221A may be a first hollow ring, that is, the first hollow portion may be an annular hollow portion.
  • the inner part of the first hollow ring 1221A and the outer side of the first hollow ring 1221A are both made of the material of the conductive light-shielding structure 122 . Therefore, the first insulating portion 1221 can be insulated from other parts of the conductive light shielding structure 122 by providing the first hollow ring 1221A.
  • the first insulating portion 1221 is an oxidized portion. That is, a part of the conductive light shielding structure 122 may be oxidized through an oxidation process to form the above-mentioned first insulating portion 1221 .
  • patterning the conductive light-shielding material layer to form the conductive light-shielding structure includes: applying the same patterning process to the conductive light-shielding material The layer is patterned to form a first body portion, a first recessed portion, and a first hollow portion. That is to say, the first concave portion and the first hollow portion are formed in the same patterning process, so that the mask process can be reduced, thereby reducing the cost.
  • patterning the conductive light-shielding material layer to form the conductive light-shielding structure includes: forming a photoresist on a side of the conductive light-shielding structure away from the base substrate; exposing and developing the photoresist to form a third photoresist pattern including a second photoresist complete removal part, a second photoresist partial removal part and a second photoresist retention part; and using the third photoresist
  • the resist pattern is used as a mask to etch the conductive light-shielding material layer to remove the conductive light-shielding material layer corresponding to the completely removed portion of the second photoresist; and the third photoresist pattern is ashed.
  • the manufacturing method can realize the formation of the first concave portion and the first hollow portion in the same mask process by using a halftone mask, so that the mask process can be reduced, thereby reducing the cost. It should be noted that the above-mentioned overlap includes the case of complete overlap, and also includes the case of substantial overlap (overlapping degree is greater than 80%).
  • the first recessed portion includes a first edge portion, at least a portion of the first recessed portion proximate the edge, eg, the first edge, in a direction from an edge of the first recessed portion to a center of the first recessed portion part, the thickness in the direction perpendicular to the base substrate decreases continuously and gradually. Since the average thickness of the first recessed portion in the direction perpendicular to the base substrate is smaller than the average thickness of the first main body portion in the direction perpendicular to the base substrate, the light-shielding performance of the first recessed portion may be affected.
  • the first concave portion Since the thickness of the first concave portion in the direction perpendicular to the base substrate decreases continuously and gradually, even if light can penetrate the first concave portion, the first concave portion can also play the role of light gathering, thereby preventing ambient light from passing through. Through the entire display substrate, and avoid ambient light to affect the normal display of the display substrate.
  • At least a portion of the first recessed portion close to the edge that is, a slope angle of the first edge portion close to the conductive layer, changes continuously. Therefore, even if light can penetrate the first recessed portion, the first recessed portion can also play a role of light gathering, thereby preventing the light from penetrating the entire display substrate and being observed by the user.
  • the surface of the first recessed portion close to the first drain electrode is a continuous arc surface, or a combined surface formed by a combination of at least a segment of a continuous arc surface and at least a segment of a plane.
  • the continuous curved surface, or the combined surface formed by at least one continuous curved surface and at least one flat surface can play the role of light converging, so that even if light can penetrate the first concave part, the first concave part can also prevent the light It penetrates through the entire display substrate and is observed by the user.
  • the orthographic projection of the first contact hole on the base substrate at least partially overlaps the orthographic projection of the first recessed portion on the base substrate.
  • the first drain electrode in the conductive layer can be connected to the first recessed portion through the first contact hole.
  • the fourth slope angle ⁇ on the surface of the first edge portion close to the conductive layer satisfies the following formula:
  • Lmax is the maximum aperture of the orthographic projection of the first recessed portion on the base substrate
  • H is the average thickness of the first main body portion
  • k is a constant greater than 1 and less than or equal to 2.
  • k 2
  • the fourth slope angle ranges from 1- ⁇ /18.
  • the size of the orthographic projection of the first recess on the base substrate in a direction parallel to the base substrate is in the range of 5-10 microns.
  • forming the first contact hole in the interlayer insulating layer and the buffer layer includes: forming a first buffer part and a second buffer part in the buffer layer, the first buffer part being located in the buffer layer.
  • the second buffer portion is disposed inside the first contact hole and in contact with the conductive light-shielding structure, and the second buffer portion is located on the side of the first buffer portion away from the center of the first recessed portion.
  • forming the conductive layer on the side of the interlayer insulating layer away from the semiconductor layer may include: forming a source-drain metal material layer on the side of the interlayer insulating layer away from the semiconductor layer, for example, a deposition process may be used on the interlayer insulating layer A source-drain metal material layer is formed on the side away from the semiconductor layer; then, a mask is used to etch the source-drain metal material layer to form a conductive layer including the above-mentioned first drain electrode.
  • the manufacturing method of the display substrate further includes: forming a passivation layer on the side of the conductive layer away from the base substrate; forming a color filter layer on the side of the passivation layer away from the conductive layer; A flat layer is formed on one side of the chemical layer; an anode layer is formed on the side of the flat layer away from the color filter layer.
  • an organic material such as an organic resin can be used as the material of the flat layer.
  • an organic material such as an organic resin
  • the embodiments of the present disclosure include but are not limited to this.
  • each sub-pixel also includes an anode located in the anode layer.
  • the display substrate further includes a third via hole in the passivation layer, and the anode is connected to the first drain electrode through the third via hole.
  • the display substrate can apply a driving current to the anode through the first thin film transistor, so as to drive the light-emitting layer corresponding to the anode to perform light-emitting display.
  • the manufacturing method of the display substrate further includes: forming a pixel defining layer on a side of the anode layer away from the color filter layer.
  • the pixel defining layer may include a plurality of openings, the plurality of openings are disposed in a one-to-one correspondence with the anodes of the plurality of sub-pixels, and each opening portion exposes a corresponding anode.
  • the manufacturing method of the display substrate further includes: forming a light emitting layer on a side of the pixel defining layer away from the anode layer.
  • the light-emitting layer is in contact with exposed portions of the anodes of the plurality of sub-pixels through the above-mentioned plurality of openings.
  • the manufacturing method of the display substrate further includes: forming a cathode on a side of the light-emitting layer away from the anode.
  • the anode, the light-emitting layer and the cathode can constitute a light-emitting unit.

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Abstract

一种显示基板及其制作方法和显示装置。在该显示基板(100)中，各子像素(300)包括：导电遮光结构(122)；缓冲层(130)，位于导电遮光结构(122)远离衬底基板(110)的一侧；半导体层(140)，位于缓冲层(130)远离导电遮光结构(122)的一侧；层间绝缘层(170)，位于半导体层(140)远离缓冲层(130)的一侧；以及导电层(180)，位于层间绝缘层(170)远离半导体层(140)的一侧，且包括导电结构(181)。导电遮光结构(122)包括第一主体部(1220)和第一凹陷部(1224)，第一凹陷部(1224)在垂直于衬底基板(110)的方向上的平均厚度小于第一主体部(1220)在垂直于衬底基板(110)的方向上的厚度，显示基板(100)还包括第一接触孔(251)，第一接触孔(251)穿过层间绝缘层(170)和缓冲层(130)，导电结构(181)通过第一接触孔(251)与第一凹陷部(1224)连接。由此，该显示基板可提高导电结构和导电遮光结构的电连接效果。

Description

显示基板及其制作方法和显示装置
本申请要求于2021年01月13日递交的中国专利申请202110039159.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种显示基板及其制作方法和显示装置。
背景技术
随着显示技术的不断发展，有源矩阵有机发光二极管显示装置(AMOLED)因其广色域、高对比度、轻薄设计、自发光、以及宽视角等优点已经成为当前各大厂商的研究热点和技术发展的方向。
目前，有源矩阵有机发光二极管显示装置(AMOLED)已经广泛地应用到各种电子产品中，小到智能手环、智能手表、智能手机、平板电脑等电子产品，大到笔记本电脑、台式电脑、电视机等电子产品。因此，市场对于有源矩阵有机发光二极管显示装置的需求也日益旺盛。
发明内容
本公开实施例提供一种显示基板及其制作方法和显示装置。该显示基板包括衬底基板和位于所述衬底基板上的多个子像素，其中，各所述子像素包括：导电遮光结构，位于所述衬底基板上；缓冲层，位于所述导电遮光结构远离所述衬底基板的一侧；半导体层，位于所述缓冲层远离所述导电遮光结构的一侧；层间绝缘层，位于所述半导体层远离所述缓冲层的一侧；以及导电层，位于所述层间绝缘层远离所述半导体层的一侧，且包括导电结构，所述导电遮光结构包括第一主体部和第一凹陷部，所述显示基板还包括第一接触孔，所述第一接触孔穿过所述层间绝缘层和所述缓冲层，所述导电结构通过所述第一接触孔与所述第一凹陷部电连接，所述第一凹陷部靠近所述导电层的表面的面积大于所述第一凹陷部在所述衬底基板上正投影的面积，所述第一凹陷部在垂直于衬底基板的方向上的平均厚度小于所述第一主体部在垂直于衬底基板的方向上的平均厚度。由此，该显示基板通过在导电遮光结构中设置第一凹陷部，使得第 一漏极与导电遮光结构的接触面积增加，接触更加充分，从可降低接触电阻，提高第一漏极和导电遮光结构的电连接效果。
本公开至少一个实施例提供一种显示基板，其包括衬底基板和位于所述衬底基板上的多个子像素，其中，各所述子像素包括：导电遮光结构，位于所述衬底基板上；缓冲层，位于所述导电遮光结构远离所述衬底基板的一侧；半导体层，位于所述缓冲层远离所述导电遮光结构的一侧；层间绝缘层，位于所述半导体层远离所述缓冲层的一侧；以及导电层，位于所述层间绝缘层远离所述半导体层的一侧，且包括导电结构，所述导电遮光结构包括第一主体部和第一凹陷部，所述显示基板还包括第一接触孔，所述第一接触孔穿过所述层间绝缘层和所述缓冲层，所述导电结构通过所述第一接触孔与所述第一凹陷部电连接，所述第一凹陷部靠近所述导电层的表面的面积大于所述第一凹陷部在所述衬底基板上正投影的面积，所述第一凹陷部在垂直于衬底基板的方向上的平均厚度小于所述第一主体部在垂直于衬底基板的方向上的平均厚度。
例如，在本公开一实施例提供的显示基板中，所述缓冲层包括：第一缓冲部，所述第一缓冲部远离所述衬底基板的一侧与所述导电层接触设置，且所述第一缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置；以及第二缓冲部，所述第二缓冲部远离所述衬底基板的一侧与所述层间绝缘层接触设置，且所述第二缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置。
例如，在本公开一实施例提供的显示基板中，所述第一接触孔包括侧壁，所述侧壁至少包括：第一子侧壁，位于所述层间绝缘层；以及第二子侧壁，位于所述缓冲层，所述第一子侧壁与所述衬底基板的夹角构成第一坡度角，所述第二子侧壁与所述衬底基板的夹角构成第二坡度角，所述第一坡度角小于所述第二坡度角；所述第二子侧壁与所述第一缓冲部的接触部位于所述第一缓冲部和所述第二缓冲部之间。
例如，在本公开一实施例提供的显示基板中，所述第一接触孔的所述侧壁还包括：第三子侧壁，位于所述第一缓冲部，所述第三子侧壁与所述衬底基板的夹角构成第三坡度角，所述第一坡度角、所述第二坡度角和所述第三坡度角不同。
例如，在本公开一实施例提供的显示基板中，沿所述第一接触孔的径向，所述第一缓冲部的长度与所述第一缓冲部的平均厚度之比大于所述第一子侧 壁的在所述衬底基板上的投影长度与所述层间绝缘层的平均厚度之比。
例如，在本公开一实施例提供的显示基板中，沿所述第一接触孔径向，所述第一子侧壁的在所述衬底基板上的投影长度与所述层间绝缘层的平均厚度之比大于所述第二子侧壁的在所述衬底基板上的投影长度与所述缓冲层的平均厚度之比。
例如，在本公开一实施例提供的显示基板中，所述第二坡度角大于所述所述第三坡度角，所述第一坡度角大于所述第三坡度角。
例如，在本公开一实施例提供的显示基板中，所述第一凹陷部在所述衬底基板上的正投影在平行于所述衬底基板的方向上的尺寸L满足下列公式：
2(Acotβ+Bcotγ+Ccotθ)<L<D
其中，A为所述第一缓冲部的最大厚度，B为所述第二缓冲部的最大厚度，C为所述层间绝缘层的最大厚度，β为所述第一坡度角，γ为所述第二坡度角，θ为所述第三坡度角，D为所述第一接触孔在所述衬底基板上的正投影在平行于所述衬底基板的方向上的最大尺寸。
例如，在本公开一实施例提供的显示基板中，所述第一凹陷部包括第一边缘部，在从所述第一凹陷部的边缘到所述第一凹陷部的中心的方向上，所述第一边缘部在垂直于衬底基板的方向上的厚度逐渐减小。
例如，在本公开一实施例提供的显示基板中，所述第一凹陷部包括第一边缘部，在垂直于所述衬底基板方向上，所述第一边缘部靠近所述导电层的表面的第四坡度角是连续变化的。
例如，在本公开一实施例提供的显示基板中，所述第一凹陷部靠近所述导电结构的表面为连续弧面，或至少一段连续弧面和至少一段平面组合而成的组合面。
例如，在本公开一实施例提供的显示基板中，所述第一凹陷部包括第一边缘部，所述第一边缘部靠近所述导电层的表面上的第四坡度角α满足下列公式：
0<α<k*H/Lmax
其中，Lmax为所述第一凹陷部在所述衬底基板上的正投影的最大孔径，H为所述第一主体部的平均厚度，k为大于1小于等于2的常数。
例如，在本公开一实施例提供的显示基板中，k＝2，所述第四坡度角的范围为1-π/18。
例如，在本公开一实施例提供的显示基板中，所述第一凹陷部包括第一边 缘部，所述第一边缘部靠近所述导电层的表面上的第四坡度角α小于所述第三子侧壁的所述第三坡度角，且满足：
(Acotβ+Bcotγ+Ccotθ+L/2tanα)≤D/2，
其中，A为所述第一缓冲部的最大厚度，B为所述第二缓冲部的最大厚度，C为所述层间绝缘层的最大厚度，β为所述第一坡度角，γ为所述第二坡度角，θ为所述第三坡度角，D为所述第一接触孔在所述衬底基板上的正投影在平行于所述衬底基板的方向上的最大尺寸。
例如，本公开一实施例提供的显示基板还包括：平坦层，位于所述导电层远离所述半导体层的一侧，且所述平坦层包括阳极孔；以及阳极，位于所述平坦层远离所述半导体层的一侧，且包括出光部、驱动部和将所述出光部和所述驱动部相连的延伸部，所述驱动部至少部分位于所述阳极孔之内，在至少一个所述子像素中，所述第一接触孔在所述衬底基板上正投影与所述驱动部在所述衬底基板上正投影至少部分交叠，所述显示基板还包括：电源线，位于所述导电层；以及感测线，位于所述导电层；所述电源线和所述感测线在第一方向上排列，所述电源线和所述感测线均沿与所述第一方向相交的第二方向延伸；所述多个子像素包括第一子像素对和第二子像素对，所述第一子像素对包括两个所述子像素，分别位于所述电源线的两侧，所述第二子像素对包括两个所述子像素，分别位于所述感测线的两侧；所述第一子像素对和所述第二子像素对在所述第一方向上交替排列，在所述第二子像素对中的两个所述子像素中，所述阳极孔与所述第一凹陷部在所述衬底基板上正投影存在第一交叠区域，所述第一交叠区域的面积小于所述第一接触孔在所述衬底基板上正投影的面积。
例如，在本公开一实施例提供的显示基板中，所述阳极在所述阳极孔的边缘位置处还包括下凹结构，所述下凹结构的凹陷方向朝向所述导电遮光结构。
例如，在本公开一实施例提供的显示基板中，所述第一凹陷部在所述衬底基板上的正投影在平行于所述衬底基板的方向上的尺寸范围为5-10微米。
例如，在本公开一实施例提供的显示基板中，所述第一接触孔在所述衬底基板上的正投影与所述第一凹陷部在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，各所述子像素包括像素驱动电路，所述像素驱动电路包括第一薄膜晶体管，所述导电结构为所述第一薄膜晶体管的第一漏极。
例如，在本公开一实施例提供的显示基板中，所述第一薄膜晶体管还包括： 第一有源层，位于所述半导体层，且包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区；第一源极，位于所述导电层，所述显示基板还包括第一过孔和第二过孔，所述第一过孔和所述第二过孔位于所述层间绝缘层之中，所述第一源极通过所述第一过孔与所述第一源极区相连，所述第一漏极通过所述第二过孔与所述第一漏极区相连。
例如，在本公开一实施例提供的显示基板中，所述导电遮光结构还包括：第一绝缘部，所述第一绝缘部在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影至少部分重叠，所述第一绝缘部在所述衬底基板上的正投影与所述第一源极区在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，所述第一绝缘部包括第一镂空部，所述第一镂空部填充有所述缓冲层的材料。
例如，在本公开一实施例提供的显示基板中，所述第一镂空部包括第一镂空环，所述第一镂空环内侧的部分与所述第一镂空环的外侧均为所述导电遮光结构的材料。
例如，在本公开一实施例提供的显示基板中，所述第一绝缘部为氧化部。
例如，本公开一实施例提供的显示基板还包括：栅极绝缘层，位于所述半导体层和所述层间绝缘层之间；栅极层，位于所述栅极绝缘层和所述层间绝缘层之间；钝化层，位于所述导电层远离所述衬底基板的一侧；彩膜层，位于所述钝化层远离所述导电层的一侧，且包括至少三种不同颜色的滤光片；以及阳极层，所述平坦层位于所述彩膜层远离所述钝化层的一侧，所述阳极层位于所述平坦层远离所述彩膜层的一侧，所述阳极位于所述阳极层。
例如，本公开一实施例提供的显示基板还包括：电源连接线，与所述导电遮光结构同层设置，所述电源连接线包括第二主体部和多个电源凹陷部，所述电源凹陷部在垂直于所述衬底基板的方向上的平均厚度均小于所述第二主体部在垂直于所述衬底基板的方向上的平均厚度，所述电源凹陷部靠近所述导电层的表面的面积大于所述电源凹陷部在所述衬底基板上正投影的面积，所述多个电源凹陷部中的至少之一在所述衬底基板上的正投影与所述彩膜层中的所述滤光片在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，所述电源凹陷部包括第二边缘部，在从所述电源凹陷部的边缘到所述电源凹陷部的中心的方向上，所述第二边缘部在垂直于衬底基板的方向上的厚度连续逐渐减小。
例如，在本公开一实施例提供的显示基板中，所述电源凹陷部包括第二边缘部，在垂直于所述衬底基板方向上，所述第二边缘部靠近所述导电层的表面的第五坡度角是连续变化的。
例如，在本公开一实施例提供的显示基板中，所述显示基板还包括电源接触孔，所述电源接触孔位于所述层间绝缘层和所述缓冲层，所述电源接触孔在所述衬底基板上的正投影与所述电源凹陷部在所述衬底基板上的正投影至少部分交叠。
例如，在本公开一实施例提供的显示基板中，所述缓冲层包括：第三缓冲部，位于所述电源接触孔之内，所述第三缓冲部远离所述衬底基板的一侧与所述电源连接线接触设置，且所述第三缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置；以及第四缓冲部，位于所述第三缓冲部远离所述电源凹陷部的中心的一侧，所述电源接触孔的侧壁包括：第四子侧壁，位于所述层间绝缘层；以及第五子侧壁，位于所述第四缓冲部，所述第四子侧壁与所述衬底基板的夹角构成第六坡度角，所述第五子侧壁与所述衬底基板的夹角构成第七坡度角，所述第六坡度角小于所述第七坡度角；所述第五子侧壁与所述第三缓冲部的接触部位于所述第三缓冲部和所述第四缓冲部之间。
例如，在本公开一实施例提供的显示基板中，所述电源接触孔的侧壁还包括：第六子侧壁，位于所述第三缓冲部，所述第六子侧壁与所述衬底基板的夹角构成第八坡度角，所述第六坡度角、所述第七坡度角和所述第八坡度角不同。
例如，在本公开一实施例提供的显示基板中，所述第七坡度角小于所述第二坡度角。
例如，在本公开一实施例提供的显示基板中，所述第八坡度角大于所述第三坡度角。
例如，本公开一实施例提供的显示基板还包括：感测连接线，与所述导电遮光结构同层设置，所述感测连接线包括第三主体部和多个感测凹陷部，所述感测凹陷部在垂直于所述衬底基板的方向上的平均厚度均小于所述第三主体部在垂直于所述衬底基板的方向上的平均厚度，所述感测凹陷部靠近所述导电层的表面的面积大于所述感测凹陷部在所述衬底基板上正投影的面积，所述多个感测凹陷部中的至少之一在所述衬底基板上的正投影与所述彩膜层中的所述滤光片在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，所述感测凹陷部包括第三边 缘部，在从所述感测凹陷部的边缘到所述感测凹陷部的中心的方向上，所述第三边缘部在垂直于衬底基板的方向上的厚度连续逐渐减小。
例如，在本公开一实施例提供的显示基板中，所述感测凹陷部包括第三边缘部，在垂直于所述衬底基板方向上，所述第三边缘部靠近所述导电层的表面的第九坡度角是连续变化的。
例如，在本公开一实施例提供的显示基板中，所述显示基板还包括感测接触孔，所述感测接触孔位于所述层间绝缘层和所述缓冲层，所述感测接触孔在所述衬底基板上的正投影与所述感测凹陷部在所述衬底基板上的正投影至少部分交叠。
例如，在本公开一实施例提供的显示基板中，所述缓冲层包括：第五缓冲部，位于所述感测接触孔之内，所述第五缓冲部远离所述衬底基板的一侧与所述感测连接线接触设置，且所述第五缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置；以及第六缓冲部，位于所述第五缓冲部远离所述感测凹陷部的中心的一侧，所述感测接触孔的侧壁包括：第七子侧壁，位于所述层间绝缘层；以及第八子侧壁，位于所述第六缓冲部；所述第七子侧壁与所述衬底基板的夹角构成第十坡度角，所述第八子侧壁与所述衬底基板的夹角构成第十一坡度角，所述第十坡度角小于所述第十一坡度角；所述第八子侧壁与所述第五缓冲部的接触部位于所述第五缓冲部和所述第六缓冲部之间。
例如，在本公开一实施例提供的显示基板中，所述缓冲层还包括：第九子侧壁，位于所述第五缓冲部，所述第九子侧壁与所述衬底基板的夹角构成第十二坡度角，所述第十坡度角、所述第十一坡度角和所述第十二坡度角不同。
例如，在本公开一实施例提供的显示基板中，所述第十一坡度角小于所述第二坡度角。
例如，在本公开一实施例提供的显示基板中，所述第十二坡度角大于所述第三坡度角。
例如，在本公开一实施例提供的显示基板中，各所述子像素包括驱动区和出光区，所述导电遮光结构位于所述驱动区，所述阳极的所述驱动部位于所述驱动区，所述阳极的出光部位于所述出光区。
例如，本公开一实施例提供的显示基板还包括：第一栅线，位于所述栅极层，且沿第一方向延伸；第二栅线，位于所述栅极层，且沿所述第一方向延伸；以及数据线，位于所述导电层，且沿与所述第二方向延伸，所述电源线沿所述 第二方向延伸，所述感测线沿所述第二方向延伸，所述多个子像素沿所述第一方向和所述第二方向阵列设置以形成沿所述第二方向排列的多个子像素行和沿所述第一方向排列的多个子像素列，在各所述子像素行中，所述第一栅线位于所述驱动区和所述出光区之间，所述第二栅线位于相邻的两个所述子像素行之间，所述电源线位于相邻的两个所述子像素列之间，所述感测线位于相邻的两个所述子像素列之间，所述数据线位于相邻的两个所述子像素列之间。
例如，在本公开一实施例提供的显示基板中，各所述子像素包括像素驱动电路，所述像素驱动电路包括第一薄膜晶体管，所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极，所述导电结构为所述第一薄膜晶体管的第一漏极，所述像素驱动电路还包括第二薄膜晶体管和第三薄膜晶体管，所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极，所述第三薄膜晶体管包括第三栅极、第三源极和第三漏极，所述半导体层还包括导体化块，所述第一薄膜晶体管的所述第一源极与所述电源线相连，所述第二薄膜晶体管的所述第二源极与所述数据线相连，所述第二薄膜晶体管的第二栅极与所述第一栅线相连，所述第二薄膜晶体管的所述第二漏极与所述第一薄膜晶体管的所述第一栅极和所述导体化块分别相连，所述第三薄膜晶体管的所述第三栅极与所述第二栅线相连，所述第三薄膜晶体管的所述第三源极与所述感测线相连，所述第三薄膜晶体管的所述第三漏极与所述第一薄膜晶体管的所述第一漏极相连，所述导电遮光结构、与所述导电遮光结构相连的所述第一漏极、和位于所述导电遮光结构和所述第一漏极之间的所述导体化块形成存储电容。
例如，在本公开一实施例提供的显示基板中，所述第一薄膜晶体管的所述第一源极通过第一连接部与所述电源线相连，所述第二薄膜晶体管的所述第二源极通过第二连接部与所述数据线相连，所述第一连接部与所述电源线同层设置，所述第二连接部与所述数据线同层设置。
例如，在本公开一实施例提供的显示基板中，所述第一源极到所述第一漏极的方向与所述第一连接部的延伸方向相交，所述第二源极到所述第二漏极的方向与所述第二连接部的延伸方向相交。
例如，在本公开一实施例提供的显示基板中，所述多个子像素至少包括第一颜色子像素、第二颜色子像素、第三颜色子像素和第四颜色子像素，在各所述子像素行，所述第一颜色子像素、所述第二颜色子像素、所述第三颜色子像素和所述第四颜色子像素沿所述第一方向依次排列并形成一个子像素组，所述 电源线位于所述子像素组中所述第二颜色子像素和所述第三颜色子像素之间。
例如，在本公开一实施例提供的显示基板中，所述显示基板还包括电源连接线，与所述导电遮光结构同层设置。
例如，在本公开一实施例提供的显示基板中，所述显示基板还包括第二接触孔、第三接触孔和第四接触孔，所述第二接触孔、所述第三接触孔和所述第四接触孔位于所述层间绝缘层和所述缓冲层，在所述子像素组中，所述电源线通过所述第二接触孔与所述电源连接线相连，所述第二颜色子像素的所述第一源极与所述电源线同层相连，所述第三颜色子像素的所述第一源极与所述电源线同层相连，所述第一颜色子像素的所述第一源极通过所述第三接触孔与所述电源连接线相连，所述第四颜色子像素的所述第一源极通过所述第四接触孔与所述电源连接线相连。
例如，在本公开一实施例提供的显示基板中，所述电源连接线包括第二主体部、第二凹陷部、第三凹陷部和第四凹陷部，所述第二凹陷部在所述衬底基板上的正投影与所述第二接触孔在所述衬底基板上的正投影至少部分重叠，所述第三凹陷部在所述衬底基板上的正投影与所述第三接触孔在所述衬底基板上的正投影至少部分重叠，所述第四凹陷部在所述衬底基板上的正投影与所述第四接触孔在所述衬底基板上的正投影至少部分重叠，所述第二凹陷部、所述第三凹陷部和所述第四凹陷部在垂直于所述衬底基板的方向上的厚度均小于所述第二主体部在垂直于所述衬底基板的方向上的厚度，所述第二凹陷部靠近所述电源线的表面的面积大于所述第二凹陷部在所述衬底基板上正投影的面积，所述第三凹陷部远离所述衬底基板的表面的面积大于所述第三凹陷部在所述衬底基板上正投影的面积，所述第四凹陷部远离所述衬底基板的表面的面积大于所述第四凹陷部在所述衬底基板上正投影的面积。
例如，在本公开一实施例提供的显示基板中，所述第二凹陷部、所述第三凹陷部和所述第四凹陷部中的至少之一在所述衬底基板上的正投影与所述彩膜层中的所述滤光片在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，所述第二颜色子像素包括第一颜色滤光片，所述第三颜色子像素包括第二颜色滤光片，所述第四颜色子像素包括第三颜色滤光片，在所述子像素组中，所述第一颜色滤光片和所述第二颜色滤光片中的至少一个在衬底基板上的正投影与所述第二凹陷部在所述衬底基板上的正投影至少部分重叠，所述第三颜色滤光片在所述衬底基板上的正 投影与所述第四凹陷部在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，所述感测线位于在第一方向上相邻的两个所述子像素组之间，在第一方向上所述相邻的两个所述子像素组包括第一子像素组和第二子像素组，所述显示基板还包括感测连接线、第五接触孔、第六接触孔、第七接触孔、第八接触孔和第九接触孔，所述感测连接线与所述导电遮光结构同层设置，所述第五接触孔、所述第六接触孔、所述第七接触孔、第八接触孔和第九接触孔位于所述层间绝缘层和所述缓冲层，在所述相邻的两个所述子像素组中，所述感测线通过所述第五接触孔与所述感测连接线相连，所述第一子像素组中的所述第三颜色子像素的所述第三源极通过所述第六接触孔与所述感测连接线相连，所述第一子像素组中的所述第四颜色子像素的所述第三源极通过所述第七接触孔与所述感测连接线相连，所述第一子像素组中的所述第一颜色子像素的所述第三源极通过所述第八接触孔与所述感测连接线相连，所述第二子像素组中的所述第二颜色子像素的所述第三源极通过所述第九接触孔与所述感测连接线相连。
例如，在本公开一实施例提供的显示基板中，所述感测连接线包括第三主体部、第五凹陷部、第六凹陷部、第七凹陷部、第八凹陷部和第九凹陷部，所述第五凹陷部在所述衬底基板上的正投影与所述第五接触孔在所述衬底基板上的正投影至少部分重叠，所述第六凹陷部在所述衬底基板上的正投影与所述第六接触孔在所述衬底基板上的正投影至少部分重叠，所述第七凹陷部在所述衬底基板上的正投影与所述第七接触孔在所述衬底基板上的正投影至少部分重叠，所述第八凹陷部在所述衬底基板上的正投影与所述第八接触孔在所述衬底基板上的正投影至少部分重叠，所述第九凹陷部在所述衬底基板上的正投影与所述第九接触孔在所述衬底基板上的正投影至少部分重叠，所述第五凹陷部、所述第六凹陷部、所述第七凹陷部、所述第八凹陷部和所述第九凹陷部在垂直于衬底基板的方向上的厚度均小于所述第三主体部在垂直于衬底基板的方向上的厚度，所述第五凹陷部靠近所述感测线的表面的面积大于所述第五凹陷部在所述衬底基板上正投影的面积，所述第六凹陷部远离所述衬底基板的表面的面积大于所述第六凹陷部在所述衬底基板上正投影的面积，所述第七凹陷部远离所述衬底基板的表面的面积大于所述第七凹陷部在所述衬底基板上正投影的面积，所述第八凹陷部远离所述衬底基板的表面的面积大于所述第八凹陷部在所述衬底基板上正投影的面积，所述第九凹陷部远离所述衬底基板的表 面的面积大于所述第九凹陷部在所述衬底基板上正投影的面积。
例如，在本公开一实施例提供的显示基板中，所述第五凹陷部、所述第六凹陷部、所述第七凹陷部、所述第八凹陷部和所述第九凹陷部中的至少之一在所述衬底基板上的正投影与所述彩膜层中的所述滤光片在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，在所述第二方向上，所述感测连接线位于所述第二栅线远离所述第一栅线的一侧，所述第一子像素组中的所述第二颜色滤光片在所述衬底基板上的正投影与在所述第二方向上相邻的所述第一子像素组的所述第六凹陷部在所述衬底基板上的正投影至少部分重叠，所述第一子像素组中的所述第三颜色滤光片在所述衬底基板上的正投影与在所述第二方向上相邻的所述第七凹陷部在所述衬底基板上的正投影至少部分重叠，所述第二子像素组中的所述第一颜色滤光片在所述衬底基板上的正投影与在所述第二方向上相邻的所述第九凹陷部在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，在所述子像素组中，所述第一颜色滤光片在所述衬底基板上的正投影与所述电源连接线在所述衬底基板上的正投影至少部分重叠，所述第二颜色滤光片在所述衬底基板上的正投影分别与所述电源连接线在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影至少部分重叠，所述第三颜色滤光片在所述衬底基板上的正投影与所述电源连接线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，在所述子像素组中，所述第一颜色滤光片在所述衬底基板上的正投影与所述感测连接线在所述衬底基板上的正投影至少部分重叠，所述第二颜色滤光片在所述衬底基板上的正投影分别与所述感测连接线在所述衬底基板上的正投影至少部分重叠，所述第三颜色滤光片在所述衬底基板上的正投影与所述感测连接线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，所述数据线包括第一数据线、第二数据线、第三数据线和第四数据线，在所述子像素组中，所述第一数据线和所述第二数据线位于所述第一颜色子像素和所述第二颜色子像素之间，所述第一数据线与所述第一颜色子像素的所述第二源极相连，所述第二数据线与所述第二颜色子像素的所述第二源极相连，所述第三数据线和所述第四数据线位 于所述第三颜色子像素和所述第四颜色子像素之间，所述第三数据线与所述第三颜色子像素的所述第二源极相连，所述第四数据线与所述第四颜色子像素的所述第二源极相连。
例如，在本公开一实施例提供的显示基板中，在所述子像素组中，所述第一颜色滤光片在所述衬底基板上的正投影与所述第二数据线在所述衬底基板上的正投影至少部分重叠，所述第二颜色滤光片在所述衬底基板上的正投影分别与所述第三数据线在所述衬底基板上的正投影至少部分重叠，所述第三颜色滤光片在所述衬底基板上的正投影和所述第四数据线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，所述第一薄膜晶体管还包括：第一有源层，位于所述半导体层，且包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区；所述第一栅极位于所述栅极层，所述第一栅极在所述衬底基板上的正投影与所述第一沟道区在所述衬底基板上的正投影至少部分重叠；所述第一源极和所述第一漏极均位于所述导电层，所述显示基板还包括第一过孔和第二过孔，所述第一过孔和所述第二过孔位于所述层间绝缘层之中，所述第一源极通过所述第一过孔与所述第一源极区相连，所述第一漏极通过所述第二过孔与所述第一漏极区相连。
例如，在本公开一实施例提供的显示基板中，所述第一沟道区在所述衬底基板上的正投影落入所述第一主体部在所述衬底基板上的正投影。
例如，在本公开一实施例提供的显示基板中，所述显示基板还包括：第四过孔，位于层间绝缘层之中，所述第二漏极通过所述第四过孔与所述导体化块相连，所述导电遮光结构还包括：第二绝缘部，所述第二绝缘部在所述衬底基板上的正投影与所述第四过孔在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板中，所述第二绝缘部包括第二镂空部，所述第二镂空部填充有所述缓冲层的材料。
例如，在本公开一实施例提供的显示基板中，所述第二镂空部包括第二镂空环，所述第二镂空环内侧的部分与所述第二镂空环的外侧均为所述导电遮光结构的材料。
例如，在本公开一实施例提供的显示基板中，所述第二绝缘部为氧化部。
例如，在本公开一实施例提供的显示基板中，所述第一过孔和所述第四过孔在所述衬底基板上的正投影的形状均为各向异性的图形，且均包括长边。
例如，在本公开一实施例提供的显示基板中，在所述子像素组中，所述第二颜色子像素的所述第一过孔的所述长边和所述第三颜色子像素的所述第一过孔的所述长边均沿所述第一方向延伸，所述第一颜色子像素的所述第一过孔的所述长边和所述第四颜色子像素的所述第一过孔的所述长边均沿所述第二方向延伸。
例如，在本公开一实施例提供的显示基板中，在所述子像素组中，所述第二颜色子像素的所述第四过孔的所述长边和所述第三颜色子像素的所述第四过孔的所述长边均沿所述第二方向延伸，所述第一颜色子像素的所述第四过孔的所述长边和所述第四颜色子像素的所述第四过孔的所述长边均沿所述第一方向延伸。
例如，在本公开一实施例提供的显示基板中，在所述子像素组中，所述第一颜色子像素的所述第四过孔的中心、所述第二颜色子像素的所述第四过孔的中心、所述第三颜色子像素的所述第四过孔的中心和所述第四颜色子像素的所述第四过孔的中心在所述第二方向上错位设置，所述第一颜色子像素的所述第四过孔的中心和所述第四颜色子像素的所述第四过孔的中心位于第一虚拟直线上，所述第二颜色子像素的所述第四过孔的中心和所述第三颜色子像素的所述第四过孔的中心位于与所述第一虚拟直线平行的第二虚拟直线上。
例如，在本公开一实施例提供的显示基板中，所述导电遮光结构的材料选自钼和钛的一种或多种，所述导电层的材料选自铜、钼和钛中的一种或多种。
例如，在本公开一实施例提供的显示基板中，所述导电层包括沿垂直于所述衬底基板的方向上层叠的第一子金属层和第二子金属层，所述第一子金属层的材料为铜，所述第二子金属层的材料为钼钛合金。
例如，在本公开一实施例提供的显示基板中，所述栅极层的材料选自铜、钼和钛中的一种或多种。
例如，在本公开一实施例提供的显示基板中，所述导电遮光结构在垂直于所述衬底基板的方向上的厚度范围为90-120纳米，所述导电层在垂直于所述衬底基板的方向上的厚度范围为200-600纳米。
本公开至少一个实施例还提供一种显示装置，包括上述任一项所述的显示基板。
本公开至少一个实施例还提供一种显示基板的制作方法，其包括：在衬底基板上形成导电遮光材料层；对所述导电遮光材料层进行图案化以形成导电遮 光结构；在所述导电遮光结构远离所述衬底基板的一侧形成缓冲层；在所述缓冲层远离所述导电遮光结构的一侧形成半导体层；在所述半导体层远离所述缓冲层的一侧形成层间绝缘层；在所述层间绝缘层和所述缓冲层中形成第一接触孔；在所述层间绝缘层远离所述半导体层的一侧形成导电层；所述导电层包括导电结构，所述导电遮光结构包括第一主体部和第一凹陷部，所述第一凹陷部在垂直于衬底基板的方向上的平均厚度小于所述第一主体部在垂直于衬底基板的方向上的平均厚度，所述第一接触孔穿过所述层间绝缘层和所述缓冲层，所述导电结构通过所述第一接触孔与所述第一凹陷部连接，所述第一凹陷部靠近所述导电层的表面的面积大于所述第一凹陷部在所述衬底基板上正投影的面积。
例如，在本公开一实施例提供的显示基板的制作方法中，在所述层间绝缘层和所述缓冲层中形成第一接触孔包括：在所述缓冲层中形成第一缓冲部和第二缓冲部，所述第一缓冲部远离所述衬底基板的一侧与所述导电层接触设置，且所述第一缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置，所述第二缓冲部远离所述衬底基板的一侧与所述层间绝缘层接触设置，且所述第二缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置。
例如，在本公开一实施例提供的显示基板的制作方法中，所述第一接触孔包括侧壁，所述侧壁至少包括：第一子侧壁，位于所述层间绝缘层；以及第二子侧壁，位于所述缓冲层，所述第一子侧壁与所述衬底基板的夹角构成第一坡度角，所述第二子侧壁与所述衬底基板的夹角构成第二坡度角，所述第一坡度角小于所述第二坡度角；所述第二子侧壁与所述第一缓冲部的接触部位于所述第一缓冲部和所述第二缓冲部之间。
例如，在本公开一实施例提供的显示基板的制作方法中，所述第一接触孔的所述侧壁还包括：第三子侧壁，位于所述第一缓冲部，所述第三子侧壁与所述衬底基板的夹角构成第三坡度角，所述第一坡度角、所述第二坡度角和所述第三坡度角不同。
例如，本公开一实施例提供的显示基板的制作方法还包括：在所述导电层远离所述层间绝缘层的一侧形成平坦层，所述平坦层包括阳极孔；以及在所述平坦层远离所述导电层的一侧形成阳极层以在所述衬底基板上形成多个子像素，各所述子像素包括阳极，所述阳极包括出光部、驱动部和将所述出光部和所述驱动部相连的延伸部，所述驱动部至少部分位于所述阳极孔之内，在至少 一个所述子像素中，所述第一接触孔在所述衬底基板上正投影与所述驱动部在所述衬底基板上正投影至少部分交叠，所述显示基板还包括：电源线，位于所述导电层；以及感测线，位于所述导电层；所述电源线和所述感测线在第一方向上排列，所述电源线和所述感测线均沿与所述第一方向相交的第二方向延伸；所述多个子像素包括第一子像素对和第二子像素对，所述第一子像素对包括两个所述子像素，分别位于所述电源线的两侧，所述第二子像素对包括两个所述子像素，分别位于所述感测线的两侧；所述第一子像素对和所述第二子像素对在所述第一方向上交替排列，在所述第二子像素对中的两个所述子像素中，所述阳极孔与所述第一凹陷部在所述衬底基板上正投影存在第一交叠区域，所述第一交叠区域的面积小于所述第一接触孔在所述衬底基板上正投影的面积。
例如，在本公开一实施例提供的显示基板的制作方法中，所述导电层还包括第一源极和第一漏极，所述导电结构为所述第一漏极。
例如，在本公开一实施例提供的显示基板的制作方法中，所述半导体层包括第一有源层，所述第一有源层包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区，所述制作方法还包括：在所述层间绝缘层和所述缓冲层中形成第一接触孔的同时在所述层间绝缘层形成第一过孔和第二过孔，所述第一源极通过所述第一过孔与所述第一源极区相连，所述第一漏极通过所述第二过孔与所述第一漏极区相连。
例如，在本公开一实施例提供的显示基板的制作方法中，采用同一刻蚀工艺同时图案化所述层间绝缘层和所述缓冲层以形成所述第一过孔和所述第一接触孔。
例如，在本公开一实施例提供的显示基板的制作方法中，采用半色调掩膜工艺图案化所述层间绝缘层和所述缓冲层以形成所述第一过孔和所述第一接触孔。
例如，在本公开一实施例提供的显示基板的制作方法中，采用半色调掩膜工艺图案化所述层间绝缘层和所述缓冲层以形成所述第一过孔和所述第一接触孔包括：在所述层间绝缘层远离所述衬底基板的一侧形成第一光刻胶；采用第一半色调掩膜对所述第一光刻胶进行曝光和显影，以形成包括第一光刻胶完全去除部、第一光刻胶部分去除部和第一光刻胶保留部的第一光刻胶图案；以所述第一光刻胶图案为掩膜对所述层间绝缘层进行刻蚀，以去除所述第一光刻 胶完全去除部对应的层间绝缘层；对所述第一光刻胶图案进行灰化处理，去除所述第一光刻胶部分去除部并减薄所述第一光刻胶保留部以形成第二光刻胶图案；以及以所述第二光刻胶图案为掩膜对所述缓冲层进行刻蚀，所述第一接触孔在所述衬底基板上的正投影与所述第一光刻胶完全去除部在所述衬底基板上的正投影重叠，所述第一过孔在所述衬底基板上的正投影与所述第一光刻胶部分去除部在所述衬底基板上的正投影重叠。
例如，在本公开一实施例提供的显示基板的制作方法中，所述导电遮光结构还包括第一绝缘部，所述第一绝缘部在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影至少部分重叠，所述第一绝缘部在所述衬底基板上的正投影与所述第一源极区在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一实施例提供的显示基板的制作方法中，所述第一绝缘部包括第一镂空部，所述第一镂空部填充有所述缓冲层的材料，对所述导电遮光材料层进行图案化以形成所述导电遮光结构包括：通过同一图案化工艺对所述导电遮光材料层进行图案化以形成所述第一主体部、所述第一凹陷部和所述第一镂空部。
例如，在本公开一实施例提供的显示基板的制作方法中，对所述导电遮光材料层进行图案化以形成导电遮光结构包括：在所述导电遮光结构远离所述衬底基板的一侧形成光刻胶；采用第二半色调掩膜对所述光刻胶进行曝光和显影，以形成包括第二光刻胶完全去除部、第二光刻胶部分去除部和第二光刻胶保留部的第三光刻胶图案；以所述第三光刻胶图案为掩膜对所述导电遮光材料层进行刻蚀，以去除所述第二光刻胶完全去除部对应的导电遮光材料层；对所述第三光刻胶图案进行灰化处理，去除所述第二光刻胶部分去除部并减薄所述第二光刻胶保留部以形成第四光刻胶图案；以及以所述第四光刻胶图案为掩膜对所述导电遮光材料层进行刻蚀，所述第一主体部在所述衬底基板上的正投影与所述第二光刻胶保留部在所述衬底基板上的正投影重叠，所述第一凹陷部在所述衬底基板上的正投影与所述第二光刻胶部分去除部在所述衬底基板上的正投影重叠。
例如，在本公开一实施例提供的显示基板的制作方法中，所述第一凹陷部包括第一边缘部，在从所述第一凹陷部的边缘到所述第一凹陷部的中心的方向上，所述第一边缘部在垂直于衬底基板的方向上的厚度逐渐减小。
例如，在本公开一实施例提供的显示基板的制作方法中，所述第一凹陷部 包括第一边缘部，在垂直于所述衬底基板方向上，所述第一边缘部靠近所述导电层的表面的第四坡度角是连续变化的。
例如，在本公开一实施例提供的显示基板的制作方法中，所述第一凹陷部靠近所述导电结构的表面为连续弧面，或至少一段连续弧面和至少一段平面组合而成的组合面。
例如，在本公开一实施例提供的显示基板的制作方法中，所述第一凹陷部包括第一边缘部，所述第一边缘部靠近所述导电层的表面上的第四坡度角α满足下列公式：
0<α<k*H/Lmax
其中，Lmax为所述第一凹陷部在所述衬底基板上的正投影的最大孔径，H为所述第一主体部的平均厚度，k为大于1小于等于2的常数。
例如，在本公开一实施例提供的显示基板的制作方法中，k＝2，所述第四坡度角的范围为1-π/18。
例如，在本公开一实施例提供的显示基板的制作方法中，所述第一凹陷部在所述衬底基板上的正投影在平行于所述衬底基板的方向上的尺寸范围为5-10微米。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种采用顶栅型的氧化物薄膜晶体管的显示基板的剖面示意图；
图2A为另一种显示基板的剖面示意图；
图2B为一种显示基板中接触孔的剖面示意图；
图3为一种显示基板中过孔的剖面示意图；
图4为本公开一实施例提供的一种显示基板的平面示意图；
图5A为本公开一实施例提供的一种显示基板沿图4中AA’线的剖面示意图；
图5B为本公开一实施例提供的一种显示基板沿图4中BB’线的剖面示意图；
图5C为本公开一实施例提供的一种显示基板中凹陷部的光线汇聚作用的示意图；
图5D为本公开一实施例提供的一种显示基板中阳极孔的示意图；
图6A为本公开一实施例提供的一种显示基板中第一凹陷部的剖面示意图；
图6B为本公开一实施例提供的一种显示基板中第一凹陷部的剖面示意图；
图7A为本公开一实施例提供的一种显示基板中像素驱动电路的平面示意图；
图7B为本公开一实施例提供的一种显示基板中像素驱动电路的平面示意图；
图8为本公开一实施例提供的一种显示基板中像素驱动电路的等效电路图；
图9为本公开一实施例提供的一种显示基板中像素驱动电路中各个信号线上信号的时序图；
图10A为本公开一实施例提供的一种显示基板中导电遮光结构的平面示意图；
图10B为本公开一实施例提供的另一种显示基板中导电遮光结构的平面示意图；
图10C为本公开一实施例提供的另一种显示基板中导电遮光结构的平面示意图；
图11A为本公开一实施例提供的另一种显示基板的平面示意图；
图11B为本公开一实施例提供的一种显示基板中电源凹陷部或感测凹陷部的光线汇聚作用的示意图；
图11C为本公开一实施例提供的一种显示基板中电源凹陷部在垂直于衬底基板的方向上的剖面示意图；
图11D为本公开一实施例提供的一种显示基板中感测凹陷部在垂直于衬底基板的方向上的剖面示意图；
图12为本公开一实施例提供的另一种显示基板的平面示意图；
图13为本公开一实施例提供的一种显示基板中第一漏极的剖面示意图；
图14为本公开一实施例提供的一种显示装置的示意图；以及
图15为本公开一实施例提供的一种显示基板的制作方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
通常的液晶显示面板中的薄膜晶体管(Thin Film Transistor，TFT)采用非晶硅材料作为其有源层，但是这种薄膜晶体管很难满足需要高迁移率电流驱动的自发光显示装置的驱动需要。因此，有源矩阵有机发光二极管显示装置(AMOLED)通常需要采用具有高载流子迁移率的薄膜晶体管。通常，小尺寸的有源矩阵有机发光二极管显示装置可采用低温多晶硅(LTPS)作为有源层的薄膜晶体管，而大尺寸的有源矩阵有机发光二极管显示装置可采用氧化物(Oxide)作为有源层的薄膜晶体管。
在研究中，本申请的发明人发现：相对于底栅型的薄膜晶体管，顶栅型的薄膜晶体管因具有短沟道的特点，其开态电流Ion得以有效提升，从而可显著提升显示效果并降低功耗。并且，顶栅型的薄膜晶体管中的栅极与源漏极的重叠面积小，因此产生的寄生电容也较小；所以，顶栅型的薄膜晶体管发生栅极和源漏极短路等不良的可能性也较小。
图1为一种采用顶栅型的氧化物薄膜晶体管的显示基板的剖面示意图。如图1所示，该显示基板10包括衬底基板11、遮光层12、缓冲层13、有源层14、栅极绝缘层15、栅极16、层间绝缘层17和导电层18。该显示基板10的 制作过程可包括：在衬底基板11上形成遮光层12；在遮光层12远离衬底基板11的一侧形成缓冲层13；在缓冲层13远离衬底基板11的一侧形成氧化物半导体层；对氧化物半导体层进行图案化以形成有源层14，并在非沟道区域完成导体化参杂工艺；在有源层14远离衬底基板11的一侧形成栅极绝缘层15；在栅极绝缘层15远离有源层14的一侧形成栅极16；例如，可采用自对准工艺将栅极绝缘层15和栅极16通过一个掩膜工艺制作。在栅极16远离衬底基板11的一侧形成层间绝缘层17；对形成有层间绝缘层17的显示基板进行刻蚀以同时在层间绝缘层17中形成过孔H1和过孔H2；可以与H1和H2同步刻蚀，一次性地在层间绝缘层17和缓冲层13中形成接触孔CNT；也可以在阵列基板制备过程中依次分别刻蚀缓冲层13和层间绝缘层17，在层间绝缘层17和缓冲层13中形成套孔式的接触孔CNT；在层间绝缘层17远离衬底基板11的一侧形成导电层18，导电层18包括源极S和漏极D，源极S通过第一过孔H1与有源层14的源极区相连，漏极D通过第二过孔H2与有源层14的漏极区相连，并且还通过接触孔CNT与遮光层12相连。
如图1所示，由于漏极D通过第二过孔H2与有源层14的漏极区相连，并且还通过接触孔CNT与遮光层12相连，遮光层12与漏极D可具有相同的电位；另外，漏极D还与阳极25电性相连。图2A为另一种显示基板的剖面示意图。如图2A所示，阳极25、漏极D和遮光层12具有相同的电位，因此阳极25、漏极D和遮光层12可与导电层18中的电极(并不一定为上述的漏极D，可为像素驱动电路中其他薄膜晶体管的漏极)和有源层的导体化块19形成夹层电容。
在上述的制作过程中，由于一些过孔，例如过孔H1和过孔H2只需要刻蚀层间绝缘层，而另一些过孔，例如接触孔CNT，至少需要刻蚀两层绝缘层，例如上述的层间绝缘层和缓冲层，这两类孔需要刻蚀的深度不同、需要刻蚀的材料也不同，因此同时形成这两类孔的实际工艺是非常难控制的。图2B为一种显示基板中接触孔的剖面示意图。如图2B所示，接触孔在不同膜层具有不同的坡度角，导致漏极与遮光层的接触面积变小。在图2B所示的情况下，漏极与遮光层容易出现接触电阻较大、接触不良等现象，从而大大地影响电连接效果。另一方面，图3示出了一种阵列基板中过孔的剖面示意图，如图3所示，在一些实施例中，有源层本身设计地较薄，可能会出现某些部分易缺失或者被刻蚀掉的风险，从而使得过孔直接穿过有源层和缓冲层并与遮光层接触。此时， 薄膜晶体管的源极和漏极通过遮光层电连接，从而在源极给电压时造成亮点不良。
对此，本公开实施例提供一种显示基板及其制作方法和显示装置。该显示基板包括衬底基板和位于衬底基板上的多个子像素，各子像素包括：导电遮光结构，位于衬底基板上；缓冲层，位于导电遮光结构远离衬底基板的一侧；半导体层，位于缓冲层远离导电遮光结构的一侧；层间绝缘层，位于半导体层远离缓冲层的一侧；以及导电层，位于层间绝缘层远离半导体层的一侧，且包括导电结构，导电遮光结构包括第一主体部和第一凹陷部，第一凹陷部在垂直于衬底基板的方向上的平均厚度小于第一主体部在垂直于衬底基板的方向上的平均厚度，显示基板还包括第一接触孔，第一接触孔穿过层间绝缘层和缓冲层，导电结构通过第一接触孔与第一凹陷部电连接，第一凹陷部靠近导电层的表面的面积大于第一凹陷部在衬底基板上正投影的面积。由此，该显示基板通过在导电遮光结构中设置第一凹陷部，使得第一漏极与导电遮光结构的接触面积增加，接触更加充分，从可降低接触电阻，提高第一漏极和导电遮光结构的电连接效果。
下面，结合附图对本公开实施例提供的显示基板及其制作方法和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图4为本公开一实施例提供的一种显示基板的平面示意图；图5A为本公开一实施例提供的一种显示基板沿图4中AA’线的剖面示意图；图5B为本公开一实施例提供的一种显示基板沿图4中BB’线的剖面示意图；图5C为本公开一实施例提供的一种显示基板中凹陷部的光线汇聚作用的示意图；图5D为本公开一实施例提供的一种显示基板中阳极孔的示意图。需要说明的是，图4为从显示基板的阳极层到显示基板的衬底基板的俯视图。
如图4和图5A所示，该显示基板100包括衬底基板110和位于衬底基板110上的多个子像素300；各子像素300包括导电遮光结构122、缓冲层130、半导体层140、层间绝缘层170和导电层180。导电遮光结构122位于衬底基板110上；缓冲层130位于导电遮光结构122远离衬底基板110的一侧；半导体层140位于缓冲层130远离导电遮光结构122的一侧；层间绝缘层170位于半导体层140远离缓冲层130的一侧；导电层180位于层间绝缘层170远离半导体层140的一侧，导电层180包括导电结构181，例如，导电结构181可为 第一漏极1841。例如，缓冲层130可起到将导电遮光结构122与半导体层140绝缘的效果；另一方面，缓冲层130还可对衬底基板110上的缺陷或者毛刺进行掩盖，从而提高在缓冲层130上形成的半导体层120的质量。
如图4和图5A所示，导电遮光结构122包括第一主体部1220和第一凹陷部1224，第一凹陷部1224在垂直于衬底基板110的方向上的平均厚度小于第一主体部1220在垂直于衬底基板110的方向上的平均厚度。显示基板100还包括第一接触孔251，第一接触孔251穿过层间绝缘层170和缓冲层130，导电结构181通过第一接触孔251与第一凹陷部1224连接，第一凹陷部1224靠近导电层180的表面的面积大于第一凹陷部1224在衬底基板110上正投影的面积。
在本公开实施例提供的显示基板中，导电遮光结构包括第一主体部和第一凹陷部，导电结构通过第一接触孔与第一凹陷部连接。由于第一凹陷部凹入导电遮光结构，第一凹陷部靠近第一漏极的表面的面积大于第一凹陷部在衬底基板上正投影的面积。由此，该显示基板可使得第一漏极与导电遮光结构的接触面积增加，接触更加充分，从可降低接触电阻，提高第一漏极和导电遮光结构的电连接效果并且可有效地提高由该导电结构形成的电容的充放电效率。
在一些示例中，如图4和图5A所示，各子像素300还包括：平坦层210，位于导电层180远离半导体层140的一侧，且包括阳极孔263；以及阳极225，位于平坦层210远离半导体层140的一侧，且包括出光部225A、驱动部225B和将出光部225A和驱动部225B相连的延伸部225C，驱动部225B至少部分位于阳极孔263之内。在各子像素300中，第一接触孔251在衬底基板110上正投影与驱动部225B在衬底基板110上正投影至少部分交叠。由此，可通过在第一接触孔251上方设置阳极225的驱动部225B，来使得驱动部225位于第一凹陷部1224的上方，从而可在第一凹陷部1224因减薄而导致遮光性能下降时，阳极225的驱动部225B可对透过第一凹陷部1224的光进行遮挡。另外，通过设置阳极225的驱动部225还可增加阳极225的面积，从而增大由阳极构成的夹层电容的电容值。
在一些示例中，如图4和图5A所示，显示基板100还包括：电源线186，位于导电层180；以及感测线187，位于导电层180；多个子像素300包括第一子像素对360A和第二子像素对360B，第一子像素对360A包括两个子像素300，分别位于电源线186的两侧，第二子像素对360B包括两个子像素300， 分别位于感测线187的两侧；第一子像素对360A和第二子像素对360B交替排列，在第二子像素对360B中的两个子像素300中，阳极孔263与第一凹陷部1224在衬底基板110上正投影存在第一交叠区域410，第一交叠区域410的面积小于第一接触孔251在衬底基板110上正投影的面积。电源线186和感测线187沿第一方向排列，电源线186和感测线187均沿与第一方向相交的第二方向延伸。由此，在第二子像素对360B中的两个子像素300中，阳极孔263与第一凹陷部1224存在第一交叠区域410，由此，当第一凹陷部1224因减薄而导致遮光性能下降时，阳极孔263位置处的阳极225存在弯曲的界面，从而可将光线进行汇聚，从而避免透过第一凹陷部1224的光线影响正常显示。
在一些示例中，如图5D所示，阳极225在阳极孔263的边缘位置处还包括下凹结构2258，下凹结构2258的凹陷方向朝向导电遮光结构122。由此，当第一凹陷部1224因减薄而导致遮光性能下降时，由于下凹结构存在至少两个倾斜面，从而可反射透过第一凹陷部的光线。另外，由于下凹结构本身属于微结构，该下凹结构还可对透过第一凹陷部的光线进行散射，从而进一步避免透过第一凹陷部1224的光线影响正常显示。需要说明的是，上述的阳极孔的边缘位置是指阳极孔与平坦层远离半导体层的表面的交界处。
例如，上述的导电结构181可为导电层180中的第一漏极1841，第一漏极1841可为子像素300的像素驱动电路中的第一薄膜晶体管的漏极。
在一些示例中，导电遮光结构122的材料可选自钼和钛中的一种或多种；导电层180的材料可选自铜、钼和钛中的一种或多种。例如，导电层180可以为在铜层在上，钼钛混合物在下的多层结构，此时位于下层的钼钛混合物可防止位于上层的铜材料的扩散，避免影响信号线的电连接属性。当然，本公开实施例包括但不限于此，导电遮光结构和第一漏极还可采用其他材料制作。
在一些示例中，导电遮光结构在垂直于衬底基板的方向上的厚度范围为90-120纳米，导电层在垂直于衬底基板的方向上的厚度范围为200-600纳米。
在一些示例中，半导体层的材料可为氧化物半导体，例如氧化铟镓锌(IGZO)。由此，该阵列基板的像素驱动电路中的薄膜晶体管具有高载流子迁移率。
在一些示例中，层间绝缘层可选择一种材料或两种不同的材料，使用不同温度的工艺沉积制成。例如，层间绝缘层的材料可选自氧化硅、氮化硅、氮氧化硅中的一种或多种。
在一些示例中，缓冲层的材料也可选自氧化硅、氮化硅、氮氧化硅中的一种或多种。需要说明的是，缓冲层和层间绝缘层通常采用不同的材料，即时缓冲层和层间绝缘层中的元素组成相同，这些元素的比例也不同。
例如，层间绝缘层的总厚度范围为350-600纳米。例如，层间绝缘层的总厚度可为400纳米。
在一些示例中，如图4和图5A所示，第一凹陷部1224包括第一边缘部12240，在从第一凹陷部1224的边缘到第一凹陷部1224的中心的方向上，第一边缘部12240在垂直于衬底基板110的方向上的厚度连续逐渐减小。由于第一凹陷部1224在垂直于衬底基板的方向上的平均厚度小于第一主体部在垂直于衬底基板的方向上的平均厚度，因此第一凹陷部的遮光性能可能会受到影响。然而，在该示例提供的显示基板中，由于第一边缘部或者整个第一凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，使得在第一凹陷部位置处的导电结构远离衬底基板的表面为凸面，该凸面具有使得光线汇聚的功能；当有光线可以穿透第一凹陷部，该凸面可对光线汇聚的作用，从而防止部分环境光在基板内部不受控制的反射，避免环境光影响显示基板的正常显示。需要说明的是，上述的“第一凹陷部的中心”为第一凹陷部在衬底基板上的正投影的平面形状的中心；当第一凹陷部在衬底基板上的正投影为规则形状时，该中心可为该平面形状的几何中心，当第一凹陷部在衬底基板上的正投影为不规则形状时，该中心也可为该平面形状上两点之间的最大直线的中心；另外，上述的“第一凹陷部的边缘”可为第一凹陷部在衬底基板上的正投影的边缘。
例如，如图5C所示，第一凹陷部1224位置处的导电结构181远离衬底基板110的表面为凸面，该凸面具有使得光线汇聚的功能；当有光线可以穿透第一凹陷部，该凸面可对光线汇聚的作用，从而防止部分环境光在基板内部不受控制的反射，避免环境光影响显示基板的正常显示。
在一些示例中，如图4和图5A所示，在垂直于衬底基板110方向上，至少第一凹陷部1224靠近所述边缘的部分，例如上述的第一边缘部12240靠近导电层180的表面的第四坡度角是连续变化的。由此，即时有光线可以穿透第一凹陷部，第一凹陷部可使得位于第一凹陷部位置处的导电结构远离衬底基板的凸面可起到光线汇聚的作用，从而防止光线穿透整个显示基板影响出光区域的显示效果。
在一些示例中，如图4和图5A所示，第一凹陷部1224靠近导电结构，例 如第一漏极1841，的表面为连续弧面或至少一段连续弧面和至少一段平面组合而成的组合面。连续弧面或至少一段连续弧面和至少一段平面组合而成的组合面可起到光线汇聚的作用，由此，即时有光线可以穿透第一凹陷部，第一凹陷部也可防止光线穿透整个显示基板而被用户观察到。当然，本公开实施例包括但不限于此，第一凹陷部靠近第一漏极的表面也可为弯折面。
在一些示例中，如图4和图5A所示，第一接触孔251在衬底基板110上的正投影与第一凹陷部1224在衬底基板110上的正投影至少部分重叠。由此，导电层180中的导电结构181，例如第一漏极1841可通过第一接触孔251与第一凹陷部1224相连接。
在一些示例中，如图4所示，第一凹陷部1224整体在衬底基板110上的投影形状可以是各向同性的，如圆形；也可以选择各向异性的，如正方形、矩形、椭圆形、跑道型等，本公开实施例在此不作限定。
图6A为本公开一实施例提供的一种显示基板中第一凹陷部的剖面示意图；图6B为本公开一实施例提供的一种显示基板中第一凹陷部的剖面示意图。如图6A和图6B所示，第一凹陷部1224包括第一边缘部1224，第一边缘部12240靠近导电层180的表面的第四坡度角α满足下列公式：
0<α<k*H/Lmax
其中，Lmax为第一凹陷部在衬底基板上的正投影的最大孔径，H为第一主体部的平均厚度，k为大于1小于等于2的常数。
在一些示例中，第一凹陷部1224靠近第一漏极1841的表面上各个位置的坡度角α的范围为1-π/18。例如，第一凹陷部1224靠近第一漏极1841的表面上各个位置的坡度角α的范围可为1-π/36。
在一些示例中，如图6A和图6B所示，第一凹陷部1224在衬底基板110上的正投影在平行于衬底基板110的方向上的尺寸范围为5-10微米。也就是说，第一凹陷部1224的宽度的尺寸范围是5-10微米。
例如，如图6A和图6B所示，第一凹陷部1224在衬底基板110上的正投影在平行于衬底基板110的方向上的尺寸为7.8微米。
在一些示例中，如图6A和图6B所示，缓冲层130包括：第一缓冲部131，第一缓冲部131远离衬底基板110的一侧与导电层180接触设置，且第一缓冲部131靠近衬底基板110的一侧与导电遮光结构122接触设置；以及第二缓冲部132，第二缓冲部132远离衬底基板110的一侧与层间绝缘层170接触设置， 且第二缓冲部132靠近衬底基板110的一侧与导电遮光结构122接触设置。由此，在第一接触孔251中沉积上述的导电结构181时，第一缓冲部131可起到支撑部分导电结构的作用，防止导电结构因落差过大或者坡度角过大而导致的断线不良。从而，该显示基板具有较高的良率。
例如，第一缓冲部131位于第一接触孔251之内，且与导电遮光结构122接触设置；第二缓冲部132位于第一缓冲部131远离第一凹陷部1224的中心的一侧。
在一些示例中，如图6A和图6B所示，第一接触孔251的侧壁至少包括：第一子侧壁2512，位于层间绝缘层170；以及第二子侧壁2514，位于缓冲层130，第一子侧壁2512与衬底基板110的夹角构成第一坡度角β，第二子侧壁2514与衬底基板110的夹角构成第二坡度角γ，第一坡度角β小于第二坡度角γ；第二子侧壁2514与第一缓冲部131的接触部位于第一缓冲部131和第二缓冲部132之间。在该显示基板中，由于缓冲层和层间绝缘层的材料不同，因此刻蚀剂对它们的刻蚀效率也有所不同，从而容易导致形成的第一子侧壁的坡度角与第二子侧壁的坡度角不同。需要说明的是，由于工艺条件等原因，上述的子侧壁实际可能并非光滑的平面，因此上述的各子侧壁与衬底基板构成的坡度角可为各子侧壁的剖面上等间距设置的几个点的连线与衬底基板之间的夹角。
在一些示例中，如图6A和图6B所示，第一接触孔251的侧壁还包括：第三子侧壁2516，位于第一缓冲部131，第三子侧壁2516与衬底基板110的夹角构成第三坡度角，第一坡度角β、第二坡度角γ和第三坡度角θ不同。
例如，第二坡度角γ大于第三坡度角θ，第一坡度角β大于第三坡度角θ。
在一些示例中，如图6A和图6B所示，沿第一接触孔251的径向，第一缓冲部131的长度与第一缓冲部131的平均厚度之比大于第一子侧壁2512的在衬底基板110上的投影长度与层间绝缘层170的平均厚度之比。
在一些示例中，如图6A和图6B所示，沿第一接触孔251径向，第一子侧壁2512的在衬底基板110上的投影长度与层间绝缘层170的平均厚度之比大于第二子侧壁2514的在衬底基板110上的投影长度与缓冲层130的平均厚度之比。
例如，如图6A和图6B所示，第一接触孔251的侧壁包括位于层间绝缘层170中的第一子侧壁2512、位于第一缓冲部131中的第二子侧壁2514和位 于第二缓冲部132中的第三子侧壁2516；第一子侧壁2512和第二子侧壁2514相接，第二子侧壁2514和第三子侧壁2516相接，并且第一子侧壁2512的第一坡度角β、第二子侧壁2514的第二坡度角γ和第三子侧壁2516的第三坡度角θ不同。在该显示基板中，由于缓冲层和层间绝缘层的材料不同，因此刻蚀剂对它们的刻蚀效率也有所不同，从而容易导致形成的第一子侧壁的坡度角与第二子侧壁的坡度角不同。
例如，可采用不同温度的工艺沉积制成上述的缓冲层，从而使得缓冲层内部具有不同的致密度，从而可形成上述的第一缓冲部和第二缓冲部。当然，本公开实施例包括但不限于此，上述的第一缓冲部和第二缓冲部可采用其他合适的方法制作。
在一些示例中，如图6A和图6B所示，第一子侧壁2512的第一坡度角β小于第二子侧壁2514的第二坡度角γ，第二子侧壁2514的第二坡度角γ大于第三子侧壁2516的第三坡度角θ，第一子侧壁2512的第一坡度角β大于第三子侧壁2516的第三坡度角θ。也就是说，第二坡度角γ大于第一坡度角β，第一坡度角β大于第三坡度角θ。
例如，第四坡度角α小于第三子侧壁的第三坡度角θ。
例如，如图6A和图6B所示，第一子侧壁2512的第一坡度角β的范围为45-75度；第二子侧壁2514的第二坡度角γ的范围为75-90度；第三子侧壁2516的第三坡度角θ的范围为3-15度。
例如，如图6A和图6B所示，第三子侧壁2516在衬底基板110上的正投影在平行于衬底基板110的方向上的尺寸范围为0.2-1微米。
例如，第三子侧壁2516在衬底基板110上的正投影在平行于衬底基板110的方向上的尺寸为0.5微米。
在一些示例中，如图6A和图6B所示，第一凹陷部1224在衬底基板110上的正投影在平行于衬底基板110的方向上的尺寸L满足下列公式：
2(Acotβ+Bcotγ+Ccotθ)<L<D
其中，A为第一缓冲部的最大厚度，B为第二缓冲部的最大厚度，C为层间绝缘层的最大厚度，β为所述第一坡度角，γ为所述第二坡度角，θ为第三坡度角θ，D为第一接触孔在衬底基板上的正投影在平行于衬底基板的方向上的最大尺寸。
例如，第一凹陷部1224在衬底基板110上的正投影在平行于衬底基板110 的方向上的尺寸L满足公式：8(Acotβ+Bcotγ+Ccotθ)<L<D。
在一些示例中，如图6A和图6B所示，第一凹陷部1224包括第一边缘部12240，第一边缘部12240靠近导电层180的表面上的第四坡度角α小于第三子侧壁2516的第三坡度角，且满足(Acotβ+Bcotγ+Ccotθ+L/2tanα)≤D/2，A为第一缓冲部的最大厚度，B为第二缓冲部的最大厚度，C为层间绝缘层的最大厚度，β为第一坡度角，γ为第二坡度角，θ为第三坡度角，D为第一接触孔在衬底基板上的正投影在平行于衬底基板的方向上的最大尺寸。
在一些示例中，如图4和图5A所示，该显示基板100还包括栅极绝缘层150和栅极层160；栅极绝缘层150位于半导体层140远离衬底基板110的一侧；栅极层160位于栅极绝缘层150和层间绝缘层170之间。由此，该显示基板100的像素驱动电路采用的是顶栅型薄膜晶体管，从而可具有短沟道的特点，其开态电流Ion得以有效提升，从而可显著提升显示效果并降低功耗。
在一些示例中，如图4和图5A所示，该显示基板100还包括钝化层190、彩膜层200、平坦层210和阳极层220；钝化层190位于导电层180远离衬底基板110的一侧；彩膜层200位于钝化层190远离导电层180的一侧，且包括至少三种不同颜色的滤光片350；平坦层210位于彩膜层200远离钝化层190的一侧；阳极层220位于平坦层210远离彩膜层200的一侧。
图7A为本公开一实施例提供的一种显示基板中像素驱动电路的平面示意图；图7B为本公开一实施例提供的一种显示基板中像素驱动电路的平面示意图。如图4、图5A、图5B、图7A和图7B所示，各子像素300包括像素驱动电路320，像素驱动电路320包括第一薄膜晶体管T1，第一薄膜晶体管T1还包括第一有源层141、第一栅极161、第一源极1821和上述的第一漏极1841；第一有源层141位于半导体层140，且包括第一沟道区141C和位于第一沟道区141C两侧的第一源极区141S和第一漏极区141D；第一栅极161位于栅极层160，第一栅极161在衬底基板110上的正投影与第一沟道区141C在衬底基板110上的正投影至少部分重叠，第一源极1821和第一漏极1841均位于导电层180。
在一些示例中，栅极层160的材料可选自铜、钼和钛中的一种或多种。例如，栅极层160也可以为在铜层在上，钼钛混合物在下的多层结构，此时位于下层的钼钛混合物可防止位于上层的铜材料的扩散，避免影响信号线的电连接属性。当然，本公开实施例包括但不限于此，第一栅极和第二栅极也可采用其 他材料制作。
例如，栅极层可采用单层结构或多层结构，本公开实施例在此不作限制。
在一些示例中，如图5A、图7A和图7B所示，显示基板100还包括第一过孔261和第二过孔262；第一过孔261和第二过孔262位于层间绝缘层170之中，第一源极1821通过第一过孔261与第一源极区141S相连，第一漏极1841通过第二过孔262与第一漏极区141D相连。由此，上述的第一栅极、第一有源层、第一源极和第一漏极可构成上述的第一薄膜晶体管。第一薄膜晶体管可以是顶栅型薄膜晶体管，具有短沟道的特点，其开态电流Ion得以有效提升，从而可显著提升显示效果并降低功耗。
在一些示例中，如图5B、图7A和图7B所示，第二薄膜晶体管T2还包括第二有源层142、第二栅极162、第二源极1822和第二漏极1842；第二有源层142位于半导体层140，且包括第二沟道区142C和位于第二沟道区142C两侧的第二源极区142S和第二漏极区142D；第二栅极162位于栅极层160，第二栅极162在衬底基板110上的正投影与第二沟道区142C在衬底基板110上的正投影至少部分重叠，第二源极1822和第二漏极1842均位于导电层180。第二源极1822通过层间绝缘层170中的过孔H3与第二源极区142S相连，第二漏极1842通过层间绝缘层170中的过孔H4与第二漏极区142D相连。由此，上述的第二栅极、第二有源层、第二源极和第二漏极可构成上述的第二薄膜晶体管。第二薄膜晶体管可以是顶栅型薄膜晶体管，具有短沟道的特点，其开态电流Ion得以有效提升，从而可显著提升显示效果并降低功耗。
在一些示例中，如图5B、图7A和图7B所示，第三薄膜晶体管T3还包括第三有源层143、第三栅极163、第三源极1823和第三漏极1843；第三有源层143位于半导体层140，且包括第三沟道区143C和位于第三沟道区143C两侧的第三源极区143S和第三漏极区143D；第三栅极163位于栅极层160，第三栅极163在衬底基板110上的正投影与第三沟道区143C在衬底基板110上的正投影至少部分重叠，第三源极1823和第三漏极1843均位于导电层180。第三源极1823通过层间绝缘层170中的过孔H5与第三源极区143S相连，第三漏极1843通过层间绝缘层170中的过孔H6与第三漏极区143D相连。由此，上述的第三栅极、第三有源层、第三源极和第三漏极可构成上述的第三薄膜晶体管。第三薄膜晶体管可以是顶栅型薄膜晶体管，具有短沟道的特点，其开态电流Ion得以有效提升，从而可显著提升显示效果并降低功耗。
在一些示例中，如图4、图5A、图5B、图7A和图7B所示，阳极孔263可贯穿钝化层190和上述的平坦层210，阳极225通过钝化层190和平坦层210之中的阳极孔263与第一漏极1841相连。由此，该显示基板可通过第一薄膜晶体管将驱动电流施加在阳极上，以驱动该阳极对应的发光层进行发光显示。
在一些示例中，如图7A和图7B所示，第一过孔261、第二过孔262、第一接触孔251和阳极孔263依次设置。
例如，上述的第一过孔261、第二过孔262、第一接触孔251和阳极孔263在衬底基板110上的正投影的形状可为各向同性的形状，例如圆形，也可为各向异性的形状，例如，矩形、椭圆形、跑道形等；本公开实施例在此不作限制。另外，上述的第一过孔、第二过孔、第一接触孔和第三过孔在衬底基板上的正投影的具体形状可根据显示基板的版图局部实际空间约束情况来调整各位置的孔长边或短边的延伸方向。
在一些示例中，如图4、图5A、图5B、图7A和图7B所示，像素驱动电路320还包括第二薄膜晶体管T2和第三薄膜晶体管T3；第二薄膜晶体管T2包括第二栅极162、第二源极1822和第二漏极1842，第三薄膜晶体管T3包括第三栅极163、第三源极1823和第三漏极1843。半导体层140还包括导体化块147。
图8为本公开一实施例提供的一种显示基板中像素驱动电路的等效电路图。如图7A、图7B和图8所示，第一薄膜晶体管T1的第一源极1821可与电源线186相连，第二薄膜晶体管T2的第二源极1822与数据线185相连，第二薄膜晶体管T2的第二栅极162与第一栅线165相连；例如，第一栅线165与第二薄膜晶体管T2的第二有源层142的第二沟道区142C交叠的部分就是第二栅极162；第二薄膜晶体管T2的第二漏极1842与第一薄膜晶体管T1的第一栅极161和导体化块147分别相连；第三薄膜晶体管T3的第三栅极163与第二栅线166相连；第三薄膜晶体管T3的第三源极1823与感测线187相连；第三薄膜晶体管T3的第三漏极1843与第一薄膜晶体管T1的第一漏极1841相连。此时，阳极225、导电遮光结构122、和位于阳极225和导电遮光结构122之间的第二漏极1842和导体化块147形成夹层电容，即该像素驱动电路的存储电容Cst。此时，导电遮光结构122与阳极225等电位(当第一薄膜晶体管导通时，导电遮光结构与阳极通过第三过孔电连接)为存储电容的一极，导体化块147为存储电容的另一极。
例如，如图5B、图7A和图7B所示，导体化块147位于半导体层140；导体化块147可与第一薄膜晶体管T1的有源层、第二薄膜晶体管T2的有源层和第三薄膜晶体管T3的有源层均不相连，也就是说导体化块147为与第一薄膜晶体管T1的有源层、第二薄膜晶体管T2的有源层和第三薄膜晶体管T3相独立的导体化后的半导体块。当然，本公开实施例包括但不限于此，导体化块也可第一薄膜晶体管的有源层、第二薄膜晶体管的有源层和第三薄膜晶体管的有源层相连，但是与这些有源层之间存在没有导体化的半导体间隔。
例如，如图7A和图7B所示，第二栅线166与第三薄膜晶体管T3的第三有源层143的第三沟道区143C交叠的部分就是第三栅极163。由此，该显示基板可将第三薄膜晶体管T3的一部分设置在第一主体部1220所在的位置之外，即第三薄膜晶体管T3的一部分在衬底基板110上的正投影位于第一主体部1220在衬底基板110上的正投影之外。由此，该显示基板可利用第二栅线166两侧的空间，从而优化了晶体管的分布，并提高了空间的利用率。例如，如图7A和图7B所示，由于第二栅线166与第三薄膜晶体管T3的第三有源层143的第三沟道区143C交叠的部分就是第三栅极163，第三薄膜晶体管T3的一部分还可位于第二栅线166远离第一主体部1220的一侧。
在一些示例中，如图7A和图7B所示，第二漏极1842与第一栅极161可通过同一过孔与第二有源层142的漏极区域相连，从而可降低第二漏极1842遮挡第一栅极161的面积，从而降低实际工艺中成膜形貌继承带来的击穿ILD层而短路的风险。另外，第二漏极1842与第一栅极161可通过同一过孔与第二有源层142的漏极区域相连，还可降低第二有源层142上过孔的数量，提高产品良率。
图9为本公开一实施例提供的一种显示基板中像素驱动电路中各个信号线上信号的时序图。下面，结合图8所示的等效电路图和图9所示的时序图对本公开的像素驱动电路的工作流程进行说明。
如图8和图9所示，以图8中的第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3均为P型晶体管为例，在数据写入和复位阶段，第一栅线165和第二栅线166均为开启信号，第二薄膜晶体管T2和第三薄膜晶体管T3导通，数据信号DT通过第二薄膜晶体管T2传输至第一薄膜晶体管T1的第一栅极161和存储电容Cst的第一极，即上述的导体化块147；此时，复位信号通过感测线187和第三薄膜晶体管T3向阳极225写入复位信号；第一薄 膜晶体管T1导通并阳极225充电至工作电压；在发光阶段，第一栅线165和第二栅线166上均为关闭信号，由于存储电容Cst的自举起效应，存储电容Cst两端的电压保持不变，第一薄膜晶体管T1工作在饱和状态且电流保持不变；此时，电源线186上的驱动电流通过第一薄膜晶体管T1流向阳极225，从而驱动对应的发光层发光。
如图8和图9所示，该像素驱动电路的工作流程还可包括外部补偿阶过程；在外部补偿过程，第一栅线165和第二栅线166上的信号均为开启信号，第二薄膜晶体管T2和第三薄膜晶体管T3均导通，数据信号DT通过第二薄膜晶体管T2传输至第一薄膜晶体管T1的第一栅极161；此时，模数转换器可通过感测线187和第三薄膜晶体管T3向节点S写入复位信号，第一晶体管T1导通并对节点S进行充电直至第一薄膜晶体管截止，数模转换器对感测线187上的电压取样即可得到第一薄膜晶体管T1的阈值电压。需要说明的是，该外部补偿过程可以在显示装置关机时进行。
在一些示例中，如图4、图5A、图7A和图7B所示，第一沟道区141C在衬底基板110上的正投影落入第一主体部1220在衬底基板110上的正投影。由此，第一主体部1220可对第一沟道区141C起到遮挡光线的作用，从而可稳定第一薄膜晶体管，进而可提高显示质量和使用寿命。
例如，如图4、图5A、图7A和图7B所示，像素驱动电路320在衬底基板110上的正投影与导电遮光结构122在衬底基板110上的正投影至少部分重叠，从而使得整个像素驱动电路320中的各种晶体管或者存储电容均可免于被环境光照射，从而可提高该像素驱动电路320的稳定性。
在一些示例中，如图4和图5A所示，上述的导电遮光结构122还可包括第一绝缘部1221；第一绝缘部1221在衬底基板110上的正投影与第一过孔261在衬底基板110上的正投影至少部分重叠，第一绝缘部1221在衬底基板110上的正投影与第一源极区141S在衬底基板110上的正投影至少部分重叠。上述的第一绝缘部是导电遮光结构的一部分，并且相对于导电遮光结构的其他部分，第一绝缘部与其他部分绝缘。在该显示基板中，当半导体层本身较薄而导致第一源极区存在部分缺失的情况下，刻蚀剂从第一源极区向下刻蚀到第一绝缘部时，由于第一绝缘部与导电遮光结构的其他部分绝缘，即使第一源极通过第一过孔与第一绝缘部相连，也并不会导致第一源极与导电遮光结构的其他部分电连接。由此，该显示基板可降低工艺风险，并提升良率。
图10A为本公开一实施例提供的一种显示基板中导电遮光结构的平面示意图。如图10A所示，第一绝缘部1221包括第一镂空部1221A，第一镂空部1221A填充有缓冲层130的材料。由此，第一绝缘部1221可通过第一镂空部1221A与导电遮光结构122的其他部分绝缘。需要说明的是，第一绝缘部1221本身可为第一镂空部1221A，也就是说，第一绝缘部1221可为导电遮光结构122被去除的部分。
图10B为本公开一实施例提供的另一种显示基板中导电遮光结构的平面示意图。如图10B所示，第一镂空部1221A可为第一镂空环，也即第一镂空部可为环状的镂空部。第一镂空环1221A内侧的部分1221B与第一镂空环1221A的外侧均为导电遮光结构122的材料。由此，第一绝缘部1221可通过设置第一镂空环1221A来实现与导电遮光结构122的其他部分绝缘。
图10C为本公开一实施例提供的另一种显示基板中导电遮光结构的平面示意图。如图10C所示，第一绝缘部1221为氧化部。也就是说，可通过氧化工艺将导电遮光结构122的一部分氧化，以形成上述的第一绝缘部1221。
图11A为本公开一实施例提供的另一种显示基板的平面示意图。如图11A所示，各子像素300包括驱动区310和发光区330；导电遮光结构122位于驱动区310。在该显示基板中，由于像素驱动电路310在衬底基板110上的正投影与驱动区310交叠，通过将导电遮光结构122设置在驱动区310，一方面可起到防止环境光影响像素驱动电路中的薄膜晶体管，另一方面，也可防止环境光透过驱动区并影响显示基板的正常显示。需要说明的是，该显示基板的出光方向可为从阳极层到衬底基板的方向，即该显示基板采用底发射模式，也可为衬底基板到阳极层的方向，即该显示基板采用顶发射模式。
在一些示例中，如图11A所示，该显示基板100还包括第一栅线165、第二栅线166、数据线185、电源线186和感测线187；第一栅线165和第二栅线166均位于栅极层160，并均沿第一方向延伸；数据线185、电源线186和感测线187均位于导电层180，且均沿第二方向延伸。多个子像素300沿第一方向和第二方向阵列设置以形成沿第二方向排列的多个子像素行370和沿第一方向排列的多个子像素列380。在各子像素行370中，第一栅线165位于驱动区310和出光区330之间，第二栅线166位于相邻的两个子像素行370之间；电源线186、感测线187和数据线185均位于相邻的两个子像素列380之间。需要说明的是，上述的第一方向可为子像素阵列的行方向，上述的第二方向可为子像 素阵列的列方向。
在一些示例中，如图11A所示，第一薄膜晶体管T1的第一源极1821通过第一连接部1868与电源线186相连，第二薄膜晶体管T2的第二源极1822通过第二连接部1858与数据线185相连，第一连接部1868A与电源线186同层设置，第二连接部1858与数据线185同层设置。
在一些示例中，如图11A所示，第一源极1821到第一漏极1841的方向(即第一沟道区的延伸方向)与第一连接部1868的延伸方向相交，第二源极1822到第二漏极1842的方向(即第二沟道区的延伸方向)与第二连接部1858的延伸方向相交。
例如，如图11A所示，第三源极1823到第三漏极1843的方向(即第二沟道区的延伸方向)与第二栅线166的延伸方向相交。由此，一方面，第二栅线166与第三薄膜晶体管T3的第三有源层143的第三沟道区143C交叠的部分就可作为第三栅极163，从而可利用第二栅线166两侧的空间，并优化了晶体管的分布和提高了空间的利用率；另一方面，第二栅线166上不用设置从第二栅线166上凸起或者弯折的栅极部分，从而还可降低第二栅线166上的压降，提高第二栅线166的电学性能。
例如，如图11A所示，第一源极1821到第一漏极1841的方向(即第一沟道区的延伸方向)与电源线186的延伸方向大致平行，第二源极1822到第二漏极1842的方向(即第二沟道区的延伸方向)与数据线185的延伸方向大致平行。需要说明的是，上述的“大致平行”包括完全平行的情况，也包括两个方向之间的夹角小于10度的情况。
例如，如图11A所示，第三源极1823到第三漏极1843的方向(即第二沟道区的延伸方向)与感测线187的延伸方向大致平行。
在一些示例中，如图11A所示，该显示基板100包括上述的电源线186和电源连接线1865；电源线186位于导电层180；电源连接线1865与导电遮光结构122同层设置，也就是说，电源连接线1865与导电遮光结构122可采用同一膜层通过同一图案化工艺形成。
在一些示例中，如图11A所示，电源连接线1865包括第二主体部1865A和多个电源凹陷部1865K，电源凹陷部1865K在垂直于衬底基板110的方向上的平均厚度均小于第二主体部1865A在垂直于衬底基板110的方向上的平均厚度，电源凹陷部1865K靠近导电层180的表面的面积大于电源凹陷部1865K 在衬底基板110上正投影的面积。
在该示例中，如图11A所示，电源连接线1865包括第二主体部1865A和多个电源凹陷部1865K，多个电源凹陷部1865K可用于将电源线186与多个子像素300的像素驱动电路320电性相连。由于电源凹陷部1865K凹入电源连接线1865，各电源凹陷部1865K靠近导电层180的表面的面积大于电源凹陷部1865K在衬底基板110上正投影的面积，从而可使得电连接的接触面积增加，接触更加充分，从可降低接触电阻，提高电连接效果并且可有效地避免压降(IR drop)等问题。
图11B为本公开一实施例提供的一种显示基板中电源凹陷部或感测凹陷部的光线汇聚作用的示意图。如图11A和图11B所示，多个电源凹陷部1865K中的至少之一在衬底基板110上的正投影与彩膜层200中的滤光片350在衬底基板110上的正投影至少部分重叠。与第一凹陷部类似，电源凹陷部也具有使得光线汇聚的作用，并且由于电源凹陷部可与滤光片至少部分重叠，从而可使得环境光被汇聚到对应的滤光片，从而可有效防止环境光光带来的显示不均匀，避免影响观感。
图11C为本公开一实施例提供的一种显示基板中电源凹陷部在垂直于衬底基板的方向上的剖面示意图。如图11C所示，电源凹陷部1865K靠近导电层180的表面的坡度角可与第一凹陷部靠近导电层的表面的坡度角相同。当然，本公开实施例包括但不限于此，电源凹陷部靠近导电层的表面的坡度角可与第一凹陷部靠近导电层的表面的坡度角也可不相同。
在一些示例中，如图11C所示，与第一凹陷部1224类似，电源凹陷部1865K包括第二边缘部18650；在从电源凹陷部1865K的边缘到电源凹陷部1865K的中心的方向上，第二边缘部18650在垂直于衬底基板110的方向上的厚度连续逐渐减小。由于电源凹陷部靠近边缘的部分在垂直于衬底基板的方向上的平均厚度小于第一主体部在垂直于衬底基板的方向上的平均厚度，因此电源凹陷部的遮光性能可能会受到影响。然而，在该示例提供的显示基板中，由于至少电源凹陷部靠近边缘的部分，即第二边缘部18650，在垂直于衬底基板的方向上的厚度连续逐渐减小，使得在电源凹陷部位置处的导电部分(例如电源线的一部分)远离衬底基板的表面为凸面，该凸面具有使得光线汇聚的功能；当有光线可以穿透电源凹陷部，该凸面可对光线汇聚的作用，从而防止部分环境光在基板内部不受控制的反射，避免环境光影响显示基板的正常显示。
例如，如图11C所示，电源凹陷部1865K位置处的导电部分(例如电源线的一部分)远离衬底基板110的表面为凸面，该凸面具有使得光线汇聚的功能；当有光线可以穿透电源凹陷部，该凸面可对光线汇聚的作用，从而防止部分环境光在基板内部不受控制的反射，避免环境光影响显示基板的正常显示。
在一些示例中，如11C所示，与第一凹陷部1224类似，在垂直于衬底基板110方向上，至少电源凹陷部1865K靠近边缘的部分，例如上述的第二边缘部18650导电层导电层180的表面的第五坡度角是连续变化的。由此，即时有光线可以穿透电源凹陷部，电源凹陷部可使得位于电源凹陷部位置处的导电部分远离衬底基板的凸面可起到光线汇聚的作用，从而防止光线穿透整个显示基板影响出光区域的显示效果。
在一些示例中，如图11C所示，显示基板100还包括电源接触孔551，电源接触孔551位于层间绝缘层170和缓冲层130，例如，电源接触孔551贯穿层间绝缘层170和缓冲层130。电源接触孔551在衬底基板110上的正投影与电源凹陷部1865K在衬底基板110上的正投影至少部分交叠。
在一些示例中，如图11C所示，缓冲层130包括：第三缓冲部133，位于电源接触孔551之内，第三缓冲部133远离衬底基板110的一侧与电源连接线接触设置，且第三缓冲部靠近衬底基板的一侧与导电遮光结构接触设置；以及第四缓冲部134，位于第三缓冲部133远离电源凹陷部1865K的中心的一侧。由此，在电源接触孔551中沉积上述的导电层(例如，对应电源线的部分)时，第三缓冲部133可起到支撑部分导电结构的作用，防止导电结构因落差过大或者坡度角过大而导致的断线不良。从而，该显示基板具有较高的良率。
在一些示例中，如图11C所示，电源接触孔551的侧壁包括位于层间绝缘层170中的第四子侧壁5512、位于第四缓冲层134中的第五子侧壁5514和位于第三缓冲部133中的第六子侧壁5516；第四子侧壁5512和第五子侧壁5514相接，第五子侧壁5514和第六子侧壁5516相接，并且第四子侧壁5512与衬底基板110的夹角构成第六坡度角β’、第五子侧壁5514和衬底基板110的夹角构成第七坡度角γ’，第六子侧壁5516与衬底基板110的夹角构成的第八坡度角θ’。第六坡度角、第七坡度角和第八坡度角不同。第五子侧壁5514与第三缓冲部133的接触部位于第三缓冲部133和第四缓冲部134之间。
在该显示基板中，由于缓冲层和层间绝缘层的材料不同，因此刻蚀剂对它们的刻蚀效率也有所不同，从而容易导致形成的第四子侧壁的坡度角、第五子 侧壁的坡度角与第六子侧壁的坡度角不同。
例如，可采用不同温度的工艺沉积制成上述的缓冲层，从而使得缓冲层内部具有不同的致密度，从而可形成上述的第三缓冲部和第四缓冲部。当然，本公开实施例包括但不限于此，上述的第三缓冲部和第四缓冲部可采用其他合适的方法制作。
在一些示例中，如图11C所示，第六坡度角β’小于第七坡度角γ’，第七坡度角γ’大于第八坡度角θ’，第六坡度角β’大于第八坡度角θ’。也就是说，第七坡度角γ’大于第六坡度角β’，第六坡度角β’大于第八坡度角θ’。
例如，第四坡度角α小于第八坡度角θ’。
在一些示例中，由于电源凹陷部形成在线状或条状的电源连接线上，因此电源凹陷部对应的电源接触孔和第一凹陷部对应的第一接触孔中的侧壁的角度可以不同。例如，电源接触孔中的第七坡度角γ’小于第一接触孔的第三坡度角γ。由此，由于电源接触孔中的第六坡度角较小，使得第五子侧壁更为平缓，从而可更好地防止断线等不良。当然，本公开实施例包括但不限于此，电源接触孔中的第七坡度角γ’也可大于或等于第一接触孔的第二坡度角γ。
在一些示例中，电源接触孔中的第八坡度角θ’大于第一接触孔的第三坡度角θ，从而可减小第三缓冲部的尺寸，增大与电源凹陷部的电连接效果。当然，本公开实施例包括但不限于此，电源接触孔中的第八坡度角也可小于第一接触孔的第四坡度角。
在一些示例中，如图11A所示，该显示基板100包括上述的感测线187和感测连接线1875；感测线187位于导电层180，感测连接线1875与导电遮光结构122同层设置，也就是说，电源连接线1865与导电遮光结构122可采用同一膜层通过同一图案化工艺形成。
在一些示例中，如图11A所示，感测连接线1875包括第三主体部1875A和多个感测凹陷部1875K，感测凹陷部1875K在垂直于衬底基板110的方向上的平均厚度均小于第三主体部1875A在垂直于衬底基板110的方向上的平均厚度，感测凹陷部1875K靠近导电层180的表面的面积大于感测凹陷部1875K在衬底基板110上正投影的面积。
在该示例中，感测连接线1875包括第三主体部1875A和多个感测凹陷部1875K，多个感测凹陷部1875K可用于将感测线187与多个子像素300的像素驱动电路320电性相连。由于感测凹陷部1875K凹入感测连接线1875，各感 测凹陷部1875K靠近导电层180的表面的面积大于感测凹陷部1875K在衬底基板110上正投影的面积，从而可使得电连接的接触面积增加，接触更加充分，从可降低接触电阻，提高电连接效果并且可有效地避免压降(IR drop)等问题。
在一些示例中，如图11A和图11B所示，多个感测凹陷部1875K中的至少之一在衬底基板110上的正投影与彩膜层200中的滤光片350在衬底基板110上的正投影至少部分重叠。与第一凹陷部类似，电源凹陷部也具有使得光线汇聚的作用，并且由于电源凹陷部可与滤光片至少部分重叠，从而可使得环境光被汇聚到对应的滤光片，从而可有效防止环境光光带来的显示不均匀，避免影响观感。
图11D为本公开一实施例提供的一种显示基板中感测凹陷部在垂直于衬底基板的方向上的剖面示意图。如图11D所示，感测凹陷部1875K靠近导电层180的表面的坡度角可与第一凹陷部靠近导电层的表面的坡度角相同。当然，本公开实施例包括但不限于此，感测凹陷部靠近导电层的表面的坡度角可与第一凹陷部靠近导电层的表面的坡度角也可不相同。
在一些示例中，如图11D所示，与第一凹陷部1224类似，感测凹陷部1875K包括第三边缘部18750；在从感测凹陷部1875K的边缘到感测凹陷部1875K的中心的方向上，第三边缘部18750在垂直于衬底基板110的方向上的厚度连续逐渐减小。由于感测凹陷部靠近边缘的部分在垂直于衬底基板的方向上的平均厚度小于第一主体部在垂直于衬底基板的方向上的平均厚度，因此感测凹陷部的遮光性能可能会受到影响。然而，在该示例提供的显示基板中，由于至少感测凹陷部靠近边缘的部分在垂直于衬底基板的方向上的厚度连续逐渐减小，使得在感测凹陷部位置处的导电部分(例如感测线的一部分)远离衬底基板的表面为凸面，该凸面具有使得光线汇聚的功能；当有光线可以穿透感测凹陷部，该凸面可对光线汇聚的作用，从而防止部分环境光在基板内部不受控制的反射，避免环境光影响显示基板的正常显示。
例如，如图11D所示，感测凹陷部1875K位置处的导电部分(例如感测线的一部分)远离衬底基板110的表面为凸面，该凸面具有使得光线汇聚的功能；当有光线可以穿透感测凹陷部，该凸面可对光线汇聚的作用，从而防止部分环境光在基板内部不受控制的反射，避免环境光影响显示基板的正常显示。
在一些示例中，如11D所示，与第一凹陷部1224类似，在垂直于衬底基板110方向上，第三边缘部18750靠近导电层180的表面的第九坡度角是连续 变化的。由此，即时有光线可以穿透感测凹陷部，感测凹陷部可使得位于感测凹陷部位置处的导电部分远离衬底基板的凸面可起到光线汇聚的作用，从而防止光线穿透整个显示基板影响出光区域的显示效果。
在一些示例中，如图11D所示，显示基板100还包括感测接触孔552，感测接触孔552位于层间绝缘层170和缓冲层130，例如，感测接触孔552贯穿层间绝缘层170和缓冲层130。感测接触孔552在衬底基板110上的正投影与感测凹陷部1875K在衬底基板110上的正投影至少部分交叠。
在一些示例中，如图11D所示，缓冲层130包括：第五缓冲部135，位于感测接触孔552之内，且与感测连接线1875接触设置；以及第六缓冲部136，位于第五缓冲部135远离感测凹陷部1875K的中心的一侧。由此，在感测接触孔552中沉积上述的导电层(例如，对应感测线的部分)时，第五缓冲部135可起到支撑部分导电结构的作用，防止导电结构因落差过大或者坡度角过大而导致的断线不良。从而，该显示基板具有较高的良率。
在一些示例中，如图11D所示，第五缓冲部135远离衬底基板110的一侧与感测连接线1875接触设置，且第五缓冲部135靠近衬底基板110的一侧与导电遮光结构122接触设置。
在一些示例中，如图11D所示，感测接触孔552的侧壁包括位于层间绝缘层170中的第七子侧壁5522、位于第六缓冲层136中的第八子侧壁5524和位于第五缓冲部135中的第九子侧壁5526；第七子侧壁5522和第八子侧壁5524相接，第八子侧壁5524和第九子侧壁5526相接，并且第七子侧壁5522与衬底基板110的夹角构成第十坡度角β”、第八子侧壁5524与衬底基板110的夹角构成第十一坡度角γ”，第九子侧壁5526与衬底基板110的夹角构成第十二坡度角θ”；第十坡度角、第十一坡度角和第十二坡度角不同。在该显示基板中，由于缓冲层和层间绝缘层的材料不同，因此刻蚀剂对它们的刻蚀效率也有所不同，从而容易导致形成的第七子侧壁的坡度角、第八子侧壁的坡度角与第九子侧壁的坡度角不同。
例如，可采用不同温度的工艺沉积制成上述的缓冲层，从而使得缓冲层内部具有不同的致密度，从而可形成上述的第五缓冲部和第六缓冲部。当然，本公开实施例包括但不限于此，上述的第五缓冲部和第六缓冲部可采用其他合适的方法制作。
在一些示例中，如图11D所示，第十坡度角β”小于第十一坡度角γ”，第 十一坡度角γ”大于第十二坡度角θ”，第十坡度角β”大于第十二坡度角θ”。也就是说，第十一坡度角γ”大于第十坡度角β”，第十坡度角β”大于第十二坡度角θ”。当然，本公开实施例包括但不限于此。
例如，第四坡度角α小于第十二坡度角θ”。
在一些示例中，由于感测凹陷部形成在线状或条状的感测连接线上，因此感测凹陷部对应的感测接触孔和第一凹陷部对应的第一接触孔中的侧壁的角度可以不同。例如，感测接触孔中的第十一坡度角γ”小于第一接触孔的第三坡度角γ。由此，由于感测接触孔中的第十一坡度角较小，使得第八子侧壁更为平缓，从而可更好地防止断线等不良。当然，本公开实施例包括但不限于此，感测接触孔中的第十一坡度角γ”也可大于或等于第一接触孔的第三坡度角γ。
在一些示例中，感测接触孔中的第十二坡度角θ”大于第一接触孔的第三坡度角θ，从而可减小第五缓冲部的尺寸，增大与感测凹陷部的电连接效果。当然，本公开实施例包括但不限于此，感测接触孔中的第十二坡度角也可小于第一接触孔的第三坡度角。
需要说明的是，上述的电源凹陷部和感测凹陷部的其他的具体形状和尺寸可参见图6A和图6B所示的第一凹陷部的相关描述，在此不再赘述。
在一些示例中，如图11A所示，多个子像素300包括第一颜色子像素300A、第二颜色子像素300B、第三颜色子像素300C和第四颜色子像素300D；在各子像素行370，第一颜色子像素300A、第二颜色子像素300B、第三颜色子像素300C和第四颜色子像素300D沿第一方向依次排列并形成一个子像素组390，电源线186位于子像素组390中第二颜色子像素300B和第三颜色子像素300C之间。
在一些示例中，如图11A所示，显示基板100还包括电源连接线1865，电源连接线1865与导电遮光结构122同层设置；电源线186可通过贯穿层间绝缘层和缓冲层的接触孔与电源连接线1865相连。
在一些示例中，如图11A所示，显示基板100还包括第二接触孔252、第三接触孔253和第四接触孔254，第二接触孔252、第三接触孔253和第四接触孔254位于层间绝缘层170和缓冲层130；在子像素组390中，电源线186通过第二接触孔252与电源连接线1865相连，第二颜色子像素300B的第一源极1821与电源线186同层相连，第三颜色子像素300C的第一源极1821与电源线186同层相连。需要说明的是，上述的同层相连是指第一源极和电源线直 接通过同层设置的连接线相连。
在一些示例中，如图11A所示，第一颜色子像素300A的第一源极1821通过第三接触孔253与电源连接线1865相连，第四颜色子像素300D的第一源极1821通过第四接触孔254与电源连接线1865相连。由此，在各像素行，一根电源线可同时驱动四个子像素，从而可降低布线密度。
在一些示例中，如图11A所示，电源连接线1865包括第二主体部1865A、第二凹陷部1865B、第三凹陷部1865C和第四凹陷部1865D；第二凹陷部1865B在衬底基板110上的正投影与第二接触孔252在衬底基板110上的正投影至少部分重叠，第二凹陷部1865B在垂直于衬底基板110的方向上的厚度均小于第二主体部1865A在垂直于衬底基板110的方向上的厚度，第二凹陷部1865B靠近电源线186的表面的面积大于第二凹陷部1865B在衬底基板110上正投影的面积。在该显示基板中，电源线186可通过第二接触孔252与电源连接线1865的第二凹陷部1865B相连。由于第二凹陷部1865B为凹陷结构，第二凹陷部靠近电源线的表面的面积大于第二凹陷部在衬底基板上正投影的面积。由此，该显示基板可使得电源线与电源连接线的接触面积增加，接触更加充分，从可降低接触电阻，提高电源线与电源连接线的电连接效果。
与第一凹陷部类似的是，从第二凹陷部的边缘到第二凹陷部的中心，至少第二凹陷部靠近边缘的部分在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第二凹陷部在垂直于衬底基板的方向上的平均厚度小于第二主体部在垂直于衬底基板的方向上的厚度，因此第二凹陷部的遮光性能可能会受到影响。在该示例提供的显示基板中，由于第二凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第二凹陷部，第二凹陷部也可起到光线汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。同样地，第二凹陷部靠近电源线的表面为弧面或弯折面。
在一些示例中，如图11A所示，第三凹陷部1865C在衬底基板110上的正投影与第三接触孔253在衬底基板110上的正投影至少部分重叠，第三凹陷部1865C在垂直于衬底基板110的方向上的厚度均小于第二主体部1865A在垂直于衬底基板110的方向上的厚度，第三凹陷部1865C远离衬底基板110的表面的面积大于第三凹陷部1865C在衬底基板110上正投影的面积。在该显示基板中，第一颜色子像素300A的第一源极1821可通过第三接触孔253与电源连接线1865的第三凹陷部1865C相连；例如，可通过设置在导电层的连接线 将第一颜色子像素的第一源极与第三凹陷部相连。由于第三凹陷部为凹陷结构，第三凹陷部远离衬底基板的表面的面积大于第三凹陷部在衬底基板上正投影的面积。由此，该显示基板可使得第一颜色子像素的第一源极与电源连接线的接触面积增加，接触更加充分，从可降低接触电阻，提高第一颜色子像素的第一源极与电源连接线的电连接效果。
与第一凹陷部类似的是，从第三凹陷部的边缘到第三凹陷部的中心，至少第三凹陷部靠近边缘的部分在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第三凹陷部在垂直于衬底基板的方向上的平均厚度小于第二主体部在垂直于衬底基板的方向上的厚度，因此第三凹陷部的遮光性能可能会受到影响。在该示例提供的显示基板中，由于第三凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第三凹陷部，第三凹陷部也可起到光线汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。同样地，第三凹陷部靠近电源线的表面也可为弧面或弯折面。
在一些示例中，如图11A所示，第四凹陷部1865D在衬底基板110上的正投影与第四接触孔254在衬底基板110上的正投影至少部分重叠，第四凹陷部1865D在垂直于衬底基板110的方向上的厚度均小于第二主体部1865A在垂直于衬底基板110的方向上的厚度，第四凹陷部1865D远离衬底基板110的表面的面积大于第四凹陷部1865D在衬底基板110上正投影的面积。在该显示基板中，第四颜色子像素300D的第一源极1821可通过第四接触孔254与电源连接线1865的第四凹陷部1865D相连；例如，可通过设置在导电层的连接线将第四颜色子像素的第一源极与第四凹陷部相连。由于第四凹陷部为凹陷结构，第四凹陷部远离衬底基板的表面的面积大于第四凹陷部在衬底基板上正投影的面积。由此，该显示基板可使得第四颜色子像素的第一源极与电源连接线的接触面积增加，接触更加充分，从可降低接触电阻，提高第四颜色子像素的第一源极与电源连接线的电连接效果。
与第一凹陷部类似的是，从第四凹陷部的边缘到第四凹陷部的中心，至少第四凹陷部靠近边缘的部分在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第四凹陷部在垂直于衬底基板的方向上的平均厚度小于第二主体部在垂直于衬底基板的方向上的厚度，因此第四凹陷部的遮光性能可能会受到影响。在该示例提供的显示基板中，由于第四凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第四凹陷部，第四凹陷部也可起到光线 汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。同样地，第四凹陷部靠近电源线的表面也可为弧面或弯折面。
在一些示例中，如图11A所示，第二凹陷部1865B、第三凹陷部1865C和第四凹陷部1865D中的至少之一在衬底基板110上的正投影与彩膜层200中的滤光片350在衬底基板110上的正投影至少部分重叠，从而可有效防止环境光光带来的显示不均匀，避免影响观感。
在一些示例中，如图11A所示，第二颜色子像素300B包括第一颜色滤光片351，从而可发第一颜色的光；第三颜色子像素300C包括第二颜色滤光片352，从而可发第二颜色的光；第四颜色子像素300D包括第三颜色滤光片353，从而可发第三颜色的光。例如，第一颜色子像素300D可不设置的滤光片，从而发白光。由此，该显示基板可实现全彩显示，并且由于采用白光子像素，从而使得该显示基板的亮度和对比度增加。
例如，第一颜色可为红色(R)，第二颜色可为绿色(G)，第三颜色可为蓝色(B)。当然，本公开实施例包括但不限于此，上述的三种颜色还可为其他颜色。
在一些示例中，如图11A所示，该显示基板100还可包括像素限定层370，像素限定层370包括多个开口375，多个开口375中可设置滤光片350。
例如，如图11A所示，多个开口375包括第一开口3751、第二开口3752和第三开口3753；第一颜色滤光片351至少部分设置在第一开口3751；第二颜色滤光片352至少部分设置在第二开口3752；第三颜色滤光片353至少部分设置在第三开口3753。第三颜色滤光片353的外边缘与第三开口3753的最短距离J3大于第一颜色滤光片351的外边缘与第一开口3751的最短距离J2，第三颜色滤光片353的外边缘与第三开口3753的最短距离J3也大于第二颜色滤光片352的外边缘与第二开口3752的最短距离J1。当然，本公开实施例包括但不限于此，根据不同的产品需求，第二颜色滤光片的外边缘与第二开口的最短距离也可大于第一颜色滤光片的外边缘与第一开口的最短距离和第三颜色滤光片的外边缘与第三开口的最短距离，或者第一颜色滤光片的外边缘与第一开口的最短距离也可大于第二颜色滤光片的外边缘与第二开口的最短距离和第三颜色滤光片的外边缘与第三开口的最短距离。
在一些示例中，如图11A所示，第一颜色滤光片351大部分设置在第一颜色子像素300A的出光区330；第二颜色滤光片352大部分设置在第二颜色子 像素300B的出光区330；第三颜色滤光片353大部分设置在第三颜色子像素300C的出光区330。
在一些示例中，如图11A所示，在子像素组390中，第一颜色滤光片351和第二颜色滤光片352中的至少一个在衬底基板110上的正投影与第二凹陷部1865B在衬底基板110上的正投影至少部分重叠，第三颜色滤光片351在衬底基板110上的正投影与第四凹陷部1865D在衬底基板110上的正投影至少部分重叠。由此，即使第二凹陷部或者第四凹陷部由于其厚度较薄而导致遮光性能受到影响，第一颜色滤光片和第二颜色滤光片还可对第二凹陷部起到进一步的遮光作用，第三颜色滤光片可对第四凹陷部起到进一步的遮光作用，从而可防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。
另外，当从第二凹陷部的边缘到第二凹陷部的中心，第二凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小时，即使有光线透过第二凹陷部，第二凹陷部可将光线汇聚到第一颜色滤光片和第二颜色滤光片的至少之一上，从而可有效防止环境光穿透整个显示基板。当第四凹陷部的边缘到第四凹陷部的中心，第四凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小时，即使有光线透过第四凹陷部，第四凹陷部可将光线汇聚到第三颜色滤光片上，从而可有效防止环境光光带来的显示不均匀，避免影响观感。
例如，如图11A所示，第三颜色滤光片351在衬底基板110上的正投影与第四凹陷部1865D在衬底基板110上的正投影之间的重叠面积大于第一颜色滤光片351或第二颜色滤光片352在衬底基板110上的正投影与第二凹陷部1865B在衬底基板110上的正投影之间的重叠面积。
在一些示例中，如图11A所示，感测线187位于在第一方向上相邻的两个子像素组390之间，在第一方向上相邻的两个子像素组390包括第一子像素组391和第二子像素组392。显示基板100还包括感测连接线1875、第五接触孔255、第六接触孔256、第七接触孔257、第八接触孔258和第九接触孔259；感测连接线1875与导电遮光结构122同层设置，第五接触孔255、第六接触孔256、第七接触孔257、第八接触孔258和第九接触孔259位于层间绝缘层170和缓冲层130之中。在相邻的两个子像素组390中，感测线187通过第五接触孔255与感测连接线1875相连。需要说明的是，为了清楚，图11A没有完整地示出整个第二子像素组，第二子像素组的组成可参见第一子像素组的组成。
在一些示例中，如图11A所示，第一子像素组391中的第三颜色子像素 300C的第三源极1843通过第六接触孔256与感测连接线1875相连，第一子像素组391中的第四颜色子像素300D的第三源极1843通过第七接触孔257与感测连接线1875相连。第二子像素组392中的第一颜色子像素300A的第三源极1843通过第八接触孔358与感测连接线1875相连，第二子像素组392中的第二颜色子像素300B的第三源极1843通过第九接触孔359与感测连接线1875相连。由此，在各像素行，一根感测线可同时驱动四个子像素，从而可降低布线密度。另外，由于上述的四个子像素的第三源极均通过接触孔与感测连接线相连，使得各子像素的像素驱动电路的布置空间大致相同，从而可简化各子像素的像素驱动电路的排布。
在一些示例中，如图11A所示，感测连接线1875包括第三主体部1875A、第五凹陷部1875B、第六凹陷部1875C、第七凹陷部1875D、第八凹陷部1875E、第九凹陷部1875F；第五凹陷部1875B在衬底基板110上的正投影与第五接触孔255在衬底基板110上的正投影至少部分重叠，第六凹陷部1875C在衬底基板110上的正投影与第六接触孔266在衬底基板110上的正投影至少部分重叠，第七凹陷部1875D在衬底基板110上的正投影与第七接触孔257在衬底基板110上的正投影至少部分重叠，第八凹陷部1875E在衬底基板110上的正投影与第八接触孔258在衬底基板110上的正投影至少部分重叠，第九凹陷部1875F在衬底基板110上的正投影与第九接触孔259在衬底基板110上的正投影至少部分重叠。
在一些示例中，如图11A所示，第五凹陷部1875B在垂直于衬底基板110的方向上的厚度均小于第三主体部1875A在垂直于衬底基板110的方向上的厚度；第五凹陷部155靠近感测线187的表面的面积大于第五凹陷部1875B在衬底基板110上正投影的面积。在该显示基板中，感测线187可通过第五接触孔255与感测连接线1875的第五凹陷部1875B相连。由于第五凹陷部1865B为凹陷结构，第五凹陷部靠近感测线的表面的面积大于第五凹陷部在衬底基板上正投影的面积。由此，该显示基板可使得感测线与感测连接线的接触面积增加，接触更加充分，从可降低接触电阻，提高感测线与感测连接线的电连接效果。
与第一凹陷部类似的是，从第五凹陷部的边缘到第五凹陷部的中心，第五凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第五凹陷部在垂直于衬底基板的方向上的平均厚度小于第三主体部在垂直于衬底基板的方向上的厚度，因此第五凹陷部的遮光性能可能会受到影响。在该示例提供的显示 基板中，由于第五凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第五凹陷部，第五凹陷部也可起到光线汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。同样地，第五凹陷部靠近电源线的表面为弧面或弯折面。
在一些示例中，如图11A所示，第六凹陷部1875C在垂直于衬底基板110的方向上的厚度均小于第三主体部1875A在垂直于衬底基板110的方向上的厚度，第六凹陷部1875C远离衬底基板110的表面的面积大于第六凹陷部1875C在衬底基板110上正投影的面积。在该显示基板中，第一子像素组391中的第三颜色子像素300C的第三源极1843通过第六接触孔356与感测连接线1875的第六凹陷部1875C相连。由于第六凹陷部1865C为凹陷结构，第六凹陷部1865C远离衬底基板110的表面的面积大于第六凹陷部1865C在衬底基板110上正投影的面积。由此，该显示基板可使得第一子像素组中的第三颜色子像素的第三源极与感测连接线的接触面积增加，接触更加充分，从可降低接触电阻，提高第一子像素组中的第三颜色子像素的第三源极与感测连接线的电连接效果。
与第一凹陷部类似的是，从第六凹陷部的边缘到第六凹陷部的中心，第六凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第六凹陷部在垂直于衬底基板的方向上的平均厚度小于第三主体部在垂直于衬底基板的方向上的厚度，因此第六凹陷部的遮光性能可能会受到影响。在该示例提供的显示基板中，由于第六凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第六凹陷部，第六凹陷部也可起到光线汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。同样地，第六凹陷部靠近电源线的表面为弧面或弯折面。
在一些示例中，如图11A所示，第七凹陷部1875D在垂直于衬底基板110的方向上的厚度均小于第三主体部1875A在垂直于衬底基板110的方向上的厚度，第七凹陷部1875D远离衬底基板110的表面的面积大于第七凹陷部1875D在衬底基板110上正投影的面积。在该显示基板中，第一子像素组391中的第四颜色子像素300D的第三源极1843通过第七接触孔357与感测连接线1875的第七凹陷部1875D相连。由于第七凹陷部1875D为凹陷结构，第七凹陷部1865D远离衬底基板110的表面的面积大于第七凹陷部1865D在衬底基板110上正投影的面积。由此，该显示基板可使得第一子像素组中的第四颜色子像素 的第三源极与感测连接线的接触面积增加，接触更加充分，从可降低接触电阻，提高第一子像素组中的第四颜色子像素的第三源极与感测连接线的电连接效果。
与第一凹陷部类似的是，从第七凹陷部的边缘到第七凹陷部的中心，第七凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第七凹陷部在垂直于衬底基板的方向上的平均厚度小于第三主体部在垂直于衬底基板的方向上的厚度，因此第七凹陷部的遮光性能可能会受到影响。在该示例提供的显示基板中，由于第七凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第七凹陷部，第七凹陷部也可起到光线汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。同样地，第七凹陷部靠近电源线的表面为弧面或弯折面。
在一些示例中，如图11A所示，第八凹陷部1875E在垂直于衬底基板110的方向上的厚度均小于第三主体部1875A在垂直于衬底基板110的方向上的厚度，第八凹陷部1875E远离衬底基板110的表面的面积大于第八凹陷部1875E在衬底基板110上正投影的面积。在该显示基板中，第二子像素组392中的第一颜色子像素300A的第三源极1843通过第八接触孔358与感测连接线1875的第八凹陷部1875E相连。由于第八凹陷部1875E为凹陷结构，第八凹陷部1865E远离衬底基板110的表面的面积大于第八凹陷部1865E在衬底基板110上正投影的面积。由此，该显示基板可使得第二子像素组中的第一颜色子像素的第三源极与感测连接线的接触面积增加，接触更加充分，从可降低接触电阻，提高第二子像素组中的第一颜色子像素的第三源极与感测连接线的电连接效果。
与第一凹陷部类似的是，从第八凹陷部的边缘到第八凹陷部的中心，第八凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第八凹陷部在垂直于衬底基板的方向上的平均厚度小于第三主体部在垂直于衬底基板的方向上的厚度，因此第八凹陷部的遮光性能可能会受到影响。在该示例提供的显示基板中，由于第八凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第八凹陷部，第八凹陷部也可起到光线汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。同样地，第八凹陷部靠近电源线的表面为弧面或弯折面。
在一些示例中，如图11A所示，第九凹陷部1875F在垂直于衬底基板110 的方向上的厚度均小于第三主体部1875A在垂直于衬底基板110的方向上的厚度，第九凹陷部1875F远离衬底基板110的表面的面积大于第九凹陷部1875F在衬底基板110上正投影的面积。在该显示基板中，第二子像素组392中的第二颜色子像素300B的第三源极1843通过第九接触孔359与感测连接线1875的第九凹陷部1875F相连。由于第九凹陷部1875F为凹陷结构，第九凹陷部1865F远离衬底基板110的表面的面积大于第九凹陷部1865F在衬底基板110上正投影的面积。由此，该显示基板可使得第二子像素组中的第二颜色子像素的第三源极与感测连接线的接触面积增加，接触更加充分，从可降低接触电阻，提高第二子像素组中的第二颜色子像素的第三源极与感测连接线的电连接效果。
与第一凹陷部类似的是，从第九凹陷部的边缘到第九凹陷部的中心，第九凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第九凹陷部在垂直于衬底基板的方向上的平均厚度小于第三主体部在垂直于衬底基板的方向上的厚度，因此第九凹陷部的遮光性能可能会受到影响。在该示例提供的显示基板中，由于第九凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第九凹陷部，第九凹陷部也可起到光线汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。同样地，第九凹陷部靠近电源线的表面为弧面或弯折面。
在一些示例中，如图11A所示，第五凹陷部1875B、第六凹陷部1875C、第七凹陷部1875D、第八凹陷部1875E、第九凹陷部1875F中的至少之一在衬底基板110上的正投影与彩膜层200中的滤光片350在衬底基板110上的正投影至少部分重叠，从而可有效防止环境光光带来的显示不均匀，避免影响观感。
在一些示例中，如图11A所示，在第二方向上，感测连接线1875位于第二栅线162远离第一栅线161的一侧，第一子像素组391中的第二颜色滤光片352在衬底基板110上的正投影与在第二方向上相邻的第一子像素组391的第六凹陷部1875C在衬底基板110上的正投影至少部分重叠。由此，即使第六凹陷部由于其厚度较薄而导致遮光性能受到影响，第一子像素组中的第二颜色滤光片还可对第六凹陷部起到进一步的遮光作用，从而可防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。
另外，当从第六凹陷部的边缘到第六凹陷部的中心，第六凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小时，即使有光线透过第六凹陷部，第六 凹陷部可将光线汇聚到上述的第二颜色滤光片上，从而可有效防止环境光穿透整个显示基板。
在一些示例中，如图11A所示，第一子像素组391中的第三颜色滤光片353在衬底基板110上的正投影与在第二方向上相邻的第一子像素组391的第七凹陷部1875D在衬底基板110上的正投影至少部分重叠。由此，即使第七凹陷部由于其厚度较薄而导致遮光性能受到影响，第一子像素组中的第三颜色滤光片还可对第七凹陷部起到进一步的遮光作用，从而可防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。
另外，当从第七凹陷部的边缘到第七凹陷部的中心，第七凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小时，即使有光线透过第七凹陷部，第七凹陷部可将光线汇聚到上述的第三颜色滤光片上，从而可有效防止环境光穿透整个显示基板。
在一些示例中，如图11A所示，第二子像素组392中的第一颜色滤光片351在衬底基板110上的正投影与在第二方向上相邻的第九凹陷部1875F在衬底基板110上的正投影至少部分重叠。由此，即使第九凹陷部由于其厚度较薄而导致遮光性能受到影响，第二子像素组中的第一颜色滤光片还可对第九凹陷部起到进一步的遮光作用，从而可防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。
另外，当从第九凹陷部的边缘到第九凹陷部的中心，第九凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小时，即使有光线透过第九凹陷部，第九凹陷部可将光线汇聚到上述的第一颜色滤光片上，从而可有效防止环境光穿透整个显示基板。
例如，如图11A所示，第三颜色滤光片351在衬底基板110上的正投影与感测凹陷部1875K在衬底基板110上的正投影之间的重叠面积大于第一颜色滤光片351或第二颜色滤光片352在衬底基板110上的正投影与感测凹陷部1875K在衬底基板110上的正投影之间的重叠面积。
在一些示例中，如图11A所示，在子像素组390中，第一颜色滤光片351在衬底基板110上的正投影与电源连接线1865在衬底基板110上的正投影至少部分重叠，从而可调节像素驱动电路中各种电容的电容值，进而达到较好的电学性能。第二颜色滤光片352在衬底基板110上的正投影分别与电源连接线1865在衬底基板110上的正投影和第一栅线161在衬底基板110上的正投影至 少部分重叠，从而也可调节像素驱动电路中各种电容的电容值，进而达到较好的电学性能。第三颜色滤光片353在衬底基板110上的正投影与电源连接线1865在衬底基板110上的正投影至少部分重叠，从而也可调节像素驱动电路中各种电容的电容值，进而达到较好的电学性能。
在一些示例中，如图11A所示，在子像素组390中，第一颜色滤光片351在衬底基板110上的正投影与感测连接线1875在衬底基板110上的正投影至少部分重叠，第二颜色滤光片352在衬底基板110上的正投影分别与感测连接线1875在衬底基板110上的正投影至少部分重叠，第三颜色滤光片353在衬底基板110上的正投影与感测连接线1875在衬底基板110上的正投影至少部分重叠。从而，该显示基板可通过调节滤光片与感测连接线之间的重叠关系来调节像素驱动电路中各种电容的电容值，进而达到较好的电学性能。在一些示例中，如图11A所示，数据线185包括第一数据线185A、第二数据线185B、第三数据线185C和第四数据线185D；在子像素组390中，第一数据线185A和第二数据线185B位于第一颜色子像素300A和第二颜色子像素300B之间，第一数据线185A位于第二数据线185B远离第二颜色子像素300B的一侧；第一数据线185A与第一颜色子像素300A的第二源极1842相连，第二数据线185B与第二颜色子像素300B的第二源极1842相连，第三数据线185C和第四数据线185D位于第三颜色子像素300C和第四颜色子像素300D之间，第三数据线185位于第四数据线185D远离第四颜色子像素300D的一侧；第三数据线185C与第三颜色子像素300C的第二源极1842相连，第四数据线185D与第四颜色子像素300D的第二源极1842相连。由此，该显示基板通过一根数据线来驱动一个子像素列。
在一些示例中，如图11A所示，在子像素组390中，第一颜色滤光片351在衬底基板110上的正投影与第二数据线185A在衬底基板110上的正投影至少部分重叠，第二颜色滤光片352在衬底基板110上的正投影与第三数据线185C在衬底基板110上的正投影至少部分重叠，第三颜色滤光片353在衬底基板110上的正投影与第四数据线185D在衬底基板110上的正投影至少部分重叠。
在一些示例中，如图11A所示，显示基板100还包括：第四过孔264，位于层间绝缘层170之中，第二漏极1842通过第四过孔264与导体化块147相连。导电遮光结构122还包括：第二绝缘部1222，第二绝缘部1222在衬底基 板110上的正投影与第四过孔264在衬底基板110上的正投影至少部分重叠。上述的第二绝缘部是导电遮光结构的一部分，并且相对于导电遮光结构的其他部分，第二绝缘部与其他部分绝缘。在该显示基板中，当半导体层本身较薄而导致第二漏极区存在部分缺失的情况下，刻蚀剂从第二漏极区向下刻蚀到第二绝缘部时，由于第二绝缘部与导电遮光结构的其他部分绝缘，即使第二漏极通过第三过孔与第二绝缘部相连，也并不会导致第二漏极与导电遮光结构的其他部分电连接。由此，该显示基板可降低工艺风险，并提升良率。
在一些示例中，如图10A所示，第二绝缘部1222包括第二镂空部1222A，第二镂空部1222A填充有缓冲层130的材料。由此，第二绝缘部1222可通过第二镂空部1222A与导电遮光结构122的其他部分绝缘。需要说明的是，第二绝缘部1222本身可为第二镂空部1222A，也就是说，第二绝缘部1222可为导电遮光结构122被去除的部分。
在一些示例中，如图10B所示，第二镂空部1222A可为第二镂空环，也即第二镂空部可为环状的镂空部。第二镂空环1222A内侧的部分与第二镂空环1222A的外侧均为导电遮光结构122的材料。由此，第二绝缘部1222可通过设置第二镂空环1222A来实现与导电遮光结构122的其他部分绝缘。
在一些示例中，如图10C所示，第二绝缘部1222为氧化部。也就是说，可通过氧化工艺将导电遮光结构122的一部分氧化，以形成上述的第二绝缘部1222。
在一些示例中，如图11A所示，第一过孔261和第四过孔264在衬底基板110上的正投影的形状均为各向异性的图形，且均包括长边。
在一些示例中，如图11A所示，在子像素组390中，第二颜色子像素300B的第一过孔261的长边或延伸方向和第三颜色子像素300C的第一过孔261的长边均沿第一方向延伸；第一颜色子像素300A的第一过孔261的长边和第四颜色子像素300D的第一过孔261的长边均沿第二方向延伸。在第二颜色子像素300B和第三颜色子像素300C的像素驱动电路中，由于电源信号是从第一薄膜晶体管T1的第一源极1821流向第一漏极1841，而第一源极1821到第一漏极1841的方向为第二方向，通过将第二颜色子像素300B的第一过孔261的长边或延伸方向和第三颜色子像素300C的第一过孔261的长边均沿第一方向延伸，可使得第二颜色子像素300B的第一过孔261和第三颜色子像素300C的第一过孔261在第一方向上的尺寸较大，而使得流过的电流有较大的横截面 积，从而可降低接触电阻。
在一些示例中，如图11A所示，在子像素组390中，第二颜色子像素300B的第四过孔264的长边和第三颜色子像素300C的第四过孔264的长边均沿第二方向延伸，第一颜色子像素300A的第四过孔264的长边和第四颜色子像素300D的第四过孔264的长边均沿第一方向延伸。
图12为本公开一实施例提供的另一种显示基板的平面示意图。如图12所示，由于不同颜色的子像素可采用不同宽长比的薄膜晶体管，因此，不同颜色的子像素的第四过孔的位置可以不同。例如，如图12所示，在子像素组390中，第一颜色子像素300A的第四过孔264的中心、第二颜色子像素300B的第四过孔264的中心、第三颜色子像素300C的第四过孔264的中心和第四颜色子像素300D的第四过孔264的中心在第二方向上错位设置；第一颜色子像素300A的第四过孔264的中心和第四颜色子像素300D的第四过孔264的中心位于第一虚拟直线401上，第二颜色子像素300B的第四过孔264的中心和第三颜色子像素300C的第四过孔264的中心位于与第一虚拟直线平行的第二虚拟直线402上。由此，可以防止环境光在经过第一颜色子像素300A的第四过孔、第二颜色子像素300B的第四过孔、第三颜色子像素300C的第四过孔和第四颜色子像素300D的第四过孔的反射而形成的规则的亮线，从而可提高显示质量。
图13为本公开一实施例提供的一种显示基板中第一漏极的剖面示意图。如图13所示，导电层180或者第一漏极1841包括沿垂直于衬底基板110的方向上层叠的第一子金属层1841A和第二子金属层1841B；第一子金属层1841A的材料为铜，第二子金属层1841B的材料为钼钛合金。
本公开一实施例还提供一种显示装置。图14为本公开一实施例提供的一种显示装置的示意图。如图14所示，该显示装置500包括上述的显示基板100。由此，该显示装置具有与其包括的显示基板的技术效果对应的有益技术效果。例如，在该显示装置中，导电结构通过第一接触孔与第一凹陷部连接。由于第一凹陷部凹入导电遮光结构，第一凹陷部靠近导电层的表面的面积大于第一凹陷部在衬底基板上正投影的面积。由此，导电结构，例如第一漏极与导电遮光结构的接触面积增加，接触更加充分，从可降低接触电阻，提高导电结构和导电遮光结构的电连接效果并且可有效地提高由该导电结构形成的电容的充放电效率。
例如，该显示装置可为电视、平板电脑、笔记本电脑、电子画框、导航仪、智能手机等电子产品。
本公开一实施例还提供一种显示基板的制作方法。图15为本公开一实施例提供的一种显示基板的制作方法的流程图。如图15所示，该显示基板的制作方法包括以下步骤S101-S107。
步骤S101：在衬底基板上形成导电遮光材料层。
例如，衬底基板可采用玻璃和基板等无机材料制作的透明基板。另外，衬底基板也可采用聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯等有机材料制作的透明基板。
例如，衬底基板可采用柔性基板，例如聚酰亚胺基板。当然，本公开实施例包括但不限于此，衬底基板也可采用刚性基板。
例如，导电遮光材料层的材料可选自钼和钛中的一种或多种。当然，本公开实施例包括但不限于此，导电遮光材料层的材料还可采用其他材料制作。
例如，可采用溅射工艺、气相沉积工艺等成膜工艺在衬底基板上形成导电遮光材料层。
步骤S102：对导电遮光材料层进行图案化以形成导电遮光结构。
例如，对导电遮光材料层进行图案化的工艺可包括曝光、显影、刻蚀工艺等。
例如，可先在导电遮光材料层上涂覆光刻胶，然后通过曝光和显影工艺在导电遮光材料层上形成光刻胶图案，然后利用该光刻胶图案对导电遮光材料进行刻蚀，最后剥离光刻胶图案，从而形成导电遮光结构。
步骤S103：在导电遮光结构远离衬底基板的一侧形成缓冲层。
例如，缓冲层的材料可为氮化硅、氧化硅和氮氧化硅中的至少之一。
例如，缓冲层的厚度范围可为380-420纳米。当然，本公开实施例包括但不限于此，缓冲层的厚度可根据实际需求进行设置。
步骤S104：在缓冲层远离导电遮光结构的一侧形成半导体层。
例如，半导体层的材料可为氧化物半导体，例如氧化铟镓锌(IGZO)。
例如，可采用气相沉积工艺在缓冲层远离导电遮光结构的一侧形成半导体层。当然，本公开实施例包括但不限于此，也可采用其他合适的工艺来形成半导体层。
例如，半导体层的厚度范围可为35-45纳米，例如40纳米。当然，本公 开实施例包括但不限于此，半导体层的厚度可根据实际需求进行设置。
步骤S105：在半导体层远离缓冲层的一侧形成层间绝缘层。
例如，层间绝缘层的材料可选氮化硅、氧化硅和氮氧化硅中的至少之一。当然，本公开实施例包括但不限于此，层间绝缘层的材料也可为其他材料。需要说明的是，层间绝缘层的材料与缓冲层的材料可相同或不同，即使层间绝缘层和缓冲层的材料相同，层间绝缘层和缓冲层可采用不同的工艺温度，从而形成膜层致密度也不同，从而导致层间绝缘层和缓冲层被刻蚀的坡度角不同。
例如，层间绝缘层的厚度范围可为350-600纳米，例如400纳米。当然，本公开实施例包括但不限于此，层间绝缘层的厚度可根据实际需求进行设置。
步骤S106：在层间绝缘层和缓冲层中形成第一接触孔。
例如，可采用刻蚀工艺(例如湿刻工艺)在层间绝缘层和缓冲层中形成第一接触孔。
步骤S107：在层间绝缘层远离半导体层的一侧形成导电层，导电层包括导电结构，例如第一漏极，导电遮光结构包括第一主体部和第一凹陷部，第一凹陷部在垂直于衬底基板的方向上的平均厚度小于第一主体部在垂直于衬底基板的方向上的平均厚度，第一接触孔穿过层间绝缘层和缓冲层，导电结构通过第一接触孔与第一凹陷部连接，第一凹陷部靠近导电层的表面的面积大于第一凹陷部在衬底基板上正投影的面积。
在本公开实施例提供的显示基板的制作方法中，导电遮光结构包括第一主体部和第一凹陷部，第一漏极通过第一接触孔与第一凹陷部连接。由于第一凹陷部凹入导电遮光结构，第一凹陷部靠近第一漏极的表面的面积大于第一凹陷部在衬底基板上正投影的面积。由此，该显示基板制作方法制作的显示基板可使得第一漏极与导电遮光结构的接触面积增加，接触更加充分，从可降低接触电阻，提高第一漏极和导电遮光结构的电连接效果并且可有效地提高由该导电结构形成的电容的充放电效率。
例如，导电层的材料可选自铜、钼和钛中的一种或多种。当然，本公开实施例包括但不限于此，导电层还可采用其他材料制作。
在一些示例中，所述导电遮光结构在垂直于衬底基板的方向上的厚度范围为90-120纳米，所述导电层在垂直于衬底基板的方向上的厚度范围为200-600纳米。
在一些示例中，在该显示基板的制作方法中，在层间绝缘层和缓冲层中形 成第一接触孔包括：在缓冲层中形成第一缓冲部和第二缓冲部，第一缓冲部远离衬底基板的一侧与导电层接触设置，且第一缓冲部靠近衬底基板的一侧与导电遮光结构接触设置，第二缓冲部远离衬底基板的一侧与层间绝缘层接触设置，且第二缓冲部靠近衬底基板的一侧与导电遮光结构接触设置。由此，在第一接触孔中沉积上述的导电结构时，第一缓冲部可起到支撑部分导电结构的作用，防止导电结构因落差过大或者坡度角过大而导致的断线不良。从而，该显示基板具有较高的良率。
在一些示例中，第一接触孔包括侧壁，侧壁至少包括：第一子侧壁，位于层间绝缘层；以及第二子侧壁，位于缓冲层，其中，第一子侧壁与衬底基板的夹角构成第一坡度角，第二子侧壁与衬底基板的夹角构成第二坡度角，第一坡度角小于第二坡度角；第二子侧壁与第一缓冲部的接触部位于第一缓冲部和第二缓冲部之间。
在一些示例中，第一接触孔的侧壁还包括：第三子侧壁，位于第一缓冲部，第三子侧壁与衬底基板的夹角构成第三坡度角，第一坡度角、第二坡度角和第三坡度角不同。上述的第一接触孔的侧壁的具体描述可参见图6A和图6B的相关描述，在此不再赘述。
在一些示例中，该显示基板的制作方法还包括：在导电层，例如源漏金属层，远离层间绝缘层的一侧形成平坦层，平坦层包括阳极孔；以及在平坦层远离导电层的一侧形成阳极层以在衬底基板上形成多个子像素，各子像素包括阳极，阳极包括出光部、驱动部和将出光部和驱动部相连的延伸部，驱动部至少部分位于阳极孔之内；在至少一个子像素中，第一接触孔在衬底基板上正投影与驱动部在衬底基板上正投影至少部分交叠，显示基板还包括：电源线，位于导电层；以及感测线，位于导电层；电源线和感测线在第一方向上排列，电源线和感测线均沿与第一方向相交的第二方向延伸；多个子像素包括第一子像素对和第二子像素对，第一子像素对包括两个子像素，分别位于电源线的两侧，第二子像素对包括两个子像素，分别位于感测线的两侧；第一子像素对和第二子像素对在与第一方向上交替排列，在第二子像素对中的两个子像素中，阳极孔与第一凹陷部在衬底基板上正投影存在第一交叠区域，第一交叠区域的面积小于第一接触孔在衬底基板上正投影的面积。由此，在第二子像素对中的两个子像素中，阳极孔与第一凹陷部存在第一交叠区域，由此，当第一凹陷部因减薄而导致遮光性能下降时，阳极孔位置处的阳极存在弯曲的界面，从而可将光 线进行汇聚，从而避免透过第一凹陷部的光线影响正常显示。
在一些示例中，阳极在阳极孔的边缘位置处还包括下凹结构，下凹结构的凹陷方向朝向导电遮光结构。由此，当第一凹陷部因减薄而导致遮光性能下降时，由于下凹结构存在至少两个倾斜面，从而可反射透过第一凹陷部的光线。另外，由于下凹结构本身属于微结构，该下凹结构还可对透过第一凹陷部的光线进行散射，从而进一步避免透过第一凹陷部的光线影响正常显示。需要说明的是，上述的阳极孔的边缘位置是指阳极孔与平坦层远离半导体层的表面的交界处。
在一些示例中，导电层还包括第一源极和第一漏极，导电结构为第一漏极。
在一些示例中，导电层还包括第一源极，半导体层包括第一有源层，第一有源层包括第一沟道区和位于第一沟道区两侧的第一源极区和第一漏极区，该显示基板的制作方法还包括：在层间绝缘层和缓冲层中形成第一接触孔的同时在层间绝缘层形成第一过孔和第二过孔，第一源极通过第一过孔与第一源极区相连，第一漏极通过第二过孔与第一漏极区相连。
在一些示例中，采用同一刻蚀工艺同时图案化层间绝缘层和缓冲层以形成第一过孔和第一接触孔。在这种情况下，即使第一接触孔的底部尺寸较小，但是由于第一凹陷部靠近第一漏极的表面的面积大于第一凹陷部在衬底基板上正投影的面积，该显示基板制作方法制作的显示基板可使得第一漏极与导电遮光结构的接触面积增加，接触更加充分，从可降低接触电阻，提高第一漏极和导电遮光结构的电连接效果。
在一些示例中，也采用半色调掩膜工艺图案化层间绝缘层和缓冲层以形成第一过孔和第一接触孔。
例如，采用半色调掩膜工艺图案化层间绝缘层和缓冲层以形成第一过孔和第一接触孔包括：在层间绝缘层远离衬底基板的一侧形成第一光刻胶；采用第一半色调掩膜对第一光刻胶进行曝光和显影，以形成包括第一光刻胶完全去除部、第一光刻胶部分去除部和第一光刻胶保留部的第一光刻胶图案；以第一光刻胶图案为掩膜对层间绝缘层进行刻蚀，以去除第一光刻胶完全去除部对应的层间绝缘层；对第一光刻胶图案进行灰化处理，去除第一光刻胶部分去除部并减薄第一光刻胶保留部以形成第二光刻胶图案；以及以第二光刻胶图案为掩膜对缓冲层进行刻蚀，第一接触孔在衬底基板上的正投影与第一光刻胶完全去除部在衬底基板上的正投影重叠，第一过孔在衬底基板上的正投影与第一光刻胶 部分去除部在衬底基板上的正投影重叠。需要说明的是，上述的重叠包括完全重叠的情况，也包括大致重叠的情况(重叠程度大于80％)。
在一些示例中，导电遮光结构还包括第一绝缘部，第一绝缘部在衬底基板上的正投影与第一过孔在衬底基板上的正投影至少部分重叠，第一绝缘部在衬底基板上的正投影与第一源极区在衬底基板上的正投影至少部分重叠。上述的第一绝缘部是导电遮光结构的一部分，并且相对于导电遮光结构的其他部分，第一绝缘部与其他部分绝缘。当半导体层本身较薄而导致第一源极区存在部分缺失的情况下，刻蚀剂从第一源极区向下刻蚀到第一绝缘部时，由于第一绝缘部与导电遮光结构的其他部分绝缘，即使第一源极通过第一过孔与第一绝缘部相连，也并不会导致第一源极与导电遮光结构的其他部分电连接。由此，该显示基板可降低工艺风险，并提升良率。
例如，如图10A所示，第一绝缘部1221包括第一镂空部1221A，第一镂空部1221A填充有缓冲层130的材料。由此，第一绝缘部1221可通过第一镂空部1221A与导电遮光结构122的其他部分绝缘。需要说明的是，第一绝缘部1221本身可为第一镂空部1221A，也就是说，第一绝缘部1221可为导电遮光结构122被去除的部分。
例如，如图10B所示，第一镂空部1221A可为第一镂空环，也即第一镂空部可为环状的镂空部。第一镂空环1221A内侧的部分与第一镂空环1221A的外侧均为导电遮光结构122的材料。由此，第一绝缘部1221可通过设置第一镂空环1221A来实现与导电遮光结构122的其他部分绝缘。
例如，如图10C所示，第一绝缘部1221为氧化部。也就是说，可通过氧化工艺将导电遮光结构122的一部分氧化，以形成上述的第一绝缘部1221。
在一些示例中，当第一绝缘部为图10A和图10B所示的第一绝缘部1221时，对导电遮光材料层进行图案化以形成导电遮光结构包括：通过同一图案化工艺对导电遮光材料层进行图案化以形成第一主体部、第一凹陷部和第一镂空部。也就是说，在同一图案化工艺中形成第一凹陷部和第一镂空部，从而可减小掩膜工艺，进而降低成本。
在一些示例中，对导电遮光材料层进行图案化以形成导电遮光结构包括：在所述导电遮光结构远离所述衬底基板的一侧形成光刻胶；采用第二半色调掩膜对所述光刻胶进行曝光和显影，以形成包括第二光刻胶完全去除部、第二光刻胶部分去除部和第二光刻胶保留部的第三光刻胶图案；以所述第三光刻胶图 案为掩膜对所述导电遮光材料层进行刻蚀，以去除所述第二光刻胶完全去除部对应的导电遮光材料层；对所述第三光刻胶图案进行灰化处理，去除所述第二光刻胶部分去除部并减薄所述第二光刻胶保留部以形成第四光刻胶图案；以及以所述第四光刻胶图案为掩膜对所述导电遮光材料层进行刻蚀，所述第一主体部在所述衬底基板上的正投影与所述第二光刻胶保留部在所述衬底基板上的正投影重叠，所述第一凹陷部在所述衬底基板上的正投影与所述第二光刻胶部分去除部在所述衬底基板上的正投影重叠。由此，该制作方法可通过半色调掩膜来实现在同一掩膜工艺中形成第一凹陷部和第一镂空部，从而可减小掩膜工艺，进而降低成本。需要说明的是，上述的重叠包括完全重叠的情况，也包括大致重叠的情况(重叠程度大于80％)。
在一些示例中，第一凹陷部包括第一边缘部，在从第一凹陷部的边缘到第一凹陷部的中心的方向上，至少第一凹陷部靠近所述边缘的部分，例如第一边缘部，在垂直于衬底基板的方向上的厚度连续逐渐减小。由于第一凹陷部在垂直于衬底基板的方向上的平均厚度小于第一主体部在垂直于衬底基板的方向上的平均厚度，因此第一凹陷部的遮光性能可能会受到影响。由于第一凹陷部在垂直于衬底基板的方向上的厚度连续逐渐减小，即时有光线可以穿透第一凹陷部，第一凹陷部也可起到光线汇聚的作用，从而防止环境光穿透整个显示基板，并避免环境光影响显示基板的正常显示。
在一些示例中，在垂直于衬底基板方向上，至少第一凹陷部靠近所述边缘的部分，即第一边缘部靠近导电层的坡度角是连续变化的。由此，即时有光线可以穿透第一凹陷部，第一凹陷部也可起到光线汇聚的作用，从而防止光线穿透整个显示基板而被用户观察到。
在一些示例中，第一凹陷部靠近第一漏极的表面为连续弧面，或至少一段连续弧面和至少一段平面组合而成的组合面。连续弧面，或至少一段连续弧面和至少一段平面组合而成的组合面可起到光线汇聚的作用，由此，即时有光线可以穿透第一凹陷部，第一凹陷部也可防止光线穿透整个显示基板而被用户观察到。
在一些示例中，第一接触孔在衬底基板上的正投影与第一凹陷部在衬底基板上的正投影至少部分重叠。由此，导电层中的第一漏极可通过第一接触孔与第一凹陷部相连接。
在一些示例中，第一边缘部靠近导电层的表面上的第四坡度角α满足下列 公式：
0<α<k*H/Lmax
其中，Lmax为第一凹陷部在衬底基板上的正投影的最大孔径，H为第一主体部的平均厚度，k为大于1小于等于2的常数。
在一些示例中，k＝2，第四坡度角的范围为1-π/18。
例如，第一凹陷部在衬底基板上的正投影在平行于衬底基板的方向上的尺寸范围为5-10微米。
在一些示例中，在所述层间绝缘层和所述缓冲层中形成第一接触孔包括：在所述缓冲层中形成第一缓冲部和第二缓冲部，所述第一缓冲部位于所述第一接触孔之内，且与所述导电遮光结构接触设置，第二缓冲部，位于所述第一缓冲部远离所述第一凹陷部的中心的一侧。
在一些示例中，在层间绝缘层远离半导体层的一侧形成导电层可包括：在层间绝缘层远离半导体层的一侧形成源漏金属材料层，例如可采用沉积工艺在层间绝缘层远离半导体层的一侧形成源漏金属材料层；然后，采用掩膜板对形成源漏金属材料层进行刻蚀，以形成包括上述的第一漏极的导电层。
在一些示例中，该显示基板的制作方法还包括：在导电层远离衬底基板的一侧形成钝化层；在钝化层远离导电层的一侧形成彩膜层；在彩膜层远离钝化层的一侧形成平坦层；在平坦层远离彩膜层的一侧形成阳极层。
例如，平坦层的材料可采用有机树脂等有机材料。当然，本公开实施例包括但不限于此。
例如，各子像素还包括位于阳极层的阳极。显示基板还包括位于钝化层之中的第三过孔，阳极通过第三过孔与第一漏极相连。由此，该显示基板可通过第一薄膜晶体管将驱动电流施加在阳极上，以驱动该阳极对应的发光层进行发光显示。
在一些示例中，该显示基板的制作方法还包括：在阳极层远离彩膜层的一侧形成像素限定层。像素限定层可包括多个开口，多个开口与多个子像素的阳极一一对应设置，各开口部分暴露对应的阳极。
在一些示例中，该显示基板的制作方法还包括：在像素限定层远离阳极层的一侧形成发光层。发光层通过上述的多个开口与多个子像素的阳极被暴露的部分接触。
在一些示例中，该显示基板的制作方法还包括：在发光层远离阳极的一侧 形成阴极。由此，阳极、发光层和阴极可构成一个发光单元。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (96)

  1. 一种显示基板，包括衬底基板和位于所述衬底基板上的多个子像素，其中，各所述子像素包括：
    导电遮光结构，位于所述衬底基板上；
    缓冲层，位于所述导电遮光结构远离所述衬底基板的一侧；
    半导体层，位于所述缓冲层远离所述导电遮光结构的一侧；
    层间绝缘层，位于所述半导体层远离所述缓冲层的一侧；以及
    导电层，位于所述层间绝缘层远离所述半导体层的一侧，且包括导电结构，其中，所述导电遮光结构包括第一主体部和第一凹陷部，所述显示基板还包括第一接触孔，所述第一接触孔穿过所述层间绝缘层和所述缓冲层，所述导电结构通过所述第一接触孔与所述第一凹陷部电连接，所述第一凹陷部靠近所述导电层的表面的面积大于所述第一凹陷部在所述衬底基板上正投影的面积，所述第一凹陷部在垂直于衬底基板的方向上的平均厚度小于所述第一主体部在垂直于衬底基板的方向上的平均厚度。
  2. 根据权利要求1所述的显示基板，其中，所述缓冲层包括：
    第一缓冲部，所述第一缓冲部远离所述衬底基板的一侧与所述导电层接触设置，所述第一缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置；以及
    第二缓冲部，所述第二缓冲部远离所述衬底基板的一侧与所述层间绝缘层接触设置，所述第二缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置。
  3. 根据权利要求2所述的显示基板，其中，所述第一接触孔包括侧壁，所述侧壁至少包括：
    第一子侧壁，位于所述层间绝缘层；以及
    第二子侧壁，位于所述缓冲层，
    其中，所述第一子侧壁与所述衬底基板的夹角构成第一坡度角，所述第二子侧壁与所述衬底基板的夹角构成第二坡度角，所述第一坡度角小于所述第二坡度角；所述第二子侧壁与所述第一缓冲部的接触部位于所述第一缓冲部和所述第二缓冲部之间。
  4. 根据权利要求3所述的显示基板，其中，所述第一接触孔的所述侧壁 还包括：
    第三子侧壁，位于所述第一缓冲部，
    其中，所述第三子侧壁与所述衬底基板的夹角构成第三坡度角，所述第一坡度角、所述第二坡度角和所述第三坡度角不同。
  5. 根据权利要求4所述的显示基板，其中，沿所述第一接触孔的径向，所述第一缓冲部的长度与所述第一缓冲部的平均厚度之比大于所述第一子侧壁的在所述衬底基板上的投影长度与所述层间绝缘层的平均厚度之比。
  6. 根据权利要求4所述的显示基板，其中，沿所述第一接触孔径向，所述第一子侧壁的在所述衬底基板上的投影长度与所述层间绝缘层的平均厚度之比大于所述第二子侧壁的在所述衬底基板上的投影长度与所述缓冲层的平均厚度之比。
  7. 根据权利要求4所述的显示基板，其中，所述第二坡度角大于所述第三坡度角，所述第一坡度角大于所述第三坡度角。
  8. 根据权利要求7所述的显示基板，其中，所述第一凹陷部在所述衬底基板上的正投影在平行于所述衬底基板的方向上的尺寸L满足下列公式：
    2(Acotβ+Bcotγ+Ccotθ)<L<D
    其中，A为所述第一缓冲部的最大厚度，B为所述第二缓冲部的最大厚度，C为所述层间绝缘层的最大厚度，β为所述第一坡度角，γ为所述第二坡度角，θ为所述第三坡度角，D为所述第一接触孔在所述衬底基板上的正投影在平行于所述衬底基板的方向上的最大尺寸。
  9. 根据权利要求1-8中任一项所述的显示基板，其中，所述第一凹陷部包括第一边缘部，在从所述第一凹陷部的边缘到所述第一凹陷部的中心的方向上，所述第一边缘部在垂直于衬底基板的方向上的厚度逐渐减小。
  10. 根据权利要求1-9中任一项所述的显示基板，其中，所述第一凹陷部包括第一边缘部，在垂直于所述衬底基板方向上，所述第一边缘部靠近所述导电层的表面的第四坡度角是连续变化的。
  11. 根据权利要求1-10中任一项所述的显示基板，其中，所述第一凹陷部靠近所述导电结构的表面为连续弧面，或至少一段连续弧面和至少一段平面组合而成的组合面。
  12. 根据权利要求1-11中任一项所述的显示基板，其中，所述第一凹陷部包括第一边缘部，所述第一边缘部靠近所述导电层的表面上的第四坡度角α 满足下列公式：
    0<α<k*H/Lmax
    其中，Lmax为所述第一凹陷部在所述衬底基板上的正投影的最大孔径，H为所述第一主体部的平均厚度，k为大于1小于等于2的常数。
  13. 根据权利要求12所述的显示基板，其中，k＝2，所述第四坡度角的范围为1-π/18。
  14. 根据权利要求4-8中任一项所述的显示基板，其中，所述第一凹陷部包括第一边缘部，所述第一边缘部靠近所述导电层的表面上的第四坡度角α小于所述第三子侧壁的所述第三坡度角，且满足：
    (Acotβ+Bcotγ+Ccotθ+L/2tanα)≤D/2，
    其中，A为所述第一缓冲部的最大厚度，B为所述第二缓冲部的最大厚度，C为所述层间绝缘层的最大厚度，β为所述第一坡度角，γ为所述第二坡度角，θ为所述第三坡度角，D为所述第一接触孔在所述衬底基板上的正投影在平行于所述衬底基板的方向上的最大尺寸。
  15. 根据权利要求14所述的显示基板，还包括：
    平坦层，位于所述导电层远离所述半导体层的一侧，且所述平坦层包括阳极孔；以及
    阳极，位于所述平坦层远离所述半导体层的一侧，且包括出光部、驱动部和将所述出光部和所述驱动部相连的延伸部，所述驱动部至少部分位于所述阳极孔之内，
    其中，在至少一个所述子像素中，所述第一接触孔在所述衬底基板上正投影与所述驱动部在所述衬底基板上正投影至少部分交叠，
    所述显示基板还包括：电源线，位于所述导电层；以及感测线，位于所述导电层；所述电源线和所述感测线在第一方向上排列，所述电源线和所述感测线均沿与所述第一方向相交的第二方向延伸；
    所述多个子像素包括第一子像素对和第二子像素对，所述第一子像素对包括两个所述子像素，分别位于所述电源线的两侧，所述第二子像素对包括两个所述子像素，分别位于所述感测线的两侧；所述第一子像素对和所述第二子像素对在所述第一方向上交替排列，
    在所述第二子像素对中的两个所述子像素中，所述阳极孔与所述第一凹陷部在所述衬底基板上正投影存在第一交叠区域，所述第一交叠区域的面积小于 所述第一接触孔在所述衬底基板上正投影的面积。
  16. 根据权利要求15所述的显示基板，其中，所述阳极在所述阳极孔的边缘位置处还包括下凹结构，所述下凹结构的凹陷方向朝向所述导电遮光结构。
  17. 根据权利要求1-16中任一项所述的显示基板，其中，所述第一凹陷部在所述衬底基板上的正投影在平行于所述衬底基板的方向上的尺寸范围为5-10微米。
  18. 根据权利要求1-17中任一项所述的显示基板，其中，所述第一接触孔在所述衬底基板上的正投影与所述第一凹陷部在所述衬底基板上的正投影至少部分重叠。
  19. 根据权利要求1-18中任一项所述的显示基板，其中，各所述子像素包括像素驱动电路，所述像素驱动电路包括第一薄膜晶体管，所述导电结构为所述第一薄膜晶体管的第一漏极。
  20. 根据权利要求19所述的显示基板，其中，所述第一薄膜晶体管还包括：
    第一有源层，位于所述半导体层，且包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区；
    第一源极，位于所述导电层，
    其中，所述显示基板还包括第一过孔和第二过孔，所述第一过孔和所述第二过孔位于所述层间绝缘层之中，所述第一源极通过所述第一过孔与所述第一源极区相连，所述第一漏极通过所述第二过孔与所述第一漏极区相连。
  21. 根据权利要求20所述的显示基板，其中，所述导电遮光结构还包括：
    第一绝缘部，所述第一绝缘部在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影至少部分重叠，所述第一绝缘部在所述衬底基板上的正投影与所述第一源极区在所述衬底基板上的正投影至少部分重叠。
  22. 根据权利要求21所述的显示基板，其中，所述第一绝缘部包括第一镂空部，所述第一镂空部填充有所述缓冲层的材料。
  23. 根据权利要求22所述的显示基板，其中，所述第一镂空部包括第一镂空环，所述第一镂空环内侧的部分与所述第一镂空环的外侧均为所述导电遮光结构的材料。
  24. 根据权利要求23所述的显示基板，其中，所述第一绝缘部为氧化部。
  25. 根据权利要求15所述的显示基板，还包括：
    栅极绝缘层，位于所述半导体层和所述层间绝缘层之间；
    栅极层，位于所述栅极绝缘层和所述层间绝缘层之间；
    钝化层，位于所述导电层远离所述衬底基板的一侧；
    彩膜层，位于所述钝化层远离所述导电层的一侧，且包括至少三种不同颜色的滤光片；以及
    阳极层，
    其中，所述平坦层位于所述彩膜层远离所述钝化层的一侧，所述阳极层位于所述平坦层远离所述彩膜层的一侧，所述阳极位于所述阳极层。
  26. 根据权利要求25所述的显示基板，还包括：
    电源连接线，与所述导电遮光结构同层设置，
    其中，所述电源连接线包括第二主体部和多个电源凹陷部，所述电源凹陷部在垂直于所述衬底基板的方向上的平均厚度均小于所述第二主体部在垂直于所述衬底基板的方向上的平均厚度，所述电源凹陷部靠近所述导电层的表面的面积大于所述电源凹陷部在所述衬底基板上正投影的面积。
  27. 根据权利要求26所述的显示基板，其中，所述多个电源凹陷部中的至少之一在所述衬底基板上的正投影与所述彩膜层中的所述滤光片在所述衬底基板上的正投影至少部分重叠。
  28. 根据权利要求27所述的显示基板，其中，所述电源凹陷部包括第二边缘部，在从所述电源凹陷部的边缘到所述电源凹陷部的中心的方向上，所述第二边缘部在垂直于衬底基板的方向上的厚度连续逐渐减小。
  29. 根据权利要求27所述的显示基板，其中，所述电源凹陷部包括第二边缘部，在垂直于所述衬底基板方向上，所述第二边缘部靠近所述导电层的表面的第五坡度角是连续变化的。
  30. 根据权利要求27所述的显示基板，其中，所述显示基板还包括电源接触孔，所述电源接触孔位于所述层间绝缘层和所述缓冲层，所述电源接触孔在所述衬底基板上的正投影与所述电源凹陷部在所述衬底基板上的正投影至少部分交叠。
  31. 根据权利要求30所述的显示基板，其中，所述缓冲层包括：第三缓冲部，位于所述电源接触孔之内，所述第三缓冲部远离所述衬底基板的一侧与所述电源连接线接触设置，且所述第三缓冲部靠近所述衬底基板的一侧与所述 导电遮光结构接触设置；以及第四缓冲部，位于所述第三缓冲部远离所述电源凹陷部的中心的一侧，所述电源接触孔的侧壁包括：
    第四子侧壁，位于所述层间绝缘层；以及
    第五子侧壁，位于所述第四缓冲部，其中，所述第四子侧壁与所述衬底基板的夹角构成第六坡度角，所述第五子侧壁与所述衬底基板的夹角构成第七坡度角，所述第六坡度角小于所述第七坡度角；所述第五子侧壁与所述第三缓冲部的接触部位于所述第三缓冲部和所述第四缓冲部之间。
  32. 根据权利要求31所述的显示基板，其中，所述电源接触孔的侧壁还包括：
    第六子侧壁，位于所述第三缓冲部，
    其中，所述第六子侧壁与所述衬底基板的夹角构成第八坡度角，所述第六坡度角、所述第七坡度角和所述第八坡度角不同。
  33. 根据权利要求32所述的显示基板，其中，所述第七坡度角小于所述第二坡度角。
  34. 根据权利要求32所述的显示基板，其中，所述第八坡度角大于所述第三坡度角。
  35. 根据权利要求25所述的显示基板，还包括：
    感测连接线，与所述导电遮光结构同层设置，
    其中，所述感测连接线包括第三主体部和多个感测凹陷部，所述感测凹陷部在垂直于所述衬底基板的方向上的平均厚度均小于所述第三主体部在垂直于所述衬底基板的方向上的平均厚度，所述感测凹陷部靠近所述导电层的表面的面积大于所述感测凹陷部在所述衬底基板上正投影的面积。
  36. 根据权利要求35所述的显示基板，其中，所述多个感测凹陷部中的至少之一在所述衬底基板上的正投影与所述彩膜层中的所述滤光片在所述衬底基板上的正投影至少部分重叠。
  37. 根据权利要求36所述的显示基板，其中，所述感测凹陷部包括第三边缘部，在从所述感测凹陷部的边缘到所述感测凹陷部的中心的方向上，所述第三边缘部在垂直于衬底基板的方向上的厚度连续逐渐减小。
  38. 根据权利要求36所述的显示基板，其中，所述感测凹陷部包括第三边缘部，在垂直于所述衬底基板方向上，所述第三边缘部靠近所述导电层的表面的第九坡度角是连续变化的。
  39. 根据权利要求36所述的显示基板，其中，所述显示基板还包括感测接触孔，所述感测接触孔位于所述层间绝缘层和所述缓冲层，所述感测接触孔在所述衬底基板上的正投影与所述感测凹陷部在所述衬底基板上的正投影至少部分交叠。
  40. 根据权利要求39所述的显示基板，其中，所述缓冲层包括：第五缓冲部，位于所述感测接触孔之内，所述第五缓冲部远离所述衬底基板的一侧与所述感测连接线接触设置，且所述第五缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置；以及第六缓冲部，位于所述第五缓冲部远离所述感测凹陷部的中心的一侧，所述感测接触孔的侧壁包括：
    第七子侧壁，位于所述层间绝缘层；以及
    第八子侧壁，位于所述第六缓冲部；
    其中，所述第七子侧壁与所述衬底基板的夹角构成第十坡度角，所述第八子侧壁与所述衬底基板的夹角构成第十一坡度角，所述第十坡度角小于所述第十一坡度角；所述第八子侧壁与所述第五缓冲部的接触部位于所述第五缓冲部和所述第六缓冲部之间。
  41. 根据权利要求40所述的显示基板，其中，所述缓冲层还包括：
    第九子侧壁，位于所述第五缓冲部，
    其中，所述第九子侧壁与所述衬底基板的夹角构成第十二坡度角，所述第十坡度角、所述第十一坡度角和所述第十二坡度角不同。
  42. 根据权利要求41所述的显示基板，其中，所述第十一坡度角小于所述第二坡度角。
  43. 根据权利要求41所述的显示基板，其中，所述第十二坡度角大于所述第三坡度角。
  44. 根据权利要求25所述的显示基板，其中，各所述子像素包括驱动区和出光区，所述导电遮光结构位于所述驱动区，所述阳极的所述驱动部位于所述驱动区，所述阳极的出光部位于所述出光区。
  45. 根据权利要求44所述的显示基板，还包括：
    第一栅线，位于所述栅极层，且沿所述第一方向延伸；
    第二栅线，位于所述栅极层，且沿所述第一方向延伸；以及
    数据线，位于所述导电层，且沿所述第二方向延伸，
    其中，所述电源线沿所述第二方向延伸，所述感测线沿所述第二方向延伸，
    所述多个子像素沿所述第一方向和所述第二方向阵列设置以形成沿所述第二方向排列的多个子像素行和沿所述第一方向排列的多个子像素列，
    在各所述子像素行中，所述第一栅线位于所述驱动区和所述出光区之间，所述第二栅线位于相邻的两个所述子像素行之间，所述电源线位于相邻的两个所述子像素列之间，所述感测线位于相邻的两个所述子像素列之间，所述数据线位于相邻的两个所述子像素列之间。
  46. 根据权利要求45所述的显示基板，其中，各所述子像素包括像素驱动电路，所述像素驱动电路包括第一薄膜晶体管，所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极，所述导电结构为所述第一薄膜晶体管的第一漏极，所述像素驱动电路还包括第二薄膜晶体管和第三薄膜晶体管，所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极，所述第三薄膜晶体管包括第三栅极、第三源极和第三漏极，所述半导体层还包括导体化块，
    所述第一薄膜晶体管的所述第一源极与所述电源线相连，所述第二薄膜晶体管的所述第二源极与所述数据线相连，所述第二薄膜晶体管的第二栅极与所述第一栅线相连，所述第二薄膜晶体管的所述第二漏极与所述第一薄膜晶体管的所述第一栅极和所述导体化块分别相连，
    所述第三薄膜晶体管的所述第三栅极与所述第二栅线相连，所述第三薄膜晶体管的所述第三源极与所述感测线相连，所述第三薄膜晶体管的所述第三漏极与所述第一薄膜晶体管的所述第一漏极相连，所述导电遮光结构、与所述导电遮光结构相连的所述第一漏极、和位于所述导电遮光结构和所述第一漏极之间的所述导体化块形成存储电容。
  47. 根据权利要求46所述的显示基板，其中，所述第一薄膜晶体管的所述第一源极通过第一连接部与所述电源线相连，所述第二薄膜晶体管的所述第二源极通过第二连接部与所述数据线相连，所述第一连接部与所述电源线同层设置，所述第二连接部与所述数据线同层设置。
  48. 根据权利要求47所述的显示基板，其中，所述第一源极到所述第一漏极的方向与所述第一连接部的延伸方向相交，所述第二源极到所述第二漏极的方向与所述第二连接部的延伸方向相交。
  49. 根据权利要求46所述的显示基板，其中，所述多个子像素至少包括第一颜色子像素、第二颜色子像素、第三颜色子像素和第四颜色子像素，
    在各所述子像素行，所述第一颜色子像素、所述第二颜色子像素、所述第 三颜色子像素和所述第四颜色子像素沿所述第一方向依次排列并形成一个子像素组，所述电源线位于所述子像素组中所述第二颜色子像素和所述第三颜色子像素之间。
  50. 根据权利要求49所述的显示基板，其中，所述显示基板还包括电源连接线，与所述导电遮光结构同层设置。
  51. 根据权利要求50所述的显示基板，其中，所述显示基板还包括第二接触孔、第三接触孔和第四接触孔，所述第二接触孔、所述第三接触孔和所述第四接触孔位于所述层间绝缘层和所述缓冲层，
    在所述子像素组中，所述电源线通过所述第二接触孔与所述电源连接线相连，所述第二颜色子像素的所述第一源极与所述电源线同层相连，所述第三颜色子像素的所述第一源极与所述电源线同层相连，
    所述第一颜色子像素的所述第一源极通过所述第三接触孔与所述电源连接线相连，所述第四颜色子像素的所述第一源极通过所述第四接触孔与所述电源连接线相连。
  52. 根据权利要求51所述的显示基板，其中，所述电源连接线包括第二主体部、第二凹陷部、第三凹陷部和第四凹陷部，所述第二凹陷部在所述衬底基板上的正投影与所述第二接触孔在所述衬底基板上的正投影至少部分重叠，所述第三凹陷部在所述衬底基板上的正投影与所述第三接触孔在所述衬底基板上的正投影至少部分重叠，所述第四凹陷部在所述衬底基板上的正投影与所述第四接触孔在所述衬底基板上的正投影至少部分重叠，
    所述第二凹陷部、所述第三凹陷部和所述第四凹陷部在垂直于所述衬底基板的方向上的厚度均小于所述第二主体部在垂直于所述衬底基板的方向上的厚度，所述第二凹陷部靠近所述电源线的表面的面积大于所述第二凹陷部在所述衬底基板上正投影的面积，所述第三凹陷部远离所述衬底基板的表面的面积大于所述第三凹陷部在所述衬底基板上正投影的面积，所述第四凹陷部远离所述衬底基板的表面的面积大于所述第四凹陷部在所述衬底基板上正投影的面积。
  53. 根据权利要求52所述的显示基板，其中，所述第二凹陷部、所述第三凹陷部和所述第四凹陷部中的至少之一在所述衬底基板上的正投影与所述彩膜层中的所述滤光片在所述衬底基板上的正投影至少部分重叠。
  54. 根据权利要求52所述的显示基板，其中，所述第二颜色子像素包括 第一颜色滤光片，所述第三颜色子像素包括第二颜色滤光片，所述第四颜色子像素包括第三颜色滤光片，
    在所述子像素组中，所述第一颜色滤光片和所述第二颜色滤光片中的至少一个在衬底基板上的正投影与所述第二凹陷部在所述衬底基板上的正投影至少部分重叠，所述第三颜色滤光片在所述衬底基板上的正投影与所述第四凹陷部在所述衬底基板上的正投影至少部分重叠。
  55. 根据权利要求54所述的显示基板，其中，所述感测线位于在第一方向上相邻的两个所述子像素组之间，在第一方向上所述相邻的两个所述子像素组包括第一子像素组和第二子像素组，
    所述显示基板还包括感测连接线、第五接触孔、第六接触孔、第七接触孔、第八接触孔和第九接触孔，所述感测连接线与所述导电遮光结构同层设置，所述第五接触孔、所述第六接触孔、所述第七接触孔、第八接触孔和第九接触孔位于所述层间绝缘层和所述缓冲层，
    在所述相邻的两个所述子像素组中，所述感测线通过所述第五接触孔与所述感测连接线相连，所述第一子像素组中的所述第三颜色子像素的所述第三源极通过所述第六接触孔与所述感测连接线相连，所述第一子像素组中的所述第四颜色子像素的所述第三源极通过所述第七接触孔与所述感测连接线相连，
    所述第一子像素组中的所述第一颜色子像素的所述第三源极通过所述第八接触孔与所述感测连接线相连，所述第二子像素组中的所述第二颜色子像素的所述第三源极通过所述第九接触孔与所述感测连接线相连。
  56. 根据权利要求55所述的显示基板，其中，所述感测连接线包括第三主体部、第五凹陷部、第六凹陷部、第七凹陷部、第八凹陷部和第九凹陷部，所述第五凹陷部在所述衬底基板上的正投影与所述第五接触孔在所述衬底基板上的正投影至少部分重叠，所述第六凹陷部在所述衬底基板上的正投影与所述第六接触孔在所述衬底基板上的正投影至少部分重叠，所述第七凹陷部在所述衬底基板上的正投影与所述第七接触孔在所述衬底基板上的正投影至少部分重叠，所述第八凹陷部在所述衬底基板上的正投影与所述第八接触孔在所述衬底基板上的正投影至少部分重叠，所述第九凹陷部在所述衬底基板上的正投影与所述第九接触孔在所述衬底基板上的正投影至少部分重叠，
    所述第五凹陷部、所述第六凹陷部、所述第七凹陷部、所述第八凹陷部和所述第九凹陷部在垂直于衬底基板的方向上的厚度均小于所述第三主体部在 垂直于衬底基板的方向上的厚度，所述第五凹陷部靠近所述感测线的表面的面积大于所述第五凹陷部在所述衬底基板上正投影的面积，所述第六凹陷部远离所述衬底基板的表面的面积大于所述第六凹陷部在所述衬底基板上正投影的面积，所述第七凹陷部远离所述衬底基板的表面的面积大于所述第七凹陷部在所述衬底基板上正投影的面积，所述第八凹陷部远离所述衬底基板的表面的面积大于所述第八凹陷部在所述衬底基板上正投影的面积，所述第九凹陷部远离所述衬底基板的表面的面积大于所述第九凹陷部在所述衬底基板上正投影的面积。
  57. 根据权利要求56所述的显示基板，其中，所述第五凹陷部、所述第六凹陷部、所述第七凹陷部、所述第八凹陷部和所述第九凹陷部中的至少之一在所述衬底基板上的正投影与所述彩膜层中的所述滤光片在所述衬底基板上的正投影至少部分重叠。
  58. 根据权利要求56所述的显示基板，其中，在所述第二方向上，所述感测连接线位于所述第二栅线远离所述第一栅线的一侧，所述第一子像素组中的所述第二颜色滤光片在所述衬底基板上的正投影与在所述第二方向上相邻的所述第一子像素组的所述第六凹陷部在所述衬底基板上的正投影至少部分重叠，所述第一子像素组中的所述第三颜色滤光片在所述衬底基板上的正投影与在所述第二方向上相邻的所述第七凹陷部在所述衬底基板上的正投影至少部分重叠，所述第二子像素组中的所述第一颜色滤光片在所述衬底基板上的正投影与在所述第二方向上相邻的所述第九凹陷部在所述衬底基板上的正投影至少部分重叠。
  59. 根据权利要求58所述的显示基板，其中，在所述子像素组中，所述第一颜色滤光片在所述衬底基板上的正投影与所述电源连接线在所述衬底基板上的正投影至少部分重叠，所述第二颜色滤光片在所述衬底基板上的正投影分别与所述电源连接线在所述衬底基板上的正投影和所述第一栅线在所述衬底基板上的正投影至少部分重叠，所述第三颜色滤光片在所述衬底基板上的正投影与所述电源连接线在所述衬底基板上的正投影至少部分重叠。
  60. 根据权利要求58所述的显示基板，其中，在所述子像素组中，所述第一颜色滤光片在所述衬底基板上的正投影与所述感测连接线在所述衬底基板上的正投影至少部分重叠，所述第二颜色滤光片在所述衬底基板上的正投影分别与所述感测连接线在所述衬底基板上的正投影至少部分重叠，所述第三颜 色滤光片在所述衬底基板上的正投影与所述感测连接线在所述衬底基板上的正投影至少部分重叠。
  61. 根据权利要求58所述的显示基板，其中，所述数据线包括第一数据线、第二数据线、第三数据线和第四数据线，
    在所述子像素组中，所述第一数据线和所述第二数据线位于所述第一颜色子像素和所述第二颜色子像素之间，所述第一数据线与所述第一颜色子像素的所述第二源极相连，所述第二数据线与所述第二颜色子像素的所述第二源极相连，所述第三数据线和所述第四数据线位于所述第三颜色子像素和所述第四颜色子像素之间，所述第三数据线与所述第三颜色子像素的所述第二源极相连，所述第四数据线与所述第四颜色子像素的所述第二源极相连。
  62. 根据权利要求61所述的显示基板，其中，在所述子像素组中，所述第一颜色滤光片在所述衬底基板上的正投影与所述第二数据线在所述衬底基板上的正投影至少部分重叠，所述第二颜色滤光片在所述衬底基板上的正投影分别与所述第三数据线在所述衬底基板上的正投影至少部分重叠，所述第三颜色滤光片在所述衬底基板上的正投影和所述第四数据线在所述衬底基板上的正投影至少部分重叠。
  63. 根据权利要求49所述的显示基板，其中，所述第一薄膜晶体管还包括：
    第一有源层，位于所述半导体层，且包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区；
    其中，所述第一栅极位于所述栅极层，所述第一栅极在所述衬底基板上的正投影与所述第一沟道区在所述衬底基板上的正投影至少部分重叠；所述第一源极和所述第一漏极均位于所述导电层，
    所述显示基板还包括第一过孔和第二过孔，所述第一过孔和所述第二过孔位于所述层间绝缘层之中，所述第一源极通过所述第一过孔与所述第一源极区相连，所述第一漏极通过所述第二过孔与所述第一漏极区相连。
  64. 根据权利要求63所述的显示基板，其中，所述第一沟道区在所述衬底基板上的正投影落入所述第一主体部在所述衬底基板上的正投影。
  65. 根据权利要求63所述的显示基板，其中，所述显示基板还包括：
    第四过孔，位于层间绝缘层之中，所述第二漏极通过所述第四过孔与所述导体化块相连，
    其中，所述导电遮光结构还包括：第二绝缘部，所述第二绝缘部在所述衬底基板上的正投影与所述第四过孔在所述衬底基板上的正投影至少部分重叠。
  66. 根据权利要求65所述的显示基板，其中，所述第二绝缘部包括第二镂空部，所述第二镂空部填充有所述缓冲层的材料。
  67. 根据权利要求66所述的显示基板，其中，所述第二镂空部包括第二镂空环，所述第二镂空环内侧的部分与所述第二镂空环的外侧均为所述导电遮光结构的材料。
  68. 根据权利要求65所述的显示基板，其中，所述第二绝缘部为氧化部。
  69. 根据权利要求65所述的显示基板，其中，所述第一过孔和所述第四过孔在所述衬底基板上的正投影的形状均为各向异性的图形，且均包括长边。
  70. 根据权利要求69所述的显示基板，其中，在所述子像素组中，所述第二颜色子像素的所述第一过孔的所述长边和所述第三颜色子像素的所述第一过孔的所述长边均沿所述第一方向延伸，所述第一颜色子像素的所述第一过孔的所述长边和所述第四颜色子像素的所述第一过孔的所述长边均沿所述第二方向延伸。
  71. 根据权利要求70所述的显示基板，其中，在所述子像素组中，所述第二颜色子像素的所述第四过孔的所述长边和所述第三颜色子像素的所述第四过孔的所述长边均沿所述第二方向延伸，所述第一颜色子像素的所述第四过孔的所述长边和所述第四颜色子像素的所述第四过孔的所述长边均沿所述第一方向延伸。
  72. 根据权利要求70所述的显示基板，其中，在所述子像素组中，所述第一颜色子像素的所述第四过孔的中心、所述第二颜色子像素的所述第四过孔的中心、所述第三颜色子像素的所述第四过孔的中心和所述第四颜色子像素的所述第四过孔的中心在所述第二方向上错位设置，
    所述第一颜色子像素的所述第四过孔的中心和所述第四颜色子像素的所述第四过孔的中心位于第一虚拟直线上，所述第二颜色子像素的所述第四过孔的中心和所述第三颜色子像素的所述第四过孔的中心位于与所述第一虚拟直线平行的第二虚拟直线上。
  73. 根据权利要求1-72中任一项所述的显示基板，其中，所述导电遮光结构的材料选自钼和钛的一种或多种，所述导电层的材料选自铜、钼和钛中的一种或多种。
  74. 根据权利要求73所述的显示基板，其中，所述导电层包括沿垂直于所述衬底基板的方向上层叠的第一子金属层和第二子金属层，所述第一子金属层的材料为铜，所述第二子金属层的材料为钼钛合金。
  75. 根据权利要求25所述的显示基板，其中，所述栅极层的材料选自铜、钼和钛中的一种或多种。
  76. 根据权利要求25所述的显示基板，其中，所述导电遮光结构在垂直于所述衬底基板的方向上的厚度范围为90-120纳米，所述导电层在垂直于所述衬底基板的方向上的厚度范围为200-600纳米。
  77. 一种显示装置，包括根据权利要求1-76中任一项所述的显示基板。
  78. 一种显示基板的制作方法，包括：
    在衬底基板上形成导电遮光材料层；
    对所述导电遮光材料层进行图案化以形成导电遮光结构；
    在所述导电遮光结构远离所述衬底基板的一侧形成缓冲层；
    在所述缓冲层远离所述导电遮光结构的一侧形成半导体层；
    在所述半导体层远离所述缓冲层的一侧形成层间绝缘层；
    在所述层间绝缘层和所述缓冲层中形成第一接触孔；
    在所述层间绝缘层远离所述半导体层的一侧形成导电层；
    其中，所述导电层包括导电结构，所述导电遮光结构包括第一主体部和第一凹陷部，所述第一凹陷部在垂直于衬底基板的方向上的平均厚度小于所述第一主体部在垂直于衬底基板的方向上的平均厚度，所述第一接触孔穿过所述层间绝缘层和所述缓冲层，所述导电结构通过所述第一接触孔与所述第一凹陷部连接，所述第一凹陷部靠近所述导电层的表面的面积大于所述第一凹陷部在所述衬底基板上正投影的面积。
  79. 根据权利要求78所述的显示基板的制作方法，其中，在所述层间绝缘层和所述缓冲层中形成第一接触孔包括：
    在所述缓冲层中形成第一缓冲部和第二缓冲部，所述第一缓冲部远离所述衬底基板的一侧与所述导电层接触设置，且所述第一缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置，
    所述第二缓冲部远离所述衬底基板的一侧与所述层间绝缘层接触设置，且所述第二缓冲部靠近所述衬底基板的一侧与所述导电遮光结构接触设置。
  80. 根据权利要求79所述的显示基板的制作方法，其中，所述第一接触 孔包括侧壁，所述侧壁至少包括：
    第一子侧壁，位于所述层间绝缘层；以及
    第二子侧壁，位于所述缓冲层，
    其中，所述第一子侧壁与所述衬底基板的夹角构成第一坡度角，所述第二子侧壁与所述衬底基板的夹角构成第二坡度角，所述第一坡度角小于所述第二坡度角；所述第二子侧壁与所述第一缓冲部的接触部位于所述第一缓冲部和所述第二缓冲部之间。
  81. 根据权利要求80所述的显示基板的制作方法，其中，所述第一接触孔的所述侧壁还包括：
    第三子侧壁，位于所述第一缓冲部，
    其中，所述第三子侧壁与所述衬底基板的夹角构成第三坡度角，所述第一坡度角、所述第二坡度角和所述第三坡度角不同。
  82. 根据权利要求78-81中任一项所述的显示基板的制作方法，还包括：
    在所述导电层远离所述层间绝缘层的一侧形成平坦层，所述平坦层包括阳极孔；以及
    在所述平坦层远离所述导电层的一侧形成阳极层以在所述衬底基板上形成多个子像素，各所述子像素包括阳极，所述阳极包括出光部、驱动部和将所述出光部和所述驱动部相连的延伸部，所述驱动部至少部分位于所述阳极孔之内，
    其中，在至少一个所述子像素中，所述第一接触孔在所述衬底基板上正投影与所述驱动部在所述衬底基板上正投影至少部分交叠，
    所述显示基板还包括：电源线，位于所述导电层；以及感测线，位于所述导电层；所述电源线和所述感测线在第一方向上排列，所述电源线和所述感测线均沿与所述第一方向相交的第二方向延伸；
    所述多个子像素包括第一子像素对和第二子像素对，所述第一子像素对包括两个所述子像素，分别位于所述电源线的两侧，所述第二子像素对包括两个所述子像素，分别位于所述感测线的两侧；所述第一子像素对和所述第二子像素对在所述第一方向上交替排列，
    在所述第二子像素对中的两个所述子像素中，所述阳极孔与所述第一凹陷部在所述衬底基板上正投影存在第一交叠区域，所述第一交叠区域的面积小于所述第一接触孔在所述衬底基板上正投影的面积。
  83. 根据权利要求82所述的显示基板的制作方法，其中，所述导电层还包括第一源极和第一漏极，所述导电结构为所述第一漏极。
  84. 根据权利要求83所述的显示基板的制作方法，其中，所述半导体层包括第一有源层，所述第一有源层包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区，所述制作方法还包括：
    在所述层间绝缘层和所述缓冲层中形成第一接触孔的同时在所述层间绝缘层形成第一过孔和第二过孔，
    其中，所述第一源极通过所述第一过孔与所述第一源极区相连，所述第一漏极通过所述第二过孔与所述第一漏极区相连。
  85. 根据权利要求84所述的显示基板的制作方法，其中，采用同一刻蚀工艺同时图案化所述层间绝缘层和所述缓冲层以形成所述第一过孔和所述第一接触孔。
  86. 根据权利要求84所述的显示基板的制作方法，其中，采用半色调掩膜工艺图案化所述层间绝缘层和所述缓冲层以形成所述第一过孔和所述第一接触孔。
  87. 根据权利要求86所述的显示基板的制作方法，其中，采用半色调掩膜工艺图案化所述层间绝缘层和所述缓冲层以形成所述第一过孔和所述第一接触孔包括：
    在所述层间绝缘层远离所述衬底基板的一侧形成第一光刻胶；
    采用第一半色调掩膜对所述第一光刻胶进行曝光和显影，以形成包括第一光刻胶完全去除部、第一光刻胶部分去除部和第一光刻胶保留部的第一光刻胶图案；
    以所述第一光刻胶图案为掩膜对所述层间绝缘层进行刻蚀，以去除所述第一光刻胶完全去除部对应的层间绝缘层；
    对所述第一光刻胶图案进行灰化处理，去除所述第一光刻胶部分去除部并减薄所述第一光刻胶保留部以形成第二光刻胶图案；以及
    以所述第二光刻胶图案为掩膜对所述缓冲层进行刻蚀，
    其中，所述第一接触孔在所述衬底基板上的正投影与所述第一光刻胶完全去除部在所述衬底基板上的正投影重叠，所述第一过孔在所述衬底基板上的正投影与所述第一光刻胶部分去除部在所述衬底基板上的正投影重叠。
  88. 根据权利要求84所述的显示基板的制作方法，其中，所述导电遮光 结构还包括第一绝缘部，所述第一绝缘部在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影至少部分重叠，所述第一绝缘部在所述衬底基板上的正投影与所述第一源极区在所述衬底基板上的正投影至少部分重叠。
  89. 根据权利要求88所述的显示基板的制作方法，其中，所述第一绝缘部包括第一镂空部，所述第一镂空部填充有所述缓冲层的材料，对所述导电遮光材料层进行图案化以形成所述导电遮光结构包括：
    通过同一图案化工艺对所述导电遮光材料层进行图案化以形成所述第一主体部、所述第一凹陷部和所述第一镂空部。
  90. 根据权利要求89所述的显示基板的制作方法，其中，对所述导电遮光材料层进行图案化以形成导电遮光结构包括：
    在所述导电遮光结构远离所述衬底基板的一侧形成光刻胶；
    采用第二半色调掩膜对所述光刻胶进行曝光和显影，以形成包括第二光刻胶完全去除部、第二光刻胶部分去除部和第二光刻胶保留部的第三光刻胶图案；
    以所述第三光刻胶图案为掩膜对所述导电遮光材料层进行刻蚀，以去除所述第二光刻胶完全去除部对应的导电遮光材料层；
    对所述第三光刻胶图案进行灰化处理，去除所述第二光刻胶部分去除部并减薄所述第二光刻胶保留部以形成第四光刻胶图案；以及
    以所述第四光刻胶图案为掩膜对所述导电遮光材料层进行刻蚀，
    其中，所述第一主体部在所述衬底基板上的正投影与所述第二光刻胶保留部在所述衬底基板上的正投影重叠，所述第一凹陷部在所述衬底基板上的正投影与所述第二光刻胶部分去除部在所述衬底基板上的正投影重叠。
  91. 根据权利要求78-90中任一项所述的显示基板的制作方法，其中，所述第一凹陷部包括第一边缘部，在从所述第一凹陷部的边缘到所述第一凹陷部的中心的方向上，所述第一边缘部在垂直于衬底基板的方向上的厚度逐渐减小。
  92. 根据权利要求78-91中任一项所述的显示基板的制作方法，其中，所述第一凹陷部包括第一边缘部，在垂直于所述衬底基板方向上，所述第一边缘部靠近所述导电层的表面的第四坡度角是连续变化的。
  93. 根据权利要求78-92中任一项所述的显示基板的制作方法，其中，所述第一凹陷部靠近所述导电结构的表面为连续弧面，或至少一段连续弧面和至 少一段平面组合而成的组合面。
  94. 根据权利要求78-93中任一项所述的显示基板的制作方法，其中，所述第一凹陷部包括第一边缘部，所述第一边缘部靠近所述导电层的表面上的第四坡度角α满足下列公式：
    0<α<k*H/Lmax
    其中，Lmax为所述第一凹陷部在所述衬底基板上的正投影的最大孔径，H为所述第一主体部的平均厚度，k为大于1小于等于2的常数。
  95. 根据权利要求94所述的显示基板的制作方法，其中，k＝2，所述第四坡度角的范围为1-π/18。
  96. 根据权利要求78-95中任一项所述的显示基板的制作方法，其中，所述第一凹陷部在所述衬底基板上的正投影在平行于所述衬底基板的方向上的尺寸范围为5-10微米。
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