WO2023015487A1 - 显示基板及电子装置 - Google Patents

显示基板及电子装置 Download PDF

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Publication number
WO2023015487A1
WO2023015487A1 PCT/CN2021/112067 CN2021112067W WO2023015487A1 WO 2023015487 A1 WO2023015487 A1 WO 2023015487A1 CN 2021112067 W CN2021112067 W CN 2021112067W WO 2023015487 A1 WO2023015487 A1 WO 2023015487A1
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Prior art keywords
electrode
point
layer
base substrate
display substrate
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PCT/CN2021/112067
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English (en)
French (fr)
Inventor
杨宗顺
余洪涛
黄冠达
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京东方科技集团股份有限公司
云南创视界光电科技有限公司
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Priority to PCT/CN2021/112067 priority Critical patent/WO2023015487A1/zh
Priority to CN202180002151.9A priority patent/CN115968589A/zh
Priority to EP21953111.8A priority patent/EP4280255A1/en
Publication of WO2023015487A1 publication Critical patent/WO2023015487A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/341—Short-circuit prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/19—Tandem OLEDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • Embodiments of the disclosure relate to a display substrate and an electronic device.
  • Micro OLED (Micro OLED) display involves the combination of organic light-emitting diode (OLED) technology and silicon-based CMOS technology. Research and development of organic electronics and even molecular electronics on silicon.
  • Micro OLED (Micro OLED) display has excellent display characteristics, such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, low power consumption, etc., and has broad development prospects.
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate, a dielectric layer on the base substrate, and a sequentially stacked first electrode layer located on the side of the dielectric layer away from the base substrate , a pixel defining layer, an organic functional layer and a second electrode layer.
  • the base substrate includes adjacent first sub-pixel regions and second sub-pixel regions, and the first electrode layer includes a first electrode located in the first sub-pixel region and a first electrode located in the second sub-pixel region. second electrode.
  • the pixel defining layer includes a first opening area, a second opening area, and a pixel defining portion between the first opening area and the second opening area, and the first opening area exposes the first electrode At least partly, the second opening area exposes at least a part of the second electrode, and the pixel defining part also respectively covers a part of the first electrode and the second electrode;
  • the first electrode includes The first surface and the second surface of the base substrate, and the second surface of the first electrode is closer to the base substrate than the first surface;
  • the display substrate has a In the cross-section and in the first direction parallel to the surface of the base substrate, the length of the part of the pixel defining portion located on the first surface of the first electrode is d1, the The length of the portion of the pixel defining portion located on the second surface of the first electrode is d2; d1 is smaller than d2.
  • the first electrode includes a stacked first sub-electrode and a second sub-electrode, the second sub-electrode is located on a side of the first sub-electrode away from the dielectric layer; the second sub-electrode The electrode covers the side surface of the first sub-electrode and is in contact with the dielectric layer to form the second surface of the first electrode.
  • an average thickness of a portion of the pixel defining portion in contact with the second surface of the first electrode is greater than an average thickness of the first electrode at the second surface.
  • the part of the dielectric layer corresponding to the gap includes the first groove, and the gap exposes the first groove;
  • the pixel defining portion covers the first groove and forms a second groove;
  • the spacer also exposes the first electrode edge of the first electrode close to the first groove and the second electrode edge of the dielectric layer.
  • a groove facing the first exposed portion between the first groove edges of the first electrode; in the cross-section and in the first direction, the second groove is close to the first electrode
  • the distance between the first side surface and the edge of the first electrode is d3, and d3 is greater than d1.
  • the length of the part of the pixel defining portion located on the first side surface of the second groove close to the first electrode side is y1 , and the maximum length of the second groove is d4; y1 is smaller than d4.
  • the second electrode layer includes a recessed structure corresponding to the first groove, the recessed structure includes a first recessed point and a second recessed point located in the cross section, the first recessed point and the orthographic projection of the second depression point on the base substrate are located in the orthographic projection of the second groove on the base substrate; the first depression point and the second groove The distance between the first side surface of the first side surface in the first direction is d5, and d5 is greater than d1.
  • the distance between the first concave point and the second concave point in the first direction is d6, and y1 is greater than d6.
  • the first recessed point and the second recessed point have different distances from the base substrate.
  • the second electrode layer includes a raised portion, and the raised portion at least partially overlaps with the first electrode in a direction perpendicular to the base substrate; There is a first protruding point inside, and the protruding height of the first protruding point is greater than the average thickness of the second electrode layer.
  • the concave structure further includes a second convex point located in the section, the second convex point is located between the first concave point and the second concave point, the second convex point
  • the distances from the starting point to the base substrate are respectively greater than the distances from the first depressed point and the second depressed point to the base substrate;
  • the smaller value of the height difference between the two depressions is ⁇ h.
  • ⁇ h is greater than a height difference between the first depression and the second depression.
  • ⁇ h is smaller than the protrusion height of the first protrusion point.
  • the second electrode layer has different thicknesses at the first recessed point and the second recessed point.
  • the pixel defining portion includes a first surface away from the base substrate, the orthographic projection of the first surface on the cross-section is a first curve, and the first curve is close to the first
  • the electrode has a first tangent at its endpoint, the first tangent intersecting the first direction.
  • the first curve has a second tangent near the end of the second electrode, the second tangent intersects the first direction; the first tangent and the second tangent The included angle formed with the first direction is different.
  • intersection of the first tangent line and the surface of the base substrate is located on a side of the first electrode close to the second electrode.
  • the length of the first opening area is different from the length of the second opening area.
  • the first opening area has a first side and a second side opposite in the first direction on the cross section, and the first side and the second side are opposite to the first side.
  • the included angles formed by the first surfaces of the electrodes are different.
  • the second electrode includes a first surface away from the base substrate, and the first surface of the second electrode is parallel to the plane of the base substrate; within the section and within the In the first direction, the length of the part of the pixel defining portion located on the first surface of the second electrode is d1'; d1 and d1' are not equal.
  • At least one embodiment of the present disclosure further provides an electronic device, including the display substrate provided by any one of the above embodiments.
  • FIG. 1 is a schematic plan view of a display substrate provided by some embodiments of the present disclosure
  • FIG. 2 is one of the cross-sectional views of a display substrate provided by some embodiments of the present disclosure
  • FIG. 3 is the second cross-sectional view of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic plan view of a first electrode layer and a pixel defining layer provided by some embodiments of the present disclosure
  • FIG. 5A is a schematic diagram of the formation of the mask plate of the pixel electrode layer provided by some embodiments of the present disclosure.
  • FIG. 5B is a schematic plan view of a pixel defining layer provided by some embodiments of the present disclosure.
  • FIG. 6 is the third cross-sectional view of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 7 is a fourth cross-sectional view of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 8 is the fifth cross-sectional view of the display substrate provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of an electronic device provided by some embodiments of the present disclosure.
  • Micro OLED (Micro OLED) displays usually have a size smaller than 100 microns, such as a size smaller than 50 microns, etc., involving the combination of organic light-emitting diode (OLED) technology and CMOS technology, and preparing OLED arrays on silicon-based substrates including CMOS circuits .
  • OLED organic light-emitting diode
  • OLED devices are formed by evaporating different organic functional layers (such as electron/hole injection layers) using a fine metal mask (Fine Metal Mask, FMM).
  • FFM is used to pattern the organic functional layers to Corresponding patterns are formed in different pixel regions.
  • FMM has limited precision and cannot achieve high image resolution (that is, pixels per inch, Pixels Per Inch, referred to as PPI), which limits the resolution of OLED devices. Therefore, full-color display can be realized by combining white light OLED with color filter layer.
  • the organic functional layer is usually formed as a continuous structure covering multiple sub-pixel regions, which is prone to leakage in the lateral direction, resulting in cross-color between sub-pixels and reducing the color gamut of the display device.
  • the carrier injection layer (such as electron injection layer (EIL), hole injection layer (HIL)), light-emitting layer, carrier injection layer (CGL) and other organic functional sublayers in OLED devices usually include metal elements, For example, heavily doped materials including metal ions or metal elements will generate mobile charges under the action of a voltage, thereby causing leakage between sub-pixels in the lateral direction, and causing color cross-talk.
  • EIL electron injection layer
  • HIL hole injection layer
  • CGL carrier injection layer
  • other organic functional sublayers in OLED devices usually include metal elements, For example, heavily doped materials including metal ions or metal elements will generate mobile charges under the action of a voltage, thereby causing leakage between sub-pixels in the lateral direction, and causing color cross-talk.
  • the substrate structure can be designed so that the organic functional layer is recessed between the sub-pixels, so that the leakage structure (such as the carrier injection layer, etc.) in the organic functional layer is naturally disconnected in the recess, thereby effectively avoiding
  • the cross-color between sub-pixels caused by the lateral leakage of the organic functional layer improves the color gamut of the display substrate and improves the display quality.
  • the depression of the organic functional layer causes the upper electrode layer (for example, cathode) of the light-emitting element formed above the organic functional layer to also be correspondingly depressed, thereby drawing closer to the lower electrode layer (for example, anode) of the organic functional layer.
  • the distance between them increases the risk of short circuit; in addition, the upper electrode layer is easy to form a needle-punched shape in the depression, and tip discharge is prone to occur, which further increases the risk of short circuit between the upper and lower electrode layers.
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate, a dielectric layer on the base substrate, and a first electrode layer stacked in sequence on the side of the dielectric layer away from the base substrate, An organic functional layer and a second electrode layer, the first electrode layer includes a first electrode located in the first sub-pixel area and a second electrode located in the second sub-pixel area; the first electrode and the There is a gap between the second electrodes, the dielectric layer is provided with a first groove corresponding to the gap, and the gap exposes the first groove, and the second electrode layer includes a position corresponding to the first groove A recessed structure; the gap also exposes a first exposed portion of the dielectric layer between the first electrode and the first groove.
  • the organic functional layer is recessed between the sub-pixels by setting the first grooves in the lower dielectric layer at the corresponding sub-pixel intervals, so that the leakage structure in the organic functional layer It is naturally disconnected at the recess, thereby effectively avoiding the cross-color between sub-pixels caused by the lateral leakage of the organic functional layer, improving the color gamut of the display substrate, and improving the display quality; at the same time, by setting the first exposed part, the enlarged The distance between the edge of the first electrode and the edge of the first groove is increased, thereby increasing the distance between the first electrode and the recessed structure of the second electrode layer, and reducing the short circuit between the first electrode and the second electrode layer risk and improve the yield rate of the product.
  • FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 20 includes a plurality of gate lines 11 and a plurality of data lines 12.
  • the plurality of gate lines 11 and the plurality of data lines 12 intersect with each other to define a plurality of sub-pixel regions distributed in an array in the display area.
  • Each sub-pixel area is provided with a sub-pixel, and each sub-pixel includes a light-emitting element and a driving circuit for driving the light-emitting element.
  • the driving circuit is, for example, a conventional pixel circuit.
  • the drive circuit includes a conventional 2T1C (that is, two transistors and a capacitor) pixel circuit, nTmC (n, m are positive integer) pixel circuits such as 4T2C, 5T1C, 7T1C, and in different embodiments, the drive circuit also A compensation circuit may be further included, and the compensation circuit may include an internal compensation circuit or an external compensation circuit, and the compensation circuit may include a transistor, a capacitor, and the like.
  • the drive circuit may further include a reset circuit, a light emission control circuit, a detection circuit, etc. as required.
  • the display substrate may further include a data driving circuit 6 and a gate driving circuit 7, which are respectively connected to the driving circuit of the light emitting element through the data line 12 and the gate line 11 to provide electrical signals.
  • the data drive circuit is used to provide data signals
  • the gate drive circuit is used to provide scan signals, and can further be used to provide various control signals, power supply signals and the like.
  • FIG. 1 only schematically shows the connection relationship between the gate driving circuit and the data driving circuit and the sub-pixels, and does not represent their actual positional relationship, nor is it intended to limit the present disclosure.
  • the display substrate adopts a silicon substrate as the base substrate 101, and the driving circuit (pixel circuit), the gate driving circuit 6 and the data driving circuit 7 can all be integrated on the silicon substrate.
  • the gate driving circuit 6 and the data driving circuit 7 can be formed, for example, in an area corresponding to the display area of the display substrate.
  • FIG. 2 shows an example of a cross-sectional view of the substrate shown in FIG. 1 along the section line A-A'.
  • the transistor may be a driving transistor configured to control the magnitude of the current for driving the light emitting element to emit light.
  • the transistor may also be a light emission control transistor, which is used to control whether the current for driving the light emitting element to emit light flows. Embodiments of the present disclosure do not limit this.
  • the display substrate 20 includes a base substrate 101 , a dielectric layer 102 on the base substrate 101 , and a first electrode layer 211 stacked in sequence on the side of the dielectric layer away from the base substrate 101 , and pixels.
  • the first electrode layer 211 includes a plurality of electrodes spaced apart from each other to serve as a plurality of pixel electrodes of the plurality of light emitting elements of the display substrate.
  • the plurality of pixel electrodes include a first electrode 221 located in the first sub-pixel area and a second electrode 222 located in the second sub-pixel area; between the first electrode 221 and the second electrode 222 There is a gap G.
  • the first electrode 221, the second electrode layer 212 and the part of the organic functional layer 213 between the first electrode 221 and the second electrode layer 212 constitute the light emitting element of the first sub-pixel
  • the second electrode layer 212 and the part of the organic functional layer 213 between the second electrode 222 and the second electrode layer 212 constitute the light emitting element of the second sub-pixel.
  • the dielectric layer 102 is provided with a first groove 120 corresponding to the interval G, and the interval G exposes the first groove 120, that is, the first groove 120 is arranged on the first electrode 221 facing the second electrode 221.
  • An electrode edge 221c and the second electrode 222 are between the edges of the second electrode edge 222c facing the first electrode.
  • the organic functional layer 213 and the second electrode layer 212 formed above also have a concave structure corresponding to the first groove 120, so that the organic functional layer 213 is in the first sub-pixel A depression occurs between the first subpixel and the second subpixel, so that the leakage structure in the organic functional layer is naturally disconnected at the depression, thereby effectively avoiding the connection between the first subpixel and the second subpixel caused by the lateral leakage of the organic functional layer.
  • color the color gamut of the display substrate is improved, and the display quality is improved.
  • Fig. 3 shows an example of the SEM image of the substrate shown in Fig. 1 along the section line A-A', and Fig. 3 only shows a partial schematic diagram of the first groove 120 and its surroundings.
  • the second electrode layer 212 includes a recessed structure 130 corresponding to the first groove 120;
  • the second recessed point V2, the first recessed point V1 is close to the first electrode 221, and the second recessed point V2 is close to the second recessed point V2.
  • the second electrode layer 212 at the first recessed point V1 is compared to the surrounding area of the first recessed point V1 (for example, within the range of 10 nanometers, 30 nanometers or 50 nanometers with the first recessed point V1 as the center.
  • the second electrode layer is at the second recessed point V2 than at the periphery of the second recessed point V2 (for example, 10 nanometers, 30 nanometers centered on the second recessed point V2 or within 50 nanometers) have a closer distance to the substrate substrate.
  • Fig. 4 shows a schematic plan view of the first electrode layer 211 and the pixel defining layer 230 provided by at least one embodiment of the present disclosure, and Fig. 4 also shows the position of section line A-A' correspondingly.
  • the pixel defining layer 230 includes a plurality of opening regions 232, the plurality of opening regions 232 correspond to the plurality of pixel electrodes in the first electrode layer 211, and each opening region respectively exposes a corresponding At least part of a pixel electrode thus defines the light emitting area of each light emitting element.
  • the plurality of opening areas 232 include a first opening area 232a and a second opening area 232b, the first opening area 232a exposes at least part of the first electrode 221, the second opening The region 232b exposes at least a portion of the second electrode 222 .
  • the organic functional layer 213 is in contact with each pixel electrode through each opening.
  • the first opening region 232 a and the second opening region 232 b of the pixel defining layer 230 respectively expose at least part of the first electrode 221 and the second electrode 222 .
  • the pixel electrode layer 230 also includes a pixel defining portion 231 located between the first opening region 232a and the second opening region 232b, the pixel defining portion 231 covers the first groove 120 and covers the first electrode 221 and the second electrode respectively. A part of the second electrode 222, so that the end portions of the first electrode 221 and the second electrode 222 close to the recessed structure 130 are insulated from the second electrode layer 212, and the gap between the first electrode layer 211 and the second electrode layer 212 is lowered. risk of short circuit.
  • the pixel defining portion covers the first groove 120 and forms a second groove 220
  • the second groove 220 is formed by inheriting the shape of the first groove 120 below.
  • the second groove 220 has two opposite side walls, that is, a first side surface 220a and a second side surface 220b.
  • the one side surface 220a is close to the first side surface 220a of the first electrode 221 and the second side surface 220b close to the second electrode 222 .
  • the material of the pixel defining layer 230 is an inorganic insulating material, such as silicon nitride, oxide or oxynitride.
  • Inorganic insulating materials are harder than organic materials and are easier to shape, so they are more suitable for high-precision display substrates, such as silicon-based display substrates.
  • the material of the pixel defining layer 230 is the same or similar to that of the dielectric layer 102 .
  • the boundary line between the pixel defining layer 230 and the dielectric layer 102 cannot be clearly shown in the electron microscope image shown in FIG. 3 .
  • the orthographic projections of the first depressed point V1 and the second depressed point V2 on the base substrate are both located within the orthographic projection of the second groove 220 on the base substrate, that is, located on the first side surface 220a and the first side surface 220a. between the second side surfaces 220b.
  • the distance between the first depressed point V1 and the second depressed point V2 is d6 (also referred to as y2 ).
  • the first sub-pixel is adjacent to the second sub-pixel in the first direction D1.
  • the distance between the first recessed point V1, the second recessed point V2 and the first electrode layer 211 needs to be controlled. If the distance is too large, the organic functional layer 213 cannot be sufficiently recessed between the sub-pixels so that the Sub-functional layers that are prone to electric leakage are naturally disconnected; if the distance is too small, the risk of short circuit between the first electrode layer 211 and the second electrode layer 212 is likely to increase. Due to the tip discharge effect, the risk of short circuits at the first and second depressions V1 and V2 is high.
  • the first depression V1 and the second depression V2 have different distances from the base substrate 101 ; for example, as shown in FIGS. 2 and 3 , the distance between the second depression V2 and the base substrate 101 is smaller.
  • the angle of the second electrode layer 212 at the second concave point V2 is sharper than that at the first concave point V1.
  • This arrangement can increase the slope of the bottom of the recessed structure 130 , thereby helping to further increase the level difference of the leakage structure in the organic functional layer 213 , making it easier to break.
  • the concave structure 130 and the second groove 220 are formed due to the existence of the first groove 120, the shapes of the concave structure 130 and the second groove 220 are related to the aspect ratio of the first groove 120, the second The groove 220 basically inherits the shape of the first groove 120 .
  • the aspect ratio of the first groove 120 is less than or equal to 0.5.
  • the bottom edge of the cross-sectional shape of the first groove 120 is an upwardly convex arc, but the embodiments of the present disclosure are not limited thereto.
  • the cross-sectional shape of 120 in this cross-section may also be rectangle, trapezoid, triangle and so on. For example, in the section shown in FIG.
  • the ratio of the maximum dimension of the first groove 120 in the direction perpendicular to the substrate to the maximum dimension in the first direction D1 is less than or equal to 0.5.
  • the ratio of the maximum dimension of the second groove 220 in the direction perpendicular to the substrate to the maximum dimension d4 in the first direction D1 is less than or equal to 0.5.
  • the ratio of the maximum dimension d4 of the second groove 220 in the first direction D1 to the length of the gap G in the first direction ranges from 1/2-2/3.
  • the distance between the first depressed point V1 and the base substrate is different from the distance between the second depressed point V2 and the base substrate.
  • the second recess V2 is closer to the base substrate 101 .
  • the second electrode layer 212 has different thicknesses at the first recessed point V1 and the second recessed point V2. This is also caused by the fact that the second electrode layer 212 is recessed to a different extent at the first recessed point V1 and the second recessed point V2.
  • the gap G also exposes the dielectric layer 102 located between the first electrode edge 221c of the first electrode 221 close to the first groove 120 and the first groove edge 120a of the first groove 120 facing the first electrode 221
  • the first exposed portion 121 of the second electrode 222 is close to the second electrode edge 222c of the first groove 120 and the second groove edge 120b of the first groove 120 facing the second electrode 222
  • the exposed part 122 Both the first exposed portion 121 and the second exposed portion 122 are parts of the dielectric layer 102 not covered by the first electrode layer 211 .
  • the distance between the edge of the first electrode 221/the edge of the second electrode 222 and the edge of the first groove 120 is respectively enlarged, thereby drawing
  • the distance between the first electrode 221 and the first recessed point V1 of the second electrode layer 212 and the distance between the second electrode 222 and the second recessed point V2 are increased, reducing the short circuit between the first electrode layer and the second electrode layer risk.
  • the first electrode 221 includes a first surface 221 a away from the base substrate, and the first surface 221 a is an upper surface of the first electrode 221 .
  • the first surface 221a is parallel to the board surface of the base substrate, that is, parallel to the first direction D1.
  • the part of the pixel defining portion 231 located on the first surface 221a of the first electrode 221 (that is, in the same direction as the first surface 221a
  • the length of the overlapping portion in the direction perpendicular to the base substrate) is d1 (also referred to as L3).
  • the first direction D1 is a direction in which the first sub-pixel points to the second sub-pixel, that is, the first sub-pixel is adjacent to the second sub-pixel in the first direction.
  • the first direction D1 may be that the geometric center O1 of the orthographic projection of the opening area of the first sub-pixel on the base substrate points to the orthographic projection of the opening area of the second sub-pixel on the base substrate.
  • the present disclosure does not limit the first direction D1.
  • the first electrode 211 also includes a second surface 221b away from the substrate, for example, the second surface 221b is parallel to the first direction D1, and the second surface 221b is parallel to the first surface 221a. parallel.
  • the second surface 221b is closer to the base substrate 101 than the first surface 221a.
  • the first surface 221 a and the second surface 221 b are connected by a third surface, and the third surface is an inclined plane.
  • the first surface 221 a and the second surface 221 b can be approximately regarded as continuous surfaces.
  • the first electrode layer 211 includes a stacked first sub-electrode layer and a second sub-electrode layer, and the second sub-electrode layer is located on a side of the first sub-electrode layer away from the substrate.
  • the first electrode 221 and the second electrode 222 respectively include a stacked first sub-electrode 211 a and a second sub-electrode 211 b, and the second sub-electrode 211 b is located on a side of the first sub-electrode 211 a away from the dielectric layer 102 .
  • the second sub-electrode 211b covers the side surface of the first sub-electrode 211a and is in contact with the dielectric layer 102 to form the second surface 221b of the first electrode 221 .
  • the first surface 221a and the second surface 221b of the first electrode 221 form a stepped structure, which reduces the level difference of the pixel defining portion 231 above the first electrode 221 .
  • the material of the pixel defining layer is an inorganic insulating material, the texture is relatively brittle, and the stepped structure can prevent the pixel defining layer from breaking due to too large step difference.
  • the average thickness of the portion of the pixel defining portion 231 in contact with the second surface 211b of the first electrode 211 is greater than the average thickness of the first electrode 211 at the second surface 211b.
  • the material of the first sub-electrode layer may include titanium (Ti), and the material of the second sub-electrode layer includes silver (Ag).
  • the material of the first sub-electrode layer has high conductivity, which can reduce the contact resistance with the circuit on the base substrate; the material of the second sub-electrode layer has high reflectivity, which can improve the light extraction efficiency of the top emission light-emitting element.
  • the first electrode layer may further include a third sub-electrode layer located on the side of the second sub-electrode layer away from the first sub-electrode layer, the material of the third sub-electrode layer is, for example, a transparent conductive material, for example It is a conductive material with high work function such as ITO, IZO, IGZO, AZO, etc., and the direct contact with the organic functional layer 213 can improve the hole injection rate.
  • a transparent conductive material for example It is a conductive material with high work function such as ITO, IZO, IGZO, AZO, etc.
  • the material of the second electrode layer may be a material with a low work function to serve as a cathode, such as a semi-transmissive metal or a metal alloy material, such as an Ag/Mg alloy material.
  • the second electrode layer 212 includes a first raised portion 241, and the first raised portion 241 at least partially overlaps with the first electrode 221 in a direction perpendicular to the base substrate. .
  • the first raised portion 241 corresponds to between the first surface 221a and the second surface 221b of the first electrode 221, for example, the first raised portion 241 is due to the first surface 221a and the second surface 221b of the first electrode 221.
  • the level difference between the second surfaces 221b may be caused by the pixel defining portion 231 .
  • the first protruding portion 241 at least partially overlaps with the first surface 221 a and the second surface 221 b respectively.
  • the first protruding portion 241 at least partially overlaps the pixel defining portion 231 .
  • the first protruding portion 241 has a first protruding point P1 in the cross-section.
  • the first protruding portion 241 at the first protruding point P1 is compared with that at the periphery of the first protruding point P1 (for example, taking the first protruding point P1 as the center within a range of 10 nanometers, 30 nanometers or 50 nanometers). Inner) is farther away from the substrate substrate.
  • the orthographic projection of the first protrusion point P1 on the base substrate falls within the orthographic projection of the pixel defining portion 231 on the base substrate.
  • the protrusion height h1 of the first protrusion point P1 is greater than the average thickness of the second electrode layer 212 .
  • the protrusion height h1 is based on a plane of the second electrode layer 212 parallel to the first direction D1 (that is, parallel to the surface of the base substrate).
  • the second electrode layer 212 includes a second raised portion (not shown), and the second raised portion and the second electrode 222 are at least partially overlapping.
  • the orthographic projection of the pixel electrode portion 231 on the base substrate is located between the orthographic projection of the first raised portion 241 on the base substrate and the orthographic projection of the second raised portion on the base substrate.
  • the second protruding portion also includes a protruding point, and the orthographic projection of the protruding point of the second protruding portion on the substrate falls within the orthographic projection of the pixel defining portion 231 on the substrate.
  • the recessed structure 130 further includes a second raised point P2 located in the section, the second raised point P2 is located between the first recessed point V1 and the second recessed point V2, the The distances from the second raised point P2 to the base substrate are respectively greater than the distances from the first depressed point V1 and the second depressed point V2 to the base substrate.
  • the second electrode layer 212 at the second protruding point P2 is compared to the periphery of the second protruding point P2 (for example, within the range of 10 nanometers, 30 nanometers or 50 nanometers centered on the second protruding point P2 ) is farther away from the substrate substrate.
  • the larger value ⁇ h of the height difference between the second convex point P2 and the first concave point V1 and the second concave point V2 is the convex height of the second convex point P2; as shown in Figure 3, due to the The second recessed point V2 is closer to the substrate than the first recessed point V1, and the raised height ⁇ h of the second raised point P2 is the height difference between the second raised point P2 and the second recessed point V2.
  • ⁇ h is larger than the height difference between the first depressed point and the second depressed point.
  • ⁇ h is greater than the average thickness of the second electrode layer 212 .
  • ⁇ h is smaller than the protrusion height h1 of the first protrusion point P.
  • this is not intended to limit the embodiments of the present disclosure.
  • ⁇ h is greater than the protrusion height of the first protrusion point.
  • the bottom edge of the cross-sectional shape of the second groove 220 is an upwardly convex arc, including a third raised point P3 located in the cross-section, and the third raised point P3 is located on the first raised point.
  • a concave point V1 and the second concave point V2 that is, the orthographic projection of the third raised point P3 on the substrate is located between the orthographic projection of the first concave point V1 on the substrate and the second concave point V1.
  • Point V2 is between the orthographic projections on the substrate substrate.
  • the curvature of the third raised point P3 is smaller than the curvature of the first raised point P1
  • the curvature of the third raised point P3 is smaller than the curvature of the second raised point P2 .
  • the part of the pixel defining portion 231 located on the second surface 221b of the first electrode (that is, the part perpendicular to the second surface)
  • the overlapping portion in the direction of the base substrate) has a length d2 (also referred to as L4).
  • the distance between the first side surface 220a of the second groove 220 and the first electrode edge 221c of the first electrode 221 is d3 (also known as L1).
  • the distance d3 is greater than the distance d5 (also referred to as L2) between the first concave point V1 and the first side surface of the second groove 220 (ie, the side surface of the pixel defining layer) 220a. .
  • the pixel defining portion 231 includes a first surface (that is, an upper surface) away from the base substrate, and the first surface of the pixel defining portion 231 is schematically shown in FIG. Surface 231s.
  • the first surface 231s of the pixel defining portion includes a first slope z1 corresponding to the first electrode edge 221c of the first electrode 221 and a second slope z2 connected to the first side surface 220a.
  • the first slope z1 at least partially overlaps the first electrode edge 221c; the second slope z2 at least partially overlaps the first groove edge 120a.
  • both the first slope z1 and the second slope z2 include curved surfaces; for example, the shapes of the first slope z1 and the second slope z2 in the section include arcs.
  • the first slope z1 is caused by the step between the first sub-electrode 211 a and the second sub-electrode 211 b in the first electrode 221
  • the second slope z2 is caused by the first groove edge 120 a of the first groove 120 caused by.
  • the pixel defining layer will form a curved shape instead of an ideal right angle when covering the underlying stepped shape.
  • the first surface 231s of the pixel defining portion 231 further includes a connection surface 231c located between the first slope z1 and the second slope z2.
  • a connection surface 231c located between the first slope z1 and the second slope z2.
  • at least part of the connection surface 231c is a plane.
  • the first slope z1 and the second slope z2 are not directly connected, so that The first surface 231a presents a transitional plane portion between the first slope z1 and the second slope z2.
  • the connection surface 231c is entirely flat.
  • the length y3 of the connection surface 231 c is greater than the average thickness of the pixel defining layer 230 .
  • the ratio of the length y3 of the connecting surface 231c to L3 is greater than 1/3.
  • d5 is smaller than d2.
  • d5 is greater than the average thickness of the pixel defining layer 230 .
  • the distance d3 is also greater than the length d1 of the portion of the pixel defining portion 231 located on the first surface 221 a of the first electrode 221 .
  • the distance d3 may also be less than or equal to d1.
  • the length of the portion of the pixel defining portion 231 located on the second surface 221b of the first electrode is d2 greater than the first recess V1 and the first side of the second groove 220 The distance d5 between the surfaces 220a.
  • the pixel defining part 231 covers the first electrode 221
  • the length d1 of the portion on the first surface 221a of the first surface 221a can be appropriately reduced, which can help increase the size of the opening area and increase the opening ratio.
  • the length d1 of the portion of the pixel defining portion 231 located on the first surface 221a of the first electrode 221 is smaller than the length of the portion of the pixel defining portion 231 located on the second surface 221b of the first electrode 221 d2.
  • the length d1 of the portion of the pixel defining portion 231 located on the first surface 221 a of the first electrode 221 is also smaller than the distance d3 .
  • d1 is also smaller than the average thickness of the pixel defining layer 230 .
  • the length of the first electrode 221a is f1
  • the ratio range of f1 to the distance d3 is: 8- 20.
  • the ratio of d3 to y2 is greater than 1/2.
  • the distance d3 is too small, it is not conducive to increasing the distance between the first electrode 221 and the second electrode layer 212 and reducing the risk of short circuit; if the distance d3 is too large, it is not conducive to increasing the aperture ratio.
  • the distance d3 ranges from 0.1 micron to 0.2 micron, such as 0.12 micron or 0.15 micron.
  • the length d1 of the portion of the pixel defining portion 231 located on the first surface 221 a of the first electrode 221 is greater than the first recess V1 and the first groove 220 of the second groove 220 .
  • the length y1 of the part of the pixel defining portion 231 on the side of the first side surface 220a of the second groove 220 close to the first electrode 221 in the first direction D1 is also greater than the first concave point The distance d6 between V1 and the second concave point V2 in the first direction.
  • the distance d3' (also referred to as L1 ) between the second side surface 220b of the second groove 220 and the second electrode 222 ') is greater than the distance d5' (also referred to as L2') between the second concave point V1 and the second side surface 220b of the second groove 220 .
  • the mask used to make the pixel defining layer (PDL) 230 has periodic differences due to technological reasons during the formation process, and this periodic difference makes the opening area 232 in the manufactured pixel defining layer There are periodic differences in size. This periodic difference will eventually cause horizontal or vertical stripes to appear on the display device, resulting in uneven display.
  • Fig. 5A shows the formation principle of the mask plate of the pixel defining layer
  • Fig. 5B shows a schematic plan view of the pixel defining layer formed using the mask plate
  • Fig. 5B only schematically shows The opening area 232.
  • the entire surface of the mask plate needs to be coated with a layer of metal film (such as a chromium film) during manufacture, and then the metal film is laser ablated to form a mesh pattern.
  • a layer of metal film such as a chromium film
  • ablation needs to be performed in sections, and in the second ablation, in order to prevent a certain section from being missed, it is returned for a certain distance (for example, 6-8um) and then ablated to form a repeated ablation area.
  • the mesh size of the repeated ablation area is larger than that of the first ablation area; the opening area of the pixel defining layer thus formed exhibits a correspondingly fine regularity
  • the difference makes the final display product display irregular horizontal or vertical stripes, which affects the display effect of the product. This phenomenon of uneven display is particularly evident on high-resolution display products.
  • the ablation direction is a second direction D2 perpendicular to the first direction D1, and in the second direction D2, primary ablation regions and repeated ablation regions appear alternately and periodically;
  • the size of the opening area of the pixel defining layer formed by using the mask plate changes periodically and regularly in the second direction D2; for example, the T1 segment of the pixel defining layer corresponds to the primary ablation area , T2 segment corresponds to the repeated ablation zone.
  • the severity of the display unevenness is related to the size of the opening area, the larger the opening area, the less obvious the display unevenness and the smaller the impact.
  • the length of the opening area 232 along the first direction D1 may have different values in the thickness direction of the pixel defining layer, since the effective light emitting area of the sub-pixel is determined by the minimum value of the length of the opening area 232 along the first direction D1,
  • the length x1 of the opening area 232 along the first direction D1 is defined as the minimum value.
  • the size of the opening area 232 is different between the end close to the substrate and the end away from the substrate, and x1 is taken as the size of the end of the opening area 232 away from the substrate, that is, the minimum size.
  • At least one embodiment of the present disclosure provides a display substrate, in which the length d1 of the portion of the pixel defining portion 231 located on the first surface 221a of the first electrode 221 is narrowed, thereby increasing the length x1 of the opening region 232 , Not only is it helpful to increase the aperture ratio of the display substrate, but it can also reduce the influence of the periodic difference in the size of the opening region 232 on the display uniformity, thereby improving the display uniformity of the display substrate.
  • Fig. 6 shows some other examples of SEM images showing the substrate along the section line A-A' shown in Fig. 1 .
  • the length of the portion of the pixel defining portion 231 located on the first surface 221a of the first electrode 221 (that is, the portion overlapping with the first surface 221a in a direction perpendicular to the base substrate) d1 is smaller than the length d2 of the portion of the pixel defining portion 231 located on the second surface 221b of the first electrode (ie, the portion overlapping with the second surface 221b in a direction perpendicular to the substrate).
  • the length d1 of the part of the pixel defining portion 231 located on the first surface 221a of the first electrode 221 is also smaller than the first side surface 220a of the second groove 220 and the first side surface 220a of the second groove 220.
  • the distance d3 between the first electrode edges 221c of an electrode 221 is also smaller than the first side surface 220a of the second groove 220 and the first side surface 220a of the second groove 220.
  • d1 is also smaller than the average thickness of the pixel defining layer 230 .
  • the length d1 of the portion of the pixel defining portion 231 located on the first surface 221 a of the first electrode 221 is also smaller than the first recess V1 and the second groove 220 .
  • the length y1 of the portion of the pixel defining portion 231 close to the first electrode 221 in the first direction D1 is greater than the length y1 of the first depressed point V1 and the second depressed point V2 at the second The distance d6 in one direction.
  • the length y1 of the portion of the pixel defining portion 231 close to the first electrode 221 in the first direction D1 is smaller than the length y1 of the second groove 220 in the first direction D1.
  • the largest dimension of d4 is smaller than the length y1 of the second groove 220 in the first direction D1.
  • the length y1 of the portion of the pixel defining portion 231 on the first side surface 220 a of the second groove 220 near the first electrode 221 in the first direction D1 is less than The distance d6 between the first concave point V1 and the second concave point V2 in the first direction D1.
  • the length y1 of the pixel defining portion 231 on the side of the first side surface 220a of the second groove 220 close to the first electrode 221 in the first direction D1 is also smaller than the first concave point The distance d6 between V1 and the second concave point V2 in the first direction.
  • the second electrode 222 includes a first surface 222 a away from the base substrate and parallel to the plane of the base substrate.
  • the pixel defines The length of the part of the part 231 located on the first surface 222a of the second electrode 222 is d1', the length of the part of the pixel defining part 231 located on the first surface 222a of the second electrode 222 is d1' and the length of the pixel defining part
  • the length d1 of the portion 231 located on the first surface 221a of the first electrode 221 is not equal.
  • d1 is smaller than d1'.
  • the size x1 of the opening area 231 of the first sub-pixel along the first direction D1 is different from the size x2 of the opening area 231 of the second sub-pixel along the first direction D1, so that they are located in the same pixel defining layer period (
  • the first sub-pixel and the second sub-pixel located in the T1 section or T2 section of the pixel defining layer have openings of different sizes, which interferes with the regularity of the openings of the sub-pixels in the same period, avoiding horizontal Lines or vertical lines are produced, thereby improving the uniformity of the display.
  • the second electrode layer 212 includes a first raised portion 241 between the first surface 221a and the second surface 221b corresponding to the first electrode 221, for example, the first raised portion 241 It is caused by the level difference between the first surface 221 a and the second surface 221 b of the first electrode 221 or by the pixel defining portion 231 .
  • the first protrusion 241 at least partially overlaps with the first surface and the second surface, respectively.
  • the first protruding portion 241 has a first protruding point P1 in the cross-section.
  • the raised portion 241 is at the first raised point P1 compared to at the periphery of the first raised point P1 (for example, within the range of 10 nanometers, 30 nanometers or 50 nanometers centered on the first raised point P1). farther away from the base substrate.
  • the protrusion height h1 of the first protrusion point P1 is greater than the average thickness of the second electrode layer 212 .
  • the protrusion height h1 is based on a plane of the second electrode layer 212 parallel to the first direction D1 (that is, parallel to the surface of the base substrate).
  • the recessed structure 130 further includes a second raised point P2 located in the section, the second raised point P2 is located between the first recessed point V1 and the second recessed point V2, the The distances from the second raised point P2 to the base substrate are respectively greater than the distances from the first depressed point V1 and the second depressed point V2 to the base substrate.
  • the second electrode layer 212 at the second raised point P2 is compared to the surrounding area of the second raised point P2 (for example, the range of 10 nanometers, 30 nanometers or 50 nanometers with the second raised point P2 as the center). Inner) is farther away from the substrate substrate.
  • the larger value ⁇ h of the height difference between the second convex point P2 and the first concave point and the second concave point is the convex height of the second convex point P2; as shown in Figure 3, due to the The second recessed point V2 is closer to the substrate than the first recessed point V1, and the raised height ⁇ h of the second raised point P2 is the height difference between the second raised point P2 and the second recessed point V2.
  • ⁇ h is larger than the height difference between the first depressed point and the second depressed point.
  • ⁇ h is greater than the average thickness of the second electrode layer 212 .
  • ⁇ h is greater than the protrusion height h1 of the first protrusion point P1.
  • the second electrode layer 212 shown in FIG. 6 is flatter than the second electrode layer 212 shown in FIG. 3 .
  • the protrusion height h1 of the first protrusion point P1 shown in FIG. 6 is smaller than the protrusion height h1 of the first protrusion point P1 shown in FIG. 3 .
  • FIG. 7 is a schematic diagram of a display substrate provided by other embodiments of the present disclosure. For clarity, the circuit structure below the first electrode layer is omitted in the figure.
  • the pixel defining portion 231 includes a first surface 231 a away from the base substrate 101 , the orthographic projection of the first surface 231 a of the pixel defining portion 231 on the cross section shown in FIG. 7 is a first curve n1, the first curve n1 A curve n1 is the upper contour of the pixel defining portion 231 in the section.
  • a first tangent line S1 of the first curve n1 near an end point of the first electrode 221 intersects the first direction D1 .
  • the size of the opening area of the sub-pixel is easily affected by the shape of the pixel defining portion 231 near the end of the first electrode/second electrode.
  • by forming the end of the pixel defining portion 231 close to the first electrode and/or the second electrode into a raised structure it is easy to fine-tune the size of the opening area, thereby adjusting the periodicity of the above-mentioned opening area. Interference is performed to improve display uniformity.
  • the first curve n1 intersects the first direction D1 at the second tangent S2 close to the second electrode 222 .
  • the first tangent S1 intersects the second tangent S2.
  • the first tangent S1 forms a first included angle ⁇ 1 with the first direction
  • the second tangent S2 forms a second included angle ⁇ 2 with the first direction
  • the first included angle ⁇ 1 forms a second included angle ⁇ 1 with the first direction.
  • Angle ⁇ 2 is not equal.
  • the shapes of the two ends of the pixel defining portion 231 near the first electrode and the second electrode are different, so that the two ends of the pixel defining portion 231 can respectively obtain openings of different sizes, which helps to improve the show uniformity.
  • intersection point of the first tangent line S1 and the base substrate is located at the side of the first electrode 221 close to the second electrode 222
  • the intersection point of the second tangent line S2 and the base substrate is located at the side of the second electrode 222 close to the first electrode.
  • One side of 221; that is, the two ends of the pixel defining portion 231 close to the first electrode and the second electrode are respectively raised upward (ie, away from the base substrate).
  • the above-mentioned structure of the opening region can be formed by first performing a dry etching process and then performing a wet etching process in the patterning process of the material of the pixel defining layer. Due to the high precision of the dry etching process, the opening area can be positioned and the general outline of the opening area can be formed, and then the wet etching process can be performed to form the final shape of the opening area; since the wet etching process is not as accurate as the dry etching accuracy, And it has randomness. Therefore, performing wet etching after dry etching can randomly and finely adjust the morphology of the opening area, break the above-mentioned law of the opening area, and improve display uniformity. For example, the time of the dry etching process is longer than that of the wet etching process.
  • the end of the pixel defining portion tends to form an upwardly tilted structure as shown in FIG. 7 , and the cross-sectional shape of the opening area is approximately
  • the size of the end of the opening region 232 away from the base substrate is smaller than the size of the end close to the base substrate.
  • the opening region 232 of the first sub-pixel has a first side t1 and a second side t2 opposite to each other in the first direction D1 in the cross section, and the first side t1 and the side of the first electrode 221
  • the first surface 221a forms an included angle ⁇ 3
  • the second side t2 forms an included angle ⁇ 4 with the first surface 221a of the first electrode 221, and ⁇ 3 and ⁇ 4 are not equal.
  • FIG. 8 is a schematic diagram of a display substrate provided by some other embodiments of the present disclosure.
  • the main difference between the display substrate shown in FIG. 8 and the display substrate shown in FIG. 2 is that the cross-sectional shape of the first groove 120 is a regular trapezoid.
  • the regular trapezoid has a first base angle close to the first electrode 221 and a second base angle close to the second electrode 222 .
  • the first base angle and the second base angle are not equal.
  • the end of the pixel defining portion 231 close to the first electrode 221 has a third base angle, and the angle bisector k2 of the third base angle bisects the angle of the first base angle.
  • Line k1 is not parallel.
  • the base substrate 101 may be silicon, such as single crystal silicon or high-purity silicon; the dielectric layer 102 may be silicon oxide, nitride or oxynitride formed on silicon.
  • the base substrate 101 and the dielectric layer 102 form the driving substrate 201, the driving circuit of the sub-pixel can be integrated in the driving substrate 201, and communicate with the pixel electrodes (such as the first electrode 221 and the second electrode 222) through the contact hole in the dielectric layer 102 ) are electrically connected to drive the light-emitting element to emit light.
  • the active layer i.e. the semiconductor layer
  • the first electrode and the second electrode of the transistor are formed in the driving substrate 201 through a doping process
  • an insulating layer is formed through a silicon oxidation process
  • a plurality of conductive layers are formed through a sputtering process.
  • the semiconductor layer of the transistor (such as the active layer 322 in FIG. 2 ) is located inside the base substrate 101 , or is a part of the base substrate 101 .
  • the pixel driving circuit includes a complementary metal oxide semiconductor circuit (CMOS circuit).
  • CMOS circuit complementary metal oxide semiconductor circuit
  • the above-mentioned gate driving circuit 6 and data driving circuit 7 may also be integrated into the driving substrate 201 through the above-mentioned semiconductor process.
  • the gate driving circuit and the data driving circuit may adopt a conventional circuit structure in the art, which is not limited in the embodiments of the present disclosure.
  • the first electrode 221 and the second electrode 222 are formed on the surface of the driving substrate 201, and pass through the contact hole 103 filled with a conductive material (such as tungsten) and the plurality of conductive layers and the first transistor 203.
  • the first pole 323 realizes electrical connection.
  • FIG. 2 exemplarily shows two conductive layers 105 and 106 above the transistors, however, the embodiment of the present disclosure does not limit the number of conductive layers.
  • the topmost conductive layer 106 in the driving substrate 201 is reflective, such as a stacked structure of titanium/titanium nitride/aluminum.
  • the conductive layer 106 includes a plurality of sub-layers arranged at intervals, respectively corresponding to a plurality of pixel electrodes (such as the first electrode 221 and the second electrode 222 ) in the first electrode layer 211 .
  • the conductive layer 106 can be set as a reflective layer for reflecting the light emitted by the light emitting element and improving the light extraction efficiency.
  • the orthographic projection of each pixel electrode in the first electrode layer 211 on the substrate 101 falls within the orthographic projection of the portion of the conductive layer 106 corresponding to the pixel electrode on the substrate 101 .
  • the length of the gap G between the first electrode 221 and the second electrode 222 in the first direction is less than 1 micron, such as 700 nm-900 nm.
  • the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and the embodiment of the present disclosure does not limit the type of the light-emitting element.
  • the light emitting layer of an OLED can be a small molecular organic material or a high molecular organic material.
  • the organic functional layer 213 includes a plurality of sub-functional layers stacked on each other in a direction perpendicular to the base substrate 101 , at least one of the plurality of sub-functional layers is disconnected at a place corresponding to the first groove 120 .
  • the plurality of sub-functional layers includes at least one carrier injection layer and at least one light emitting layer.
  • the carrier injection layer may be an electron injection layer (EIL) or a hole injection layer (HIL).
  • EIL electron injection layer
  • HIL hole injection layer
  • the electron injection layer is located on the side of the light-emitting layer close to the cathode, and is used to lower the potential barrier of injecting electrons from the cathode, so that electrons can be effectively injected from the cathode into the light-emitting layer.
  • the hole injection layer is located on the side of the light-emitting layer close to the anode, and is used to lower the barrier of hole injection from the anode, so that holes can be effectively injected from the anode into the light-emitting layer.
  • the electron injection layer material can be LiQ (8-hydroxyquinoline lithium), AlQ3 (8-hydroxyquinoline aluminum), etc.
  • the hole injection layer material can be CuPc (polyester carbonic acid), TiOPc, m-MTDATA, 2-TNATA et al.
  • the organic functional layer 213 may further include an electron/hole transport layer, an electron/hole blocking layer, a charge generation layer, etc. as required.
  • the organic functional layer 213 includes a plurality of light-emitting layers, and the plurality of light-emitting layers are vertical 101 in the direction of stacking.
  • the organic functional layer 213 includes two light emitting layers (yellow and blue) or three light emitting layers (red, green and blue) stacked on each other.
  • At least two of the plurality of light-emitting layers are connected in series to form a tandem structure (tandem structure) through a charge generation layer (CGL), and the charge generation layer includes an N-type charge generation layer and a P-type charge generation layer for balancing loads. transport of fluids.
  • CGL charge generation layer
  • the N-type charge generation layer may be doped with an alkali metal such as lithium (Li), sodium (Na), potassium (K) or cesium (Cs) or such as magnesium (Mg), strontium (Sr), barium (Ba) Or an organic layer of an alkaline earth metal (but not limited to any of them) of radium (Ra); the P-type charge generation layer can be formed by doping an organic matrix material having hole transport capability with a dopant The resulting organic layer was formed.
  • the series structure helps to improve the luminous efficiency and luminous brightness of the device.
  • the charge generation layer includes metal elements, it is easy to cause leakage between sub-pixels and cause cross-color.
  • a recessed structure 130 is provided between corresponding sub-pixels in the organic functional layer 213, so that the charge generation layer is naturally disconnected at the recessed structure 130 due to a large level difference, thereby effectively The color crossing between sub-pixels caused by the lateral leakage of the organic functional layer is avoided, the color gamut of the display substrate is improved, and the display quality is improved.
  • FIG. 2 shows a first transistor 203 and a second transistor 204 electrically connected to the light emitting elements of the first sub-pixel and the second sub-pixel, respectively.
  • Embodiments of the present disclosure do not limit specific types of the first transistor 203 and the second transistor 204 .
  • the first transistor 203 is exemplarily described below, and this description is also applicable to the second transistor 204 , so details are not repeated here.
  • the first transistor 203 includes a gate 321 , a gate insulating layer 325 , an active layer 322 , a first pole 323 and a second pole 324 .
  • Embodiments of the present disclosure do not limit the type, material, and structure of the first transistor 203, for example, it may be a top-gate type, a bottom-gate type, etc.
  • the active layer of the first transistor 203 may be microcrystalline silicon, amorphous silicon, Inorganic semiconductor materials such as polysilicon (low-temperature polysilicon or high-temperature polysilicon), oxide semiconductors (such as IGZO), or organic materials such as PBTTT, PDBT-co-TT, PDQT, PDVT-10, dinaphtho-di Organic semiconductor materials such as thiophene (DNTT) or pentacene.
  • the first transistor 203 can be N-type or P-type.
  • the transistors used in the embodiments of the present disclosure can be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • Some embodiments of the present disclosure use field effect transistors (such as MOS field effect transistor) as an example, in this example, the silicon substrate is doped (p-type doping or n-type doping) to form the active layer of the transistor, that is, the active layer of the transistor is located in the silicon substrate, or The active layer of the transistor is part of the silicon substrate.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, for example, it may be directly described that one pole is the first pole and the other pole is the second pole.
  • the display substrate 20 may further include a light extraction layer 214 located on a side of the second electrode layer 212 away from the base substrate.
  • the refractive index of the light extraction layer 214 is greater than the refractive index of the second conductive layer 212, so that the light extraction efficiency can be improved.
  • the display substrate 20 may further include an encapsulation layer 215 located on a side of the light extraction layer 214 away from the base substrate.
  • the encapsulation layer 215 is configured to seal the light-emitting element to prevent external moisture and oxygen from penetrating into the light-emitting element and pixel circuits to cause damage to the device.
  • the encapsulation layer 215 includes an organic thin film or a structure in which organic thin films and inorganic thin films are alternately stacked.
  • a water-absorbing layer may also be provided between the encapsulation layer 215 and the light-emitting element, configured to absorb water vapor or sol remaining in the light-emitting element during the pre-production process.
  • the display substrate 20 may further include a color filter layer 216 located on a side of the encapsulation layer 215 away from the base substrate.
  • the light-emitting elements of the display substrate are configured to emit white light, and combined with the color filter layer to realize full-color display.
  • the display substrate 20 is an organic light emitting diode (OLED) display substrate or a micro OLED (Micro OLED) display substrate.
  • OLED organic light emitting diode
  • Micro OLED Micro OLED
  • FIG. 9 shows a schematic diagram of an electronic device 40 provided by at least one embodiment of the present disclosure.
  • the electronic device 40 is a digital photo frame, a smart bracelet, a smart watch, a mobile phone, a tablet computer, a monitor, a notebook computer, a navigator, and other products or components with any display function.

Abstract

一种显示基板及电子装置。该显示基板包括衬底基板、位于该衬底基板上的介质层、像素界定层和第一电极层。该第一电极层包括间隔的第一电极和第二电极。该像素界定层包括位于第一开口区和第二开口区之间的像素界定部；该第一电极包括远离衬底基板的第一表面和第二表面，且该第二表面相较于该第一表面更靠近该衬底基板；该显示基板具有与衬底基板垂直的截面，在该截面内且在平行于该衬底基板的方向上，该像素界定部位于该第一电极的第一表面和第二表面上的部分的长度分别为d1和d2；d1小于d2。该显示基板有助于提高显示均一性。

Description

显示基板及电子装置 技术领域
本公开实施例涉及一种显示基板及电子装置。
背景技术
微型OLED(Micro OLED)显示器涉及有机发光二极管(OLED)技术和硅基CMOS技术的结合，与光电子产业和微电子产业的交叉集成相关，促进了新一代微型显示技术的发展，也推进了硅上有机电子、甚至是硅上分子电子的研究和发展。
微型OLED(Micro OLED)显示器具有优秀的显示特性，例如分辨率高、亮度高、色彩丰富、驱动电压低、响应速度快、功耗低等，具有广阔的发展前景。
发明内容
本公开至少一实施例提供一种显示基板，包括衬底基板、位于所述衬底基板上的介质层、以及位于所述介质层远离所述衬底基板一侧且依次层叠的第一电极层、像素界定层、有机功能层和第二电极层。所述衬底基板包括相邻的第一子像素区和第二子像素区，所述第一电极层包括位于所述第一子像素区的第一电极和位于所述第二子像素区的第二电极。所述像素界定层包括第一开口区和第二开口区以及位于所述第一开口区和所述第二开口区之间的像素界定部，所述第一开口区暴露所述第一电极的至少部分，所述第二开口区暴露所述第二电极的至少部分，所述像素界定部还分别覆盖所述第一电极和所述第二电极的一部分；所述第一电极包括远离所述衬底基板的第一表面和第二表面，且所述第一电极的第二表面相较于所述第一表面更靠近所述衬底基板；所述显示基板具有与所述衬底基板垂直的截面，在所述截面内且在平行于所述衬底基板板面的第一方向上，所述像素界定部位于所述第一电极的第一表面上的部分的长度为d1，所述像素界定部位于所述第一电极的第二表面上的部分的长度为d2；d1小于d2。
在一些示例中，所述第一电极包括层叠的第一子电极和第二子电极，所述第二子电极位于所述第一子电极远离所述介质层的一侧；所述第二子电极包覆第一子电极的侧表面并与所述介质层接触形成所述第一电极的所述第二表面。
在一些示例中，所述像素界定部的与所述第一电极的第二表面接触的部分的平均厚度大于所述第一电极在所述第二表面处的平均厚度。
在一些示例中，所述第一电极和所述第二电极之间存在间隔，所述介质层对应所述间隔的部分包括所述第一凹槽，所述间隔暴露所述第一凹槽；所述像素界定部覆盖所述第一凹槽并形成第二凹槽；所述间隔还暴露所述介质层位于所述第一电极靠近所述第一凹槽的第一电极边缘与所述第一凹槽朝向所述第一电极的第一凹槽边缘之间的第一裸露部；在所述截面内且在所述第一方向上，所述第二凹槽靠近所述第一电极的第一侧表面与所述第一电极边缘之间的距离为d3，d3大于d1。
在一些示例中，在所述截面内且在所述第一方向上，所述像素界定部位于所述第二凹槽的第一侧表面靠近所述第一电极一侧的部分的长度为y1，且所述第二凹槽的最大长度为d4；y1小于d4。
在一些示例中，所述第二电极层在对应所述第一凹槽处包括凹陷结构，所述凹陷结构包括位于所述截面的第一凹陷点和第二凹陷点，所述第一凹陷点和所述第二凹陷点在所述衬底基板上的正投影均位于所述第二凹槽在所述衬底基板上的正投影内；所述第一凹陷点与所述第二凹槽的第一侧表面在所述第一方向上的距离为d5，d5大于d1。
在一些示例中，所述第一凹陷点和所述第二凹陷点在所述第一方向上的距离为d6，y1大于d6。
在一些示例中，所述第一凹陷点与所述第二凹陷点与所述衬底基板的距离不同。
在一些示例中，所述第二电极层包括凸起部，所述凸起部与所述第一电极在垂直于所述衬底基板的方向至少部分重叠；所述凸起部在所述截面内具有第一凸起点，所述第一凸起点的凸起高度大于所述第二电极层的平均厚度。
在一些示例中，所述凹陷结构还包括位于所述截面内的第二凸起点， 所述第二凸起点位于所述第一凹陷点和所述第二凹陷点之间，所述第二凸起点到所述衬底基板的距离分别大于所述第一凹陷点及所述第二凹陷点到所述衬底基板的距离；所述第二凸起点与所述第一凹陷点及所述第二凹陷点的高度差的较小值为△h。
在一些示例中，△h大于所述第一凹陷点和所述第二凹陷点的高度差。
在一些示例中，△h小于所述第一凸起点的凸起高度。
在一些示例中，所述第二电极层在所述第一凹陷点和所述第二凹陷点的厚度不同。
在一些示例中，所述像素界定部包括远离所述衬底基板的第一表面，所述第一表面在所述截面的正投影为第一曲线，所述第一曲线在靠近所述第一电极的端点处具有第一切线，所述第一切线与所述第一方向相交。
在一些示例中，所述第一曲线在靠近所述第二电极的端点处具有第二切线，所述第二切线与所述第一方向相交；所述第一切线和所述第二切线与所述第一方向所成的夹角不同。
在一些示例中，所述第一切线与所述衬底基板的板面的交点位于所述第一电极靠近所述第二电极的一侧。
在一些示例中，在所述第一方向上，所述第一开口区的长度与所述第二开口区的长度不同。
在一些示例中，所述第一开口区在所述截面上具有在所述第一方向上相对的第一边和第二边，所述第一边和所述第二边与所述第一电极的第一表面所成的夹角不同。
在一些示例中，所述第二电极包括远离所述衬底基板的第一表面，所述第二电极的第一表面与所述衬底基板板面平行；在所述截面内且在所述第一方向上，所述像素界定部位于所述第二电极的第一表面上的部分的长度为d1’；d1与d1’不相等。
本公开至少一实施例还提供一种电子装置，包括以上任一实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为本公开一些实施例提供的显示基板的平面示意图；
图2为本公开一些实施例提供的显示基板的剖视图之一；
图3为本公开一些实施例提供的显示基板的剖视图之二；
图4为本公开一些实施例提供的第一电极层和像素界定层的平面示意图；
图5A为本公开一些实施例提供的像素电极层的掩膜板的形成原理图；
图5B为本公开一些实施例提供的像素界定层的平面示意图；
图6为本公开一些实施例提供的显示基板的剖视图之三；
图7为本公开一些实施例提供的显示基板的剖视图之四；
图8为本公开一些实施例提供的显示基板的剖视图之五；以及
图9为本公开一些实施例提供的电子装置的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物 件及其等同，而不排除其他元件或者物件。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
微型OLED(Micro OLED)显示器通常具有小于100微米的尺寸，例如小于50微米的尺寸等，涉及有机发光二极管(OLED)技术和CMOS技术的结合，将OLED阵列制备在包括CMOS电路的硅基基板上。
通常情况下，OLED器件通过采用精细金属掩模(Fine Metal Mask，FMM)蒸镀不同的有机功能层(如电子/空穴注入层)的方式形成，例如，采用FFM对有机功能层进行构图从而在不同像素区形成对应的图案。然而，FMM精度有限，无法实现高图像分辨率(即每英寸所拥有的像素，Pixels Per Inch，简称PPI)，这对OLED器件的分辨率造成了限制。因此，可以采用白光OLED结合彩膜层的方式实现全彩显示。然而，在这种工艺中，通常有机功能层形成为覆盖多个子像素区的连续结构，容易在横向上发生漏电，造成子像素间的串色，并降低了显示器件的色域。例如，OLED器件中的载流子注入层(如电子注入层(EIL)、空穴注入层(HIL))、发光层、载流子注入层(CGL)等有机功能子层通常包括金属元素，例如包括金属离子或为含金属元素的重掺杂材料，在电压作用下会产生移动的电荷，从而引起横向上的子像素之间的漏电，进而造成串色问题。
例如，可以对基板结构进行设计，使得有机功能层在子像素之间发生凹陷，从而使得该有机功能层中的漏电结构(如载流子注入层等)在凹陷处自然断开，从而有效避免有机功能层的横向漏电导致的子像素间串色，提高了该显示基板的色域，改善了显示质量。
发明人发现，有机功能层的凹陷导致形成在该有机功能层上方的发光元件的上电极层(例如为阴极)也相应凹陷，从而会拉近与有机功能层的下电极层(例如为阳极)之间的距离，增加短路风险；此外，上电极层在凹陷处容易形成针刺形状，容易发生尖端放电，更进一步增加了上下电极层之间的短路风险。
本公开至少一实施例提供一种显示基板，包括衬底基板、位于所述衬底基板上的介质层以及位于所述介质层远离所述衬底基板一侧且依 次层叠的第一电极层、有机功能层和第二电极层，所述第一电极层包括位于所述第一子像素区的第一电极和位于所述第二子像素区的第二电极；所述第一电极和所述第二电极之间存在间隔，所述介质层对应所述间隔设置有第一凹槽，所述间隔暴露所述第一凹槽，所述第二电极层在对应所述第一凹槽处包括凹陷结构；所述间隔还暴露所述介质层位于所述第一电极和所述第一凹槽之间的第一裸露部。
本公开至少一实施例提供的显示基板，通过在下方的介质层中对应子像素间隔处设置第一凹槽，使得有机功能层在子像素之间发生凹陷，从而使得有机功能层中的漏电结构在凹陷处自然断开，从而有效避免有机功能层的横向漏电导致的子像素间串色，提高了该显示基板的色域，改善了显示质量；同时，通过设置该第一裸露部，拉大了该第一电极的边缘与第一凹槽的边缘之间的间距，从而拉大了该第一电极与第二电极层的凹陷结构的距离，降低了第一电极与第二电极层的短路风险，提高了产品的良率。
图1为本公开实施例提供的一种显示基板的平面示意图。如图1所示，该显示基板20包括多条栅线11和多条数据线12，多条栅线11和多条数据线12彼此交叉在显示区中定义出阵列分布的多个子像素区，每个子像素区设置一个子像素，每个子像素包括发光元件和驱动该发光元件的驱动电路。该驱动电路例如为常规的像素电路。例如，该驱动电路包括常规的2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数)像素电路，并且不同的实施例中，该驱动电路还可以进一步包括补偿电路，该补偿电路包括内部补偿电路或外部补偿电路，补偿电路可以包括晶体管、电容等。例如，根据需要，该驱动电路还可以进一步包括复位电路、发光控制电路、检测电路等。
例如，该显示基板还可以包括数据驱动电路6和栅极驱动电路7，该数据驱动电路和栅极驱动电路分别通过数据线12和栅线11与发光元件的驱动电路连接以提供电信号。该数据驱动电路用于提供数据信号，该栅极驱动电路用于提供扫描信号，还可以进一步用于提供各种控制信号、电源信号等。
需要说明的是，图1中仅示意性地示出该栅极驱动电路和数据驱动电路与子像素的连接关系，并不代表它们实际的位置关系，也并不作为对本公开的限制。例如，该显示基板采用硅基板作为衬底基板101，该驱动电路(像素电路)、该栅极驱动电路6和数据驱动电路7都可以集成于该硅基板上。在此情形下，由于硅基电路可以实现较高的精度，该栅极驱动电路6和数据驱动电路7例如可以形成于对应于该显示基板的显示区的区域中。
图2示出了图1所示显示基板沿剖面线A-A’的截面图的一个示例。
为了清楚起见，图2中仅示出了相邻的第一子像素区和第二子像素区中的第一子像素100a和第二子像素100b，并且对于每个子像素，仅示出了发光元件以及像素驱动电路中与该发光元件直接连接的晶体管。例如，该晶体管可以是驱动晶体管，配置为控制驱动发光元件发光的电流的大小。例如，该晶体管也可以为发光控制晶体管，用于控制驱动发光元件发光的电流是否流过。本公开的实施例对此不作限制。
如图2所示，该显示基板20包括衬底基板101、位于该衬底基板101上的介质层102以及位于该介质层远离衬底基板一侧101且依次层叠的第一电极层211、像素界定层230、有机功能层213和第二电极层212，该第一电极层211包括多个彼此间隔的电极，以分别作为该显示基板的多个发光元件的多个像素电极。如图2所示，该多个像素电极包括位于该第一子像素区的第一电极221和位于该第二子像素区的第二电极222；该第一电极221和第二电极222之间存在间隔G。
该第一电极221、第二电极层212以及该有机功能层213位于该第一电极221和第二电极层212之间的部分构成该第一子像素的发光元件，该第二电极222、第二电极层212以及该有机功能层213位于该第二电极222和第二电极层212之间的部分构成该第二子像素的发光元件。
该介质层102对应该间隔G设置有第一凹槽120，该间隔G暴露该第一凹槽120，也即该第一凹槽120设置在该第一电极221朝向该第二电极221的第一电极边缘221c和第二电极222朝向该第一电极的第二电极边缘222c边缘之间。
由于该第一凹槽120的存在，上方形成的有机功能层213和第二电极层212在对应该第一凹槽120处也相应地具有凹陷结构，从而使得有机功能层213在第一子像素和第二子像素之间发生凹陷，从而使得有机功能层中的漏电结构在凹陷处自然断开，从而有效避免有机功能层的横向漏电导致的第一子像素和第二子像素之间的串色，提高了该显示基板的色域，改善了显示质量。
图3示出了图1所示显示基板沿剖面线A-A’的电镜图的一个示例，图3中仅示出了该第一凹槽120及周边的局部示意图。
如图2-3所示，该第二电极层212在对应该第一凹槽120处包括凹陷结构130；例如，该凹陷结构130的在该截面内呈W形状，具有第一凹陷点V1和第二凹陷点V2，该第一凹陷点V1靠近第一电极221，该第二凹陷点V2靠近第二凹陷点V2。例如，该第二电极层212在该第一凹陷点V1处相较于在该第一凹陷点V1的周边处(例如以该第一凹陷点V1为中心10纳米、30纳米或50纳米范围内)距离衬底基板更近，该第二电极层在该第二凹陷点V2处相较于在该第二凹陷点V2的周边处(例如以该第二凹陷点V2为中心10纳米、30纳米或50纳米范围内)具有距离衬底基板更近。
图4示出了本公开至少一实施例提供的第一电极层211和像素界定层230的平面示意图，图4中还相应示出了剖面线A-A’的位置。
结合参考图2-4，该像素界定层230包括多个开口区232，该多个开口区232与该第一电极层211中的多个像素电极一一对应，每个开口区分别暴露对应的一个像素电极的至少部分从而定义出各发光元件的发光区。例如，如图2-4所示，该多个开口区232包括第一开口区232a和第二开口区232b，该第一开口区232a暴露出该第一电极221的至少部分，该第二开口区232b暴露出该第二电极222的至少部分。
有机功能层213通过各开口与各像素电极接触。例如，该像素界定层230的第一开口区232a和第二开口区232b分别暴露出第一电极221和第二电极222的至少部分。
该像素电极层230还包括位于该第一开口区232a和第二开口区232b之间的像素界定部231，该像素界定部231覆盖该第一凹槽120 并分别覆盖该第一电极221和第二电极222的一部分，从而分别将该第一电极221、第二电极222靠近该凹陷结构130的端部与该第二电极层212绝缘，降低第一电极层211与第二电极层212之间的短路风险。
如图2-3所示，该像素界定部覆盖该第一凹槽120并形成第二凹槽220，该第二凹槽220因继承了下方第一凹槽120的形貌所形成。在该截面内且与该衬底基板板面平行的第一方向D1上，该第二凹槽220具有相对的两个侧壁，也即第一侧表面220a和第二侧表面220b，该第一侧表面220a靠近第一电极221的第一侧表面220a以及靠近第二电极222的第二侧表面220b。
例如，像素界定层230的材料为无机绝缘材料，例如为硅的氮化物、氧化物或者氮氧化物。无机绝缘材料的质地较有机材料硬，比较容易塑型，因此更适合于高精度的显示基板，例如硅基显示基板。
例如，该像素界定层230的材料与该介质层102的材料相同或相近。
例如，由于该像素界定层230的材料与该介质层102的材料相同或相近，图3所示的电镜图中并不能明显地示出该像素界定层230与介质层102的分界线。
例如，该第一凹陷点V1和第二凹陷点V2在衬底基板上的正投影均位于该第二凹槽220在衬底基板上的正投影内，也即位于该第一侧表面220a和第二侧表面220b之间。在该截面内且与该衬底基板板面平行的第一方向D1上，该第一凹陷点V1与第二凹陷点V2的距离为d6(也称作y2)。该第一子像素与第二子像素在第一方向D1上相邻。
该第一凹陷点V1、第二凹陷点V2与该第一电极层211的距离需要进行控制，如果该距离太大则不能使得该有机功能层213在子像素之间充分地凹陷以使得其中的容易发生漏电的子功能层自然断开；如果该距离太小则容易提高第一电极层211与第二电极层212之间的短路风险。由于尖端放电效应，该第一凹陷点V1和第二凹陷点V2处的短路风险较大。
例如，第一凹陷点V1和第二凹陷点V2与衬底基板101的距离不同；例如，如图2和3所示，第二凹陷点V2与衬底基板101的距离更小。例如，该第二电极层212在第二凹陷点V2处的角度相较于在第一 凹陷点V1处的角度更尖锐。
这种设置可以增大该凹陷结构130底部的坡度，从而有助于进一步增大有机功能层213中的漏电结构的段差，使其更容易发生断裂。
该凹陷结构130和第二凹槽220由于该第一凹槽120的存在而形成，该凹陷结构130与第二凹槽220的形貌与该第一凹槽120的纵横比有关，该第二凹槽220基本继承了该第一凹槽120的形貌。例如，该第一凹槽120的纵横比小于或等于0.5。例如，如图2所示，该第一凹槽120的截面形状的底边为向上凸起的弧形，然而本公开实施例对此不作限制，在另一些实施例中，该第一凹槽120在该截面内的截面形状还可以是矩形、梯形、三角形等。例如，在图2所示的截面内，该第一凹槽120在垂直于衬底基板的方向上的最大尺寸与在第一方向D1上的最大尺寸的比值小于或等于0.5。例如，在图2所示的截面内，该第二凹槽220在垂直于衬底基板的方向上的最大尺寸与在第一方向D1上的最大尺寸d4的比值小于或等于0.5。
例如，如图2-3所示，该第二凹槽220在第一方向D1上的最大尺寸d4与间隔G在第一方向的长度的比值范围为1/2-2/3。
例如，在垂直于衬底基板的方向上，该第一凹陷点V1与衬底基板的距离和该第二凹陷点V2与衬底基板的距离不同。如图2所示，该第二凹陷点V2更靠近该衬底基板101。
例如，该第二电极层212在该第一凹陷点V1和第二凹陷点V2处的厚度不同。这也是由于该第二电极层212在第一凹陷点V1和第二凹陷点V2处凹陷程度不同造成的。
该间隔G还暴露该介质层102位于该第一电极221靠近该第一凹槽120的第一电极边缘221c和该第一凹槽120朝向该第一电极221的第一凹槽边缘120a之间的第一裸露部121以及该第二电极222靠近该第一凹槽120的第二电极边缘222c与该第一凹槽120朝向该第二电极222的第二凹槽边缘120b之间的第二裸露部122。该第一裸露部121和第二裸露部122均为该介质层102未被第一电极层211覆盖的部分。
通过设置该第一裸露部121和第二裸露部122，分别拉大了该第一电极221的边缘/第二电极222的边缘与该第一凹槽120的边缘之间的 间距，从而分别拉大了该第一电极221与该第二电极层212的第一凹陷点V1的距离以及该第二电极222与第二凹陷点V2的距离，降低了第一电极层与第二电极层的短路风险。
如图2-3所示，该第一电极221包括远离衬底基板的第一表面221a，该第一表面221a为该第一电极221的上表面。例如该第一表面221a与该衬底基板的板面平行，也即与第一方向D1平行。
在该截面内且在与该衬底基板板面平行的第一方向D1上，该像素界定部231位于该第一电极221的第一表面221a上的部分(也即与该第一表面221a在垂直于衬底基板的方向上重叠的部分)的长度为d1(也称L3)。
例如，该第一方向D1为第一子像素指向第二子像素的方向，也即第一子像素与第二子像素在第一方向上相邻。例如，如图4所示，该第一方向D1可以是第一子像素的开口区在衬底基板上的正投影的几何中心O1指向第二子像素的开口区在衬底基板上的正投影的几何中心O2的方向。然而，本公开并不对第一方向D1进行限定。
如图2-3所示，该第一电极211还包括远离衬底基板的第二表面221b，例如，该第二表面221b与该第一方向D1平行，该第二表面221b与第一表面221a平行。
该第二表面221b相较于该第一表面221a更靠近衬底基板101。例如，如图2所示，该第一表面221a与第二表面221b之间由第三表面连接，该第三表面为一个斜面。在图3中，由于该第三表面在第一方向D1的尺寸很小从而被省略了，该第一表面221a和第二表面221b可以近似看作连续的表面。
例如，如图2-3所示，该第一电极层211包括层叠的第一子电极层和第二子电极层，第二子电极层位于第一子电极层远离衬底基板的一侧。该第一电极221和第二电极222分别包括层叠的第一子电极211a和第二子电极211b，该第二子电极211b位于第一子电极211a远离介质层102的一侧。例如，该第二子电极211b包覆第一子电极211a的侧表面并与该介质层102接触形成该第一电极221的第二表面221b。由 此，该第一电极221的第一表面221a与第二表面221b形成台阶状结构，降低了位于该第一电极221上方的像素界定部231的段差。当该像素界定层的材料为无机绝缘材料时，质地较脆，该台阶状结构可以防止该像素界定层因段差太大而发生断裂。
例如，像素界定部231的与该第一电极211的第二表面211b接触的部分的平均厚度大于该第一电极211在该第二表面211b处的平均厚度。
例如，该第一子电极层的材料可包括钛(Ti)、第二子电极层的材料包括银(Ag)。第一子电极层的材料的导电率较高，可以降低与衬底基板上线路的接触电阻；第二子电极层的材料的反射率较高，可以提高顶发射发光元件的出光效率。
在另一些示例中，该第一电极层还可以包括位于第二子电极层远离第一子电极层一侧的第三子电极层，该第三子电极层的材料例如为透明导电材料，例如为ITO、IZO、IGZO、AZO等具有高功函数的导电材料，与有机功能层213直接接触可以提高空穴注入率。
例如，第二电极层的材料可以为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，如图2-3所示，该第二电极层212包括第一凸起部241，该第一凸起部241与该第一电极221在垂直于所述衬底基板的方向至少部分重叠。
例如，该第一凸起部241对应于该第一电极221的第一表面221a和第二表面221b之间，例如，该第一凸起部241由于该第一电极221的第一表面221a和第二表面221b之间的段差或者由像素界定部231所引起的。
例如，在垂直于衬底基板的方向上，该第一凸起部241分别与该第一表面221a和第二表面221b至少部分重叠。
例如，在垂直于衬底基板的方向上，该第一凸起部241与像素界定部231至少部分重叠。
该第一凸起部241在所述截面内具有第一凸起点P1。例如，该第一凸起部241在该第一凸起点P1处相较于在该第一凸起点P1的周边处(例 如以该第一凸起点P1为中心10纳米、30纳米或50纳米范围内)距离衬底基板更远。例如，该第一凸起点P1在衬底基板的正投影落入该像素界定部231在衬底基板上的正投影内。
例如，该第一凸起点P1的凸起高度h1大于所述第二电极层212的平均厚度。例如，该凸起高度h1以该第二电极层212与第一方向D1平行(也即与衬底基板板面平行)的平面为基准。
例如，如图2-3所示，该第二电极层212包括第二凸起部(未示出)，该第二凸起部该第二电极222在垂直于衬底基板的方向上至少部分重叠。
例如，像素电极部231在衬底基板上的正投影位于该第一凸起部241在衬底基板上的正投影和该第二凸起部在衬底基板上的正投影之间。
例如，该第二凸起部也包括凸起点，该第二凸起部的凸起点在衬底基板的正投影落入该像素界定部231在衬底基板上的正投影内。
例如，如图2-3所示，该凹陷结构130还包括位于该截面内的第二凸起点P2，该第二凸起点P2位于该第一凹陷点V1和第二凹陷点V2之间，该第二凸起点P2到该衬底基板的距离分别大于该第一凹陷点V1及该第二凹陷点V2到该衬底基板的距离。
例如，该第二电极层212在该第二凸起点P2处相较于在该第二凸起点P2的周边处(例如以该第二凸起点P2为中心10纳米、30纳米或50纳米范围内)距离衬底基板更远。
例如，该第二凸起点P2与该第一凹陷点V1及第二凹陷点V2的高度差的较大值△h为该第二凸起点P2的凸起高度；如图3所示，由于该第二凹陷点V2相较于第一凹陷点V1更靠近衬底基板，该第二凸起点P2的凸起高度△h为该第二凸起点P2与该第二凹陷点V2的高度差。
例如，△h大于所述第一凹陷点和所述第二凹陷点的高度差。
例如，△h大于所述第二电极层212的平均厚度。
例如，如图2所示，△h小于所述第一凸起点P的凸起高度h1。然而这并不作为对本公开实施例的限制，例如，如图3所示，△h大于所述第一凸起点的凸起高度。
例如，如图2所示，该第二凹槽220的截面形状的底边为向上凸起的弧形，包括位于所述截面内的第三凸起点P3，该第三凸起点P3位于 该第一凹陷点V1和所述第二凹陷点V2之间，即第三凸起点P3在衬底基板上的正投影位于该第一凹陷点V1在衬底基板上的正投影和所述第二凹陷点V2在衬底基板上的正投影之间。
例如，如图2所示，该第三凸起点P3的曲率小于所述第一凸起点P1的曲率，该第三凸起点P3的曲率小于第二凸起点P2的曲率。
如图2-3所示，在该截面内且在该第一方向D1上，该像素界定部231位于该第一电极的第二表面221b上的部分(也即与该第二表面在垂直于衬底基板的方向上重叠的部分)的长度为d2(也称作L4)。
如图2-3所示，在该截面内且在该第一方向D1上，该第二凹槽220的第一侧表面220a与该第一电极221的第一电极边缘221c之间的距离为d3(也称作L1)。
在该截面内，该距离d3大于该第一凹陷点V1与该第二凹槽220的第一侧表面(也即该像素界定层的侧表面)220a之间的距离d5(也称作L2)。
通过这种设置，可以缓解甚至避免在该第一电极221与第二电极层212之间最近的地方、第一电极221与第二电极层212之间的短路现象以及第二电极层212的穿刺现象。
例如，如图2-3所示，该像素界定部231包括远离衬底基板的第一表面(也即上表面)，图3中用曲线示意性地示出了该像素界定部231的第一表面231s。该像素界定部的第一表面231s包括对应于该第一电极221的第一电极边缘221c的第一斜面z1以及与该第一侧表面220a连接的第二斜面z2。
在垂直于衬底基板的方向上，该第一斜面z1与该第一电极边缘221c至少部分重叠；该第二斜面z2与该第一凹槽边缘120a至少部分重叠。
例如，如图2-3所示，该第一斜面z1与该第二斜面z2均包括曲面；例如，该第一斜面z1与该第二斜面z2在该截面内的形状均包括弧形。
该第一斜面z1由该第一电极221中的第一子电极211a和第二子电极211b之间的台阶所引起，该第二斜面z2由该第一凹槽120的第一凹槽边缘120a所引起。例如，由于刻蚀的各向同性并不是理想的，该像素界定层在覆盖下方的台阶形状时会出形成曲面形状，而不是理想的直 角。
例如，如图2-3所示，该像素界定部231的第一表面231s还包括位于该第一斜面z1与该第二斜面z2之间的连接表面231c。例如，该连接表面231c的至少部分为平面。
由于该第二凹槽220的第一侧表面220a与该第一电极221的第一电极边缘221c之间的距离d3足够长，因此该第一斜面z1与第二斜面z2并不直接连接，从而该第一表面231a在该第一斜面z1与第二斜面z2之间出现了过渡的平面部分。例如，该连接表面231c整个为平面。
例如，如图2所示，在该截面内，该连接表面231c的长度y3大于该像素界定层230的平均厚度。
例如，如图2所示，在该截面内，该连接表面231c的长度y3与L3的比值大于1/3。
例如，如图2-3所示，d5小于d2。例如，d5大于像素界定层230的平均厚度。
例如，如图2-3所示，该距离d3还大于该像素界定部231位于该第一电极221的第一表面221a上的部分的长度d1。然而，本公开实施例并不限于此。在另一些实施例中，该距离d3也可以小于或者等于d1。
例如，如图2-3所示，该像素界定部231位于该第一电极的第二表面221b上的部分的长度为d2大于该第一凹陷点V1与该第二凹槽220的第一侧表面220a之间的距离d5。
由于第一电极内缩形成该第一裸露部，拉大了第一电极与第二电极层之间的距离，降低了二者的短路风险，因此，该像素界定部231覆盖该第一电极221的第一表面221a上的部分的长度d1可以适当缩小，从而可以有助于提高开口区的大小，提高开口率。
参考图2和图3，该像素界定部231位于该第一电极221的第一表面221a上的部分的长度d1小于该像素界定部231位于该第一电极的第二表面221b上的部分的长度d2。
例如，如图2和图3所示，该像素界定部231位于该第一电极221的第一表面221a上的部分的长度d1还小于该距离d3。
例如，d1还小于像素界定层230的平均厚度。
例如，如图3所示，在所述截面内且在所述第一方向上，该第一电极221a的长度为f1，f1与该距离d3(也称作L1)的比值范围为：8-20。
例如，d3与y2的比值大于1/2。
该距离d3太小，则不利于拉大该第一电极221与第二电极层212之间的距离以及降低短路风险；该距离d3太大，则不利于开口率的提高。
例如，该距离d3范围为0.1微米-0.2微米，例如为0.12微米或者0.15微米。
例如，如图2和图3所示，该像素界定部231位于该第一电极221的第一表面221a上的部分的长度d1大于该第一凹陷点V1与该第二凹槽220的第一侧表面220a在第一方向D1上的距离d5。
例如，如图3所示，在该截面内，该像素界定部231位于该第二凹槽220的第一侧表面220a靠近该第一电极221一侧的部分在第一方向D1上的长度y1大于该第二凹槽220在第一方向D1上的最大尺寸d4(也称作L5)。
例如，在该截面内，该像素界定部231位于该第二凹槽220的第一侧表面220a靠近该第一电极221一侧的部分在第一方向D1上的长度y1还大于第一凹陷点V1与第二凹陷点V2在第一方向上的距离d6。
将该像素界定部231靠近该第一电极221一侧设置得较长可以提高该像素界定部231的绝缘性能，降低第一电极221与第二电极层212的短路风险。然而这并不作为对本公开的限制。
例如，如图3所示，在该截面内且在该第一方向D1上，该第二凹槽220的第二侧表面220b与该第二电极222之间的距离d3’(也称作L1’)大于该第二凹陷点V1与该第二凹槽220的第二侧表面220b之间的距离d5’(也称作L2’)。
发明人发现，用于制作像素界定层(PDL)230的掩膜板在形成过程中由于工艺原因存在周期性的差异，这种周期性的差异使得制作出来的像素界定层中的开口区232的尺寸存在周期性差异。这种周期性差异最终会导致显示装置在显示时出现横纹或竖纹，发生显示不均。
图5A示出了该像素界定层的掩膜板的形成原理，图5B示出了使 用该掩膜板形成的像素界定层的平面示意图，图5B中仅示意性地示出了像素界定层中的开口区232。
例如，该掩膜板在制作时首先需整面涂覆一层金属膜(例如为铬膜)，然后对该金属膜进行激光烧蚀形成网孔图案。在进行烧蚀时，需要分段进行烧蚀，而第二次烧蚀时，为防止遗漏某一段，进行回位一段距离(例如6-8um)再进行烧蚀从而形成重复烧蚀区。重复烧蚀区与一次烧蚀区域存在细微差异，例如，重复烧蚀区的网孔比一次烧蚀区的网孔尺寸较大；这样形成的像素界定层的开口区相应地表现出细微规律性差异，使得最终的显示产品在显示时出现规律横纹或竖纹的显示不均，影响产品显示效果。这种显示不均的现象在高分辨率的显示产品上表现得尤为明显。
如图5A所示，例如，烧蚀的方向为与该第一方向D1垂直的第二方向D2，在该第二方向D2上，一次烧蚀区与重复烧蚀区交替出现并成周期规律；相应地，如图5B所示，使用该掩膜板形成的像素界定层的开口区的尺寸在第二方向D2发生周期性的规律变化；例如，像素界定层的T1段对应于一次烧蚀区，T2段对应于重复烧蚀区。
发明人又发现，该显示不均的严重程度与开口区的尺寸有关，开口区越大，显示不均越不明显，影响越小。例如，如图2所示，在该截面内，该第一子像素的开口区232沿第一方向D1的长度x1越小，该开口区232的尺寸的周期性差异对显示均一性的影响越严重。
例如，开口区232沿第一方向D1的长度可能在像素界定层的厚度方向上具有不同的值，由于子像素的有效发光区由该开口区232沿第一方向D1的长度的最小值决定，这里开口区232沿第一方向D1的长度x1即定义为该最小值。例如，如图2所示，开口区232在靠近衬底基板的一端与远离基板的一端的尺寸不同，x1取开口区232远离衬底基板的一端的尺寸，也即最小尺寸。
本公开至少一实施例提供一种显示基板，对该像素界定部231位于该第一电极221的第一表面221a上的部分的长度d1进行了窄化，从而增大开口区232的长度x1，不仅有助于提高显示基板的开口率，还可以降低开口区232的尺寸的周期性差异对显示均一性的影响，从而提高 显示基板的显示均一性。
图6示出了图1所示显示基板沿剖面线A-A’的电镜图的另一些示例。参考图2和图6，该像素界定部231位于该第一电极221的第一表面221a上的部分(也即与该第一表面221a在垂直于衬底基板的方向上重叠的部分)的长度d1小于该像素界定部231位于该第一电极的第二表面221b上的部分(也即与该第二表面221b在垂直于衬底基板的方向上重叠的部分)的长度d2。
例如，如图2和图6所示，该像素界定部231位于该第一电极221的第一表面221a上的部分的长度d1还小于该第二凹槽220的第一侧表面220a与该第一电极221的第一电极边缘221c之间的距离d3。
例如，d1还小于像素界定层230的平均厚度。
例如，如图2和图6所示，该像素界定部231位于该第一电极221的第一表面221a上的部分的长度d1还小于该第一凹陷点V1与该第二凹槽220的第一侧表面220a在第一方向D1上的距离d5。
例如，在如图2所示的截面内，该像素界定部231靠近该第一电极221一侧的部分在第一方向D1上的长度y1大于第一凹陷点V1与第二凹陷点V2在第一方向上的距离d6。
将该像素界定部231靠近该第一电极221一侧设置得较长可以提高该像素界定部231的绝缘性能，降低第一电极221与第二电极层212的短路风险。然而这并不作为对本公开的限制。
例如，如图6所示，在该截面内，该像素界定部231靠近该第一电极221一侧的部分在第一方向D1上的长度y1小于该第二凹槽220在第一方向D1上的最大尺寸d4。
例如，如图6所示，在该截面内，该像素界定部231位于第二凹槽220的第一侧表面220a靠近该第一电极221一侧的部分在第一方向D1上的长度y1小于该第一凹陷点V1与第二凹陷点V2在第一方向D1上的距离d6。
例如，在该截面内，该像素界定部231位于该第二凹槽220的第一侧表面220a靠近该第一电极221一侧的部分在第一方向D1上的长度y1还小于第一凹陷点V1与第二凹陷点V2在第一方向上的距离d6。
在像素密度一定的情形下，y1越小，相邻子像素的开口区232之间的间隔越小，那么子像素的开口区232越大，不仅有助于提高显示基板的开口率，还可以降低开口区232的尺寸的周期性差异对显示均一性的影响，从而提高显示基板的显示均一性。
例如，如图2和图6所示，该第二电极222包括远离衬底基板且与该衬底基板板面平行的第一表面222a在该截面内且在第一方向D1上，该像素界定部231位于该第二电极222的第一表面222a上的部分的长度为d1’，该像素界定部231位于该第二电极222的第一表面222a上的部分的长度d1’与该像素界定部231位于该第一电极221的第一表面221a上的部分的长度d1不相等。例如，如图2所示，d1小于d1’。
通过上述设置，使得第一子像素的开口区231沿第一方向D1的尺寸x1与第二子像素的开口区231沿第一方向D1的尺寸x2不同，从而使得位于同一像素界定层周期内(例如均位于像素界定层的T1段或者T2段)的第一子像素与第二子像素具有不同尺寸的开口区，对同一周期内的子像素的开口区的规律性进行了干扰，避免了横纹或竖纹的产生，从而提高了显示的均一性。
例如，如图6所示，该第二电极层212在对应该第一电极221的第一表面221a和第二表面221b之间包括第一凸起部241，例如，该第一凸起部241由于该第一电极221的第一表面221a和第二表面221b之间的段差或者由像素界定部231所引起的。
例如，在垂直于衬底基板的方向上，该第一凸起部241分别与该第一表面和第二表面至少部分重叠。
该第一凸起部241在所述截面内具有第一凸起点P1。例如，该凸起部241在该第一凸起点P1处相较于在该第一凸起点P1的周边处(例如以该第一凸起点P1为中心10纳米、30纳米或50纳米范围内)距离衬底基板更远。
例如，该第一凸起点P1的凸起高度h1大于所述第二电极层212的平均厚度。例如，该凸起高度h1以该第二电极层212与第一方向D1平行(也即与衬底基板板面平行)的平面为基准。
例如，如图2-3所示，该凹陷结构130还包括位于该截面内的第二凸 起点P2，该第二凸起点P2位于该第一凹陷点V1和第二凹陷点V2之间，该第二凸起点P2到该衬底基板的距离分别大于该第一凹陷点V1及该第二凹陷点V2到该衬底基板的距离。例如，该第二电极层212在该第二凸起点P2处相较于在该第二凸起点P2的周边处(例如以该该第二凸起点P2为中心10纳米、30纳米或50纳米范围内)距离衬底基板更远。
例如，该第二凸起点P2与该第一凹陷点及所述第二凹陷点的高度差的较大值△h为该第二凸起点P2的凸起高度；如图3所示，由于该第二凹陷点V2相较于第一凹陷点V1更靠近衬底基板，该第二凸起点P2的凸起高度△h为该第二凸起点P2与该第二凹陷点V2的高度差。
例如，△h大于所述第一凹陷点和所述第二凹陷点的高度差。
例如，△h大于所述第二电极层212的平均厚度。
例如，如图6所示，△h大于所述第一凸起点P1的凸起高度h1。
例如，图6所示第二电极层212相较于图3所示的第二电极层212更平坦。例如，图6所示的第一凸起点P1的凸起高度h1小于图3所示的第一凸起点P1的凸起高度h1。
图7为本公开另一些实施例提供的显示基板的示意图，为了清楚起见，图中省略了第一电极层下方的电路结构。如图7所示，像素界定部231包括远离衬底基板101的第一表面231a，该像素界定部231的第一表面231a在图7所示的截面的正投影为第一曲线n1，该第一曲线n1也就是该像素界定部231在该截面内的上轮廓。该第一曲线n1在靠近第一电极221的端点处的第一切线S1与第一方向D1相交。
由于像素界定部231靠近第一电极/第二电极端部的形貌容易对子像素的开口区的大小影响。本公开至少一实施例通过将该像素界定部231靠近第一电极和/或第二电极的端部形成为翘起结构，容易对开口区的大小进行微调，从而对上述开口区的周期性规律进行干扰，提高显示均一性。
例如，如图7所示，该第一曲线n1在靠近第二电极222的第二切线S2与第一方向D1相交。例如，该第一切线S1与第二切线S2相交。
例如，如图7所示，该第一切线S1与第一方向成第一夹角β1，该第二切线S2与第一方向成第二夹角β2，第一夹角β1与第二夹角β2 不相等。
通过上述设置，该像素界定部231在靠近第一电极和第二电极的两个端部的形貌不同，从而能够得到像素界定部231的两端分别得到不同尺寸的开口区，有助于提高显示均一性。
例如，该第一切线S1与衬底基板的交点位于该第一电极221靠近第二电极222的一侧，该第二切线S2与衬底基板的交点位于该第二电极222靠近第一电极221的一侧；也即，该像素界定部231在靠近第一电极和第二电极的两个端部分别朝向上方(也即远离衬底基板的方向)翘起。
例如，上述开口区的结构可以通过在对像素界定层材料的构图工艺中先进行干刻工艺然后进行湿刻工艺形成。由于干刻工艺精度较高，可以对开口区进行定位并形成开口区的大致轮廓，然后再进行湿刻工艺形成最终的开口区的形貌；由于湿法刻蚀工艺精度没有干刻精度高，并且具有随机性，因此，在干刻后进行湿刻可以对开口区的形貌进行随机的细微调整，打破上述开口区的规律，提高显示均一性。例如，干刻工艺的时间长于湿刻工艺的时间。
例如，由于湿法刻蚀具各向同性，并且在刻蚀中容易发生横向钻蚀，因此像素界定部的端部容易形成如图7所示的向上翘起的结构，开口区的截面形状近似于正梯形，也即该开口区232远离衬底基板一端的尺寸小于其靠近衬底基板一端的尺寸。
例如，如图7所示，第一子像素的开口区232在该截面内具有在第一方向D1上相对的第一边t1和第二边t2，该第一边t1与第一电极221的第一表面221a成夹角β3，该第二边t2与第一电极221的第一表面221a成夹角β4，β3与β4不相等。
图8为本公开又一些实施例提供的显示基板的示意图。图8所示显示基板与图2所示显示基板的主要区别在于该第一凹槽120的截面形状为正梯形。
例如，如图8所示，该正梯形具有靠近第一电极221的第一底角和靠近第二电极222的第二底角。例如，该第一底角和第二底角不相等。
例如，在如图8所示的截面内，该像素界定部231靠近第一电极 221的端部具有第三底角，该第三底角的角平分线k2与该第一底角的角平分线k1不平行。
需要说明的是，在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
例如，该衬底基板101可以是硅，例如为单晶硅或者高纯度硅；介质层102可以是硅上形成的硅的氧化物、氮化物或者氮氧化物。该衬底基板101和介质层102构成驱动基板201，子像素的驱动电路可以集成于驱动基板201中，并通过介质层102中的接触孔与像素电极(例如第一电极221和第二电极222)电连接从而驱动发光元件发光。
例如，通过掺杂工艺在驱动基板201中形成晶体管的有源层(即半导体层)、第一极和第二极，并通过硅氧化工艺形成绝缘层、以及通过溅射工艺形成多个导电层105、106等。晶体管的半导体层(如图2中的有源层322)位于衬底基板101的内部，或者为衬底基板101的一部分。
例如，像素驱动电路包括互补型金属氧化物半导体电路(CMOS电路)。例如，上述栅极驱动电路6和数据驱动电路7也可以通过上述半导体工艺集成在驱动基板201中。该栅极驱动电路和数据驱动电路可以采用本领域内的常规电路结构，本公开的实施例对此不作限制。
如图2所示，第一电极221和第二电极222形成于该驱动基板201的表面，并通过填充有导电材料(例如为钨)的接触孔103以及该多个导电层与第一晶体管203的第一极323实现电连接。图2中在晶体管的上方示例性地示出了两层导电层105、106，然而本公开实施例对于导电层的层数不作限制。
例如，如图2所示，驱动基板201中的最顶层导电层106具有反射性，例如为钛/氮化钛/铝的层叠结构。例如，该导电层106包括间隔设置的多个子层，分别与第一电极层211中的多个像素电极(例如第一电极221和第二电极222)一一对应设置。在顶发射结构中，该导电层106可以设置为反射层，用于反射发光元件发出的光线，提高出光效率。例如，第一电极层211中的每个像素电极在衬底基板101上的正投影落入该像素电极对应的导电层106的部分在该衬底基板101上的正投影内。
有赖于成熟的CMOS集成电路技术，硅基工艺可以实现较高的精度(例如PPI可以达到6500甚至一万以上)。例如，第一电极221与第二电极222之间的间隔G在第一方向的长度小于1微米，例如为700纳米-900纳米。
例如，该发光元件可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等，本公开实施例对于发光元件的类型不作限定。例如，OLED的发光层可以为小分子有机材料或高分子有机材料。
该有机功能层213包括在垂直于衬底基板101方向上彼此堆叠的多个子功能层，该多个子功能层的至少一个在对应第一凹槽120处断开。
例如，该多个子功能层包括至少一个载流子注入层和至少一个发光层。该载流子注入层可以是电子注入层(EIL)或空穴注入层(HIL)。电子注入层位于发光层靠近阴极的一侧，用于降低从阴极注入电子的势垒，使电子能从阴极有效地注入到发光层中。空穴注入层位于发光层靠近阳极的一侧，用于降低从阳极注入空穴的势垒，使空穴能从阳极有效地注入到发光层中。因此，在选择电子/空穴注入层材料的时候，需要考虑材料能级和电极材料的匹配。例如，电子注入层材料可以是LiQ(8-羟基喹啉锂)、AlQ3(8-羟基喹啉铝)等；空穴注入层的材料可以是CuPc(聚酯碳酸)，TiOPc、m-MTDATA、2-TNATA等。
例如，该有机功能层213根据需要还可以包括电子/空穴传输层、电子/空穴阻挡层、电荷生成层等。
例如，为了提高发光效率以及发光器件的色域，也可以采用多层彼此堆叠的发光层发白光，也即该有机功能层213包括多个发光层，该多个发光层在垂直于衬底基板101的方向上堆叠。例如，该有机功能层213包括彼此堆叠的两个发光层(黄蓝)或三个发光层(红绿蓝)。
例如，该多个发光层中的至少两个彼此通过电荷生成层(CGL)串联形成串联结构(tandem结构)，该电荷生成层包括N型电荷生成层以及P型电荷生成层，用于平衡载流子的输送。该N型电荷产生层可以由掺杂有诸如锂(Li)、钠(Na)、钾(K)或铯(Cs)的碱金属或诸如镁(Mg)、锶(Sr)、钡(Ba)或镭(Ra)的碱土金属(但不限于它们中的任何一种)的有机层形成；该P型电荷产生层可以由通过将 具有空穴传输能力的有机基质材料与掺杂剂掺杂而获得的有机层形成。串联结构有助于提高器件的发光效率和发光亮度。
例如，由于该电荷生成层中包括金属元素，容易在子像素之间发生漏电而导致串色。本公开至少一实施例提供的显示基板通过在有机功能层213中对应子像素之间设置有凹陷结构130，使得该电荷生成层在该凹陷结构130处由于段差较大而自然断开，从而有效避免有机功能层的横向漏电导致的子像素间串色，提高了该显示基板的色域，改善了显示质量。
继续参照图2，图2分别示出了与第一子像素和第二子像素的发光元件电连接的第一晶体管203和第二晶体管204。本公开的实施例对第一晶体管203和第二晶体管204的具体类型不作限制。以下对第一晶体管203进行示例性说明，该说明也适用于第二晶体管204，因而不再赘述。
例如，第一晶体管203包括栅极321、栅极绝缘层325、有源层322、第一极323和第二极324。本公开的实施例对于第一晶体管203的类型、材料、结构不作限制，例如其可以为顶栅型、底栅型等，第一晶体管203的有源层可以为微晶硅、非晶硅、多晶硅(低温多晶硅或高温多晶硅)、氧化物半导体(例如IGZO)等无机半导体材料，或者还可以为有机材料，例如为PBTTT、PDBT-co-TT、PDQT、PDVT-10、二萘并-并二噻吩(DNTT)或并五苯等有机半导体材料。例如，第一晶体管203可以为N型或P型。
需要说明的是，本公开实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的一些实施例以形成在硅基板中的场效应晶体管(如MOS场效应晶体管)为例进行说明，在该示例中，对硅基板进行掺杂(p型掺杂或n型掺杂)形成晶体管的有源层，也即晶体管的有源层位于硅基板内，或者晶体管的有源层为硅基板的一部分。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，例如，可直接描述了其中一极为第一极，另一极为第二极。
例如，如图3和图6所示，该显示基板20还可以包括位于第二电极层212远离衬底基板一侧的光提取层214。例如，该光提取层214的折射率大于第二导电层212的折射率，从而可提高出光效率。
例如，如图3和图6所示，该显示基板20还可以包括位于光提取层214远离衬底基板一侧的封装层215。例如，该封装层215配置为对发光元件进行密封以防止外界的湿气和氧向该发光元件及像素电路的渗透而造成对器件的损坏。例如，封装层215包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层215与发光元件之间还可以设置吸水层，配置为吸收发光元件在前期制作工艺中残余的水汽或者溶胶。
例如，如图3所示，该显示基板20还可以包括位于封装层215远离衬底基板一侧的彩膜层216。例如，该显示基板的发光元件配置为发白光，并结合彩膜层实现全彩显示。
例如，该显示基板20为有机发光二极管(OLED)显示基板或微型OLED(Micro OLED)显示基板。
本公开实施例还提供一种电子装置，包括上述显示基板20。图9示出了本公开至少一实施例提供的电子装置40的示意图。例如，该电子装置40为数码相框、智能手环、智能手表、手机、平板电脑、显示器、笔记本电脑、导航仪等具有任何显示功能的产品或者部件。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，包括相邻的第一子像素区和第二子像素区，
    位于所述衬底基板上的介质层，以及
    位于所述介质层远离所述衬底基板一侧且依次层叠的第一电极层、像素界定层、有机功能层和第二电极层，所述第一电极层包括位于所述第一子像素区的第一电极和位于所述第二子像素区的第二电极，
    其中，所述像素界定层包括第一开口区和第二开口区以及位于所述第一开口区和所述第二开口区之间的像素界定部，所述第一开口区暴露所述第一电极的至少部分，所述第二开口区暴露所述第二电极的至少部分，所述像素界定部还分别覆盖所述第一电极和所述第二电极的一部分；
    所述第一电极包括远离所述衬底基板的第一表面和第二表面，且所述第一电极的第二表面相较于所述第一表面更靠近所述衬底基板；
    所述显示基板具有与所述衬底基板垂直的截面，在所述截面内且在平行于所述衬底基板板面的第一方向上，所述像素界定部位于所述第一电极的第一表面上的部分的长度为d1，所述像素界定部位于所述第一电极的第二表面上的部分的长度为d2；
    d1小于d2。
  2. 如权利要求1所述的显示基板，其中，所述第一电极包括层叠的第一子电极和第二子电极，所述第二子电极位于所述第一子电极远离所述介质层的一侧；
    所述第二子电极包覆第一子电极的侧表面并与所述介质层接触形成所述第一电极的所述第二表面。
  3. 如权利要求1或2所述的显示基板，其中，所述像素界定部的与所述第一电极的第二表面接触的部分的平均厚度大于所述第一电极在所述第二表面处的平均厚度。
  4. 如权利要求1-3任一所述的显示基板，其中，所述第一电极和所 述第二电极之间存在间隔，所述介质层对应所述间隔的部分包括第一凹槽，所述间隔暴露所述第一凹槽；所述像素界定部覆盖所述第一凹槽并形成第二凹槽；
    所述间隔还暴露所述介质层位于所述第一电极靠近所述第一凹槽的第一电极边缘与所述第一凹槽朝向所述第一电极的第一凹槽边缘之间的第一裸露部；
    在所述截面内且在所述第一方向上，所述第二凹槽靠近所述第一电极的第一侧表面与所述第一电极边缘之间的距离为d3，d3大于d1。
  5. 如权利要求4所述的显示基板，其中，在所述截面内且在所述第一方向上，所述像素界定部位于所述第二凹槽的第一侧表面靠近所述第一电极一侧的部分的长度为y1，且所述第二凹槽的最大长度为d4；
    y1小于d4。
  6. 如权利要求5所述的显示基板，其中，所述第二电极层对应所述第一凹槽的部分包括凹陷结构，所述凹陷结构包括位于所述截面的第一凹陷点和第二凹陷点，所述第一凹陷点和所述第二凹陷点在所述衬底基板上的正投影均位于所述第二凹槽在所述衬底基板上的正投影内；
    所述第一凹陷点与所述第二凹槽的第一侧表面在所述第一方向上的距离为d5，d5大于d1。
  7. 如权利要求6所述的显示基板，其中，所述第一凹陷点和所述第二凹陷点在所述第一方向上的距离为d6，y1大于d6。
  8. 如权利要求6或7所述的显示基板，其中，所述第一凹陷点与所述第二凹陷点与所述衬底基板的距离不同。
  9. 如权利要求6-8任一所述的显示基板，其中，所述第二电极层包括凸起部，所述凸起部与所述第一电极在垂直于所述衬底基板的方向至少部分重叠；
    所述凸起部在所述截面内具有第一凸起点，所述第一凸起点的凸起高度大于所述第二电极层的平均厚度。
  10. 如权利要求9所述的显示基板，其中，所述凹陷结构还包括位于所述截面内的第二凸起点，所述第二凸起点位于所述第一凹陷点和所述第二凹陷点之间，所述第二凸起点到所述衬底基板的距离分别大于所述第一凹陷点及所述第二凹陷点到所述衬底基板的距离；
    所述第二凸起点与所述第一凹陷点及所述第二凹陷点的高度差的较小值为△h。
  11. 如权利要求10所述的显示基板，其中，△h大于所述第一凹陷点和所述第二凹陷点的高度差。
  12. 如权利要求10或11所述的显示基板，其中，△h小于所述第一凸起点的凸起高度。
  13. 如权利要求6-12任一所述的显示基板，其中，所述第二电极层在所述第一凹陷点和所述第二凹陷点的厚度不同。
  14. 如权利要求1-13任一所述的显示基板，其中，所述像素界定部包括远离所述衬底基板的第一表面，所述第一表面在所述截面的正投影为第一曲线，所述第一曲线在靠近所述第一电极的端点处具有第一切线，所述第一切线与所述第一方向相交。
  15. 如权利要求14所述的显示基板，其中，所述第一曲线在靠近所述第二电极的端点处具有第二切线，所述第二切线与所述第一方向相交；
    所述第一切线和所述第二切线与所述第一方向所成的夹角不同。
  16. 如权利要求14或15所述的显示基板，其中，所述第一切线与所述衬底基板的板面的交点位于所述第一电极靠近所述第二电极的一 侧。
  17. 如权利要求1-16任一所述的显示基板，其中，
    在所述第一方向上，所述第一开口区的长度与所述第二开口区的长度不同。
  18. 如权利要求1-17任一所述的显示基板，其中，所述第一开口区在所述截面上具有在所述第一方向上相对的第一边和第二边，所述第一边和所述第二边与所述第一电极的第一表面所成的夹角不同。
  19. 如权利要求1-18任一所述的显示基板，其中，所述第二电极包括远离所述衬底基板的第一表面，所述第二电极的第一表面与所述衬底基板板面平行；
    在所述截面内且在所述第一方向上，所述像素界定部位于所述第二电极的第一表面上的部分的长度为d1’；
    d1与d1’不相等。
  20. 一种电子装置，包括如权利要求1-19任一所述的显示基板。
PCT/CN2021/112067 2021-08-11 2021-08-11 显示基板及电子装置 WO2023015487A1 (zh)

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KR20050098596A (ko) * 2004-04-08 2005-10-12 삼성에스디아이 주식회사 유기 전계 발광 표시장치 및 그 제조 방법
CN110993806A (zh) * 2019-11-06 2020-04-10 深圳市华星光电半导体显示技术有限公司 一种oled显示面板及其制备方法
CN111668381A (zh) * 2020-06-19 2020-09-15 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN111668382A (zh) * 2020-06-19 2020-09-15 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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CN110993806A (zh) * 2019-11-06 2020-04-10 深圳市华星光电半导体显示技术有限公司 一种oled显示面板及其制备方法
CN111668381A (zh) * 2020-06-19 2020-09-15 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
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