WO2020140767A1 - 透明显示基板及其制作方法和透明显示面板 - Google Patents

透明显示基板及其制作方法和透明显示面板 Download PDF

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WO2020140767A1
WO2020140767A1 PCT/CN2019/126874 CN2019126874W WO2020140767A1 WO 2020140767 A1 WO2020140767 A1 WO 2020140767A1 CN 2019126874 W CN2019126874 W CN 2019126874W WO 2020140767 A1 WO2020140767 A1 WO 2020140767A1
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Prior art keywords
thin film
film transistor
electrode
substrate
transparent display
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PCT/CN2019/126874
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English (en)
French (fr)
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宋振
王国英
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京东方科技集团股份有限公司
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Priority to US16/964,127 priority Critical patent/US11489029B2/en
Publication of WO2020140767A1 publication Critical patent/WO2020140767A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/816—Multilayers, e.g. transparent multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/818—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3031—Two-side emission, e.g. transparent OLEDs [TOLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers

Definitions

  • the present disclosure relates to the field of display technology, and particularly to a transparent display substrate and display panel.
  • a transparent display substrate includes: a first substrate; and a plurality of sub-pixels disposed on the first substrate. At least one sub-pixel of the plurality of sub-pixels has a light-emitting area and a transparent area.
  • Each sub-pixel of the at least one sub-pixel includes at least one thin-film transistor, a capacitor, and a self-luminous device located in the light-emitting region; along a direction perpendicular to the first substrate, the capacitor is located between the self-luminous device and the at least one thin-film transistor At least one thin film transistor and the capacitor are electrically connected to form at least a part of a driving circuit for driving light from the light emitting device.
  • the capacitor includes a first pole configured to be impermeable to light; wherein the orthographic projection of the self-luminous device on the first substrate is located in the orthographic projection of the first pole on the first substrate Within the range; and/or, the orthographic projection of the at least one thin film transistor on the first substrate is within the range of the orthographic projection of the first pole on the first substrate.
  • the self-luminous device includes: an anode disposed on a side of the first electrode away from the first substrate, the anode is further configured as a second electrode of the capacitor; the transparent display substrate further includes: a first insulating layer, It is arranged between the first pole and the second pole.
  • the self-luminous device further includes: a cathode disposed on a side of the anode away from the first substrate, the cathode configured to transmit light; and a light-emitting functional layer disposed between the cathode and the anode.
  • the material of the anode includes a transparent conductive material; the material of the cathode includes a metallic material.
  • the first electrode is a single-layer structure, and the single-layer structure includes a reflective electrode that can reflect light; or, the first electrode is a multilayer structure formed by stacking, and the multilayer structure includes at least one reflective electrode that can reflect light and At least one layer of transparent electrodes that can transmit light.
  • the at least one thin film transistor includes a driving thin film transistor; the driving thin film transistor includes a first gate, a first source, and a first drain; the first gate is electrically connected to the first electrode.
  • the first insulating layer is provided with a first via hole in a portion located in the light emitting region; the second electrode is electrically connected to the first drain electrode or the first source electrode through the first via hole.
  • the at least one thin film transistor further includes at least one switched thin film transistor, and the at least one switched thin film transistor includes a first switched thin film transistor; the first switched thin film transistor includes a second gate, a second source, and Second drain.
  • the transparent display substrate further includes a data line and a gate line, the second source electrode is electrically connected to the data line, the second gate electrode is electrically connected to the gate line, and the second drain electrode is electrically connected to the first electrode.
  • both the driving thin film transistor and the first switching thin film transistor are top-gate thin film transistors; the first gate and the second gate are arranged in the same layer; the first source, the second source, and the first drain , And the second drain are arranged in the same layer.
  • the transparent display substrate further includes: a second insulating layer disposed between the capacitor and the at least one thin film transistor; the second insulating layer covers at least the display area of the transparent display substrate.
  • the transparent display substrate further includes: a flat layer disposed between the second insulating layer and the capacitor; the flat layer has no or substantially no coverage in the transparent area of each sub-pixel.
  • the portion of the second insulating layer located in the light-emitting region is provided with second vias, third vias, and fourth vias; the portion of the flat layer located in the light-emitting region is provided with a communication with the second via A fifth via, a sixth via communicating with the third via, and a seventh via communicating with the fourth via.
  • the at least one thin film transistor includes a driving thin film transistor and a first switching thin film transistor
  • the first electrode of the capacitor is electrically connected to the second drain of the first switching thin film transistor through the second via hole and the fifth via hole
  • the first electrode of the capacitor is electrically connected to the first gate of the driving thin film transistor through the third via and the sixth via
  • the second electrode of the capacitor is electrically connected to the driving thin film transistor through the fourth via and the seventh via The first source or the first drain.
  • a method for manufacturing a transparent display substrate includes: providing a first substrate; and forming a plurality of sub-pixels on the first substrate. At least one sub-pixel of the plurality of sub-pixels has a light-emitting area and a transparent area; each sub-pixel in the at least one sub-pixel includes at least one thin film transistor, capacitor, and self-luminous device formed in sequence in its light-emitting area; In a direction perpendicular to the first substrate, the capacitor is located between the self-luminous device and the at least one thin film transistor; the at least one thin film transistor and the capacitor are electrically connected to form the self-driving device At least a part of the driving circuit where the light emitting device emits light.
  • the step of forming a plurality of sub-pixels on the first substrate includes:
  • the driving thin film transistor includes a first gate, a first source and a first drain, and the first switching thin film transistor includes a second gate, a second source and a second drain ;
  • a first electrode layer is formed on the side of the source-drain metal layer away from the first substrate, the first electrode layer includes a first electrode of the capacitor; the first electrode of the capacitor is electrically connected to the first gate, and the first electrode of the capacitor is The second drain is electrically connected;
  • a second electrode layer is formed on a side of the first insulating layer away from the first substrate; the second electrode layer includes a second electrode of the capacitor, and the second electrode of the capacitor is electrically connected to the first source electrode or the first drain electrode.
  • a transparent display substrate includes the transparent display substrate as described in any of the above embodiments.
  • the transparent display panel further includes a cover plate disposed on one side of the transparent display substrate.
  • the cover plate includes: a second substrate; a color filter layer and a black matrix provided on the second substrate; the color filter layer and the black matrix are located in an area corresponding to the light emitting area on the transparent display substrate.
  • the color filter layer includes a plurality of filter parts, and the plurality of filter parts correspond to the plurality of light emitting regions on the transparent display substrate in one-to-one correspondence.
  • the cover plate further includes: a third insulating layer disposed on the side of the color filter layer remote from the second substrate; an auxiliary electrode disposed on the side of the third insulating layer remote from the second substrate
  • the cathode is electrically connected to the cathode included in the self-luminous device of the transparent display substrate.
  • the orthographic projection of the auxiliary cathode on the second substrate is within the range of the orthographic projection of the black matrix on the second substrate.
  • FIG. 1 is a cross-sectional view of a sub-pixel provided according to the related art
  • FIG. 2 is a top view of a transparent display substrate according to some embodiments disclosed.
  • FIG. 3 is a cross-sectional view of a sub-pixel provided according to some embodiments of the disclosure.
  • FIG. 4 is a top view of a light-emitting area according to some embodiments of the disclosure.
  • FIG. 5 is a cross-sectional view based on the AA' direction of FIG. 4 according to some embodiments of the disclosure.
  • FIG. 6 is a cross-sectional view based on the BB′ direction of FIG. 4 according to some embodiments of the disclosure.
  • FIG. 7 is an equivalent circuit diagram of a driving circuit according to some embodiments disclosed.
  • FIG. 8 is a flowchart of a method for manufacturing a transparent display substrate according to some embodiments of the present disclosure
  • FIG. 9 is a flowchart of another method for manufacturing a transparent display substrate according to some embodiments of the present disclosure.
  • FIG. 10 is a top view of a transparent display panel according to some embodiments of the present disclosure.
  • FIG. 11 is a cross-sectional view of a cover plate according to some embodiments of the present disclosure.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • Coupled and “connected” and their derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components do not directly contact each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • the storage capacitor in order to increase the transparency of the transparent display device and enhance the display effect, it is necessary to reduce the occupied area of the light emitting area as much as possible.
  • the storage capacitor is usually formed by extending a part of the structure in the TFT (Thin Film Transistor, thin film transistor). That is, as shown in FIG. 1, the storage capacitor Cst is located on the side of the top light-emitting device close to the substrate, one of the electrodes of the storage capacitor Cst is extended by the active layer 314' in the TFT, and the other of the storage capacitor Cst
  • the source electrode 312' and the drain electrode 313' are arranged in the same layer.
  • the storage capacitor Cst only occupies part of the area of the light-emitting area A 1 , when increasing the transparency of the display substrate by increasing the area of the transparent area A 2 , as the area of the light-emitting area A 1 decreases, the occupied layout of the storage capacitor Cst The area decreases accordingly. At this time, although the transparency of the display substrate is increased to a certain extent, due to the reduction of the layout area occupied by the storage capacitor Cst, the pixel capacitance value is reduced, which makes it easy to produce display mura under the influence of parasitic capacitance. That is, the phenomenon of uneven display brightness.
  • the transparent display substrate includes a first substrate 1 and a plurality of sub-pixels 11 disposed on the first substrate 1, At least one sub-pixel 11 of the plurality of sub-pixels 11 includes a light-emitting area A 1 and a transparent area A 2 .
  • the at least one sub-pixel 11 may be a sub-pixel located in the display area, or may be a sub-pixel located in the non-display area (that is, a dummy pixel).
  • each of the at least one sub-pixel 11 includes at least one thin film transistor 3, a capacitor 4, and a self-luminous device 2 located in the light-emitting area A 1 .
  • the capacitor 4 is located between the self-luminous device 2 and at least one thin film transistor 3.
  • the at least one thin film transistor 3 and the capacitor 4 are electrically connected to form at least a part of a driving circuit for driving the self-luminous device 2 to emit light.
  • the at least one thin film transistor 3 and the capacitor 4 since the at least one thin film transistor 3 and the capacitor 4 constitute at least a part of the driving circuit for driving the light emitting device 2, the person skilled in the art should understand that How to set the capacitor 4 and at least one thin film transistor 3 in the driving circuit.
  • the capacitor 4 On the basis that the driving circuit drives the light emitting device 2 to emit light, the capacitor 4 must necessarily be electrically connected to the at least one thin film transistor 3.
  • the present disclosure does not limit the connection manner of the capacitor 4 and at least one thin film transistor 3 as long as the at least one thin film transistor 3 can provide different potentials for the first and second electrodes of the capacitor 4.
  • the capacitor 4 since the capacitor 4 is disposed between the self-luminous device 2 and at least one thin film transistor 3, the capacitor in the related art only occupies part of the area of the light emitting area A 1 (as shown in FIG. 1 storage capacitor Cst Located on the side of the TFT), the occupied layout area of the capacitor 4 in the embodiment of the present disclosure is larger, and the occupied layout area of the capacitor 4 can be determined by the area of the light-emitting area A 1 , for example, it can be roughly equal to that of the light-emitting area A 1 area. In this way, when the area of the transparent area A 2 is increased, although the area of the light-emitting area A 1 is reduced, a certain pixel capacitance value can be ensured, so that the occurrence of display mura can be prevented.
  • the first substrate 1 may be a flexible substrate or a rigid substrate such as a glass substrate.
  • a buffer layer may also be provided between the first substrate 1 and at least one thin film transistor 3. In this way, the problem of poor quality of subsequent film formation due to impurities in the first substrate 1 entering the active layer of at least one thin film transistor 3 or the unevenness of the first substrate 1 itself can be avoided, thereby ensuring at least one thin film transistor 3 performance.
  • the capacitor 4 includes a first pole 41, and the first pole 41 of the capacitor 4 is configured to be impermeable to light, that is, the first pole 41 of the capacitor 4 is opaque.
  • the orthographic projection of the self-luminous device 2 on the first substrate 1 may be within the range of the orthographic projection of the first pole 41 of the capacitor 4 on the first substrate 1.
  • the self-luminous device 2 includes at least an anode, a light-emitting layer, and a cathode.
  • the front projection of the self-luminous device 2 on the first substrate 1 may be Only refers to the orthographic projection of the light emitting layer on the first substrate 1.
  • the first electrode 41 of the capacitor 4 can prevent the light emitted from the light-emitting device 2 from irradiating at least one thin film transistor 3, thereby preventing the performance of at least one thin film transistor 3 from being affected.
  • the orthographic projection of the at least one thin film transistor 2 on the first substrate 1 may also be within the range of the orthographic projection of the first electrode 41 of the capacitor 4 on the first substrate 1.
  • the orthographic projection of the at least one thin film transistor 2 on the first substrate 1 may only refer to Orthographic projection of the source layer on the first substrate 1.
  • the self-luminous device 2 is a double-sided light-emitting device
  • the first electrode 41 of the capacitor 4 can prevent the light emitted from the light-emitting device 2 from irradiating the active layer of at least one thin film transistor 3, thereby preventing Performance has an impact.
  • the above self-luminous device 2 includes an anode 21 and a cathode 22 that are sequentially disposed on the first substrate 1, wherein the cathode 22 is configured to transmit light.
  • the above capacitor 4 is disposed between the self-luminous device 2 and the at least one thin film transistor 3.
  • the self-luminous device 2 may be a top light-emitting device or a two-sided light-emitting device, which is not specifically limited herein.
  • the self-luminous device 2 may further include a light-emitting functional layer 23 that is disposed between the anode 21 and the cathode 22.
  • each light-emitting device 2 may be provided with a light-emitting functional layer 23 independently.
  • the light-emitting functional layer 23 may be provided in one layer to cover the display area A.
  • the light-emitting functional layer 23 emits white light, and the light-emitting functional layer 23 may be formed by evaporation through an opening mask (Open Mask).
  • the light emitting functional layer 23 may include a light emitting layer, a hole transport layer, an electron transport layer, and the like. Moreover, the light-emitting function layer 23 may further include a hole injection layer, an electron injection layer, and the like.
  • the material of the light-emitting layer may be an organic light-emitting material or a quantum dot (Quantum dots) light-emitting material.
  • the cathode 22 may cover the display area A. That is, the cathode 22 is located in the transparent area A 2 in addition to the light-emitting area A 1 .
  • the anode 21 also serves as the second pole of the capacitor 4, and the first pole 41 and the second pole 42 of the capacitor 4 are separated by a first insulating layer 43 .
  • the second electrode 42 by the capacitor 4 is used as the anode 21, it is possible to avoid adding additional electrodes A 1 light emitting region 42 as a second electrode of the capacitor 4, thereby reducing the thickness of the emission region A 1.
  • the capacitance of the capacitor 4 can meet the requirements.
  • the self-light emitting device 2 may be a top light emitting device or a double-sided light emitting device.
  • the material of the anode 21 of the self light emitting device 2 may be Including metal materials, for example, the anode 21 is a stack structure having a first transparent electrode/metal reflective electrode/second transparent electrode (for example, ITO/Ag/ITO), and when the self-luminous device 2 is a double-sided light-emitting device, the anode 21 The material may be a transparent conductive material.
  • the material of the anode 21 is a transparent conductive material
  • the material of the cathode 22 is a metal material
  • the first electrode of the capacitor 4 is a single-layer structure or a multilayer structure composed of layers, wherein the single-layer structure includes a light-reflecting material A reflective electrode, such as a metal reflective electrode; the multilayer structure includes at least one reflective electrode that can reflect light and at least one transparent electrode that can transmit light.
  • the first transparent electrode/reflective metal electrode/second transparent electrode in the anode 21 is equivalent to splitting the stack structure of the first transparent electrode/reflective metal electrode/second transparent electrode in the anode 21 and using one of the transparent electrodes as the second pole 42 of the capacitor 4 .
  • the metal reflective electrode, or the stacked structure of the metal reflective electrode and another layer of transparent electrode, is used as the first pole 41 of the capacitor 4. Since the first pole of the capacitor 4 includes the metal reflective electrode, it can reflect The role. In this way, on the one hand, the influence of the metal work function on the luminous efficiency of the self-luminous device 2 can be reduced; on the other hand, the thickness of the middle first insulating layer 43 can be used to reduce the design difficulty of the microcavity structure.
  • the at least one thin film transistor 3 includes a driving thin film transistor 31; the driving thin film transistor 31 includes a first gate 311, a first electrode 41 of the capacitor 4 and the driving thin film The first gate 311 of the transistor 31 is electrically connected.
  • the driving thin film transistor 31 may further include a first source 312 and a first drain 313, the first source 312 is electrically connected to the power supply line VDD, and the first drain 313 is connected to the The anode 21 of the light emitting device 2 is electrically connected.
  • the first drain 313 is electrically connected to the power supply line VDD, and the first source 312 is electrically connected to the anode 21 of the self-luminous device 2.
  • the anode adjacent to the first side of the substrate 1 is provided with a case where the first insulating layer 43 of 21, may be located in a first region of the light emitting portion is provided through a hole in the first insulating N 43, so that The anode 21 may be electrically connected to the above-mentioned first source electrode 312 or first drain electrode 313 through the first via hole.
  • the at least one thin film transistor 3 further includes at least one switching thin film transistor, and the at least one switching thin film transistor includes the first switching thin film transistor 32.
  • the first switching thin film transistor 32 includes a second gate 321, a second source 322, and a second drain 323.
  • the second source electrode 322 is electrically connected to the data line DL
  • the second gate electrode 321 is electrically connected to the gate line GL
  • the second drain electrode 323 is electrically connected to the first electrode 41 of the capacitor 4.
  • the first electrode 41 of the capacitor 4 is also electrically connected to the first gate 311 of the driving thin film transistor 31, when the second drain 323 is electrically connected to the first electrode 41 of the capacitor 4, the second drain 323 and the first gate 311 may be electrically connected through the first electrode 41 of the capacitor 4.
  • the first switching thin-film transistor and the driving thin-film transistor described above may be top-gate thin-film transistors or bottom-gate thin-film transistors.
  • the bottom gate type can be divided into a back channel type (Back Channel Etch, BCE) structure and an etch barrier type (Etch Stop, Layer, ESL).
  • the embodiments of the present disclosure are not limited thereto, and may be connected by two thin film transistors (such as a driving thin film transistor and a first switching thin film transistor) as above
  • the formation may also be formed by connecting more than two thin film transistors (such as one driving thin film transistor and multiple first switching thin film transistors).
  • the driving thin-film transistor and the first switching thin-film transistor are both top-gate thin-film transistors, and the first gate 311 and the second gate 321 are arranged in the same layer, the first The source electrode 312 and the second source electrode 322, and the first drain electrode 313 and the second drain electrode 323 are all disposed in the same layer.
  • the first gate 311 and the second gate 321 can be formed by the same patterning process, and the second source 322 and the first source 312, and the first drain 313 and the second drain 323 are also the same It can be formed by the same patterning process. Therefore, the manufacturing process of the transparent display substrate can be simplified, the manufacturing difficulty can be reduced, and the production efficiency can be improved.
  • the gate line GL is shared with the second gate 321 for illustration, but the embodiment of the present disclosure is not limited to this, and the gate line GL and the second gate 321 may also be provided separately.
  • the equivalent circuit diagram of the driving circuit composed of the one switching thin film transistor 32, one driving thin film transistor 31, and the capacitor 4 can be referred to FIG. 7.
  • the gate line GL is turned on
  • the switching thin film transistor 32 is turned on, and the input signal on the data line DL is transmitted to the first gate 311 of the driving thin film transistor 31 to charge the capacitor 4, and when the gate line GL is closed, the driving thin film The voltage of the first gate 311 of the transistor 31 is held by the capacitor 4.
  • the transparent area A 2 is called a "transparent area” is that each film layer provided in this area transmits light. In other words, the transparent area A 2 is transparent as a whole. The transparent area A 2 does not participate in the display.
  • the film layer of the transparent area A 2 is not specifically limited.
  • the transparent area A 2 may be formed by extending each light-transmitting film layer in the light-emitting area A 1 .
  • the transparent region A 2 may be extended by a light-transmitting film layer such as a first substrate 1, a buffer layer, a first insulating layer 43, and a cathode 22.
  • a second insulating layer 5 and a flat layer 6 are further provided between the capacitor 4 and at least one thin film transistor 3, and the second insulating layer 5 covers the display area A;
  • the flat layer 6 has no or substantially no coverage in the transparent area A 2 .
  • the second insulating layer 5 is an inorganic insulating layer
  • the flat layer 6 is an organic flat layer.
  • the second insulating layer 5 is provided with a second via N 2 , a third via N 3 and a fourth via N 4 in the light emitting region.
  • the light emitting region of the planarization layer 6 is provided with a portion of the second communicating via N 2 via a fifth N 5, third through hole communicating with the through hole sixth N 3 N 6, N and a fourth via hole 4 Connected seventh via N 7 .
  • the first pole 41 of the capacitor 4 is electrically connected to the first switching thin film through the second via N 2 and the fifth via N 5
  • the second drain 323 of the transistor 32 and the first pole 41 of the capacitor 4 are electrically connected to the first gate 311 of the driving thin film transistor 31 through the third via N 3 and the sixth via N 6 .
  • the second electrode 42 of the capacitor 4 is electrically connected to the first source electrode or the first drain electrode of the driving thin film transistor through the fourth via hole N 4 and the seventh via hole N 7 .
  • the second electrode 42 of the capacitor 4 will be electrically connected to the first source of the driving thin film transistor through the first via N 1 , the fourth via N 4 and the seventh via N 7 Electrode or first drain.
  • the manufacturing method includes:
  • the first substrate 1 is provided.
  • the first substrate 1 may be a flexible substrate or a rigid substrate such as a glass substrate.
  • each of the at least one sub-pixel 11 at least one thin film transistor comprising a sub-pixel 11 are sequentially formed thereon in the light emitting region a 1 3, 4 and self-capacitance of the light emitting device 2;
  • X in the direction of the first substrate 1 in a vertical, self-capacitance of the light emitting device 4 is positioned with the at least 2 Between one thin film transistor 3; the at least one thin film transistor 3 and the capacitor 4 are electrically connected to form at least a part of a driving circuit for driving the light emitting device 2 to emit light.
  • the capacitor 4 since the transparent display substrate manufactured by the above manufacturing method, since the capacitor 4 is located between the self-luminous device 2 and the at least one thin film transistor 3, the capacitor in the related art only occupies a part of the light emitting area A 1 Compared with the area (as shown in FIG. 1 where the storage capacitor Cst is located on the side of the TFT), in the transparent display substrate formed in this embodiment, the occupied layout area of the capacitor 4 is larger, and the occupied layout area of the capacitor 4 can be determined by the light-emitting area A The area of 1 is determined, for example, to be approximately equal to the area of the light-emitting area A 1 . In this way, when the area of the transparent area A 2 is increased, although the area of the light-emitting area A 1 is reduced, a certain pixel capacitance value can be ensured, so that the occurrence of display mura can be prevented.
  • the above S2 includes S21 to S24.
  • the at least one thin film transistor 3 includes a driving thin film transistor 31 and a first switching thin film transistor 32, the driving thin film transistor 31 includes a first gate 311, a first source 312 and a first drain 313, the first switching thin film transistor 32 The second gate 321, the second source 322, and the second drain 323 are included.
  • a buffer layer may be deposited after the first substrate 1 is cleaned, and then a semiconductor material may be deposited and patterned to form an active layer.
  • the active layer includes a first active layer 314 driving the thin film transistor 31 and a first switch
  • the second active layer 324 of the thin film transistor 32 can be understood that the first active layer 314 and the second active layer 324 are both located in the light emitting area A 1 .
  • the gate insulating layer includes a first light emitting region of A 1
  • gate metal layer includes a light-emitting region A 1
  • an interlayer insulating layer 316 is deposited through a deposition process and etched to form vias for electrical connection.
  • a metal material is then deposited and patterned to form a source-drain metal layer.
  • the source-drain metal layer includes a first source 312, a first drain 313, a second source 322, and a second drain 323.
  • the first source electrode 312 and the first drain electrode 313 are located above the first active layer 314, and are in contact with the first active layer 314 through the via in the interlayer insulating layer 316; the second source electrode 322 and the second drain electrode 323 is located above the second active layer 324 and contacts the second active layer 324 through the via in the interlayer insulating layer 316.
  • a first electrode layer is formed on the side of the source-drain metal layer away from the first substrate 1, the first electrode layer includes the first electrode 41 of the capacitor 4, the first electrode 41 of the capacitor 4 and the first gate
  • the pole 311 is electrically connected, and the first pole 41 and the second drain 323 of the capacitor 4 are electrically connected.
  • a second electrode layer is formed on the side of the first insulating layer 43 away from the first substrate 1.
  • the second electrode layer includes the second electrode 42 of the capacitor 4, the second electrode 42 of the capacitor 4 and the first source electrode 312 or The first drain 313 is electrically connected.
  • the method further includes the steps of forming a second insulating layer 5 (such as an inorganic insulating layer) and a flat layer 6 (such as an organic flat layer) .
  • the second insulating layer 5 may be deposited by a deposition process, and the second insulating layer 5 is etched to form vias for electrical connection (such as the second via N 2 and the third via N in FIGS. 5 and 6) 3 and the fourth via N 4 ).
  • an organic planarization material e.g. resin material
  • a planarization layer 6 and etched to form vias for electrical connection (FIG. 5 V via N in FIG.
  • the first pole 41 of the capacitor 4 and the second pole 42 of the capacitor 4 may be electrically connected to the second drain through the second via N 2 and the fifth via N 5 323, a first capacitor electrode 414 may be connected electrically to the first gate through a third via hole 6 and the sixth via hole N 3 N 311; capacitance of the second electrode 424 may be N 4 and the second through the fourth via hole
  • the seven via N 7 is electrically connected to the first source 312 or the first drain 313.
  • the subsequent formation of a first insulating layer 43 is also etched with a first hole through N 1, so The second electrode 42 of the capacitor 4 may be electrically connected to the first source electrode 312 or the first drain electrode 313 through the first via hole N 1 , the fourth via hole N 4 and the seventh via hole N 7 .
  • 5 shows that the second pole 42 of the capacitor 4 is electrically connected to the first drain 313 through the first via N 1 , the fourth via N 4 and the seventh via N 7 .
  • the above-mentioned first electrode layer, first insulating layer 43 and second electrode layer may be formed by the following steps. For example, first, metal materials and transparent conductive materials (such as Ag/ITO) are deposited in sequence, and then the first electrode layer is formed after patterning, that is, the first pole 41 of the capacitor 4 and the first pole of the capacitor 4 are formed in the light-emitting area A 1 41 is electrically connected to the second drain electrode 323 and the first gate electrode 311 through via holes formed in the inorganic insulating layer 5 and the organic flat layer 6, respectively.
  • first, metal materials and transparent conductive materials such as Ag/ITO
  • a first insulating layer 43 is deposited, and a via hole (ie, a first via hole N 1 ) for electrical connection is formed on the insulating layer 43 by etching.
  • deposition of a transparent conductive material e.g., ITO
  • ITO transparent conductive material
  • the second electrode 41 of the capacitor 4 can also be used as the anode 21 of the self-luminous device 2, so that the pixel defining layer 7 can be directly formed later (as shown in FIG. 3 ), and light emission can be defined through the pixel defining layer 7 In the area A 1 , the light-emitting functional layer 23 is vapor-deposited, and finally the cathode 22 is deposited, so that the production of the self-luminous device 2 can be completed.
  • the pixel defining layer 7 includes a portion surrounding the light-emitting area A 1 and a portion for filling each recessed area in the light-emitting area A 1 (that is, the position corresponding to the via hole). In this way, the light-emitting functional layer 23 to be formed later can be flatter.
  • the material forming the pixel defining layer 7 is a transparent material.
  • the metal electrode involved in at least one thin film transistor 3 of the transparent display substrate 01 silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), and alloy materials can be used.
  • the structure of the metal electrode may be a multi-layer metal structure, such as MoNb/Cu/MoNb.
  • the structure of the metal electrode may also be a stack structure formed of metal and transparent conductive oxide (such as ITO, AZO, etc.), such as Mo/AlNd/ITO, ITO/Ag/ITO, etc.
  • the material may be transparent amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), IZTO, amorphous silicon ( a-Si), polycrystalline silicon (p-Si), at least one of hexathiophene and polythiophene.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO amorphous silicon
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • the materials of the buffer layer, the gate insulating layer 315, the interlayer insulating layer 316, and the second insulating layer 5 include but are not limited to dielectric materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or each A new type of organic insulating materials, or high dielectric constant (High) materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc.
  • the material of the organic flat layer 6 includes but is not limited to polysiloxane-based, acrylic-based or polyimide-based materials.
  • Some embodiments of the present disclosure also provide a transparent display panel, including the transparent display substrate 01 described above.
  • the transparent display panel has the same beneficial effects as the transparent display substrate, and will not be repeated here.
  • the transparent display panel further includes a cover plate 02, and the cover plate 02 is disposed on a side close to the cathode of the transparent display substrate 01.
  • the cover plate 02 includes a second substrate 020, a color filter layer and a black matrix 022 disposed on the second substrate 020.
  • the color filter layer and the black matrix 022 are provided in an area corresponding to the light emitting area A 1 on the transparent display substrate 01.
  • the second substrate 020 may be a flexible substrate or a rigid substrate such as a glass substrate.
  • the color filter layer includes a plurality of filter portions 021, and the plurality of filter portions 021 correspond to the plurality of light emitting areas A 1 on the transparent display substrate 01 in one-to-one correspondence.
  • the color filter layer includes at least a first primary color filter (such as a red filter), a second primary color filter (such as a green filter), and a third primary color filter (such as a blue filter) Filters for three primary colors.
  • each first primary color filter pattern, each second primary color filter pattern, and each third primary color filter pattern are respectively located in the light emitting area of one sub-pixel 11.
  • the transparent display panel can be used for a large-size display, in which the color filter layer 021 and the black matrix 022 are provided in The area corresponding to the light-emitting area A 1 on the transparent display substrate 01 can ensure that the transparent area A 2 is transparent.
  • the area on the cover plate 02 corresponding to the part between two pixels is also provided with a black matrix, so that The black matrix blocks the vertical metal lines between two pixels.
  • the transparent areas A 2 of all sub-pixels 11 in each pixel can be connected together, thereby increasing The proportion of transparent areas in the transparent display panel is shown.
  • the cover plate 02 further includes a third insulating layer 024 disposed on a side of the color filter layer away from the second substrate 020, and a third insulating layer 024 disposed on the third insulating layer 024
  • the auxiliary cathode 023 on the side far from the second substrate 020 may be electrically connected to the cathode 22 on the transparent display substrate 01.
  • the orthographic projection of the auxiliary cathode 023 on the second substrate 020 is within the range of the orthographic projection of the black matrix 022 on the second substrate 020, which can avoid reducing the aperture ratio.
  • the material of the auxiliary cathode 023 is a metal material.
  • the shape of the auxiliary cathode 023 may be the same as the black matrix 022, that is, the shape of the auxiliary cathode 023 may be a grid shape.
  • the voltage drop on the cathode 22 can be reduced.

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Abstract

一种透明显示基板。该透明显示基板包括：第一衬底；以及，设置于第一衬底上的多个亚像素。所述多个亚像素中的至少一个亚像素具有发光区和透明区。所述至少一个亚像素中的每个亚像素包括位于其发光区内的至少一个薄膜晶体管，电容以及自发光器件；沿垂直于第一衬底的方向，电容位于自发光器件与至少一个薄膜晶体管之间；至少一个薄膜晶体管和电容电连接形成用于驱动自发光器件发光的驱动电路的至少一部分。

Description

透明显示基板及其制作方法和透明显示面板
本申请要求于2019年01月02日提交的、申请号为201910002677.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种透明显示基板和显示面板。
背景技术
随着信息社会的发展，新颖的显示技术如透明显示装置等由于良好的用户体验，而具有广阔的市场前景。
发明内容
一方面，提供一种透明显示基板。该透明显示基板包括：第一衬底；以及，设置于第一衬底上的多个亚像素。所述多个亚像素中的至少一个亚像素具有发光区和透明区。所述至少一个亚像素中的每个亚像素包括位于其发光区内的至少一个薄膜晶体管，电容以及自发光器件；沿垂直于第一衬底的方向，电容位于自发光器件与至少一个薄膜晶体管之间；至少一个薄膜晶体管和电容电连接形成用于驱动自发光器件发光的驱动电路的至少一部分。
在一些实施例中，电容包括第一极，第一极配置为不可透过光；其中，自发光器件在第一衬底上的正投影位于第一极在第一衬底上的正投影的范围之内；和/或，至少一个薄膜晶体管在第一衬底上的正投影位于第一极在第一衬底上的正投影的范围之内。
在一些实施例中，自发光器件包括：阳极，设置于第一极的远离第一衬底的一侧，阳极还被配置为电容的第二极；透明显示基板还包括：第一绝缘层，设置于第一极和第二极之间。
在一些实施例中，自发光器件还包括：阴极，设置于阳极的远离第一衬底的一侧，阴极配置为可透过光；发光功能层，设置于阴极与阳极之间。
在一些实施例中，阳极的材料包括透明导电材料；阴极的材料包括金属材料。
在一些实施例中，第一极为单层结构，单层结构包括可反射光线的反射电极；或者，第一极为层叠构成的多层结构，多层结构包括至少一层可反射光线的反射电极和至少一层可透过光线的透明电极。
在一些实施例中，所述至少一个薄膜晶体管包括一个驱动薄膜晶体管；驱动薄膜晶体管包括第一栅极，第一源极和第一漏极；第一栅极与第一极电连接。
在一些实施例中，第一绝缘层在位于发光区的部分设置有第一过孔；第二极通过第一过孔与第一漏极或第一源极电连接。
在一些实施例中，所述至少一个薄膜晶体管还包括至少一个开关薄膜晶体管，所述至少一个开关薄膜晶体管包括第一开关薄膜晶体管；第一开关薄膜晶体管包括第二栅极、第二源极和第二漏极。透明显示基板还包括数据线和栅线，第二源极与数据线电连接，第二栅极与栅线电连接，第二漏极与第一极电连接。
在一些实施例中，驱动薄膜晶体管和第一开关薄膜晶体管均为顶栅型薄膜晶体管；第一栅极和第二栅极同层设置；第一源极，第二源极，第一漏极，及第二漏极同层设置。
在一些实施例中，所述透明显示基板还包括：第二绝缘层，设置在电容和至少一个薄膜晶体管之间；第二绝缘层至少覆盖透明显示基板的显示区。
在一些实施例中，透明显示基板还包括：平坦层，设置于第二绝缘层和电容之间；平坦层在各亚像素的透明区无覆盖或大致无覆盖。
在一些实施例中，第二绝缘层的位于发光区的部分设置有第二过孔、第三过孔和第四过孔；平坦层的位于发光区的部分设置有与第二过孔连通的第五过孔，与第三过孔连通的第六过孔，以及与第四过孔连通的第七过孔。在所述至少一个薄膜晶体管包括驱动薄膜晶体管和第一开关薄膜晶体管的情况下，电容的第一极通过第二过孔和第五过孔电连接至第一开关薄膜晶体管的第二漏极，并且电容的第一极通过第三过孔和第六过孔电连接至驱动薄膜晶体管的第一栅极；电容的第二极通过第四过孔和第七过孔电连接至驱动薄膜晶体管的第一源极或第一漏极。
另一方面，提供一种透明显示基板的制作方法。该制作方法包括：提供第一衬底；在所述第一衬底上形成多个亚像素。所述多个亚像素中的至少一个亚像素具有发光区和透明区；所述至少一个亚像素中的每个亚像素包括依次形成在其发光区的至少一个薄膜晶体管、电容及自发光器件；沿垂直于所述第一衬底的方向，所述电容位于所述自发光器件与所述至少一个薄膜晶体管之间；所述至少一个薄膜晶体管和所述电容电 连接形成用于驱动所述自发光器件发光的驱动电路的至少一部分。
在一些实施例中，在第一衬底上形成多个亚像素的步骤，包括：
在第一衬底上形成有源层、栅绝缘层、栅金属层以及源漏金属层；有源层、栅绝缘层、栅金属层以及源漏金属层形成至少一个薄膜晶体管；至少一个薄膜晶体管包括驱动薄膜晶体管和第一开关薄膜晶体管，驱动薄膜晶体管包括第一栅极、第一源极和第一漏极，第一开关薄膜晶体管包括第二栅极、第二源极和第二漏极；
在源漏金属层远离第一衬底的一侧形成第一电极层，第一电极层包括电容的第一极；电容的第一极与第一栅极电连接，并且电容的第一极与第二漏极电连接；
在第一电极层远离第一衬底的一侧形成第一绝缘层；
在第一绝缘层远离第一衬底的一侧形成第二电极层；第二电极层包括电容的第二极，电容的第二极与第一源极或第一漏极电连接。
再一方面，提供一种透明显示基板。该透明显示基板包括如上述任一实施例所述的透明显示基板。
在一些实施例中，透明显示面板还包括设置于透明显示基板一侧的盖板。盖板包括：第二衬底；设置于第二衬底上的彩色滤光层和黑矩阵；彩色滤光层和黑矩阵位于与透明显示基板上的发光区对应的区域。
在一些实施例中，彩色滤光层包括多个滤光部，多个滤光部与透明显示基板上的多个发光区一一对应。
在一些实施例中，盖板还包括：第三绝缘层，设置于彩色滤光层的远离第二衬底一侧；辅助电极，设置于第三绝缘层的远离第二衬底一侧，辅助阴极与透明显示基板的自发光器件所包括的阴极电连接。
在一些实施例中，辅助阴极在第二衬底上的正投影位于黑矩阵在第二衬底上的正投影的范围之内。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术提供的一种亚像素的剖视图；
图2为本根据公开一些实施例提供的一种透明显示基板的俯视图；
图3为本根据公开一些实施例提供的一种亚像素的剖视图；
图4为本根据公开一些实施例提供的一种发光区的俯视图；
图5为本根据公开一些实施例提供的基于图4的A-A'方向的剖视图；
图6为本根据公开一些实施例提供的基于图4的B-B'方向的剖视图；
图7为本根据公开一些实施例提供的一种驱动电路的等效电路图；
图8为根据本公开一些实施例提供的一种透明显示基板的制作方法的流程图；
图9为根据本公开一些实施例提供的另一种透明显示基板的制作方法的流程图；
图10为根据本公开一些实施例提供的一种透明显示面板的俯视图；
图11为根据本公开一些实施例提供的一种盖板的剖视图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在相关技术中，为了提高透明显示装置的透明度，提升显示效果，需要尽量降低发光区的占用面积。对于存储电容设置在发光区的情况而言，存储电容通常由TFT(Thin Film Transistor，薄膜晶体管)中的部分结构延伸形成。即，如图1所示，存储电容Cst位于顶发光器件靠近衬底的一侧，该存储电容Cst的其中一极由TFT中的有源层314'延伸形成，而该存储电容Cst的另一极与源极312'和漏极313'同层设置。由于存储电容Cst仅占用部分发光区A 1的面积，因此，在通过增加透明区A 2的面积来增加显示基板的透明度时，随着发光区A 1的面积减小，存储电容Cst的占用版图面积随之减小。此时，虽然在一定程度上增加了显示基板的透明度，但由于减小了存储电容Cst占用版图面积减小，造成像素电容值降低，从而使得在寄生电容的影响下，容易产生显示mura，也即显示亮度不均匀的现象。
基于此，本公开的一些实施例提供了一种透明显示基板，如图2所示，该透明显示基板包括第一衬底1以及设置于第一衬底1上的多个若干亚像素11，所述多个亚像素11中的至少一个亚像素11包括发光区A 1和透明区A 2。其中，所述至少一个亚像素11可以是位于显示区内的亚像素，也可以是位于非显示区的亚像素(也即dummy像素)。
如图3所示，上述至少一个亚像素11中的每个亚像素11包括位于其发光区A 1内的至少一个薄膜晶体管3、电容4以及自发光器件2。其中，沿垂直于第一衬底1的方向X，电容4位于自发光器件2与至少一个薄膜晶体管3之间。该至少一个薄膜晶体管3和电容4电连接形成用 于驱动该自发光器件2发光的驱动电路的至少一部分。
其中，对于至少一个薄膜晶体管3和电容4而言，由于该至少一个薄膜晶体管3和电容4构成用于驱动自发光器件2发光的驱动电路的至少一部分，因此，本领域技术人员应该明白，不管驱动电路中的电容4以及至少一个薄膜晶体管3如何设置，在该驱动电路实现驱动自发光器件2发光的基础上，电容4必然需要与至少一个薄膜晶体管3电连接。
另外，本公开对该电容4与至少一个薄膜晶体管3的连接方式不做限定，只要该至少一个薄膜晶体管3能够为该电容4的第一极和第二极提供不同的电位即可。
本公开实施例中，由于该电容4设置于该自发光器件2与至少一个薄膜晶体管3之间，因此，与相关技术中电容仅占用部分发光区A 1的面积(如图1中存储电容Cst位于TFT的一侧)相比，本公开实施例中的电容4的占用版图面积更大，该电容4的占用版图面积可以由发光区A 1的面积决定，例如可以大致等于发光区A 1的面积。这样，在增加透明区A 2的面积时，虽然发光区A 1的面积减小了，但仍能够保证一定的像素电容值，从而能够防止显示mura的产生。
需要说明的是，第一衬底1可以为柔性衬底，也可以为玻璃基板等刚性衬底。在一些示例中，该第一衬底1和至少一个薄膜晶体管3之间还可以设置有缓冲层。这样，可避免由于第一衬底1的杂质进入至少一个薄膜晶体管3的有源层或者由于第一衬底1本身不平坦而导致后续成膜质量较差的问题，从而可保证至少一个薄膜晶体管3的性能。
在一些实施例中，如图3所示，电容4包括第一极41，电容4的第一极41被配置为不可透过光，也即电容4的第一极41不透明。在此基础上，自发光器件2在第一衬底1上的正投影可以位于电容4的第一极41在第一衬底1上的正投影的范围之内。此处，需要说明的是，自发光器件2至少包括阳极、发光层和阴极，当每个自发光器件2独立设置一个发光层，上述自发光器件2在第一衬底1上的正投影可以仅指发光层在第一衬底1上的正投影。这样，当自发光器件2为两面发光器件时，电容4的第一极41能够防止自发光器件2发出的光照射到至少一个薄膜晶体管3，从而防止对至少一个薄膜晶体管3的性能产生影响。另外，至少一个薄膜晶体管2在第一衬底1上的正投影也可以位于电容4的第一极41在第一衬底1上的正投影的范围之内。此处，需要说明的是，光 线照射薄膜晶体管3的有源层时，对薄膜晶体管3的性能影响较大，因此上述至少一个薄膜晶体管2在第一衬底1上的正投影可以仅指有源层在第一衬底1上的正投影。这样，当自发光器件2为两面发光器件时，电容4的第一极41能够防止自发光器件2发出的光照射到至少一个薄膜晶体管3的有源层，从而防止对至少一个薄膜晶体管3的性能产生影响。
参见图3，上述自发光器件2包括依次设置于第一衬底1上的阳极21和阴极22，其中，阴极22配置为可透过光。上述电容4设置于该自发光器件2与所述至少一个薄膜晶体管3之间。
其中，对于自发光器件2而言，该自发光器件2可以为顶发光器件，也可以为两面发光器件，在此不做具体限定。
如图3所示，自发光器件2还可以包括发光功能层23，该发光功能层23设置在阳极21和阴极22之间。
其中，对于发光功能层23而言，可以是每个自发光器件2独立设置一个发光功能层23。也可以是，发光功能层23整层设置，覆盖显示区A。当发光功能层23整层设置时，该发光功能层23发白光，该发光功能层23可通过开口掩模板(Open Mask)蒸镀形成。
发光功能层23可以包括发光层、空穴传输层和电子传输层等。而且发光功能层23还可以包括空穴注入层和电子注入层等。发光层的材料可以采用有机发光材料或量子点(Quantum dots)发光材料等。
对于阴极22而言，为方便向阴极22供电，阴极22可以覆盖显示区A。即，阴极22除位于发光区A 1以外，也位于透明区A 2。
在本公开的一些实施例中，如图3所示，该阳极21还用作电容4的第二极，该电容4的第一极41和第二极42之间通过第一绝缘层43隔离。
在本实施例中，通过将阳极21用作电容4的第二极42，能够避免在发光区A 1额外增设电极作为该电容4的第二极42，从而可以降低发光区A 1的厚度。
另外，在本实施例中，由于该电容4的第一极41和第二极42之间通过第一绝缘层43隔离，根据平行板电容公式可知，电容4的容值与构成电容4的两极之间的间距成反比，因而，通过控制电容4的两极之间的第一绝缘层43的厚度，可使电容4的容值满足需求。
需要说明的是，如上所述，该自发光器件2可以为顶发光器件，也 可以为两面发光器件，当该自发光器件2为顶发光器件时，该自发光器件2的阳极21的材料可以包括金属材料，如该阳极21为具有第一透明电极/金属反射电极/第二透明电极(例如ITO/Ag/ITO)的堆栈结构，而当自发光器件2为两面发光器件时，阳极21的材料可以为透明导电材料。
在一些实施例中，阳极21的材料为透明导电材料，阴极22的材料为金属材料，电容4的第一极为单层结构或层叠构成的多层结构，其中，单层结构包括可反射光线的反射电极，例如金属反射电极；多层结构包括至少一层可反射光线的反射电极和至少一层可透过光线的透明电极。
在本实施例中，相当于将阳极21中的第一透明电极/反射金属电极/第二透明电极的堆栈结构拆分开来，将其中的一层透明电极用作电容4的第二极42，将金属反射电极、或者金属反射电极和另一层透明电极的层叠结构，用作电容4的第一极41，由于该电容4的第一极包含有金属反射电极，因此，能够起到反射的作用。这样一来，一方面，可以降低金属功函数对自发光器件2发光效率的影响；另一方面，可以利用中间第一绝缘层43的厚度来降低微腔结构的设计难度。
在一些示例中，参见图3、4和图6，该至少一个薄膜晶体管3包括一个驱动薄膜晶体管31；该驱动薄膜晶体管31包括第一栅极311，电容4的第一极41与该驱动薄膜晶体管31的第一栅极311电连接。
可以理解的是，如图4所示，该驱动薄膜晶体管31还可以包括第一源极312和第一漏极313，第一源极312与电源线VDD电连接，第一漏极313与自发光器件2的阳极21电连接。或者，第一漏极313与电源线VDD电连接，第一源极312与自发光器件2的阳极21电连接。另外，参见图3，在阳极21的靠近第一衬底1一侧设置有第一绝缘层43的情况下，可以在第一绝缘43位于发光区的部分设置第一过孔N 1，从而使阳极21可以通过第一过孔电连接至上述第一源极312或第一漏极313。
基于此，当阳极21还用作电容4的第二极时，则，如图3和5所示，电容4的第二极42与该驱动薄膜晶体管31的第一漏极313或第一源极312电连接。其中，图5以电容4的第二极42与该驱动薄膜晶体管31的第一漏极313电连接进行示意。
基于此，在本公开的一些实施例中，参见图3、图4和图6，该至少一个薄膜晶体管3还包括至少一个开关薄膜晶体管，该至少一个开关薄膜晶体管包括第一开关薄膜晶体管32。该第一开关薄膜晶体管32包括 第二栅极321、第二源极322和第二漏极323。该第二源极322与数据线DL电连接，该第二栅极321与栅线GL电连接，该第二漏极323与该电容4的第一极41电连接。
由于电容4的第一极41还与该驱动薄膜晶体管31的第一栅极311电连接，因此，当第二漏极323与该电容4的第一极41电连接时，该第二漏极323与该第一栅极311可以通过该电容4的第一极41电连接。
其中，以上所述的第一开关薄膜晶体管和驱动薄膜晶体管可以为顶栅型薄膜晶体管，也可以是底栅型薄膜晶体管。而底栅型又可以分为背沟道型(Back Channel Etch，BCE)结构和刻蚀阻挡型(Etch Stop Layer，ESL)。
需要说明的是，对于所述至少一个薄膜晶体管3而言，本公开的实施例对此并不做限定，可以由如上两个薄膜晶体管(如一个驱动薄膜晶体管和一个第一开关薄膜晶体管)连接形成，也可以由两个以上的薄膜晶体管(如一个驱动薄膜晶体管和多个第一开关薄膜晶体管)连接形成。
在本公开的一些示例中，如图3所示，该驱动薄膜晶体管和第一开关薄膜晶体管均为顶栅型薄膜晶体管，且第一栅极311和第二栅极321同层设置，第一源极312和第二源极322，以及第一漏极313和第二漏极323均同层设置。
这样一来，第一栅极311和第二栅极321可以通过同一次构图工艺形成，且第二源极322和第一源极312、以及第一漏极313和第二漏极323同样也可以通过同一次构图工艺形成。从而可以简化该透明显示基板的制作工艺，降低制作难度，提高生产效率。
另外，需要说明的是，图4中是以栅线GL与第二栅极321共用进行示意，但本公开的实施例并不限于此，栅线GL与第二栅极321还可以分开设置。
基于此，由该一个开关薄膜晶体管32和一个驱动薄膜晶体管31、电容4构成的驱动电路，其等效电路图可参考图7所示。在栅线GL开启时，开关薄膜晶体管32导通，将数据线DL上的输入信号传输至驱动薄膜晶体管31的第一栅极311，对电容4进行充电，在栅线GL关闭时，驱动薄膜晶体管31的第一栅极311的电压被电容4保持。
基于上述描述，需要说明的是，对于透明区A 2而言，之所以称为“透明区”，是设置于该区域的各膜层均透光。也就是说，透明区A 2整体呈 透明。该透明区A 2不参与显示。
其中，对该透明区A 2的膜层不做具体限定。该透明区A 2可以由发光区A 1中的各个透光膜层延伸形成。
在本公开的一些示例中，该透明区A 2可以由第一衬底1、缓冲层、第一绝缘层43、阴极22等透光膜层延伸形成。
在本公开的一实施例中，继续参见图3，在电容4和至少一个薄膜晶体管3之间还设置有第二绝缘层5和平坦层6，该第二绝缘层5覆盖该显示区A；该平坦层6在该透明区A 2无覆盖或大致无覆盖。在此示例中，通过将有机平坦层6仅覆盖发光区A 1，能够减小构成透明区A 2的膜层的总厚度，从而提升透明区A 2的透明度，进而提升透明显示基板的透明度。示例性地，第二绝缘层5为无机绝缘层，平坦层6为有机平坦层。
在上述实施例中，第二绝缘层5的位于发光区的部分设置有第二过孔N 2、第三过孔N 3和第四过孔N 4。平坦层6的位于发光区的部分设置有与第二过孔N 2连通的第五过孔N 5，与第三过孔N 3连通的第六过孔N 6，以及与第四过孔N 4连通的第七过孔N 7。
在至少一个薄膜晶体管3包括驱动薄膜晶体管31和第一开关薄膜晶体管32的情况下，电容4的第一极41通过第二过孔N 2和第五过孔N 5电连接至第一开关薄膜晶体管32的第二漏极323，并且电容4的第一极41通过第三过孔N 3和第六过孔N 6电连接至驱动薄膜晶体管31的第一栅极311。电容4的第二极42通过第四过孔N 4和第七过孔N 7电连接至驱动薄膜晶体管的第一源极或第一漏极。而在设置有第一绝缘层43时，电容4的第二极42将通过第一过孔N 1、第四过孔N 4和第七过孔N 7电连接至驱动薄膜晶体管的第一源极或第一漏极。
以亚像素11包括发光区A 1和透明区A 2，且位于发光区A 1中的至少一个薄膜晶体管3包括一个开关薄膜晶体管和一个驱动薄膜晶体管为例，参考图2～图9所示，下面提供一种透明显示基板1的制作方法。如图8所示，该制作方法包括：
S1、提供第一衬底1。其中，第一衬底1可以为柔性衬底，也可以为玻璃基板等刚性衬底。
S2、在第一衬底1上形成多个亚像素11；多个亚像素11中的至少一个亚像素11具有发光区A 1和透明区A 2；所述至少一个亚像素11中 的每个亚像素11包括依次形成在其发光区A 1的至少一个薄膜晶体管3、电容4及自发光器件2；沿垂直于第一衬底1的方向X，电容4位于自发光器件2与所述至少一个薄膜晶体管3之间；所述至少一个薄膜晶体管3和电容4电连接形成用于驱动自发光器件2发光的驱动电路的至少一部分。
本公开实施例中，通过上述制作方法制作出的透明显示基板，由于电容4位于自发光器件2与所述至少一个薄膜晶体管3之间，因此，与相关技术中电容仅占用部分发光区A 1的面积(如图1中存储电容Cst位于TFT的一侧)相比，该实施例形成的透明显示基板中，电容4的占用版图面积更大，而且电容4的占用版图面积可以由发光区A 1的面积决定，例如可以大致等于发光区A 1的面积。这样，在增加透明区A 2的面积时，虽然发光区A 1的面积减小了，但仍能够保证一定的像素电容值，从而能够防止显示mura的产生。
示例性地，如图9所示，上述S2包括S21～S24。
S21、在第一衬底上形成有源层、栅绝缘层、栅金属层以及源漏金属层；有源层、栅绝缘层、栅极层以及源漏金属层形成所述至少一个薄膜晶体管3；所述至少一个薄膜晶体管3包括驱动薄膜晶体管31和第一开关薄膜晶体管32，驱动薄膜晶体管31包括第一栅极311、第一源极312和第一漏极313，第一开关薄膜晶体管32包括第二栅极321、第二源极322和第二漏极323。在一些示例中，可以在清洗第一衬底1后沉积缓冲层，再沉积半导体材料并图形化以形成有源层，有源层包括驱动薄膜晶体管31的第一有源层314和第一开关薄膜晶体管32的第二有源层324，可以理解，该第一有源层314和第二有源层324均位于发光区A 1。
在此基础上，示例性地，可以连续沉积栅绝缘材料和金属材料，通过自对准工艺(Self-Aligned)形成栅绝缘层和栅金属层，栅绝缘层包括位于发光区A 1的第一栅绝缘图案315和第二栅绝缘图案325，第一栅绝缘图案315位于第一有源层314上方，第二栅绝缘图案位于第二有源层324上方，栅金属层包括位于发光区A 1的第一栅极311和第二栅极321，第一栅极311位于第一栅绝缘图案315上方，第二栅极321位于第二栅绝缘图案325上方。
然后通过沉积工艺沉积层间绝缘层316，刻蚀形成用于电连接的过孔。再沉积金属材料并图形化，形成源漏金属层，源漏金属层包括第一 源极312、第一漏极313、第二源极322和第二漏极323。第一源极312和第一漏极313位于第一有源层314上方，且通过层间绝缘层316中的过孔与第一有源层314接触；第二源极322和第二漏极323位于第二有源层324上方，且通过层间绝缘层316中的过孔与第二有源层324接触。从而形成上述驱动薄膜晶体管31和第一开关薄膜晶体管32。
S22、在源漏金属层远离第一衬底1的一侧形成第一电极层，第一电极层包括所述电容4的第一极41，所述电容4的第一极41与第一栅极311电连接，并且电容4的第一极41与第二漏极323电连接。
S23、在第一电极层远离第一衬底1的一侧形成第一绝缘层43。
S24、在第一绝缘层43远离第一衬底1的一侧形成第二电极层，第二电极层包括电容4的第二极42，电容4的第二极42与第一源极312或第一漏极313电连接。
示例性地，在形成上述第一电极层、第一绝缘层43及第二电极层之前，还包括形成第二绝缘层5(如无机绝缘层)和平坦层6(如有机平坦层)的步骤。例如可以通过沉积工艺沉积形成第二绝缘层5，并刻蚀第二绝缘层5形成用于电连接的过孔(如图5和图6中的第二过孔N 2、第三过孔N 3和第四过孔N 4)。然后涂覆有机平坦化材料(例如树脂材料)，形成平坦层6，并刻蚀形成用于电连接的过孔(如图5和图6中的第五过孔N 5、第六过孔N 6和第七过孔N 7)，并在透明区A 2将平坦层6刻蚀掉，以提高透明区A 2的透明度。这样，在形成电容4的第一极41和电容4的第二极42后，电容4的第一极41可以通过第二过孔N 2和第五过孔N 5电连接至第二漏极323，电容4的第一极41可以通过第三过孔N 3和第六过孔N 6电连接至第一栅极311；电容4的第二极42可以通过第四过孔N 4和第七过孔N 7电连接至第一源极312或第一漏极313。需要说明的是，为了使电容4的第二极42电连接至第一源极312或第一漏极313，后续形成的第一绝缘层43中还刻蚀有第一过孔N 1，这样，电容4的第二极42可以通过第一过孔N 1，第四过孔N 4和第七过孔N 7电连接至第一源极312或第一漏极313。其中，图5示出了电容4的第二极42通过第一过孔N 1，第四过孔N 4和第七过孔N 7电连接至第一漏极313。
在一些示例中，可以通过以下步骤形成上述第一电极层、第一绝缘层43及第二电极层。例如，首先，依次沉积金属材料和透明导电材料(如Ag/ITO)，图形化后形成上述第一电极层，即在发光区A 1形成电容4 的第一极41，电容4的第一极41通过形成在无机绝缘层5和有机平坦层6中的过孔分别与第二漏极323和第一栅极311电连接。然后，沉积第一绝缘层43，并在绝缘层43上刻蚀形成用于电连接的过孔(即第一过孔N 1)。最后，沉积透明导电材料(如ITO)，图形化后形成上述第二电极层，即在发光区A 1形成电容4的第二极41，第二极41通过形成在第二绝缘层5、平坦层6和第一绝缘层43中的过孔与第一漏极313电连接。
示例性地，电容4的第二极41还可以用作自发光器件2的阳极21，这样，后续可以直接形成像素界定层7(如图3所示)，通过像素界定层7可以定义出发光区A 1，蒸镀发光功能层23，最后沉积阴极22，即可完成自发光器2的制作。其中，示例性地，参见图3，像素界定层7包括围设出发光区A 1的部分，和用于填充发光区A 1中各凹陷区域(即对应设置有过孔的位置)的部分。这样使得后续形成的发光功能层23可以更加平整。示例性地，形成像素界定层7的材料为透明材料。
需要说明的是，对于上述透明显示基板01的至少一个薄膜晶体管3中涉及的金属电极，其材料可采用银(Ag)，铜(Cu)，铝(Al)，钼(Mo)，以及合金材料如铝钕(AlNd)、钼铌(MoNb)等中的至少一种。金属电极的结构可以为多层金属结构，如MoNb/Cu/MoNb等。此外，金属电极的结构也可以是金属和透明导电氧化物(如ITO、AZO等)形成的堆栈结构，如Mo/AlNd/ITO、ITO/Ag/ITO等。
对于上述透明显示基板01的至少一个薄膜晶体管3中涉及的有源层，其材料可以采用透明非晶铟镓锌氧化物(a-IGZO)，氮氧化锌(ZnON)，IZTO，非晶硅(a-Si)，多晶硅(p-Si)，六噻吩和聚噻吩中的至少一种。
缓冲层、栅绝缘层315、层间绝缘层316、第二绝缘层5的材料包括但不限于氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiON)等介质材料，或各种新型的有机绝缘材料，或高介电常数(High k)材料如氧化铝(AlOx)，氧化铪(HfOx)，氧化钽(TaOx)等。有机平坦层6的材料包含但不限于聚硅氧烷系、亚克力系或聚酰亚胺系材料。
本公开的一些实施例还提供一种透明显示面板，包括上述的透明显示基板01。该透明显示面板具有与透明显示基板相同的有益效果，在此不再赘述。
在一些实施例中，如图10和图11所示，该透明显示面板还包括盖 板02，盖板02设置于靠近透明显示基板01的阴极的一侧。该盖板02包括第二衬底020和设置于所述第二衬底020上的彩色滤光层和黑矩阵022。彩色滤光层和黑矩阵022设置于与透明显示基板01上的发光区A 1对应的区域。其中，第二衬底020可以为柔性衬底，也可以为玻璃基板等刚性衬底。
示例性地，如图11所示，彩色滤光层包括多个滤光部021，所述多个滤光部021与所述透明显示基板01上的多个发光区A 1一一对应。例如，彩色滤光层至少包括第一基色滤光部(如红色滤光部)、第二基色滤光部(如绿色滤光部)和第三基色滤光部(如蓝色滤光部)三种基色的滤光部。其中，每个第一基色滤光图案、每个第二基色滤光图案、每个第三基色滤光图案分别位于一个亚像素11的发光区。
本示例中，通过在第二衬底020上形成彩色滤光层和黑矩阵022，可使该透明显示面板用于大尺寸的显示器，其中，将彩色滤光层021和黑矩阵022设置于与透明显示基板01上的发光区A 1对应的区域，可保证透明区A 2透明。示例性地，如图10所示，盖板02上与两个像素(如图10中每个像素包括三个亚像素11)之间的部分对应的区域也设置有黑矩阵，这样，可以通过黑矩阵遮挡两个像素之间纵向设置的金属线。而且由于每个像素中的任意相邻两个亚像素11的透明区A 2之间无黑矩阵遮挡，使得每个像素中的所有亚像素11的透明区A 2可以连在一起，从而增大了透明显示面板中透明区的占比。
在一些实施例中，如图11所示，所述盖板02还包括设置于彩色滤光层的远离第二衬底020一侧的第三绝缘层024，以及设置于第三绝缘层024的远离第二衬底020一侧的辅助阴极023，辅助阴极023可以与透明显示基板01上的阴极22电连接。
在此基础上，示例性地，辅助阴极023在第二衬底020上的正投影位于黑矩阵022在第二衬底020上的正投影的范围之内，这样可避免降低开口率。
示例性地，辅助阴极023的材料为金属材料。辅助阴极023的形状可与黑矩阵022相同，即，辅助阴极023的形状可以为网格形状。
通过在第二衬底020上设置辅助阴极023，并使辅助阴极023与透明显示基板01上的阴极22电连接，可降低阴极22上的电压压降。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不 局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种透明显示基板，包括：
    第一衬底；以及，
    设置于所述第一衬底上的多个亚像素；所述多个亚像素中的至少一个亚像素具有发光区和透明区；
    所述至少一个亚像素中的每个亚像素包括位于其发光区内的至少一个薄膜晶体管，电容以及自发光器件；沿垂直于所述第一衬底的方向，所述电容位于所述自发光器件与所述至少一个薄膜晶体管之间；所述至少一个薄膜晶体管和所述电容电连接形成用于驱动所述自发光器件发光的驱动电路的至少一部分。
  2. 根据权利要求1所述的透明显示基板，其中，所述电容包括第一极，所述第一极配置为不可透过光；其中，
    所述自发光器件在所述第一衬底上的正投影位于所述第一极在所述第一衬底上的正投影的范围之内；和/或，
    所述至少一个薄膜晶体管在所述第一衬底上的正投影位于所述第一极在所述第一衬底上的正投影的范围之内。
  3. 根据权利要求2所述的透明显示基板，其中，所述自发光器件包括：
    阳极，设置于所述第一极的远离所述第一衬底的一侧，所述阳极还被配置为所述电容的第二极；
    所述透明显示基板还包括：
    第一绝缘层，设置于所述第一极和所述第二极之间。
  4. 根据权利要求3所述的透明显示基板，其中，所述自发光器件还包括：
    阴极，设置于所述阳极的远离所述第一衬底的一侧，所述阴极配置为可透过光；
    发光功能层，设置于所述阴极与所述阳极之间。
  5. 根据权利要求4所述的透明显示基板，其中，所述阳极的材料包括透明导电材料；所述阴极的材料包括金属材料。
  6. 根据权利要求2～5中任一项所述的透明显示基板，其中，
    所述第一极为单层结构，所述单层结构包括可反射光线的反射电极；或者，
    所述第一极为层叠构成的多层结构，所述多层结构包括至少一层可反射光线的反射电极和至少一层可透过光线的透明电极。
  7. 根据权利要求3～6中任一项所述的透明显示基板，其中，所述至少一个薄膜晶体管包括一个驱动薄膜晶体管；
    所述驱动薄膜晶体管包括第一栅极，第一源极和第一漏极；所述第一栅极与所述第一极电连接。
  8. 根据权利要求7所述的透明显示基板，其中，所述第一绝缘层在位于所述发光区的部分设置有第一过孔；
    所述第二极通过所述第一过孔与所述第一漏极或所述第一源极电连接。
  9. 根据权利要求7或8所述的透明显示基板，其中，所述至少一个薄膜晶体管还包括至少一个开关薄膜晶体管，所述至少一个开关薄膜晶体管包括第一开关薄膜晶体管；所述第一开关薄膜晶体管包括第二栅极、第二源极和第二漏极；
    所述透明显示基板还包括数据线和栅线，所述第二源极与所述数据线电连接，所述第二栅极与所述栅线电连接，所述第二漏极与所述第一极电连接。
  10. 根据权利要求9所述的透明显示基板，其中，
    所述驱动薄膜晶体管和所述第一开关薄膜晶体管均为顶栅型薄膜晶体管；所述第一栅极和所述第二栅极同层设置；所述第一源极，所述第二源极，所述第一漏极，及所述第二漏极同层设置。
  11. 根据权利要求1～10中任一项所述的透明显示基板，其中，所述透明显示基板还包括：
    第二绝缘层，设置在所述电容和所述至少一个薄膜晶体管之间；所述第二绝缘层至少覆盖所述透明显示基板的显示区。
  12. 根据权利要求11所述的透明显示基板，其中，所述透明显示基板还包括：
    平坦层，设置于所述第二绝缘层和所述电容之间；所述平坦层在各所述亚像素的透明区无覆盖或大致无覆盖。
  13. 根据权利要求12所述的透明显示基板，其中，所述第二绝缘层的位于所述发光区的部分设置有第二过孔、第三过孔和第四过孔；
    所述平坦层的位于所述发光区的部分设置有与所述第二过孔连通的第五过孔，与所述第三过孔连通的第六过孔，以及与所述第四过孔连通的第七过孔；
    在所述至少一个薄膜晶体管包括所述驱动薄膜晶体管和所述第一 开关薄膜晶体管的情况下，所述电容的第一极通过所述第二过孔和所述第五过孔电连接至所述第一开关薄膜晶体管的第二漏极，并且所述电容的第一极通过所述第三过孔和所述第六过孔电连接至所述驱动薄膜晶体管的第一栅极；
    所述电容的第二极通过所述第四过孔和所述第七过孔电连接至所述驱动薄膜晶体管的第一源极或第一漏极。
  14. 一种透明显示基板的制作方法，包括：
    提供第一衬底；
    在所述第一衬底上形成多个亚像素；所述多个亚像素中的至少一个亚像素具有发光区和透明区；
    所述至少一个亚像素中的每个亚像素包括依次形成在其发光区的至少一个薄膜晶体管、电容及自发光器件；沿垂直于所述第一衬底的方向，所述电容位于所述自发光器件与所述至少一个薄膜晶体管之间；
    所述至少一个薄膜晶体管和所述电容电连接形成用于驱动所述自发光器件发光的驱动电路的至少一部分。
  15. 根据权利要求14所述的制作方法，其中，所述在所述第一衬底上形成多个亚像素的步骤，包括：
    在所述第一衬底上形成有源层、栅绝缘层、栅金属层以及源漏金属层；所述有源层、栅绝缘层、栅金属层以及源漏金属层形成所述至少一个薄膜晶体管；所述至少一个薄膜晶体管包括驱动薄膜晶体管和第一开关薄膜晶体管，所述驱动薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第一开关薄膜晶体管包括第二栅极、第二源极和第二漏极；
    在所述源漏金属层远离所述第一衬底的一侧形成第一电极层，所述第一电极层包括所述电容的第一极；所述电容的第一极与所述第一栅极电连接，并且所述电容的第一极与所述第二漏极电连接；
    在所述第一电极层远离所述第一衬底的一侧形成第一绝缘层；
    在所述第一绝缘层远离所述第一衬底的一侧形成第二电极层；所述第二电极层包括所述电容的第二极，所述电容的第二极与所述第一源极或所述第一漏极电连接。
  16. 一种透明显示面板，包括如权利要求1～13中任一项所述的透明显示基板。
  17. 根据权利要求16所述的透明显示面板，其中，所述透明显示面板还包括：
    设置于所述透明显示基板一侧的盖板，所述盖板包括：
    第二衬底；
    设置于所述第二衬底上的彩色滤光层和黑矩阵；所述彩色滤光层和所述黑矩阵位于与所述透明显示基板上的发光区对应的区域。
  18. 根据权利要求17所述的透明显示面板，其中，所述彩色滤光层包括多个滤光部，所述多个滤光部与所述透明显示基板上的多个发光区一一对应。
  19. 根据权利要求17或18所述的透明显示面板，其中，所述盖板还包括：
    第三绝缘层，设置于所述彩色滤光层的远离所述第二衬底一侧；
    辅助电极，设置于所述第三绝缘层的远离所述第二衬底一侧，所述辅助阴极与所述透明显示基板的自发光器件所包括的阴极电连接。
  20. 根据权利要求19所述的透明显示面板，其中，所述辅助阴极在第二衬底上的正投影位于所述黑矩阵在所述第二衬底上的正投影的范围之内。
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