WO2023123668A1 - 一种控制放大电路、灵敏放大器和半导体存储器 - Google Patents

一种控制放大电路、灵敏放大器和半导体存储器 Download PDF

Info

Publication number
WO2023123668A1
WO2023123668A1 PCT/CN2022/079726 CN2022079726W WO2023123668A1 WO 2023123668 A1 WO2023123668 A1 WO 2023123668A1 CN 2022079726 W CN2022079726 W CN 2022079726W WO 2023123668 A1 WO2023123668 A1 WO 2023123668A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
circuit
control
voltage value
switch tube
Prior art date
Application number
PCT/CN2022/079726
Other languages
English (en)
French (fr)
Inventor
尚为兵
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22912974.7A priority Critical patent/EP4276829A1/en
Priority to US17/807,135 priority patent/US11894048B2/en
Publication of WO2023123668A1 publication Critical patent/WO2023123668A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, in particular to a control amplifier circuit, a sensitive amplifier and a semiconductor memory.
  • Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers, consisting of many repeated storage units.
  • DRAM Dynamic Random Access Memory
  • the read data signal of each memory cell is read through the local data line, the global data line and the data bus in turn; otherwise, in the process of data writing, the write data signal is sequentially passed through The data bus, the global data lines and the local data lines write to the memory cells.
  • the disclosure provides a control amplifier circuit, a sensitive amplifier and a semiconductor memory, which can improve the problems of slow signal amplification and easy noise generation.
  • an embodiment of the present disclosure provides a control amplifier circuit, including:
  • the power output circuit is used to receive the power switching signal, and select one of the preset voltage values from at least two preset voltage values according to the power switching signal to output as the preset power signal;
  • the isolated control circuit is used to receive the control command signal and the preset power signal, and generate an isolated control signal according to the control command signal;
  • the amplifying circuit is used to receive the isolated control signal and the signal to be processed, and amplify the signal to be processed based on the isolated control signal to obtain a target amplified signal.
  • the power switching signal includes a first power switching signal and/or a second power switching signal
  • the control amplifier circuit further includes a power switching circuit; the power switching circuit is used to output the first power switching signal and/or the second Power switching signal; power output circuit, specifically for receiving the first power switching signal and/or the second power switching signal, and selecting from at least two preset voltage values according to the first power switching signal and/or the second power switching signal Select one of the preset voltage values to output as the preset power signal.
  • the preset voltage value includes a first voltage value and a second voltage value; the power supply output circuit is also used for when the first power switching signal is in the first level state and the second power switching signal is in the second In the level state, select the first voltage value to output as the preset power signal; or when the first power switching signal is in the second level state and the second power switching signal is in the first level state, select the second voltage value
  • the output is a preset power supply signal; wherein, both the first voltage value and the second voltage value belong to the second level state, and the first voltage value is greater than the second voltage value.
  • the signal control circuit is used to output the control instruction signal; the isolation control circuit is also used to generate an isolation control signal with a third voltage value when the control instruction signal is in the first state; or when the control instruction signal When in the second state, an isolation control signal with the same voltage value as the preset power supply signal is generated; wherein, the first state is the first level state or the second level state, and the second state is the first level state or the second level state. Level state, the level state of the first state and the second state are different; the third voltage value belongs to the first level state, and the third voltage value is smaller than the second voltage value.
  • the power output circuit includes a first preset power supply, a second preset power supply, a first switching tube, and a second switching tube; wherein, the first end of the first switching tube is connected to the first power switching signal, The first end of the second switching tube is connected to the switching signal of the second power supply; the second end of the first switching tube is connected to the first preset power supply, and the second end of the second switching tube is connected to the second preset power supply; the first The third end of the switch tube is connected to the third end of the second switch tube, and is used to output a preset power supply signal; wherein, the first preset power supply is used to output the first voltage value, and the second preset power supply is used to output the first preset power supply signal. Two voltage values.
  • the isolation control circuit includes a first inverter, a third switching tube, and a fourth switching tube; wherein, the input end of the first inverter is connected to the control instruction signal, and the output end of the first inverter respectively connected to the first end of the third switching tube and the first end of the fourth switching tube; the second end of the third switching tube is connected to the preset power signal, and the third end of the fourth switching tube is connected to the ground signal; The third end of the three switch tubes is connected to the second end of the fourth switch tube for outputting an isolation control signal.
  • the amplifying circuit includes a cross-coupling circuit and a control circuit; wherein, the amplifying circuit is also used to receive the signal to be processed through the cross-coupling circuit, receive the isolated control signal through the control circuit, and perform processing on the signal to be processed according to the isolated control signal. Amplify and process to obtain the target amplified signal.
  • the cross-coupling circuit includes a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eighth switch tube
  • the control circuit includes a ninth switch tube and a tenth switch tube
  • the first end of the fifth switch tube is connected to the third end of the ninth switch tube for receiving the signal to be processed, the second end of the fifth switch tube, the third end of the seventh switch tube, and the eighth switch tube
  • the first end is connected to the second end of the tenth switch tube;
  • the first end of the sixth switch tube is connected to the third end of the tenth switch tube for receiving the reference signal to be processed, the second end of the sixth switch tube, the third end of the eighth switch tube, and the seventh switch tube
  • the first end of the ninth switch tube is connected to the second end;
  • the third terminal of the fifth switching tube and the third terminal of the sixth switching tube are connected to the first reference signal
  • the second terminal of the seventh switching tube and the second terminal of the eighth switching tube are connected to the second reference signal
  • the ninth switching tube is connected to the second reference signal.
  • the first end of the switch tube and the first end of the tenth switch tube are connected to the isolation control signal.
  • the amplifying circuit further includes a first reference circuit and a second reference circuit; wherein the first reference circuit is configured to receive the first reference control signal, and output the first reference signal according to the first reference control signal;
  • the second reference circuit is configured to receive the second reference control signal, and output the second reference signal according to the second reference control signal; wherein, the voltage value of the first reference signal is the fourth voltage value or the fifth voltage value, and the second The voltage value of the reference signal is the fourth voltage value or the sixth voltage value, and the fourth voltage value is an intermediate value between the fifth voltage value and the sixth voltage value.
  • the first reference circuit includes n eleventh switch tubes, where n is a positive integer; the first terminal of the eleventh switch tube is connected to the first reference control signal, and the third terminal of the eleventh switch tube connected to the ground signal; the second end of the eleventh switch tube is connected to the output end of the first reference circuit for outputting the first reference signal.
  • the second reference circuit includes m twelfth switch tubes, where m is a positive integer; the first end of the twelfth switch tube is connected to the second reference control signal, and the second end of the twelfth switch tube connected to the third preset power supply; the second end of the twelfth switch tube is connected to the output end of the second reference circuit for outputting the second reference signal.
  • the amplification circuit further includes a first signal establishment circuit and a second signal establishment circuit; wherein, the first signal establishment circuit is used to receive the first control input signal and output the first reference control signal; the second signal establishment The circuit is used for receiving the second control input signal and outputting the second reference control signal.
  • the first signal establishment circuit includes n second inverters, and the second signal establishment circuit includes n third inverters; wherein, the input terminal of the second inverter is connected to the first control input signal connected, the output terminal of the second inverter is used to output the first reference control signal; wherein, in the n second inverters, the first reference control signal of each eleventh switching tube passes through a second inverter The output of the third inverter; the input end of the third inverter is connected to the first control input signal, and the output end of the third inverter is used to output the second reference control signal; wherein, in the m third inverters, each The second reference control signal of the twelfth switch tube is output through a third inverter.
  • the amplifying circuit further includes a pre-charging circuit
  • the pre-charging circuit includes a thirteenth switching tube and a fourteenth switching tube; wherein, the first end of the thirteenth switching tube, the first terminal of the fourteenth switching tube One end is connected to the pre-charging signal; the second end of the thirteenth switch tube is connected to the fourth preset power supply, and the third end of the thirteenth switch tube is connected to the second end of the sixth switch tube;
  • the third end of the fourteenth switch transistor is connected to the second end of the fifth switch transistor, and the second end of the fourteenth switch transistor is connected to the second end of the sixth switch transistor.
  • the amplifying circuit further includes a noise elimination circuit
  • the noise elimination circuit includes a fifteenth switch tube and a sixteenth switch tube; wherein, the first end of the fifteenth switch tube, the first end of the sixteenth switch tube The end is connected with the noise elimination signal; the second end of the fifteenth switch tube is connected with the second end of the fifth switch tube, and the third end of the fifteenth switch tube is connected with the first end of the fifth switch tube; the sixteenth switch tube is connected with the first end of the fifth switch tube; The second end of the switch transistor is connected to the second end of the sixth switch transistor, and the third end of the sixteenth switch transistor is connected to the first end of the sixth switch transistor.
  • the first switch tube, the second switch tube, the third switch tube, the seventh switch tube and the eighth switch tube are P-type channel field effect tubes; the fourth switch tube, the fifth switch tube, the sixth switch tube N Type Trench Field Effect Transistor.
  • the embodiment of the present disclosure provides a control method of an amplifying circuit, which is applied to an amplifying circuit connected to a target detection unit, and the control method includes:
  • the power output circuit selects the second voltage value to output as the preset power signal according to the power switching signal, and the isolation control circuit generates an isolation control signal with the second voltage value according to the control instruction signal of the second state , the amplifying circuit receives the isolated control signal and the signal to be processed, and performs preliminary amplification processing on the signal to be processed;
  • the power output circuit selects the first voltage value to output as the preset power signal according to the power switching signal, and the isolation control circuit generates an isolation control signal with the first voltage value according to the control command signal in the second state, and amplifies
  • the circuit receives and performs secondary amplification processing on the signal to be processed according to the isolated control signal.
  • the amplifying circuit is still in the standby phase, the first charge sharing phase, the second charge sharing phase and the pre-charging phase; the method further includes:
  • the power output circuit selects the second voltage value according to the power switching signal to output as a preset power signal, and the isolation control circuit generates a control command signal according to the second state.
  • the isolation control signal of the second voltage value when the amplifying circuit is in the first charge sharing stage, the power output circuit selects the second voltage value to output as the preset power signal according to the power switching signal, and the isolation control circuit according to the control command signal of the first state An isolation control signal with a third voltage value is generated, and the amplifying circuit receives the signal to be processed to perform the first charge sharing.
  • an embodiment of the present disclosure provides a sense amplifier, including the control amplifier circuit described in any one of the first aspect.
  • an embodiment of the present disclosure provides a semiconductor memory, including the sense amplifier according to any one of the third aspect.
  • An embodiment of the present disclosure provides a control amplifier circuit, a sense amplifier, and a semiconductor memory.
  • the control amplifier circuit includes: a power output circuit for receiving a power switching signal and selecting from at least two preset voltage values according to the power switching signal One of the preset voltage value outputs is the preset power signal; the isolation control circuit is used to receive the control command signal and the preset power signal, and generates an isolated control signal according to the control command signal; the amplifier circuit is used to receive the isolation control signal and the standby power signal.
  • the signal is processed, and the signal to be processed is amplified based on the isolated control signal to obtain the target amplified signal.
  • the specific voltage value of the preset power signal can be adjusted by using the power switching signal, and then the specific voltage value of the isolation control circuit can be adjusted, the signal amplification process can be optimized, and the problems of slow signal amplification and easy noise generation can be partially improved.
  • Fig. 1 is a schematic diagram of an application scenario of a sensitive amplifier
  • FIG. 2 is a schematic diagram of the composition and structure of a control amplifier circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of the composition and structure of another control amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a partial detailed structure of a control amplifier circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a partial detailed structural schematic diagram of another control amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of an inverter provided by an embodiment of the present disclosure.
  • FIG. 7 is a partial detailed structural schematic diagram of another control amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of an application scenario of a control amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic flowchart of a method for controlling an amplifying circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic flowchart of another method for controlling an amplifying circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of an application scenario of another control amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of signal timing of an amplification circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of signal timing provided by the related art.
  • FIG. 14 is a schematic diagram of the composition and structure of a sense amplifier provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the composition and structure of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific ordering of objects. Understandably, “first ⁇ second ⁇ third 3" where permitted, the specific order or sequence may be interchanged such that the embodiments of the disclosure described herein can be practiced in sequences other than those illustrated or described herein.
  • P-type field effect tube hole type field effect tube
  • N-type field effect tube electronic field effect tube.
  • FIG. 1 shows a schematic diagram of an application scenario of a sense amplifier.
  • the application scenario includes a first signal line 11 , a second signal line 12 , and a sense amplifier 113 . in,
  • the first signal line 11 has a first switch 111 and a first capacitor 112 for inputting the signal Vin+ to be processed; the second signal line 12 has a second switch 121 and a second capacitor 122 for inputting a reference signal to be processed
  • the signal Vin-, the sense amplifier 113 is used to amplify the signal to be processed Vin+ and the reference signal Vin- to be processed, and the signal Vin+ to be processed and the reference signal Vin- to be processed have a voltage difference of ⁇ Vin.
  • the first switch 111 and the first capacitor 112 can be regarded as a storage unit, and the second switch 121 and the second capacitor 122 can be regarded as another storage unit.
  • the sense amplifier includes a first switch tube 131 , a second switch tube 132 , a third switch tube 133 and a fourth switch tube 134 .
  • the first end of the first switch tube 131, the first end of the second switch tube 132, the third end of the third switch tube 133, and the second end of the fourth switch tube 134 are all connected to the reference signal Vin- to be processed.
  • the third end of the first switch 131 , the second end of the second switch 132 , the first end of the third switch 133 , and the first end of the fourth switch 134 are all connected to the signal Vin+ to be processed.
  • a fifth switching tube 135 and a sixth switching tube 136 there are also a fifth switching tube 135 and a sixth switching tube 136, the first end of the fifth switching tube 135 is connected to the first control signal SAP, the second end of the fifth switching tube 135 is connected to the power signal VBLH, The third terminal of the fifth switching transistor 135, the second terminal of the first switching transistor 131 and the second terminal of the third switching transistor 133 are connected to form a first reference signal terminal.
  • the first terminal of the sixth switching tube 136 is connected to the second control signal SAN, the second terminal of the sixth switching tube 136 is connected to the ground signal GND, the second terminal of the sixth switching tube 136, the third terminal of the second switching tube 132 terminal is connected to the third terminal of the fourth switch tube 134 to form a second reference signal terminal.
  • the first switch tube 131, the third switch tube 132, and the fifth switch tube 135 are P-type field effect transistors, the first end of the P-type field effect transistor is a gate pin, and the second end of the P-type field effect transistor is is the source pin, the third end of the P-type field effect transistor is the drain pin; the second switch tube 132, the fourth switch tube 134 and the sixth switch tube 136 are N-type field effect tubes, and the N-type field effect tube
  • the first terminal of the NFET is the gate pin, the second terminal of the NFET is the drain pin, and the third terminal of the NFET is the source pin.
  • pre-charging circuit between the first signal line 11 and the second signal line 12
  • pre-charging circuit between the second terminal of the third switching tube 133 and the third terminal of the fourth switching tube. , for performing precharge processing on the first reference signal terminal and the second reference signal terminal.
  • the signal amplification speed of the sensitive amplifier is slow, the circuit is prone to noise, and the power consumption is high, which affects the performance of the semiconductor memory.
  • An embodiment of the present disclosure provides a control amplifier circuit, including: a power output circuit, configured to receive a power switching signal, and select one of the preset voltage values from at least two preset voltage values according to the power switching signal to output as a preset Power signal; isolated control circuit, used to receive control command signal and preset power signal, and generate isolated control signal according to control command signal; amplifying circuit, used to receive isolated control signal and signal to be processed, and to be processed based on isolated control signal The signal is amplified to obtain the target amplified signal.
  • the specific voltage value of the preset power signal can be adjusted by using the power switching signal, and then the specific voltage value of the isolation control signal can be adjusted, the signal amplification process can be optimized, and the problems of slow signal amplification and easy noise generation can be improved.
  • FIG. 2 shows a schematic diagram of the composition and structure of a control amplifier circuit 20 provided by an embodiment of the present disclosure.
  • the control amplifier circuit 20 may include:
  • the power output circuit 21 is used to receive the power switching signal, and select one of the preset voltage values from at least two preset voltage values according to the power switching signal to output as the preset power signal;
  • the isolation control circuit 22 is used to receive the control instruction signal and the preset power supply signal, and generate an isolation control signal according to the control instruction signal;
  • the amplifying circuit 23 is configured to receive the isolation control signal and the signal to be processed, and amplify the signal to be processed based on the isolation control signal to obtain a target amplified signal.
  • control amplifier circuit 20 provided by the embodiment of the present disclosure can be applied in various signal amplification scenarios, for example, a sense amplifier in a DRAM.
  • the control amplifier circuit 20 receives the power switching signal, the control instruction signal and the signal to be processed from the outside, completes the signal amplification process based on the power switching signal and the control instruction signal, and finally obtains the target amplified signal.
  • both the control command signal and the power switching signal need to be determined according to the specific working stage of the amplifier circuit.
  • the control amplifier circuit 20 through the power output circuit 21, at least two preset voltage values are selected and output according to the power switching signal to obtain the preset power signal; through the isolation control circuit 22, according to the control instruction signal and The power supply signal is preset, and an isolation control signal is output; through the amplifying circuit 23, the signal to be processed is amplified according to the isolation control signal, and a target amplified signal is output.
  • the specific voltage value of the preset power signal can be adjusted by using the power switching signal, and then the specific voltage value of the isolation control signal output by the isolation control circuit 22 can be adjusted, the signal amplification process can be optimized, and the problems of slow signal amplification and easy noise generation can be improved.
  • the power switching signal may include a first power switching signal and/or a second power switching signal.
  • the control amplifier circuit 20 may also include a power switching circuit 24;
  • a power switching circuit 24 configured to output a first power switching signal and/or a second power switching signal
  • the power output circuit 21 is specifically configured to receive the first power switching signal and/or the second power switching signal, and select one of at least two preset voltage values according to the first power switching signal and/or the second power switching signal The preset voltage value is output as a preset power signal.
  • the power switching signal may only include one signal, such as the first power switching signal or the second power switching signal; or, the power switching signal may include a pair of signals with opposite level states, such as including the first power switching signal and the second power switching signal.
  • the power switching signal includes both the first power switching signal and the second power switching signal.
  • the power output circuit 21 is also used to generate a preset power signal with a first voltage value when the first power switching signal is in the first level state and the second power switching signal is in the second level state; or
  • both the first voltage value and the second voltage value belong to the second level state, and the first voltage value is greater than the second voltage value.
  • the first level state can make it in an on state, and the second level state can make it in an off state; for an N-type field effect transistor, the second level state can make it in an off state; A level state enables it to be in an off state, and a second level state enables it to be in an on state.
  • the first level states of different switch tubes may be in different voltage ranges.
  • the power switching signal only includes the first power switching signal.
  • the power output circuit 21 is also used to generate a preset power signal with a first voltage value when the first power switching signal is in the first level state; or when the first power switching signal is in the second level state , generating a preset power signal with a second voltage value.
  • the power output circuit 21 can output two preset power signals with different voltage values instead of a power signal with a fixed voltage value.
  • more control means can be provided by adjusting the voltage value of the preset power supply signal, thereby partially improving the problems of slow signal amplification speed and large circuit noise.
  • control amplifier circuit 20 may further include a signal control circuit 25;
  • a signal control circuit 25, configured to output a control command signal
  • the isolation control circuit 22 is further configured to generate an isolation control signal with a third voltage value when the control command signal is in the first state;
  • the first state is the first level state
  • the second state is the second level state
  • the first state is the second level state
  • the second state is the first level state
  • the isolation control signal if the control command signal is in the first level state and the preset power supply signal has the first voltage value, the isolation control signal has the first voltage value; if the control command signal is in the In the first level state, and the preset power signal has a second voltage value, the isolation control signal has a second voltage value; if the control instruction signal is in the first state, the isolation control signal has a third voltage value.
  • the isolation control signal has the first voltage value; when the control instruction signal is in the second level state and the preset When the power signal has the second voltage value, the isolation control signal has the second voltage value; when the control instruction signal is in the first level state, the isolation control signal has the third voltage value.
  • the third voltage value belongs to the first level state, both the first voltage value and the second voltage value belong to the second level state, and the third voltage value is lower than the second voltage value, and the second voltage value is lower than the first voltage value. a voltage value.
  • the first level state can be represented by logic "0”
  • the second level state can be represented by logic "1”
  • the third voltage value can be represented by logic " 0”
  • the first voltage value and the second voltage value can both be expressed as a logic "1”
  • the above is only a schematic illustration, and does not have actual limiting content.
  • the power output circuit 21 is provided by taking the power switching signal including both the first power switching signal and the second power switching signal as an example.
  • the power output circuit 21 includes a first preset power supply VisoH, a second preset power supply VisoL, a first switch tube 301 and a second switch tube 302; wherein,
  • the first end of the first switching tube 301 is connected to the first power switching signal, and the first end of the second switching tube 302 is connected to the second power switching signal;
  • the second end of the first switching tube 301 is connected to the first preset power supply VisoH, and the second end of the second switching tube 302 is connected to the second preset power supply VisoL;
  • the third end of the first switch tube 301 is connected to the third end of the second switch tube 302 for outputting a preset power signal VisoInt.
  • the first preset power supply VisoH is used to output the first voltage value
  • the second preset power supply VisoL is used to output the second voltage value
  • both the first switching transistor 301 and the second switching transistor 302 are P-type field effect transistors.
  • the first end of the P-type field effect transistor is a gate pin
  • the second end of the P-type field effect transistor is a source pin
  • the third end of the P-type field effect transistor is a drain pin.
  • the first switch tube 301 when the first power switching signal is in the first level state and the second power switching signal is in the second level state, the first switch tube 301 is turned on and the second switch tube 302 is turned off, so the preset The voltage value of the power supply signal VisoInt is the same as that of the first preset power supply VisoH, that is, the preset power supply signal VisoInt is the first voltage value; when the first power switching signal is in the second level state and the second power switching signal is in the first level state, the first switch 301 is turned off and the second switch 302 is turned on, so the voltage value of the preset power signal VisoInt is the same as that of the second preset power source VisoL, that is, the preset power signal VisoInt is the second voltage value.
  • the isolation control signal Iso can also be controlled to a higher voltage (first voltage value) or a lower voltage (second voltage value). , to adapt to the voltage requirements and signal transmission speed of different amplification stages, and then optimize the signal amplification process, increase the signal amplification speed, and reduce circuit noise.
  • the isolation control circuit 22 includes a first inverter 321, a third switching tube 303, and a fourth switching tube 304; wherein,
  • the input end of the first inverter 321 is connected with the output end of the signal control circuit 25, and receives the control command signal output by the signal control circuit 25, and the output end of the first inverter 321 is connected with the first end of the third switching tube 303 respectively. connected to the first end of the fourth switching tube 304;
  • the second terminal of the third switching tube 303 is connected to the preset power signal VisoInt, and the third terminal of the fourth switching tube 304 is connected to the ground signal;
  • the third terminal of the third switching transistor 303 is connected to the second terminal of the fourth switching transistor 304 for outputting the isolation control signal Iso.
  • the third switch transistor 303 is a P-type field effect transistor
  • the fourth switch transistor 304 is an N-type field effect transistor.
  • the first end of the NFET is a gate pin
  • the second end of the NFET is a drain pin
  • the third end of the NFET is a source pin.
  • the isolation control signal Iso has a third voltage value, which is equivalent to grounding Potential;
  • the third switch tube 303 is in the conduction state, and the fourth switch tube 304 is in the off state, thereby isolating the voltage value of the control signal Iso from the voltage value of the preset power supply signal
  • the voltage values VisoInt are the same, that is, the first voltage value or the second voltage value.
  • the circuit of the isolation control circuit 22 may also only include the third switching tube 303 and the fourth switching tube 304, and the signal control circuit 25
  • the output end of the third switch tube 303 is connected to the first end of the fourth switch tube 304, and other connections remain unchanged;
  • the third switch tube 303 is in the off state, and the fourth switch tube 304 is in the on state, so that the isolation control signal Iso has a third voltage value, which is equivalent to grounding Potential;
  • the third switch tube 303 is in the conduction state, and the fourth switch tube 304 is in the off state, thereby isolating the voltage value of the control signal Iso from the voltage value of the preset power supply signal
  • the voltage values VisoInt are the same, that is, the first voltage value or the second voltage value.
  • the amplifying circuit 23 includes a cross-coupling circuit 231 and a control circuit 232; wherein,
  • the amplifying circuit 23 is also used to receive the signal to be processed through the cross-coupling circuit 231, receive the isolation control signal through the control circuit 232, and amplify the signal to be processed according to the isolation control signal to obtain the target amplified signal.
  • the cross-coupling circuit 231 is connected to a target detection unit through a bit line, and is connected to a complementary storage unit through a complementary bit line.
  • the potentials on the bit line and the complementary bit line are the same.
  • the storage unit on the bit line i.e. the target detection unit
  • the storage unit on the complementary bit line shares the charge with the bit line, so that the potential on the bit line increases or decreases; the storage unit on the complementary bit line is always off, so The potential on the complementary bit line does not change.
  • the signal received by the cross-coupling circuit 231 from the bit line can be regarded as a signal to be processed, and the signal received by the cross-coupling circuit 231 from the complementary bit line can be regarded as a reference signal to be processed.
  • the cross-coupling circuit 231 also includes a read bit line connected to one set of switch transistors and a complementary read bit line connected to another set of switch transistors.
  • the control circuit 22 controls the isolation control signal to be in the first level state, the bit line and the readout bit line are not connected, and the complementary bit line is not connected to the complementary readout bit line; when the isolation control signal is in the first level state At this time, the control circuit 22 can control the connection of the bit line and the read bit line, and the connection of the complementary bit line and the complementary read bit line.
  • the cross-coupling circuit 231 will complete the signal amplification process by means of the readout bit line/complementary readout bit line. For details, refer to the subsequent content.
  • control circuit 232 includes a ninth switching tube 309 and a tenth switching tube 310; wherein,
  • the first end of the fifth switch tube 305 is connected to the third end of the ninth switch tube 309 for receiving the signal to be processed, the second end of the fifth switch tube 305, the third end of the seventh switch tube 307, the third end of the seventh switch tube 307, The first end of the eighth switch tube 308 is connected to the second end of the tenth switch tube 310; the second end of the fifth switch tube 305, the third end of the seventh switch tube 307, the first end of the eighth switch tube 308 and The second ends of the tenth switch transistors 310 are both connected to the complementary readout bit lines.
  • the first end of the sixth switch tube 306 is connected to the third end of the tenth switch tube 310 for receiving the reference signal to be processed, the second end of the sixth switch tube 306, the third end of the eighth switch tube 308, The first end of the seventh switch tube 307 is connected to the second end of the ninth switch tube 309; the second end of the sixth switch tube 306, the third end of the eighth switch tube 308, the first end of the seventh switch tube 307 and the second terminal of the ninth switch transistor 309 are both connected to the read bit line.
  • the third terminal of the fifth switching tube 305 and the third terminal of the sixth switching tube 306 are connected to the first reference signal NCS, and the second terminal of the seventh switching tube 307 and the second terminal of the eighth switching tube 308 are connected to the second reference signal NCS.
  • the signal PCS is connected, and the first end of the ninth switching transistor 309 and the first end of the tenth switching transistor 310 are connected to the isolation control signal Iso.
  • the fifth switch tube 305, the sixth switch tube 306, the ninth switch tube 309 and the tenth switch tube 310 are N-type field effect transistors, and the seventh switch tube 307 and the eighth switch tube 308 are P-type field effect transistors. effect tube.
  • the ninth switch tube 309 and the tenth switch tube 310 in the control circuit 232 are turned on,
  • the cross-coupling circuit 231 receives the signal to be processed; when the isolation control signal Iso is in the first level state (with a third voltage value), the ninth switching tube 309 and the tenth switching tube 310 in the control circuit 232 are turned off Yes, the cross-coupling circuit 231 is not connected to external signals.
  • the first reference signal NCS can be used to provide a low reference potential for the cross-coupling circuit 231
  • the second reference signal PCS can be used to provide a high reference potential for the cross-coupling circuit 231 .
  • the amplification stage of the cross-coupling circuit 231 includes: a first amplification stage and an evolution stage.
  • the isolation control signal Iso is at the second voltage value of the second level state
  • the ninth switch tube 309 and the tenth switch tube 310 are turned on
  • the bit line is connected to the read bit line
  • the complementary bit line is connected to the complementary bit line.
  • the read bit line is connected.
  • the reference signal to be processed is transmitted to the read bit line so that the sixth switch tube 306 is in a conducting state, and the potential of the read bit line is pulled down based on the low reference potential, and then the seventh switch tube 307 is in a conducting state, and pulls up the potential of the complementary readout bit line based on the high reference potential; and
  • the isolation control signal Iso is at the first voltage value of the second level state
  • the conduction degree of the ninth switch tube 309 and the tenth switch tube 310 increases, and the transmission of the ninth switch tube 309 will pull down the
  • the potential of the read bit line is transmitted to the bit line
  • the reference signal to be processed on the bit line is quickly pulled down
  • the reference signal to be processed on the complementary bit line is quickly pulled up through the transmission of the tenth switch tube 310, so that The pressure difference between the signal to be processed and the reference signal to be processed is increased to obtain the target amplified signal.
  • the fifth switch tube 305 is in the conduction state, and the complementary readout bit is based on the low reference potential
  • the potential of the line is pulled down, the eighth switch tube 308 is in the on state, and the potential of the read bit line is pulled up based on the high reference potential;
  • the isolation control signal Iso is at the first voltage value of the second level state
  • the turn-on degree of the ninth switch tube 309 and the tenth switch tube 310 is increased
  • the pulled-up read bit line potential is transmitted to the bit line line, quickly pull up the reference signal to be processed on the bit line, and quickly pull down the reference signal to be processed on the complementary bit line through the transmission of the tenth switch tube 310, so that the difference between the signal to be processed and the reference signal to be processed The pressure difference between them increases, so that the target amplification signal can be obtained subsequently.
  • the isolation control signal Iso is at the second voltage value
  • the gate voltages of the ninth switching tube 309 and the tenth switching tube 310 are relatively low.
  • the voltage of the bit line or the complementary bit line rises slowly, no large noise will be generated, and thus the stored data of the adjacent memory cells will not be affected, so the sensing range of the amplifying circuit 23 can be improved, but the internal nodes of the amplifying circuit 23 are Ability to quickly reach low or high reference potentials.
  • the isolation control signal Iso is at the first voltage value, the gate voltages of the nine switch tubes 309 and the tenth switch tube 310 become higher, and the voltage flowing through the bit line or the complementary bit line becomes larger, due to the internal node voltage of the amplifier circuit 23 has been changed, it will quickly pull the bit line or complementary bit line high or low, improve the signal amplification speed, and suppress the noise when the potential of the bit line or complementary bit line rises.
  • the amplifying circuit 23 further includes a first reference circuit 233 and a second reference circuit 234; wherein,
  • the first reference circuit 233 is configured to receive a first reference control signal, and output a first reference signal according to the first reference control signal;
  • the second reference circuit 234 is configured to receive a second reference control signal, and output a second reference signal according to the second reference control signal;
  • the voltage value of the first reference signal is the fourth voltage value or the fifth voltage value
  • the voltage value of the second reference signal is the fourth voltage value or the sixth voltage value
  • the fourth voltage value is the fifth voltage value and the sixth voltage value.
  • the first reference signal can provide a low reference potential for the cross-coupling circuit 231
  • the second reference signal can provide a high reference potential for the cross-coupling circuit, so that the cross-coupling circuit 231 can be based on the high reference potential (that is, the fifth voltage value) and the low reference potential (that is, the sixth voltage value) to amplify the signal to be processed and the reference signal to be processed.
  • the first reference circuit 233 includes n eleventh switching transistors (for example, the eleventh switching transistor 311-1, the eleventh switching transistor 311-2, and the eleventh switching transistor in FIG. switch tube 311-3), n is a positive integer;
  • the first end of the eleventh switch tube is connected to the first reference control signal (such as pdn1, pdn2, pdn3 in FIG. 5), and the third end of the eleventh switch tube 311 is connected to the ground signal;
  • the first reference control signal such as pdn1, pdn2, pdn3 in FIG. 5
  • the second end of the eleventh switching transistor is connected to the output end of the first reference circuit 233 for outputting the first reference signal NCS.
  • first switching transistors there may be more or fewer eleventh switching transistors in actual application scenarios.
  • first reference control signals there are multiple first reference control signals, and one first reference control signal corresponds to one eleventh switch tube.
  • the level states of the multiple first reference control signals may be different, that is, the respective level states of pdn1 , pdn2 and pdn3 are changed independently. That is to say, one eleventh switching transistor is independently controlled by one first reference control signal.
  • all the eleventh switch transistors may be N-type field effect transistors.
  • the eleventh switching tube 311-1 when the first reference control signal pdn1 is in the first level state, the eleventh switching tube 311-1 is turned off; when the first reference control signal pdn1 is In the second level state, the eleventh switch transistor 311-1 is turned on.
  • the potential of the first reference signal NCS can be adjusted by using the eleventh switch tube in the on state, so as to provide a low reference potential for the cross-coupling circuit 231 .
  • different eleventh switch tubes are respectively connected to a separate ground potential, and specific voltage values of these ground potentials may be different, so as to provide different reduction speeds of the voltage of the first reference signal NCS.
  • the speed at which the voltage of the first reference signal NCS decreases can also be controlled. In this way, the noise generated when the voltage of the signal to be processed drops rapidly during the signal amplification process can be reduced by controlling the voltage adjustment speed to be different.
  • the second reference circuit 234 includes m twelfth switch transistors (for example, the twelfth switch transistor 312-1, the twelfth switch transistor 312-2, the twelfth switch transistor 312-2 in FIG. Twelve switching tubes 312-3), m is a positive integer; the respective first ends of the twelfth switching tubes are connected to the second reference control signal (such as pup1, pup2, pup3 in FIG. 5), and the twelfth switching tubes are respectively The second end of the second end is connected with the third preset power supply (such as Vblh1, Vblh2, Vblh3 in Figure 5);
  • the second terminal of the twelfth switch tube is connected to the output terminal of the second reference circuit 234 for outputting the second reference signal PCS.
  • twelfth switch transistors are shown in FIG. 5 , but in actual application scenarios, there may be more or less twelfth switch transistors 312 .
  • the level states of the plurality of second reference control signals may be different, that is, the respective level states of pup1, pup2 and pup3 are changed independently. That is to say, a twelfth switching transistor is controlled independently by a second reference control signal.
  • the twelfth switch transistor may be an N-type field effect transistor. Therefore, taking the twelfth switch tube 312-1 as an example, when the second reference control signal pup1 is in the first level state, the twelfth switch tube 312-1 is turned off; When pup1 is in the second level state, the eleventh switch tube 312-1 is turned on.
  • the twelfth switch tube in the conduction state charges the second reference signal PCS to the second level state (high reference potential), so as to provide a high reference potential for the cross-coupling circuit 231 .
  • Different twelfth switch tubes are respectively connected to an independent third preset power supply, and the voltage values of these third preset power supplies may be different, so as to provide different voltage rising speeds of the second reference signal PCS.
  • the voltage rising speed can also be controlled. In this way, the noise generated by the second reference signal when the voltage rises rapidly during the signal amplification process can be reduced by controlling the voltage rise speed to be different.
  • the amplifying circuit 23 further includes a first signal establishing circuit 235 and a second signal establishing circuit 236; wherein,
  • the first signal establishment circuit 235 is configured to receive a first control input signal and output a first reference control signal
  • the second signal establishment circuit 236 is configured to receive a second control input signal and output a second reference control signal.
  • the first signal establishment circuit 235 includes n second inverters (such as the second inverter 322-1, the second inverter 322 in FIG. 5 -2, the second inverter 322-3), the second signal establishment circuit 236 includes m third inverters (such as the third inverter 323-1 and the third inverter 323-2 in FIG. 5 , the third inverter 323-3); where,
  • the input terminal of the second inverter is connected with the first control input signal (such as Vpd1, Vpd2, Vpd3 in FIG. 5), and the output terminal of the second inverter is used to output the first reference control signal (such as Vpd1 in FIG. 5 pdn1, pdn2, pdn3); wherein, in the n second inverters, the first reference control signal of each eleventh switching tube is output through one second inverter;
  • the input terminal of the third inverter is connected with the second control input signal (such as Vpu1, Vpu2, Vpu3 in Fig. 5), and the output terminal of the third inverter is used to output the second reference control signal (such as Vpu1 in Fig. 5 pup1, pup2, pup3); wherein, the second reference control signal of each twelfth switching tube is output through a third inverter.
  • the second control input signal such as Vpu1, Vpu2, Vpu3 in Fig. 5
  • the second reference control signal such as Vpu1 in Fig. 5 pup1, pup2, pup3
  • the input end of the second inverter is also connected to the power signal Vncsg.
  • the second inverter When the first control input signal is in the first level state, the second inverter outputs the first reference control signal in the second level state according to the power supply signal Vncsg, and when the first control input signal is in the second level state In the case of the state, the second inverter outputs the first reference control signal in the state of the first level.
  • the input terminal of the third inverter is also connected to the power signal Vpcsg.
  • the third inverter When the second control input signal is in the first level state, the third inverter outputs the second reference control signal in the second level state according to the power signal, and when the second control input signal is in the second level state In the case of , the third inverter outputs the second reference control signal in the first level state.
  • the second inverter and the third inverter may adopt the same circuit structure, for example, implemented by an N-type field effect transistor and a P-type field effect transistor.
  • FIG. 6 it shows a schematic structural diagram of an inverter provided by an embodiment of the present disclosure. The specific structure of the second inverter is shown in Figure 6(a), and the specific structure of the third inverter is shown in Figure 6(b).
  • first control input signals there are multiple first control input signals, one second inverter is used to receive one first control input signal, and the level states of these first control input signals may be different.
  • the second inverter 322-1 when the first control input signal Vpd1 is in the first level state, the second inverter 322-1 outputs the first reference signal in the second level state.
  • control signal pdn1 the eleventh switching tube 311-1 is in the conduction state at this time; on the contrary, when the first control input signal Vpd1 is in the second level state, the output of the second inverter 322-1 is in the first state
  • the level state of the first reference control signal pdn1 at this time the eleventh switch tube 311-1 is in the off state.
  • one third inverter is used to receive one second control input signal, and the level states of these second control input signals may be different.
  • the third inverter 323-1 outputs the second reference signal in the second level state.
  • control signal pup1 at this time the twelfth switching tube 312-1 is in the conduction state; conversely, when the second control input signal Vpu1 is in the second level state, the output of the third inverter 323-1 is in the first state.
  • the level state of the second reference control signal pup1, at this time the twelfth switching tube 312-1 is in the off state.
  • the first reference signal and the second reference signal with different voltage adjustment speeds can be provided to the cross-coupling circuit, and the signal to be processed can be realized. the amplification process.
  • the amplifying circuit 23 further includes a pre-charging circuit, and the pre-charging circuit includes a thirteenth switching tube 313 and a fourteenth switching tube 314; wherein,
  • the first end of the thirteenth switching tube 313 and the first end of the fourteenth switching tube 314 are connected to the pre-charging signal Eq;
  • the second end of the thirteenth switching tube 313 is connected to the fourth preset power supply, and the third end of the thirteenth switching tube 313 is connected to the second end of the sixth switching tube 306;
  • the third end of the fourteenth switch transistor 314 is connected to the second end of the fifth switch transistor 305 , and the second end of the fourteenth switch transistor 314 is connected to the second end of the sixth switch transistor 306 .
  • the thirteenth switching transistor 313 and the fourteenth switching transistor 314 are both N-type field effect transistors.
  • the precharge circuit performs precharge processing for the amplifying circuit 23 in response to the precharge signal Eq, so that each circuit node of the amplifying circuit 23 is at the same voltage value after the precharge processing is completed.
  • the amplifying circuit 23 further includes a noise elimination circuit, and the noise elimination circuit includes a fifteenth switch tube 315 and a sixteenth switch tube 316; wherein,
  • the first end of the fifteenth switch tube 315 and the first end of the sixteenth switch tube 316 are connected to the noise canceling signal Nc;
  • the second end of the fifteenth switch tube 315 is connected to the second end of the fifth switch tube 305, and the third end of the fifteenth switch tube 315 is connected to the first end of the fifth switch tube 305;
  • the second end of the sixteenth switching transistor 316 is connected to the second end of the sixth switching transistor 306 , and the third end of the sixteenth switching transistor 316 is connected to the first end of the sixth switching transistor 306 .
  • the fifteenth switching transistor 315 and the sixteenth switching transistor 316 are both n-type field effect transistors. Therefore, when the noise canceling signal is in the second level state, the fifteenth switch tube 315 and the sixteenth switch tube 316 are in the on state, so that the first terminal and the third terminal of the fifth switch tube 305 are short-circuited. connected, and the first terminal and the third terminal of the sixth switching transistor 306 are short-circuited, so that the offset elimination operation is performed on the fifth switching transistor 305 and the sixth switching transistor 306 . In this way, the threshold value difference of the switch tube during the signal amplification process can be further eliminated, and the accuracy of sensing the signal to be processed during the amplification process can be improved.
  • Fig. 4, Fig. 5 and Fig. 7 are only an optional circuit structure of the control amplifier circuit, wherein the first switch tube 301, the second switch tube 302, the third switch tube 303, the seventh switch tube 307 and The eighth switch tube 308 is a P-type trench field effect tube; the fourth switch tube 304, the fifth switch tube 305, the sixth switch tube 306, the ninth switch tube 309, the tenth switch tube 310, the eleventh switch tube 311,
  • the twelfth switch tube 312 , the thirteenth switch tube 313 , the fourteenth switch tube 314 , the fifteenth switch tube 315 and the sixteenth switch tube 316 are N-type channel field effect transistors.
  • the selection of the above switch tubes does not constitute a limitation of the embodiments of the present disclosure.
  • the aforementioned circuit control logic can be implemented through various types of circuit devices, and specific selection can be made according to the actual application scenarios.
  • a preset power signal with two voltage values (first voltage value or second voltage value) is provided, and the isolation control circuit can be based on the preset power
  • the signal output is an isolated control signal with three different voltage values (first voltage value, second voltage value or third voltage value).
  • the voltage of the preset power signal can be lowered to the second voltage value, so as to reduce the leakage phenomenon of the switch tube in the isolation control circuit, avoid the failure of the switch tube, and prolong the service life of the isolation control circuit;
  • adjust the voltage value of the isolation control signal to be at the first voltage value or the second voltage value, eliminate the noise when the potential of the signal to be processed rises, speed up the voltage change speed of the signal to be processed, and optimize the signal
  • the amplification process is used to improve the problems of slow signal amplification and large circuit noise.
  • FIG. 8 shows a schematic diagram of an application scenario of a control amplifier circuit 20 provided by an embodiment of the present disclosure.
  • a bit line Bla there are a bit line Bla, a complementary bit line Blb, a read bit line saBla, a complementary read bit line saBlb and a control amplifier circuit 20 .
  • a first memory cell 51 is provided on the bit line B1a
  • a second memory cell 52 is provided on the complementary bit line B1b.
  • both the first storage unit 51 and the second storage unit 52 can serve as the aforementioned target detection unit.
  • the control amplifier circuit 20 includes a power output circuit 21 , an isolation control circuit 22 , a power switching circuit 214 , the isolation control circuit 22 and an amplification circuit 23 .
  • the power output circuit 21 includes a first switch tube 301 and a second switch tube 302
  • the isolation control circuit 22 includes a third switch tube 303 , a fourth switch tube 304 and a first inverter 321 .
  • the amplifying circuit 23 may include a fifth switching tube 305, a sixth switching tube 306, a seventh switching tube 307, an eighth switching tube 308, a ninth switching tube 309, a tenth switching tube 310, and three eleventh switching tubes (Fig.
  • FIG. 9 shows a schematic flowchart of a method for controlling an amplifying circuit provided by an embodiment of the present disclosure. As shown in Figure 9, the method may include:
  • the isolation control circuit When the amplifying circuit is in a standby stage, the isolation control circuit generates an isolation control signal having a second voltage value, and the voltages of each node of the amplifying circuit, the first reference signal, and the second reference signal maintain a fourth voltage value.
  • the pre-charge signal is in the second level state
  • the thirteenth switch tube 313 and the fourteenth switch tube 314 are turned on
  • the first reference control signal and the second reference control signal are connected to the fourth power supply
  • each of the amplifying circuits The node voltage, the first reference signal and the second reference signal maintain a fourth voltage value. That is, the bit line Bla, the complementary bit line Blb, the sense bit line saBla, and the complementary sense bit line saBlb are all at the fourth voltage value.
  • the pre-charge signal is in the first level state, and both the thirteenth switch tube 313 and the fourteenth switch tube 314 are turned off.
  • the target detection unit is turned on according to the operation instruction, and transmits the stored potential to the connected bit line Bla to form a signal to be processed, and the amplifying circuit is in the first charge sharing stage.
  • the power output circuit selects the second voltage value according to the power switching signal to output as the preset power signal, and the isolation control circuit generates the isolation control signal Iso with the third voltage value according to the control command signal of the first state.
  • the ninth switch tube 309 and the tenth switch 310 are in the off state, the bit line Bla performs charge sharing with the target detection unit, and the potential of the bit line Bla will be lower or higher than the fourth voltage value.
  • the amplifying circuit receives the signal to be processed and is in the second charge sharing stage; and controlling the isolation control signal to maintain the second voltage value, controlling the first reference signal to maintain the fifth voltage value, and controlling the second reference signal to maintain the sixth voltage value.
  • the power output circuit selects the second voltage value according to the power switching signal to output as the preset power signal, and the isolation control circuit generates the second voltage value according to the control instruction signal of the second state. With the isolation control signal Iso having the second voltage value, the ninth switch 309 and the tenth switch 310 are turned on.
  • the bit line Bla is connected to the read bit line saBla
  • the complementary bit line Blb is connected to the complementary read bit line saBlb
  • the bit line Bla with a voltage value lower than or higher than the fourth voltage is shared with the read bit line saBla, so that the read The potential of the bit line saBla is lower or higher than the fourth voltage value.
  • the amplifying circuit enters a signal amplification stage based on the first reference signal and the second reference signal, and the amplifying circuit amplifies the signal to be processed according to the first reference signal and the second reference signal to obtain a target amplified signal.
  • the signal amplification stage includes a first amplification stage and an evolution stage.
  • the shown method also includes:
  • the power output circuit selects the second voltage value to output as the preset power signal according to the power switching signal, and the isolation control circuit generates an isolation signal with the second voltage value according to the control instruction signal of the second state.
  • the amplifying circuit receives the isolated control signal and the signal to be processed, and performs preliminary amplification processing on the signal to be processed.
  • the isolation control signal continues to maintain the second voltage value, the ninth switching tube 309 and the tenth switching tube 310 are turned on, and the first reference signal is dropped from the fourth voltage value to the fifth Voltage value, the second reference signal rises from the fourth voltage value to the sixth voltage value, due to the change in the potential of the read bit line saBla, the sixth switch tube 306 and the seventh switch tube 307 are turned on, and the read bit line The potential of saBla is pulled up to the sixth voltage value, or the fifth switch transistor 305 or the eighth switch transistor 308 is turned on, and the potential of the read bit line saBla is pulled down to the fifth voltage value.
  • the power output circuit selects the first voltage value to output as the preset power signal according to the power switching signal, and the isolation control circuit generates an isolation control signal with the first voltage value according to the control instruction signal of the second state , the amplifying circuit receives and performs secondary amplifying processing on the signal to be processed according to the isolation control signal.
  • the power output circuit selects the first voltage value to output as the preset power signal according to the power switching signal, and the isolation control circuit generates the isolation control signal Iso with the first voltage value according to the control instruction signal of the second state , the turn-on degree of the ninth switch tube 309 and the tenth switch tube 310 increases, and the potential of the bit line saBla is read out to quickly pull up or down the potential of the bit line Bla to obtain the target amplified signal.
  • pulling up or pulling down the potential of the bit line Bla causes the potential of the connected target detection unit to change synchronously, so as to realize the recovery of the stored data in the target detection unit.
  • the method for controlling the amplifying circuit provided in the embodiment of the present disclosure is applied to the aforesaid amplifying circuit.
  • the amplifying circuit is connected with the target detection unit.
  • the target detection unit may be a storage unit (or called Cell) in the DRAM.
  • the signal amplification stage also includes a precharge stage
  • the switch of the control target detection unit is turned off, and then the amplifying circuit is in the pre-charging stage, and the isolation control signal is controlled to continue to maintain the first voltage value, and the equalization signal is in the second voltage state, passing the fourth preset
  • the power supply controls the first reference signal to recover from the fifth voltage value to the fourth voltage value, controls the second reference signal to recover from the sixth voltage value to the fourth voltage value, and the voltage of each node of the amplifier circuit also recovers to the fourth voltage value.
  • the amplifying circuit when the amplifying circuit is in an evolving state, it is necessary to amplify the signal to be processed, and at the same time write back data to the target detection unit to prevent the data of the target detection unit from being lost after being read.
  • the amplifying circuit is in the pre-charging stage so that the amplifying circuit returns to the state of the standby stage to receive the operation of the next preset operation instruction.
  • FIG. 11 shows a schematic diagram of an application scenario of another control amplifier circuit 20 provided by an embodiment of the present disclosure.
  • the amplifying circuit also has a fifteenth switching tube 315 and a sixteenth switching tube 316 .
  • the amplifying circuit still has a noise elimination phase after the standby phase and before the first charge sharing phase.
  • the isolation control circuit when the amplifying circuit is in the noise elimination stage, the isolation control circuit generates an isolation control signal having a third voltage value according to the control instruction signal in the first state, the first reference signal NCS is a fifth voltage value, and the second reference signal PCS is the sixth voltage value, the noise canceling signal is at the first level state, the fifteenth switch 315 and the sixteenth switch 316 are turned on, and the noise canceling process of the noise canceling circuit is realized.
  • the fifteenth switch tube 315 and the sixteenth switch tube 316 are in the on state, so that the first end and the third end of the fifth switch tube 305 are short-circuited, and the sixth switch The first terminal and the third terminal of the transistor 306 are short-circuited, so as to perform an offset elimination operation on the fifth switching transistor 305 and the sixth switching transistor 306 , and eliminate the threshold voltage difference between the fifth switching transistor 305 and the sixth switching transistor 306 .
  • Vt refers to the threshold voltage of the fifteenth switching tube (or the sixteenth switching tube), which reduces the voltage change speed of the signal to be processed, can suppress the noise in the circuit when the signal to be processed rises, and avoid affecting other storage units , to increase the amplification margin.
  • FIG. 12 shows a schematic diagram of a signal timing sequence of an amplification circuit provided by an embodiment of the present disclosure.
  • the working stages of the amplifying circuit include: a standby stage (or called IDEL), a noise elimination stage (or called NC), a charge sharing stage (or called CS), and a signal amplification stage.
  • the signal amplification stage may also include a first signal amplification stage, an evolution stage and a pre-charging stage.
  • VisoInt refers to the aforementioned preset power signal, which can be the first voltage value and the second voltage value; Iso refers to the aforementioned isolation control signal, which can be the first voltage value, the second voltage value, the third Voltage value; Eq refers to the aforementioned precharge signal, Nc refers to the aforementioned noise elimination signal; SanEn refers to the aforementioned first reference control signal, SapEn refers to the aforementioned second reference control signal; WL refers to the word line open signal , when WL is in the second level state, the word line where the target detection unit is located is turned on, so that the target detection unit and the bit line are connected, and when WL is in the first level state, the word line where the target detection unit is closed is turned off, Thus the target detection unit and the bit line are not connected; NCS/PCS refers to the first reference signal/second reference signal, the first reference signal has the fourth voltage value and the fifth voltage value, and the second reference signal has the fourth voltage value The voltage directions of the
  • the preset power signal VisoInt maintains the second voltage value
  • the isolation control signal Iso maintains the second voltage value
  • the pre-charge signal Eq and the noise elimination signal Nc are in the second level state
  • the first reference control signal SanEn/second reference control signal SapEn are in the first level state
  • the word line WL is in the off state
  • the first reference signal NCS/second reference signal PCS maintain the fourth voltage value
  • the bit line Bla Both the /complementary bit line Blb and the sense bit line saBla/complementary sense bit line saBlb are at the fourth level.
  • each circuit node of the amplifying circuit 23 is at the same voltage value, which is ready for the execution of the user's operation command.
  • the amplifying circuit 23 enters the noise elimination stage from the standby stage, and the isolation control signal Iso is adjusted from the second voltage value to the third voltage value at this time.
  • voltage value the precharge signal Eq is adjusted from the second level state to the first level state
  • the first reference control signal SanEn/second reference control signal SapEn is adjusted from the first level state to the second level state, so
  • the first reference signal NCS changes from the fourth voltage value to the fifth voltage value
  • the second reference signal PCS changes from the fourth voltage value to the sixth voltage value
  • the noise canceling signal Nc still maintains the second level state, so that the amplification
  • the circuit 23 performs noise cancellation processing.
  • the first reference control signal SanEn/second reference control signal SapEn switches to the first level state
  • the first reference signal NCS and the second reference signal PCS continue to be powered by the pre-charge power supply to recover to the fourth voltage value.
  • the word line on signal WL changes to the second level state, and the word line where the target detection unit is located is adjusted to the open state, so that the amplifying circuit 23 enters the first charge sharing stage.
  • the target detection unit For example, the first storage unit 51
  • the target detection unit performs reading.
  • the voltage of the bit line Bla is stable, that is, a signal to be processed is generated, and the complementary bit line Blb forms a reference signal to be processed.
  • the first charge sharing stage can be regarded as the charge sharing between the target detection unit and the bit line Bla.
  • the preset power signal maintains the second voltage value
  • the isolation control signal Iso maintains the third voltage value, so that the bit line Bla and the read bit line saBla are not connected, and the complementary bit line Blb and the complementary read bit line are not connected. out saBlb does not connect.
  • the pre-charging signal Eq, the noise canceling signal Nc, the first reference control signal SanEn/the second reference control signal SapEn are all in the first level state.
  • the amplifying circuit 23 After finishing the first charge sharing stage, the amplifying circuit 23 enters the second charge sharing stage.
  • the isolation control signal Iso maintains the second voltage value, so that the bit line Bla is connected to the read bit line saBla, and the complementary bit line Blb is connected to the complementary read saBlb, so that the amplifying circuit 23 converts the signal to be processed
  • the bit line Bla/complementary bit line Blb and the read bit line saBla/complementary read bit line saBlb perform read charge sharing.
  • other signals except the isolation control signal Iso maintain the voltage value of the previous stage.
  • the amplifying circuit 23 After finishing the second charge sharing stage, the amplifying circuit 23 enters the first signal amplifying stage, and the first reference control signal SanEn/second reference control signal SapEn is adjusted from the first level state to the second level state, so that the first reference
  • the signal NCS changes from the fourth voltage value to the fifth voltage value
  • the second reference signal PCS changes from the fourth voltage value to the sixth voltage value, so that the amplifying circuit 23 can be processed according to the first reference signal NCS/second reference signal PCS
  • the signal (signal of bit line Bla)/reference signal to be processed (signal of complementary bit line Blb) is amplified, and the isolation control signal Iso still maintains the second voltage value to complete the signal to be processed (signal of bit line Bla)/reference signal to be processed.
  • the amplifying circuit 23 enters the evolution stage, at this time, the preset power signal VisoInt maintains the first voltage value, the isolation control signal Iso maintains the first voltage value, and the ninth switching tube 309 and the tenth switching tube are added 310, so as to complete the signal amplification on the signal to be processed (signal of the bit line Bla)/reference signal to be processed (complementary bit line Blb), the amplified signal is output through the subsequent module to obtain the target amplified signal, and the reading is completed. operate. At this stage, data write-back of the target detection unit is also completed to avoid data failure due to read operations. As shown in FIG. 12 , before the end of the evolution phase, the first reference control signal SanEn/second reference control signal SapEn returns to the first level state.
  • the amplifying circuit 23 After the evolution phase is over, the amplifying circuit 23 enters the pre-charge phase, and the pre-charge signal Eq and the noise elimination signal Nc are adjusted to the second level state. At this time, the first reference signal NCS/second reference signal PCS will return to the fourth level.
  • the voltage values of the bit line Bla/complementary bit line Blb and sense bit line saBla/complementary sense bit line saBlb return to the same voltage value.
  • the amplifying circuit 23 After finishing the pre-charging phase, the amplifying circuit 23 enters the standby phase again to prepare for the next operation.
  • the user's operation instructions can be read instructions, refresh instructions and write instructions.
  • the amplifier circuit During the process of executing the read instructions, refresh instructions and write instructions, the amplifier circuit:
  • the preset power supply signal is the second voltage value in the standby stage, noise elimination stage, first charge sharing stage, second charge sharing stage, and first signal amplification stage of the amplifying circuit. is the first voltage value.
  • the isolation control signal is the second voltage value in the standby stage of the amplifying circuit, the third voltage value in the noise elimination stage and the first charge sharing stage, and the second voltage value in the second charge sharing stage and the first signal amplification stage. Both the evolution phase and the pre-charging phase maintain the first voltage value.
  • the amplifier circuit is in the process of executing the write command, and the evolution stage of the amplifier circuit is the writing stage, which is used to write the externally transmitted data into the memory cell through the voltage change of the bit line Bla.
  • the amplifying circuit By presetting the voltage changes of the power supply signal and the isolated control signal, it is convenient for the amplifying circuit to improve the signal processing speed and suppress the circuit noise in the signal processing process during the process of executing the read command, refresh command and write command.
  • FIG. 13 shows a schematic diagram of signal timing provided by the related art.
  • the preset power signal (not shown) is a fixed voltage value, so the isolation control signal Iso has two voltage values, which respectively belong to the first level state and the second level state.
  • the meanings and changing principles of other signals can be understood with reference to FIG. 12 , and will not be described in detail.
  • the control amplifier circuit 20 provided by the embodiment of the present disclosure has at least the following advantages: On the one hand, in the standby phase, the isolation control signal is a lower voltage value in the second level state (second Voltage value), can avoid the problem of switch tube leakage, reduce device failure, and improve the service life of semiconductor memory; on the other hand, when entering the noise elimination stage from the standby stage, the isolation control signal needs to be adjusted from the second level state It is the first level state, because the isolation control signal in the embodiment of the present disclosure has a lower voltage value in the standby stage, so the level state adjustment is faster, and the speed of signal processing can be improved; on the other hand, when entering the second signal sharing After the stage, because the isolation control signal is a lower voltage value (second voltage value) in the second level state, the voltage value of the signal to be processed will not be higher than (second voltage value-Vt), which can reduce the voltage in the circuit Noise, to avoid affecting other memory cells, improve the amplification margin; on the other
  • the embodiment of the present disclosure provides a control amplifier circuit and its control method. Through this embodiment, the specific implementation of the foregoing embodiments is described in detail. It can be seen from the above that the specific voltage value of the preset power signal can be adjusted by using the power switching signal size, thereby partially improving the problems of slow signal amplification and large circuit noise.
  • FIG. 14 shows a schematic diagram of the composition and structure of a sense amplifier 60 provided by an embodiment of the present disclosure.
  • the sense amplifier 60 may include the control amplifier circuit 20 described in any one of the foregoing embodiments.
  • the sense amplifier 60 can include the control amplifier circuit 20 described in any one of the preceding embodiments, the specific voltage value of the preset power signal can be adjusted by using the power switching signal, thereby partially improving the slow signal amplification speed and large circuit noise. The problem.
  • FIG. 15 shows a schematic structural diagram of a semiconductor memory 70 provided by an embodiment of the present disclosure.
  • the semiconductor memory 70 may include the sense amplifier 60 described in any one of the foregoing embodiments.
  • the semiconductor memory 70 may be a DRAM chip.
  • the semiconductor memory 70 includes the aforementioned sense amplifier 60, the specific voltage value of the preset power signal can be adjusted by using the power switching signal, thereby partially improving the problems of slow signal amplification and large circuit noise.
  • An embodiment of the present disclosure provides a control amplifier circuit, a sense amplifier, and a semiconductor memory.
  • the control amplifier circuit includes: a power output circuit for receiving a power switching signal and selecting from at least two preset voltage values according to the power switching signal One of the preset voltage value outputs is the preset power signal; the isolation control circuit is used to receive the control command signal and the preset power signal, and generates an isolated control signal according to the control command signal; the amplifier circuit is used to receive the isolation control signal and the standby power signal.
  • the signal is processed, and the signal to be processed is amplified based on the isolated control signal to obtain the target amplified signal.
  • the specific voltage value of the preset power signal can be adjusted by using the power switching signal, and then the specific voltage value of the isolation control circuit can be adjusted, the signal amplification process can be optimized, and the problems of slow signal amplification and easy noise generation can be partially improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Amplifiers (AREA)
  • Static Random-Access Memory (AREA)

Abstract

本公开实施例提供了一种控制放大电路、灵敏放大器和半导体存储器，该控制放大电路包括：电源输出电路，用于接收电源切换信号，并根据电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号；隔离控制电路，用于接收控制指令信号和所述预设电源信号，并根据所述控制指令信号生成隔离控制信号；放大电路，用于接收所述隔离控制信号和待处理信号，并基于所述隔离控制信号对所述待处理信号进行放大，得到目标放大信号。

Description

一种控制放大电路、灵敏放大器和半导体存储器
相关申请的交叉引用
本公开基于申请号为202111657770.X、申请日为2021年12月31日、发明名称为“一种控制放大电路、灵敏放大器和半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体存储器技术领域，尤其涉及一种控制放大电路、灵敏放大器和半导体存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。在数据读取的过程中，每个存储单元的读出数据信号依次经由本地数据线、全局数据线和数据总线进行读出；反之，在数据写入的过程中，则写入数据信号依次经由数据总线、全局数据线和本地数据线向存储单元写入。
目前，在DRAM中存在灵敏放大器，用于进行信号放大处理，但是相关技术中灵敏放大器的放大速度慢，且容易产生噪声。
发明内容
本公开提供了一种控制放大电路、灵敏放大器和半导体存储器，能够改善信号放大速度慢且容易产生噪声的问题。
第一方面，本公开实施例提供了一种控制放大电路，包括：
电源输出电路，用于接收电源切换信号，并根据电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号；
隔离控制电路，用于接收控制指令信号和预设电源信号，并根据控制指令信号生成隔离控制信号；
放大电路，用于接收隔离控制信号和待处理信号，并基于隔离控制信号对待处理信号进行放大，得到目标放大信号。
在一些实施例中，电源切换信号包括第一电源切换信号和/或第二电源切换信号，控制放大电路还包括电源切换电路；电源切换电路，用于输出第一电源切换信号和/或第二电源切换信号；电源输出电路，具体用于接收 第一电源切换信号和/或第二电源切换信号，并根据第一电源切换信号和/或第二电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号。
在一些实施例中，预设电压值包括第一电压值和第二电压值；电源输出电路，还用于在第一电源切换信号处于第一电平状态，且第二电源切换信号处于第二电平状态时，选择第一电压值输出为预设电源信号；或者在第一电源切换信号处于第二电平状态，且第二电源切换信号处于第一电平状态时，选择第二电压值输出为预设电源信号；其中，第一电压值和第二电压值均属于第二电平状态，且第一电压值大于第二电压值。
在一些实施例中，信号控制电路，用于输出控制指令信号；隔离控制电路，还用于在控制指令信号处于第一状态时，生成具有第三电压值的隔离控制信号；或者在控制指令信号处于第二状态时，生成与预设电源信号电压值相同的隔离控制信号；其中，第一状态为第一电平状态或第二电平状态，第二状态为第一电平状态或第二电平状态，第一状态与第二状态所处的电平状态不同；第三电压值属于第一电平状态，且第三电压值小于第二电压值。
在一些实施例中，电源输出电路包括第一预设电源、第二预设电源、第一开关管和第二开关管；其中，第一开关管的第一端与第一电源切换信号连接，第二开关管的第一端与第二电源切换信号连接；第一开关管的第二端与第一预设电源连接，第二开关管的第二端与第二预设电源连接；第一开关管的第三端，与第二开关管的第三端连接，用于输出预设电源信号；其中，第一预设电源用于输出第一电压值，第二预设电源用于输出第二电压值。
在一些实施例中，隔离控制电路包括第一反向器、第三开关管和第四开关管；其中，第一反向器的输入端与控制指令信号连接，第一反向器的输出端分别与第三开关管的第一端和第四开关管的第一端连接；第三开关管的第二端与预设电源信号连接，第四开关管的第三端与地信号连接；第三开关管的第三端，与第四开关管的第二端连接，用于输出隔离控制信号。
在一些实施例中，放大电路包括交叉耦合电路和控制电路；其中，放大电路，还用于通过交叉耦合电路接收待处理信号，通过控制电路接收隔离控制信号，并根据隔离控制信号对待处理信号进行放大处理，得到目标放大信号。
在一些实施例中，交叉耦合电路包括第五开关管、第六开关管、第七开关管和第八开关管，控制电路包括第九开关管和第十开关管；
第五开关管的第一端，与第九开关管的第三端连接，用于接收待处理信号，第五开关管的第二端、第七开关管的第三端、第八开关管的第一端与第十开关管的第二端连接；
第六开关管的第一端，与第十开关管的第三端连接，用于接收参考待 处理信号，第六开关管的第二端、第八开关管的第三端、第七开关管的第一端与第九开关管的第二端连接；
第五开关管的第三端、第六开关管的第三端与第一参考信号连接，第七开关管的第二端、第八开关管的第二端与第二参考信号连接，第九开关管的第一端、第十开关管的第一端与隔离控制信号连接。
在一些实施例中，放大电路还包括第一参考电路和第二参考电路；其中，第一参考电路，用于接收第一参考控制信号，并根据第一参考控制信号，输出第一参考信号；第二参考电路，用于接收第二参考控制信号，并根据第二参考控制信号，输出第二参考信号；其中，第一参考信号的电压值为第四电压值或者第五电压值，第二参考信号的电压值为第四电压值或者第六电压值，第四电压值为第五电压值和第六电压值的中间值。
在一些实施例中，第一参考电路包括n个第十一开关管，n为正整数；第十一开关管的第一端与第一参考控制信号连接，第十一开关管的第三端与地信号连接；第十一开关管的第二端，与第一参考电路的输出端连接，用于输出第一参考信号。
在一些实施例中，第二参考电路包括m个第十二开关管，m为正整数；第十二开关管的第一端与第二参考控制信号连接，第十二开关管的第二端与第三预设电源连接；第十二开关管的第二端，与第二参考电路的输出端连接，用于输出第二参考信号。
在一些实施例中，放大电路还包括第一信号建立电路和第二信号建立电路；其中，第一信号建立电路，用于接收第一控制输入信号，输出第一参考控制信号；第二信号建立电路，用于接收第二控制输入信号，输出第二参考控制信号。
在一些实施例中，第一信号建立电路包括n个第二反向器，第二信号建立电路包括n个第三反向器；其中，第二反向器的输入端与第一控制输入信号连接，第二反向器的输出端用于输出第一参考控制信号；其中，在n个第二反向器中，每个第十一开关管的第一参考控制信号通过一个第二反向器输出；第三反向器的输入端与第一控制输入信号连接，第三反向器的输出端用于输出第二参考控制信号；其中，在m个第三反向器中，每个第十二开关管的第二参考控制信号通过一个第三反向器输出。
在一些实施例中，放大电路还包括预充电路，且预充电路包括第十三开关管和第十四开关管；其中，第十三开关管的第一端、第十四开关管的第一端与预充信号连接；第十三开关管的第二端与第四预设电源连接，第十三开关管的第三端与第六开关管的第二端连接；
第十四开关管的第三端与第五开关管的第二端连接，第十四开关管的第二端与第六开关管的第二端连接。
在一些实施例中，放大电路还包括噪声消除电路，噪声消除电路包括第十五开关管和第十六开关管；其中，第十五开关管的第一端、第十六开 关管的第一端与噪声消除信号连接；第十五开关管的第二端与第五开关管的第二端连接，第十五开关管的第三端与第五开关管的第一端连接；第十六开关管的第二端与第六开关管的第二端连接，第十六开关管的第三端与第六开关管的第一端连接。
在一些实施例中，第一开关管、第二开关管、第三开关管、第七开关管和第八开关管为P型沟道场效应管；第四开关管、第五开关管、第六开关管、第九开关管、第十开关管、第十一开关管、第十二开关管、第十三开关管、第十四开关管、第十五开关管和第十六开关管为N型沟道场效应管。
第二方面，本公开实施例提供了一种放大电路的控制方法，应用于与目标检测单元连接的放大电路，控制方法包括：
在放大电路处于第一放大阶段时，电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，隔离控制电路根据第二状态的控制指令信号生成具有第二电压值的隔离控制信号，放大电路接收隔离控制信号和待处理信号，对待处理信号进行初步放大处理；
在放大电路处于演进阶段时，电源输出电路根据电源切换信号选择第一电压值输出为预设电源信号，隔离控制电路根据第二状态的控制指令信号生成具有第一电压值的隔离控制信号，放大电路接收根据隔离控制信号对待处理信号进行二次放大处理。
在一些实施例中，放大电路还处于待机阶段、第一电荷分享阶段、第二电荷分享阶段和预充阶段；该方法还包括：
在放大电路处于待机阶段、第二电荷分享阶段或预充阶段时，电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，隔离控制电路根据第二状态的控制指令信号生成具有第二电压值的隔离控制信号；在放大电路处于第一电荷分享阶段时，电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，隔离控制电路根据第一状态的控制指令信号生成具有第三电压值的隔离控制信号，放大电路接收待处理信号执行第一电荷分享。
第三方面，本公开实施例提供了一种灵敏放大器，包括如第一方面中任一项所述的控制放大电路。
第四方面，本公开实施例提供了一种半导体存储器，包括如第三方面中任一项所述的灵敏放大器。
本公开实施例提供了一种控制放大电路、灵敏放大器和半导体存储器，该控制放大电路包括：电源输出电路，用于接收电源切换信号，并根据电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号；隔离控制电路，用于接收控制指令信号和预设电源信号，并根据控制指令信号生成隔离控制信号；放大电路，用于接收隔离控制信号和待处理信号，并基于隔离控制信号对待处理信号进行放大，得到目标放大信 号。这样，利用电源切换信号能够调整预设电源信号的具体电压值大小，进而调整隔离控制电路的具体电压值大小，优化信号放大过程，部分改善信号放大速度慢、容易产生噪声的问题。
附图说明
图1为一种灵敏放大器的应用场景示意图；
图2为本公开实施例提供的一种控制放大电路的组成结构示意图；
图3为本公开实施例提供的另一种控制放大电路的组成结构示意图；
图4为本公开实施例提供的一种控制放大电路的局部详细结构示意图；
图5为本公开实施例提供的另一种控制放大电路的局部详细结构示意图；
图6为本公开实施例提供的一种反向器的结构示意图；
图7为本公开实施例提供的又一种控制放大电路的局部详细结构示意图；
图8为本公开实施例提供的一种控制放大电路的应用场景示意图；
图9为本公开实施例提供的一种放大电路的控制方法的流程示意图；
图10为本公开实施例提供的另一种放大电路的控制方法的流程示意图；
图11为本公开实施例提供的另一种控制放大电路的应用场景示意图；
图12为本公开实施例提供的一种放大电路的信号时序示意图；
图13为相关技术提供的一种信号时序示意图；
图14为本公开实施例提供的一种灵敏放大器的组成结构示意图；
图15为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的 本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下为本公开实施例中涉及到的专业名词解释以及部分名词的对应关系：
P型场效应管：空穴型场效应管；
N型场效应管：电子型场效应管。
可以理解，在DRAM的工作过程中，需要利用灵敏放大器实现多种操作过程中的信号放大。参见图1，其示出了一种灵敏放大器的应用场景示意图。如图1所示，该应用场景包括第一信号线11、第二信号线12、灵敏放大器113。其中，
第一信号线11上具有第一开关111和第一电容112，用于传入待处理信号Vin+；第二信号线12上具有第二开关121和第二电容122，用于传入参考待处理信号Vin-，灵敏放大器113用于对待处理信号Vin+及参考待处理信号Vin-进行放大，待处理信号Vin+与参考待处理信号Vin-的具有ΔVin的电压差。在这里，第一开关111和第一电容112可视为一个存储单元，第二开关121和第二电容122可视为另一个存储单元。
具体地，灵敏放大器包括第一开关管131、第二开关管132、第三开关管133和第四开关管134。第一开关管131的第一端、第二开关管132的第一端、第三开关管133的第三端、第四开关管134的第二端均与参考待处理信号Vin-连接，第一开关管131的第三端、第二开关管132的第二端、第三开关管133的第一端、第四开关管134的第一端均与所述待处理信号Vin+连接。该应用场景中还存在第五开关管135和第六开关管136，第五开关管135的第一端与第一控制信号SAP连接，第五开关管135的第二端与电源信号VBLH连接，第五开关管135的第三端、第一开关管131的第二端和第三开关管133的第二端连接，形成第一参考信号端。第六开关管136的第一端与第二控制信号SAN连接，第六开关管136的第二端与地信号GND连接，第六开关管136的第二端、第二开关管132的第三端和第四开关管134的第三端连接，形成第二参考信号端。其中，第一开关管131、第三开关管132、第五开关管135为P型场效应管，P型场效应管的第一端为栅极引脚，P型场效应管的第二端为源极引脚，P型场效应管的第三端为漏极引脚；第二开关管132、第四开关管134和第六开关管136为N型场效应管，N型场效应管的第一端为栅极引脚，N型场效应管的第二端为漏极引脚，N型场效应管的第三端为源极引脚。
另外，在第一信号线11和第二信号线12之间还可以存在预充电路，且第三开关管133的第二端和第四开关管的第三端之间也可以存在预充电路，用于对第一参考信号端和第二参考信号端进行预充处理。
目前，灵敏放大器的信号放大速度较慢、电路容易产生噪声，而且功耗较高，影响了半导体存储器的性能。
本公开实施例提供了一种控制放大电路，包括：电源输出电路，用于 接收电源切换信号，并根据电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号；隔离控制电路，用于接收控制指令信号和预设电源信号，并根据控制指令信号生成隔离控制信号；放大电路，用于接收隔离控制信号和待处理信号，并基于隔离控制信号对待处理信号进行放大，得到目标放大信号。这样，利用电源切换信号能够调整预设电源信号的具体电压值大小，进而调整隔离控制信号的具体电压值大小，优化信号放大过程，改善信号放大速度慢、容易产生噪声的问题。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图2，其示出了本公开实施例提供的一种控制放大电路20的组成结构示意图。如图2所示，该控制放大电路20可以包括：
电源输出电路21，用于接收电源切换信号，并根据电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号；
隔离控制电路22，用于接收控制指令信号和预设电源信号，并根据控制指令信号生成隔离控制信号；
放大电路23，用于接收隔离控制信号和待处理信号，并基于隔离控制信号对待处理信号进行放大，得到目标放大信号。
需要说明的是，本公开实施例提供的控制放大电路20可以应用在多种信号放大的场景中，例如以DRAM中的灵敏放大器。
本公开实施例提供的控制放大电路20从外部接收电源切换信号、控制指令信号和待处理信号，基于电源切换信号和控制指令信号完成待处理信号放大过程，最终得到目标放大信号。在这里，控制指令信号和电源切换信号均是需要根据放大电路所处的具体工作阶段进行确定。
具体地，对于控制放大电路20来说，通过电源输出电路21，根据电源切换信号对至少两个预设电压值进行选择输出，得到预设电源信号；通过隔离控制电路22，根据控制指令信号和预设电源信号，输出隔离控制信号；通过放大电路23，根据隔离控制信号对待处理信号进行放大，输出目标放大信号。
这样，利用电源切换信号能够调整预设电源信号的具体电压值大小，进而调整隔离控制电路22输出隔离控制信号的具体电压值大小，优化信号放大过程，改善信号放大速度慢、容易产生噪声的问题。
在一些实施例中，电源切换信号可以包括第一电源切换信号和/或第二电源切换信号。在图2的基础上，如图3所示，控制放大电路20还可以包括电源切换电路24；
电源切换电路24，用于输出第一电源切换信号和/或第二电源切换信号；
电源输出电路21，具体用于接收第一电源切换信号和/或第二电源切换信号，并根据第一电源切换信号和/或第二电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号。
需要说明的是，电源切换信号可以仅包括一个信号，例如第一电源切换信号或第二电源切换信号；或者，电源切换信号可以包括电平状态相反的一对信号，例如同时包括第一电源切换信号和第二电源切换信号。
在一种具体的实施例中，预设电压值设置有两个，为第一电压值和第二电压值；电源切换信号同时包括第一电源切换信号和第二电源切换信号。此时，电源输出电路21，还用于在第一电源切换信号处于第一电平状态，且第二电源切换信号处于第二电平状态时，生成具有第一电压值的预设电源信号；或者
在第一电源切换信号处于第二电平状态，且第二电源切换信号处于第一电平状态时，生成具有第二电压值的预设电源信号。
在这里，第一电压值和第二电压值均属于第二电平状态，且第一电压值大于第二电压值。
需要说明的是，对于P型场效应管来说，第一电平状态能够使其处于导通状态，第二电平状态能够使其处于关断状态；对于N型场效应管来说，第一电平状态能够使其处于关断状态，第二电平状态能够使其处于导通状态。在这里，由于不同开关管的规格不一样，不同开关管的第一电平状态可能是不相同的电压范围。
在另一种具体的实施例中，电源切换信号仅包括第一电源切换信号。此时，电源输出电路21，还用于在第一电源切换信号处于第一电平状态，生成具有第一电压值的预设电源信号；或者在第一电源切换信号处于第二电平状态时，生成具有第二电压值的预设电源信号。
这样，电源输出电路21可以输出两种不同电压值的预设电源信号，而非一种固定电压值的电源信号。这样，在放大电路23的不同工作阶段，可以通过调整预设电源信号的电压值来提供更多的控制手段，从而部分改善信号放大速度慢、电路噪声大的问题。
在一些实施例中，如图3所示，控制放大电路20还可以包括信号控制电路25；
信号控制电路25，用于输出控制指令信号；
隔离控制电路22，还用于在控制指令信号处于第一状态时，生成具有第三电压值的隔离控制信号；或者
在控制指令信号处于第二状态时，生成与预设电源信号电压值相同的隔离控制信号。
在这里，第一状态为第一电平状态，第二状态为第二电平状态；或者，第一状态为第二电平状态，第二状态为第一电平状态。
需要说明的是，对于隔离控制电路22来说，若控制指令信号处于第一电平状态，且预设电源信号具有第一电压值，则隔离控制信号具有第一电压值；若控制指令信号处于第一电平状态，且预设电源信号具有第二电压值，则隔离控制信号具有第二电压值；若控制指令信号处于第一状态，则 隔离控制信号具有第三电压值。
或者，若控制指令信号处于第二电平状态，且预设电源信号具有第一电压值的情况下，隔离控制信号具有第一电压值；在控制指令信号处于第二电平状态，且预设电源信号具有第二电压值的情况下，隔离控制信号具有第二电压值；控制指令信号处于第一电平状态的情况下，隔离控制信号具有第三电压值。
在这里，第三电压值属于第一电平状态，第一电压值和第二电压值均属于第二电平状态，且第三电压值低于第二电压值，第二电压值低于第一电压值。
示例性地，在一种习惯性的表示方法中，第一电平状态可以用逻辑“0”表示，第二电平状态可以用逻辑“1”进行表示，第三电压值可以表示为逻辑“0”，第一电压值和第二电压值均可以表示为逻辑“1”，以上仅为示意性说明，并不具有实际限定内容。
这样，隔离控制信号存在三种不同的电压值，可以提供更多的控制手段，以便优化信号放大过程，部分改善信号放大速度慢、电路噪声大的问题。
以下以电源切换信号同时包括第一电源切换信号和第二电源切换信号为例，提供一种电源输出电路21的可行结构。
在图3的基础上，如图4所示，电源输出电路21包括第一预设电源VisoH、第二预设电源VisoL、第一开关管301和第二开关管302；其中，
第一开关管301的第一端与第一电源切换信号连接，第二开关管302的第一端与第二电源切换信号连接；
第一开关管301的第二端与第一预设电源VisoH连接，第二开关管302的第二端与第二预设电源VisoL连接；
第一开关管301的第三端，与第二开关管302的第三端连接，用于输出预设电源信号VisoInt。
在这里，第一预设电源VisoH用于输出第一电压值，第二预设电源VisoL用于输出第二电压值。
需要说明的是，如图4所示，第一开关管301、第二开关管302均为P型场效应管。在后续说明中，P型场效应管的第一端为栅极引脚，P型场效应管的第二端为源级引脚，P型场效应管的第三端为漏极引脚。
需要说明的是，在第一电源切换信号处于第一电平状态且第二电源切换信号处于第二电平状态时，第一开关管301导通且第二开关管302关断，所以预设电源信号VisoInt与第一预设电源VisoH的电压值相同，即预设电源信号VisoInt为第一电压值；在第一电源切换信号处于第二电平状态且第二电源切换信号处于第一电平状态时，第一开关管301关断且第二开关管302导通，所以预设电源信号VisoInt与第二预设电源VisoL的电压值相同，即预设电源信号VisoInt为第二电压值。
这样，本公开实施例中，在隔离控制信号Iso处于第二电平状态的前提下，还可以控制隔离控制信号Iso为较高电压(第一电压值)或者较低电压(第二电压值)，以适应不同放大阶段的电压需求和信号传输速度，进而优化信号放大过程，提高信号放大速度，减弱电路噪声。
以下针对第一状态为第一电平状态，第二状态为第二电平状态为例，给出一种隔离控制电路22的可行结构。在一些实施例中，如图4所示，隔离控制电路22电路包括第一反向器321、第三开关管303和第四开关管304；其中，
第一反向器321的输入端与信号控制电路25的输出端连接，接收信号控制电路25输出的控制指令信号，第一反向器321的输出端分别与第三开关管303的第一端和第四开关管304的第一端连接；
第三开关管303的第二端与预设电源信号VisoInt连接，第四开关管304的第三端与地信号连接；
第三开关管303的第三端，与第四开关管304的第二端连接，用于输出隔离控制信号Iso。
需要说明的是，第三开关管303为P型场效应管，第四开关管304为N型场效应管。在后续说明中，N型场效应管的第一端为栅极引脚，N型场效应管的第二端为漏级引脚，N型场效应管的第三端为源级引脚。
这样，在控制指令信号处于第一电平状态的情况下，第三开关管303处于关断状态，第四开关管304处于导通状态，从而隔离控制信号Iso具有第三电压值，相当于接地电位；在控制指令信号处于第二电平状态的情况下，第三开关管303处于导通状态，第四开关管304处于关断状态，从而隔离控制信号Iso的电压值与预设电源信号的电压值VisoInt相同，即第一电压值或者第二电压值。
另外，针对第一状态为第二电平状态，第二状态为第一电平状态的情况，隔离控制电路22电路也可仅包括第三开关管303和第四开关管304，信号控制电路25的输出端与第三开关管303的第一端和第四开关管304的第一端连接，其他连接不变；
此时，控制指令信号处于第二电平状态的情况下，第三开关管303处于关断状态，第四开关管304处于导通状态，从而隔离控制信号Iso具有第三电压值，相当于接地电位；在控制指令信号处于第一电平状态的情况下，第三开关管303处于导通状态，第四开关管304处于关断状态，从而隔离控制信号Iso的电压值与预设电源信号的电压值VisoInt相同，即第一电压值或者第二电压值。
在一些实施例中，如图3所示，放大电路23包括交叉耦合电路231和控制电路232；其中，
放大电路23，还用于通过交叉耦合电路231接收待处理信号，通过控制电路232接收隔离控制信号，并根据隔离控制信号对待处理信号进行放 大处理，得到目标放大信号。
需要说明的是，以DRAM为例，交叉耦合电路231通过位线连接目标检测单元，通过互补位线连接互补存储单元。在初始状态，位线和互补位线上的电位是相同的。在位线上的存储单元(即目标检测单元)开启后，该存储单元与位线进行电荷分享，从而位线上的电位升高或者降低；互补位线上的存储单元始终是关闭的，因此互补位线上的电位不变。由于位线上的电位升高和降低，位线和互补位线之间的压差会发生变化，从而交叉耦合电路231中的部分器件接通，执行信号放大处理。此时，交叉耦合电路231从位线上接收的信号可以视为待处理信号，交叉耦合电路231从互补位线上接收的信号可以视为参考待处理信号。
还需要说明的是，交叉耦合电路231还包括连接一组开关管的读出位线和连接另一组开关管的互补读出位线。控制电路22控制隔离控制信号处于第一电平状态时，位线与读出位线不接通，且互补位线与互补读出位线不接通；在隔离控制信号处于第一电平状态时，通过控制电路22能够控制位线与读出位线接通，且互补位线与互补读出位线接通。后续，交叉耦合电路231将借助读出位线/互补读出位线完成信号放大过程，具体说明参见后续内容。
在一种具体的实施中，在图3的基础上，如图5所示，交叉耦合电路231可以包括第五开关管305、第六开关管306、第七开关管307和第八开关管308，控制电路232包括第九开关管309和第十开关管310；其中，
第五开关管305的第一端，与第九开关管309的第三端连接，用于接收待处理信号，第五开关管305的第二端、第七开关管307的第三端、第八开关管308的第一端与第十开关管310的第二端连接；第五开关管305的第二端、第七开关管307的第三端、第八开关管308的第一端及第十开关管310的第二端均连接在互补读出位线上。
第六开关管306的第一端，与第十开关管310的第三端连接，用于接收参考待处理信号，第六开关管306的第二端、第八开关管308的第三端、第七开关管307的第一端与第九开关管309的第二端连接；第六开关管306的第二端、第八开关管308的第三端、第七开关管307的第一端及第九开关管309的第二端连接均连接在读出位线上。
第五开关管305的第三端、第六开关管306的第三端与第一参考信号NCS连接，第七开关管307的第二端、第八开关管308的第二端与第二参考信号PCS连接，第九开关管309的第一端、第十开关管310的第一端与隔离控制信号Iso连接。
需要说明的是，第五开关管305、第六开关管306、第九开关管309和第十开关管310为N型场效应管，第七开关管307和第八开关管308为P型场效应管。
这样，在隔离控制信号Iso处于第二电平状态(具有第一电压值或者第 二电压值)的情况下，控制电路232中的第九开关管309和第十开关管310是导通的，交叉耦合电路231接收待处理信号；在隔离控制信号Iso处于第一电平状态(具有第三电压值)的情况下，控制电路232中的第九开关管309和第十开关管310是关断的，交叉耦合电路231不与外部信号连接。
需要说明的是，在信号放大的过程中，第一参考信号NCS可以用于为交叉耦合电路231提供低参考电位，第二参考信号PCS可以用于为交叉耦合电路231提供高参考电位。基于此，以下对交叉耦合电路231的放大原理进行简单说明：
假设目标检测单元存储数据为“0”，待处理信号的电压会低于参考待处理信号的电压，交叉耦合电路231的放大阶段包括：第一放大阶段和演进阶段。
在第一放大阶段，隔离控制信号Iso处于第二电平状态的第二电压值，第九开关管309和第十开关管310导通，位线与读出位线连接，互补位线与互补读出位线连接，此时，参考待处理信号传输至读出位线使第六开关管306处于导通状态，基于低参考电位对读出位线电位进行拉低处理，进而第七开关管307处于导通状态，基于高参考电位对互补读出位线进行电位进行拉高处理；以及
在演进阶段，隔离控制信号Iso处于第二电平状态的第一电压值，第九开关管309和第十开关管310导通程度增大，通过第九开关管309的传输，将拉低后的读出位线电位传输至位线，将位线上的待处理参考信号迅速拉低，通过第十开关管310的传输，将互补位线上的参考待处理参考信号迅速拉高，以使得待处理信号和参考待处理信号之间的压差增大，得到目标放大信号。
假设目标检测单元存储数据为“1”，待处理信号的电压高于参考待处理信号的电压，在第一放大阶段，第五开关管305处于导通状态，基于低参考电位对互补读出位线进行电位拉低处理，第八开关管308处于导通状态，基于高参考电位对读出位线进行电位拉高处理；以及
在演进阶段，隔离控制信号Iso处于第二电平状态的第一电压值，第九开关管309和第十开关管310导通程度增大，将拉高后的读出位线电位传输至位线，将位线上的待处理参考信号迅速拉高，通过第十开关管310的传输，将互补位线上的参考待处理参考信号迅速拉低，以使得待处理信号和参考待处理信号之间的压差增大，以便后续得到目标放大信号。
还需要说明的是，在信号放大的过程中，放大电路23在开始放大的时候，由于隔离控制信号Iso处于第二电压值，第九开关管309和第十开关管310的栅极电压较低，位线或互补位线的电压升高缓慢，不会产生较大噪声，从而不会影响相邻存储单元的存储数据，因此能够提高放大电路23的感测幅度，但放大电路23内部节点却能够迅速达到低参考电位或高参考电位。在演进阶段隔离控制信号Iso处于第一电压值，九开关管309和第十开关管 310的栅极电压变高，流经位线或互补位线的电压变大，由于放大电路23内部节点电压已经变化，会快速将位线或互补位线拉高或拉低，提高信号放大速度，抑制位线或互补位线电位升高时的噪声。
在一些时候例中，如图3所示，放大电路23还包括第一参考电路233和第二参考电路234；其中，
第一参考电路233，用于接收第一参考控制信号，并根据第一参考控制信号，输出第一参考信号；
第二参考电路234，用于接收第二参考控制信号，并根据第二参考控制信号，输出第二参考信号；
其中，第一参考信号的电压值为第四电压值或者第五电压值，第二参考信号的电压值为第四电压值或者第六电压值，第四电压值为第五电压值和第六电压值的中间值。
需要说明的是，第一参考信号可以为交叉耦合电路231提供低参考电位，第二参考信号可以为交叉耦合电路提供高参考电位，以便于交叉耦合电路231可以根据高参考电位(即第五电压值)和低参考电位(即第六电压值)对待处理信号和参考待处理信号进行放大处理。
示例性地，如图5所示，第一参考电路233包括n个第十一开关管(例如图5中的第十一开关管311-1、第十一开关管311-2、第十一开关管311-3)，n为正整数；
第十一开关管的第一端与第一参考控制信号(例如图5中的pdn1、pdn2、pdn3)连接，第十一开关管311的第三端与地信号连接；
第十一开关管的第二端，与第一参考电路233的输出端连接，用于输出第一参考信号NCS。
需要说明的是，图5中示出了3个第十一开关管，但实际应用场景中第十一开关管可以更多或者更少。另外，第一参考控制信号的数量也为多个，且一个第一参考控制信号对应一个第十一开关管。多个第一参考控制信号的电平状态可以是不同的，即pdn1、pdn2和pdn3各自的电平状态是单独变化的。也就是说，一个第十一开关管被一个第一参考控制信号单独进行控制。
如图5所示，所有的第十一开关管可以为N型场效应管。以第十一开关管311-1为例，在第一参考控制信号pdn1为第一电平状态的情况下，第十一开关管311-1是关断的；在第一参考控制信号pdn1为第二电平状态的情况下，第十一开关管311-1是导通的。
这样，通过第一参考电路233，可以利用处于导通状态的第十一开关管调节第一参考信号NCS的电位，从而为交叉耦合电路231提供低参考电位。除此之外，不同的第十一开关管各自连接一个单独的地电位，这些地电位的具体电压值可以不相同，以提供不同的第一参考信号NCS电压降低速度。另外，通过控制处于导通状态的第十一开关管数量，也可以控制第一参考 信号NCS电压降低速度。这样，通过控制电压调整速度不同，可以减少信号放大过程中待处理信号在电压快速降低时产生的噪声。
在一些实施例中，如图5所示，第二参考电路234包括m个第十二开关管(例如图5中的第十二开关管312-1、第十二开关管312-2、第十二开关管312-3)，m为正整数；第十二开关管各自的第一端与第二参考控制信号(例如图5中的pup1、pup2、pup3)连接，第十二开关管各自的第二端与第三预设电源(例如图5中的Vblh1、Vblh2、Vblh3)连接；
第十二开关管第二端，与第二参考电路234的输出端连接，用于输出第二参考信号PCS。
需要说明的是，图5中示出了3个第十二开关管，但实际应用场景中第十二开关管312可以更多或者更少。另外，第二参考控制信号的数量也为多个，且一个第二参考控制信号对应一个第十二开关管。多个第二参考控制信号的电平状态可以是不同的，即pup1、pup2和pup3各自的电平状态是单独变化的。也就是说，一个第十二开关管被一个第二参考控制信号单独进行控制。
如图5所示，第十二开关管可以为N型场效应管。因此，以第十二开关管312-1为例，在第二参考控制信号pup1为第一电平状态的情况下，第十二开关管312-1是关断的；在第一参考控制信号pup1为第二电平状态的情况下，第十一开关管312-1是导通的。
这样，处于导通状态的第十二开关管将第二参考信号PCS充电至第二电平状态(高参考电位)，以实现为交叉耦合电路231提供高参考电位。不同的第十二开关管各自连接一个单独的第三预设电源，这些第三预设电源的电压值可以不相同，以提供第二参考信号PCS不同的电压升高速度。另外，通过控制处于导通状态的第十二开关管数量，也可以控制电压升高速度。这样，通过控制电压升高速度不同，可以减少信号放大过程中第二参考信号在电压快速升高时产生的噪声。
在一些实施例中，如图3所示，放大电路23还包括第一信号建立电路235和第二信号建立电路236；其中，
第一信号建立电路235，用于接收第一控制输入信号，输出第一参考控制信号；
第二信号建立电路236，用于接收第二控制输入信号，输出第二参考控制信号。
在一种具体的实施例中，如图5所示，第一信号建立电路235包括n个第二反向器(例如图5中的第二反向器322-1、第二反向器322-2、第二反向器322-3)，第二信号建立电路236包括m个第三反向器(例如图5中的第三反向器323-1、第三反向器323-2、第三反向器323-3)；其中，
第二反向器的输入端与第一控制输入信号(例如图5中的Vpd1、Vpd2、Vpd3)连接，第二反向器的输出端用于输出第一参考控制信号(例如图5 中的pdn1、pdn2、pdn3)；其中，在n个第二反向器中，每个第十一开关管的第一参考控制信号通过一个第二反向器输出；
第三反向器的输入端与第二控制输入信号(例如图5中的Vpu1、Vpu2、Vpu3)连接，第三反向器的输出端用于输出第二参考控制信号(例如图5中的pup1、pup2、pup3)；其中，每个第十二开关管的第二参考控制信号通过一个第三反向器输出。
需要说明的是，如图5所示，第二反向器的输入端还与电源信号Vncsg连接。在第一控制输入信号处于第一电平状态的情况下，第二反向器根据电源信号Vncsg输出处于第二电平状态的第一参考控制信号，在第一控制输入信号处于第二电平状态的情况下，第二反向器输出处于第一电平状态的第一参考控制信号。
类似地，第三反向器的输入端还与电源信号Vpcsg连接。在第二控制输入信号处于第一电平状态的情况下，第三反向器根据电源信号输出处于第二电平状态的第二参考控制信号，在第二控制输入信号处于第二电平状态的情况下，第三反向器输出处于第一电平状态的第二参考控制信号。
第二反向器和第三反向器可采用相同的电路结构，例如通过一个N型场效应管和一个P型场效应管实现。参见图6，其示出了本公开实施例提供的反向器的结构示意图。第二反向器具体结构如图6(a)所示，第三反向器的具体结构如图6(b)所示。
还需要说明的是，第一控制输入信号的数量也是多个，一个第二反向器用于接收一个第一控制输入信号，且这些第一控制输入信号的电平状态可以是不同的。以图5中的第一控制输入信号Vpd1为例，在第一控制输入信号Vpd1处于第一电平状态的情况下，第二反向器322-1输出处于第二电平状态的第一参考控制信号pdn1，此时第十一开关管311-1处于导通状态；反之，在第一控制输入信号Vpd1处于第二电平状态的情况下，第二反向器322-1输出处于第一电平状态的第一参考控制信号pdn1，此时第十一开关管311-1处于关断状态。
类似地，第二控制输入信号的数量也是多个，一个第三反向器用于接收一个第二控制输入信号，且这些第二控制输入信号的电平状态可以是不同的。以图5中的第二控制输入信号Vpd1为例，在第二控制输入信号Vpu1处于第一电平状态的情况下，第三反向器323-1输出处于第二电平状态的第二参考控制信号pup1，此时第十二开关管312-1处于导通状态；反之，在第二控制输入信号Vpu1处于第二电平状态的情况下，第三反向器323-1输出处于第一电平状态的第二参考控制信号pup1，此时第十二开关管312-1处于关断状态。
这样，通过第一信号建立电路、第二信号建立电路、第一参考电路、第二参考电路，能够为交叉耦合电路提供不同电压调整速度的第一参考信号和第二参考信号，实现待处理信号的放大过程。
在一些实施例中，如图5所示，放大电路23还包括预充电路，且预充电路包括第十三开关管313和第十四开关管314；其中，
第十三开关管313的第一端、第十四开关管314的第一端与预充信号Eq连接；
第十三开关管313的第二端与第四预设电源连接，第十三开关管313的第三端与第六开关管306的第二端连接；
第十四开关管314的第三端与第五开关管305的第二端连接，第十四开关管314的第二端与第六开关管306的第二端连接。
在这里，第十三开关管313和第十四开关管314均为N型场效应管。
这样，预充电路响应于预充信号Eq，为放大电路23进行预充处理，在预充处理结束后使得放大电路23的各电路节点处于相同的电压值。
在一些实施例中，在图5的基础上，如图7所示，放大电路23还包括噪声消除电路，噪声消除电路包括第十五开关管315和第十六开关管316；其中，
第十五开关管315的第一端、第十六开关管316的第一端与噪声消除信号Nc连接；
第十五开关管315的第二端与第五开关管305的第二端连接，第十五开关管315的第三端与第五开关管305的第一端连接；
第十六开关管316的第二端与第六开关管306的第二端连接，第十六开关管316的第三端与第六开关管306的第一端连接。
在这里，第十五开关管315和第十六开关管316均为n型场效应管。因此，在噪声消除信号处于第二电平状态的情况下，第十五开关管315和第十六开关管316处于接通状态，以使得第五开关管305的第一端和第三端短接，且第六开关管306的第一端和第三端短接，从而对第五开关管305和第六开关管306进行偏移消除操作。这样，可以进一步消除信号放大过程中的开关管的阈值差异，提高放大过程中对待处理信号感测的准确性。
特别地，图4、图5、图7仅为控制放大电路的一种可选电路结构，其中，第一开关管301、第二开关管302、第三开关管303、第七开关管307和第八开关管308为P型沟道场效应管；第四开关管304、第五开关管305、第六开关管306、第九开关管309、第十开关管310、第十一开关管311、第十二开关管312、第十三开关管313、第十四开关管314、第十五开关管315和第十六开关管316为N型沟道场效应管。当然，以上开关管的选型并不构成本公开实施例的限制，在实际应用场景中，可以通过多种类型的电路器件实现前述的电路控制逻辑，可以依据实际应用场景进行具体选择。
综上可知，在本公开实施例中，通过增加电源切换电路，从而提供具有两个电压值(第一电压值或第二电压值)的预设电源信号，进而隔离控制电路可以根据预设电源信号输出具有三个不同电压值(第一电压值、第二电压值或者第三电压值)的隔离控制信号。在放大电路处于非工作状态 时，可以将预设电源信号的电压下降至第二电压值，以减少隔离控制电路中的开关管漏电现象，避免开关管失效，能够延长隔离控制电路的使用寿命；另外，在放大电路工作的不同阶段，调整隔离控制信号的电压值处于第一电压值或第二电压值，消除待处理信号电位升高时的噪声，加快待处理信号的电压变化速度，优化信号放大过程，以改善信号放大速度慢、电路噪声大的问题。
在本公开的另一实施例中，参见图8，其示出了本公开实施例提供的一种控制放大电路20的应用场景示意图。如图8所示，在该应用场景中，存在位线Bla、互补位线Blb、读出位线saBla、互补读出位线saBlb和控制放大电路20。在位线Bla上设置有第一存储单元51，在互补位线Blb上设置有第二存储单元52。在这里，第一存储单元51和第二存储单元52均可作为前述的目标检测单元。
控制放大电路20包括电源输出电路21、隔离控制电路22、电源切换电路214、隔离控制电路22和放大电路23。在这里，电源输出电路21包括第一开关管301和第二开关管302，隔离控制电路22包括第三开关管303、第四开关管304和第一反向器321。放大电路23可以包括第五开关管305、第六开关管306、第七开关管307、第八开关管308、第九开关管309、第十开关管310、3个第十一开关管(图9中的第十一开关管311-1、第十一开关管311-2和第十一开关管311-3)、3个第十二开关管(图9中的第十二开关管312-1、第十二开关管312-2和第十二开关管312-3)、第十三开关管313、第十四开关管314、3个第二反向器(图9中的第二反向器322-1、第二反向器322-2、第二反向器322-3)和3个第三反向器(图9中的第三反向器323-1、第三反向器323-2、第三反向器323-3)构成，各器件的连接关系和类型如图9所示，其电路的工作原理具体可参见前述内容，在此不做赘述。
基于以上电路结构，对放大电路23的控制方法进行简要说明。
参见图9，其示出了本公开实施例提供的一种放大电路的控制方法的流程示意图。如图9所示，该方法可以包括：
S401：在放大电路处于待机阶段时，隔离控制电路生成具有第二电压值的隔离控制信号，放大电路的各节点电压、第一参考信号及第二参考信号维持第四电压值。
此时，预充信号处于第二电平状态，第十三开关管313和第十四开关管314导通，第一参考控制信号和第二参考控制信号与第四电源连接，放大电路的各节点电压、第一参考信号及第二参考信号维持第四电压值。即位线Bla、互补位线Blb、读出位线saBla、互补读出位线saBlb均处于第四电压值。之后预充信号处于第一电平状态，第十三开关管313和第十四开关管314均断开。
S402：在放大电路处于第一电荷分享阶段的情况下，对目标检测单元中的存储数据进行读取处理，生成待处理信号；以及控制隔离控制信号维持第三电压值。
需要说明的是，目标检测单元根据操作指令打开，向所连接的位线Bla传输所存储的电位形成待处理信号，放大电路处于第一电荷分享阶段。
电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，隔离控制电路根据第一状态的控制指令信号生成具有第三电压值的隔离控制信号Iso，此时，由于第九开关管309和第十开关管310处于断开状态，位线Bla与目标检测单元进行电荷分享，位线Bla的电位会低于或高于第四电压值。
S403：放大电路接收待处理信号，处于第二电荷分享阶段；以及控制隔离控制信号维持第二电压值，控制第一参考信号维持第五电压值，控制第二参考信号维持第六电压值。
需要说明的是，经过第一电荷分享阶段，位线Bla电位稳定后，电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，隔离控制电路根据第二状态的控制指令信号生成具有第二电压值的隔离控制信号Iso，第九开关管309和第十开关管310导通。
位线Bla与读出位线saBla连接，互补位线Blb与互补读出位线saBlb连接，低于或高于第四电压值的位线Bla与读出位线saBla进行电荷分享，使读出位线saBla的电位低于或高于第四电压值。
S404：放大电路基于第一参考信号和第二参考信号进入信号放大阶段，放大电路依据第一参考信号和第二参考信号对待处理信号进行放大处理，得到目标放大信号。
需要说明的是，在一些实施例中，信号放大阶段包括第一放大阶段和演进阶段。在图9的基础上，如图10所示，所示方法还包括：
S4041：在放大电路处于第一放大阶段时，电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，隔离控制电路根据第二状态的控制指令信号生成具有第二电压值的隔离控制信号，放大电路接收隔离控制信号和待处理信号，对待处理信号进行初步放大处理。
需要说明的是，在第一放大阶段，继续维持隔离控制信号具有第二电压值，第九开关管309、第十开关管310导通，将第一参考信号由第四电压值下降至第五电压值，第二参考信号由第四电压值升高至第六电压值，由于读出位线saBla电位的变化，使第六开关管306及第七开关管307导通，将读出位线saBla的电位拉高至第六电压值，或者第五开关管305或第八开关管308导通，将读出位线saBla的电位拉低至第五电压值。
S4042：在放大电路处于演进阶段时，电源输出电路根据电源切换信号选择第一电压值输出为预设电源信号，隔离控制电路根据第二状态的控制指令信号生成具有第一电压值的隔离控制信号，放大电路接收根据隔离控 制信号对待处理信号进行二次放大处理。
需要说明的是，在演进阶段，电源输出电路根据电源切换信号选择第一电压值输出为预设电源信号，隔离控制电路根据第二状态的控制指令信号生成具有第一电压值的隔离控制信号Iso，第九开关管309和第十开关管310导通程度增大，读出位线saBla的电位会快速将位线Bla的电位拉高或拉低，得到目标放大信号。
同时，位线Bla的电位的拉高或拉低，导致相连接的目标检测单元电位同步变化，实现目标检测单元中存储数据的恢复。
需要说明的是，本公开实施例提供的放大电路的控制方法应用于前述的放大电路。具体地，该放大电路与目标检测单元连接。在这里，目标检测单元可以是DRAM中的存储单元(或称为Cell)。
在一些实施例中，信号放大阶段还包括预充阶段；
目标检测单元中存储数据恢复后，控制目标检测单元的开关断开，之后放大电路处于预充阶段，控制隔离控制信号继续维持第一电压值，均衡信号处于第二电压状态，通过第四预设电源控制第一参考信号从第五电压值恢复至第四电压值，控制第二参考信号从第六电压值恢复至第四电压值，放大电路各节点电压也恢复至第四电压值。
需要说明的是，在放大电路处于演进状态时，需要对待处理信号进行放大，同时对目标检测单元进行数据回写，防止目标检测单元的数据在读出后丢失。通过放大电路处于预充阶段以便于放大电路恢复至待机阶段的状态，以接收下一预设操作指令的操作。
在图8的基础上，参见图11，其示出了本公开实施例提供的另一种控制放大电路20的应用场景示意图。如图11所示，放大电路中还具有第十五开关管315和第十六开关管316，此时放大电路在待机阶段之后和第一电荷分享阶段之前，还存在噪声消除阶段。
相应地，在放大电路处于噪声消除阶段时，隔离控制电路根据第一状态的控制指令信号生成具有第三电压值的隔离控制信号，第一参考信号NCS为第五电压值，第二参考信号PCS为第六电压值，噪声消除信号为第一电平状态，第十五开关管315和第十六开关管316导通，实现噪声消除电路的噪声消除处理。
需要说明的是，在噪声消除阶段，第十五开关管315和第十六开关管316处于接通状态，以使得第五开关管305的第一端和第三端短接，且第六开关管306的第一端和第三端短接，从而对第五开关管305和第六开关管306进行偏移消除操作，消除第五开关管305和第六开关管306的阈值电压差。
还需要说明是，第十五开关管(或者第十六开关管)的栅极电压越高，其开启程度越大，通过第十五开关管(或者第十六开关管)的电荷速度越快，电压变化越快。因此，在进入第一放大阶段后，由于隔离控制信号为 第二电平状态中的较低电压值(第二电压值)，待处理信号的电压值不会高于(第二电压值-Vt)，Vt是指第十五开关管(或者第十六开关管)的阈值电压，降低待处理信号的电压变化速度，能够抑制待处理信号升高时电路中的噪声，避免影响其他的存储单元，提高放大裕度。
在图11的基础上，参见图12，其示出了本公开实施例提供的一种放大电路的信号时序示意图。如图12所示，放大电路的工作阶段包括：待机阶段(或称为IDEL)、噪声消除阶段(或称为NC)、电荷分享阶段(或称为CS)、信号放大阶段。其中，信号放大阶段还可以包括第一信号放大阶段、演进阶段和预充阶段。
在图12中，VisoInt是指前述的预设电源信号，可以为第一电压值、第二电压值；Iso是指前述的隔离控制信号，可以为第一电压值、第二电压值、第三电压值；Eq是指前述的预充信号，Nc是指前述的噪声消除信号；SanEn是指前述的第一参考控制信号，SapEn是指前述的第二参考控制信号；WL是指字线开启信号，在WL为第二电平状态时，目标检测单元所在的字线开启，从而目标检测单元和位线接通，在WL为第一电平状态时，目标检测单元关所在的字线关闭，从而目标检测单元和位线不接通；NCS/PCS是指第一参考信号/第二参考信号，第一参考信号具有第四电压值和第五电压值，第二参考信号具有第四电压值和第六电压值，第四电压值和第六电压值的电压方向不同；Bla是指位线，Blb是指互补位线，saBla是指读出位线，saBlb是指互补读出位线。
如图12所示，在放大电路处于待机阶段时，预设电源信号VisoInt维持第二电压值，隔离控制信号Iso维持第二电压值，预充信号Eq和噪声消除信号Nc处于第二电平状态，第一参考控制信号SanEn/第二参考控制信号SapEn均处于第一电平状态，字线WL处于未开启状态，第一参考信号NCS/第二参考信号PCS维持第四电压值，位线Bla/互补位线Blb以及读出位线saBla/互补读出位线saBlb均处于第四电平值。此时，放大电路23的各电路节点处于一相同电压值，为执行用户的操作指令做好前期准备。
假设目标检测单元为第一存储单元51，在用户发送了针对目标检测单元的操作指令后，放大电路23由待机阶段进入噪声消除阶段，此时隔离控制信号Iso由第二电压值调整为第三电压值，预充信号Eq由第二电平状态调整为第一电平状态，第一参考控制信号SanEn/第二参考控制信号SapEn均由第一电平状态调整为第二电平状态，所以第一参考信号NCS由第四电压值向第五电压值变化，第二参考信号PCS由第四电压值向第六电压值变化，而噪声消除信号Nc仍保持第二电平状态，从而对放大电路23进行噪声消除处理。之后，第一参考控制信号SanEn/第二参考控制信号SapEn切换至第一电平状态，第一参考信号NCS和第二参考信号PCS继续由预充电电源供电恢复至第四电压值。
在结束噪声消除阶段后，字线开启信号WL变化为第二电平状态，目 标检测单元所在的字线调整为开启状态，从而放大电路23进入第一电荷分享阶段，此时对目标检测单元(例如第一存储单元51)进行读取。如图12所示，在第一电荷分享阶段结束后，位线Bla电压变化稳定，即产生了待处理信号，互补位线Blb则形成参考待处理信号。换句话说，第一电荷分享阶段可以视为目标检测单元与位线Bla之间的电荷分享。另外，在第一电荷分享阶段，预设电源信号维持第二电压值，隔离控制信号Iso维持第三电压值，使得位线Bla与读出位线saBla不接通，互补位线Blb与互补读出saBlb不接通。预充信号Eq、噪声消除信号Nc、第一参考控制信号SanEn/第二参考控制信号SapEn均处于第一电平状态。
在结束第一电荷分享阶段后，放大电路23进入第二电荷分享阶段。在第二电荷分享阶段，隔离控制信号Iso维持第二电压值，使得位线Bla与读出位线saBla接通，互补位线Blb与互补读出saBlb接通，从而放大电路23将待处理信号和参考待处理信号接收到内部节点，可以视为位线Bla/互补位线Blb与读出位线saBla/互补读出位线saBlb进行读电荷分享。另外，除隔离控制信号Iso之外的其他信号均维持前一阶段的电压值。
在结束第二电荷分享阶段后，放大电路23进入第一信号放大阶段，第一参考控制信号SanEn/第二参考控制信号SapEn由第一电平状态调整为第二电平状态，从而第一参考信号NCS由第四电压值向第五电压值变化，第二参考信号PCS由第四电压值向第六电压值变化，从而放大电路23能够根据第一参考信号NCS/第二参考信号PCS对待处理信号(位线Bla的信号)/参考待处理信号(互补位线Blb的信号)进行放大，隔离控制信号Iso仍然维持第二电压值，以完成对待处理信号(位线Bla的信号)/参考待处理信号(互补位线Blb)上的信号放大。另外，由于隔离控制信号Iso处于第二电压值，所以位线Bla/互补位线Blb上的信号不会最高不会超过(第二电压值-Vt)，避免影响其他的存储单元，但是处于放大电路23内部的读出位线saBla/互补读出位线saBlb上的信号可以很快的达到高参考电位/低参考电位。
在结束第二电荷分享阶段后，放大电路23进入演进阶段，此时预设电源信号VisoInt维持第一电压值，隔离控制信号Iso维持第一电压值，增加第九开关管309和第十开关管310的导通程度，从而完成对待处理信号(位线Bla的信号)/参考待处理信号(互补位线Blb)上的信号放大，放大后的信号经由后续模块进行输出得到目标放大信号，完成读操作。在这一阶段，还会完成目标检测单元的数据回写，避免由于读操作造成数据失效。如图12所示，在演进阶段结束前，第一参考控制信号SanEn/第二参考控制信号SapEn恢复为第一电平状态。
在结束演进阶段后，放大电路23进入预充阶段，预充信号Eq和噪声消除信号Nc调整为第二电平状态，此时，第一参考信号NCS/第二参考信号PCS将恢复至第四电压值，位线Bla/互补位线Blb、读出位线saBla/互补 读出位线saBlb将恢复至相同的电压值。
在结束预充阶段后，放大电路23再次进入待机阶段，以准备下一次操作。上述过程中，用户的操作指令可以为读指令，刷新指令和写指令，放大电路在执行读指令，刷新指令和写指令的过程中：
预设电源信号在放大电路的待机阶段、噪声消除阶段、第一电荷分享阶段、第二电荷分享阶段、第一信号放大阶段均为第二电压值，在放大电路的演进阶段和预充阶段均为第一电压值。
隔离控制信号在放大电路的待机阶段为第二电压值，在噪声消除阶段和第一电荷分享阶段为第三电压值，第二电荷分享阶段、第一信号放大阶段均处于第二电压值，在演进阶段和预充阶段均维持第一电压值。
其中，放大电路在执行写指令的过程，放大电路的演进阶段为写入阶段，用于将外部传输的数据通过位线Bla电压变化写入存储单元。
通过预设电源信号和隔离控制信号的电压变化，便于放大电路在执行读指令，刷新指令和写指令的过程中，提高信号处理速度，抑制信号处理过程中的电路噪声。
在相关技术中，参见图13，其示出了相关技术提供的一种信号时序示意图。在图13中，预设电源信号(未示出)为一固定电压值，所以隔离控制信号Iso存在两个电压值，分别属于第一电平状态和第二电平状态。其他各信号含义及变化原理可参照图12理解，不作赘述。
根据图12和图13可以看出，本公开实施例提供的控制放大电路20至少具有以下优点：一方面，在待机阶段，隔离控制信号为第二电平状态中的较低电压值(第二电压值)，能够避免开关管漏电的问题，较少器件失效现象，提高半导体存储器的使用寿命；另一方面，在由待机阶段进入噪声消除阶段时，隔离控制信号需要由第二电平状态调整为第一电平状态，由于本公开实施例的隔离控制信号在待机阶段具有较低电压值，所以电平状态调整较快，能够提升信号处理的速度；又一方面，在进入第二信号分享阶段后，由于隔离控制信号为第二电平状态中的较低电压值(第二电压值)，待处理信号的电压值不会高于(第二电压值-Vt)，能够减少电路中的噪声，避免影响其他的存储单元，提高放大裕度；再一方面，由于待处理信号的电压值不会高于(第二电压值-Vt)，还能够减少待处理信号电压升高过程中的噪声；再一方面，通过控制3个第十一开关管的状态，可以调整第一参考信号NCS的放电速度，从而减少待处理信号电位降低过程中的噪声。
本公开实施例提供了一种控制放大电路及其控制方法，通过本实施例对前述实施例的具体实现进行详细阐述，从中可以看出，利用电源切换信号能够调整预设电源信号的具体电压值大小，从而部分改善信号放大速度慢和电路噪声大的问题。
在本公开的又一实施例中，参见图14，其示出了本公开实施例提供的 一种灵敏放大器60的组成结构示意图。如图14所示，灵敏放大器60可以包括前述实施例任一项所述的控制放大电路20。
这样，由于灵敏放大器60可以包括前述实施例任一项所述的控制放大电路20，能够利用电源切换信号能够调整预设电源信号的具体电压值大小，从而部分改善信号放大速度慢和电路噪声大的问题。
在本公开的再一实施例中，参见图15，其示出了本公开实施例提供的一种半导体存储器70的组成结构示意图。如图15所示，半导体存储器70可以包括前述实施例任一项所述的灵敏放大器60。
在本公开实施例中，半导体存储器70可以为DRAM芯片。
这样，由于半导体存储器70包括前述的灵敏放大器60，能够利用电源切换信号能够调整预设电源信号的具体电压值大小，从而部分改善信号放大速度慢和电路噪声大的问题。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种控制放大电路、灵敏放大器和半导体存储器，该控制放大电路包括：电源输出电路，用于接收电源切换信号，并根据电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号；隔离控制电路，用于接收控制指令信号和预设电源信号，并根据 控制指令信号生成隔离控制信号；放大电路，用于接收隔离控制信号和待处理信号，并基于隔离控制信号对待处理信号进行放大，得到目标放大信号。这样，利用电源切换信号能够调整预设电源信号的具体电压值大小，进而调整隔离控制电路的具体电压值大小，优化信号放大过程，部分改善信号放大速度慢、容易产生噪声的问题。

Claims (20)

  1. 一种控制放大电路，包括：
    电源输出电路，用于接收电源切换信号，并根据所述电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号；
    隔离控制电路，用于接收控制指令信号和所述预设电源信号，并根据所述控制指令信号生成隔离控制信号；
    放大电路，用于接收所述隔离控制信号和待处理信号，并基于所述隔离控制信号对所述待处理信号进行放大，得到目标放大信号。
  2. 根据权利要求1所述的控制放大电路，其中，所述电源切换信号包括第一电源切换信号和/或第二电源切换信号，所述控制放大电路还包括电源切换电路；
    所述电源切换电路，用于输出所述第一电源切换信号和/或所述第二电源切换信号；
    所述电源输出电路，具体用于接收所述第一电源切换信号和/或所述第二电源切换信号，并根据所述第一电源切换信号和/或所述第二电源切换信号从至少两个预设电压值中选择其中一预设电压值输出为预设电源信号。
  3. 根据权利要求2所述的控制放大电路，其中，所述预设电压值包括第一电压值和第二电压值；
    所述电源输出电路，还用于在所述第一电源切换信号处于第一电平状态，且所述第二电源切换信号处于第二电平状态时，选择第一电压值输出为预设电源信号；或者
    在所述第一电源切换信号处于第二电平状态，且所述第二电源切换信号处于第一电平状态时，选择第二电压值输出为预设电源信号；
    其中，所述第一电压值和所述第二电压值均属于第二电平状态，且所述第一电压值大于所述第二电压值。
  4. 根据权利要求1所述的控制放大电路，其中，所述控制放大电路还包括信号控制电路；其中，
    所述信号控制电路，用于输出所述控制指令信号；
    所述隔离控制电路，还用于在所述控制指令信号处于第一状态时，生成具有第三电压值的所述隔离控制信号；或者
    在所述控制指令信号处于第二状态时，生成与所述预设电源信号电压值相同的所述隔离控制信号；
    其中，第一状态为第一电平状态或第二电平状态，第二状态为第一电平状态或第二电平状态，所述第一状态与所述第二状态所处的电平状态不同；所述第三电压值属于所述第一电平状态，且所述第三电压值小于所述第二电压值。
  5. 根据权利要求3所述的控制放大电路，其中，所述电源输出电路包括第一预设电源、第二预设电源、第一开关管和第二开关管；其中，
    所述第一开关管的第一端与所述第一电源切换信号连接，所述第二开关管的第一端与所述第二电源切换信号连接；
    所述第一开关管的第二端与所述第一预设电源连接，所述第二开关管的第二端与所述第二预设电源连接；
    所述第一开关管的第三端，与所述第二开关管的第三端连接，用于输出所述预设电源信号；
    其中，所述第一预设电源用于输出所述第一电压值，所述第二预设电源用于输出所述第二电压值。
  6. 根据权利要求1所述的控制放大电路，其中，所述隔离控制电路包括第一反向器、第三开关管和第四开关管；其中，
    所述第一反向器的输入端与所述控制指令信号连接，所述第一反向器的输出端分别与所述第三开关管的第一端和第四开关管的第一端连接；
    所述第三开关管的第二端与所述预设电源信号连接，所述第四开关管的第三端与地信号连接；
    所述第三开关管的第三端，与所述第四开关管的第二端连接，用于输出所述隔离控制信号。
  7. 根据权利要求1所述的控制放大电路，其中，所述放大电路包括交叉耦合电路和控制电路；其中，
    所述放大电路，还用于通过所述交叉耦合电路接收所述待处理信号，通过所述控制电路接收所述隔离控制信号，并根据所述隔离控制信号对所述待处理信号进行放大处理，得到目标放大信号。
  8. 根据权利要求7所述的控制放大电路，其中，所述交叉耦合电路包括第五开关管、第六开关管、第七开关管和第八开关管，所述控制电路包括第九开关管和第十开关管；
    所述第五开关管的第一端，与所述第九开关管的第三端连接，用于接收所述待处理信号，所述第五开关管的第二端、所述第七开关管的第三端、所述第八开关管的第一端与第十开关管的第二端连接；
    所述第六开关管的第一端，与所述第十开关管的第三端连接，用于接收参考待处理信号，所述第六开关管的第二端、所述第八开关管的第三端、所述第七开关管的第一端与第九开关管的第二端连接；
    所述第五开关管的第三端、所述第六开关管的第三端与第一参考信号连接，所述第七开关管的第二端、所述第八开关管的第二端与第二参考信号连接，所述第九开关管的第一端、所述第十开关管的第一端与所述隔离控制信号连接。
  9. 根据权利要求8所述的控制放大电路，其中，所述放大电路还包括第一参考电路和第二参考电路；其中，
    所述第一参考电路，用于接收第一参考控制信号，并根据所述第一参考控制信号，输出第一参考信号；
    所述第二参考电路，用于接收第二参考控制信号，并根据所述第二参考控制信号，输出第二参考信号；
    其中，所述第一参考信号的电压值为第四电压值或者第五电压值，所述第二参考信号的电压值为第四电压值或者第六电压值，且第四电压值为第五电压值和第六电压值的中间值。
  10. 根据权利要求9所述的控制放大电路，其中，所述第一参考电路包括n个第十一开关管，n为正整数；
    所述第十一开关管的第一端与所述第一参考控制信号连接，所述第十一开关管的第三端与地信号连接；
    所述第十一开关管的第二端，与所述第一参考电路的输出端连接，用于输出所述第一参考信号。
  11. 根据权利要求10所述的控制放大电路，其中，所述第二参考电路包括m个第十二开关管，m为正整数；
    第十二开关管的第一端与所述第二参考控制信号连接，所述第十二开关管的第二端与第三预设电源连接；
    第十二开关管的第二端，与所述第二参考电路的输出端连接，用于输出所述第二参考信号。
  12. 根据权利要求11所述的控制放大电路，其中，所述放大电路还包括第一信号建立电路和第二信号建立电路；其中，
    所述第一信号建立电路，用于接收第一控制输入信号，输出所述第一参考控制信号；
    所述第二信号建立电路，用于接收第二控制输入信号，输出所述第二参考控制信号。
  13. 根据权利要求12所述的控制放大电路，其中，所述第一信号建立电路包括n个第二反向器，所述第二信号建立电路包括n个第三反向器；其中，
    所述第二反向器的输入端与所述第一控制输入信号连接，所述第二反向器的输出端用于输出所述第一参考控制信号；其中，在n个所述第二反向器中，每个所述第十一开关管的所述第一参考控制信号通过一个所述第二反向器输出；
    所述第三反向器的输入端与所述第一控制输入信号连接，所述第三反向器的输出端用于输出所述第二参考控制信号；其中，在m个所述第三反向器中，每个所述第十二开关管的所述第二参考控制信号通过一个所述第三反向器输出。
  14. 根据权利要求8所述的控制放大电路，其中，所述放大电路还包括预充电路，且所述预充电路包括第十三开关管和第十四开关管；其中，
    所述第十三开关管的第一端、所述第十四开关管的第一端与预充信号连接；
    所述第十三开关管的第二端与第四预设电源连接，所述第十三开关管的第三端与所述第六开关管的第二端连接；
    所述第十四开关管的第三端与所述第五开关管的第二端连接，所述第十四开关管的第二端与所述第六开关管的第二端连接。
  15. 根据权利要求8所述的控制放大电路，其中，所述放大电路还包括噪声消除电路，所述噪声消除电路包括第十五开关管和第十六开关管；其中，
    所述第十五开关管的第一端、第十六开关管的第一端与噪声消除信号连接；
    所述第十五开关管的第二端与所述第五开关管的第二端连接，所述第十五开关管的第三端与所述第五开关管的第一端连接；
    所述第十六开关管的第二端与所述第六开关管的第二端连接，所述第十六开关管的第三端与所述第六开关管的第一端连接。
  16. 根据权利要求5-15任一项所述的控制放大电路，其中，第一开关管、第二开关管、第三开关管、第七开关管和第八开关管为P型沟道场效应管；
    第四开关管、第五开关管、第六开关管、第九开关管、第十开关管、第十一开关管、第十二开关管、第十三开关管、第十四开关管、第十五开关管和第十六开关管为N型沟道场效应管。
  17. 一种放大电路的控制方法，应用于与目标检测单元连接的放大电路，所述控制方法包括：
    在放大电路处于第一放大阶段时，电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，隔离控制电路根据第二状态的控制指令信号生成具有第二电压值的隔离控制信号，所述放大电路接收所述隔离控制信号和待处理信号，对所述待处理信号进行初步放大处理；
    在放大电路处于演进阶段时，所述电源输出电路根据电源切换信号选择第一电压值输出为预设电源信号，所述隔离控制电路根据第二状态的控制指令信号生成具有第一电压值的隔离控制信号，所述放大电路接收根据隔离控制信号对所述待处理信号进行二次放大处理。
  18. 根据权利要求17所述的控制方法，其中，所述放大电路还处于待机阶段、第一电荷分享阶段、第二电荷分享阶段和预充阶段；所述方法还包括：
    在所述放大电路处于待机阶段、第二电荷分享阶段或预充阶段时，所述电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，所述隔离控制电路根据第二状态的控制指令信号生成具有第二电压值的隔离控制信号；
    在所述放大电路处于第一电荷分享阶段时，所述电源输出电路根据电源切换信号选择第二电压值输出为预设电源信号，所述隔离控制电路根据第一状态的控制指令信号生成具有第三电压值的隔离控制信号，所述放大电路接收待处理信号执行第一电荷分享。
  19. 一种灵敏放大器，包括如权利要求1至16任一项所述的控制放大电路。
  20. 一种半导体存储器，包括如权利要求19所述的灵敏放大器。
PCT/CN2022/079726 2021-12-31 2022-03-08 一种控制放大电路、灵敏放大器和半导体存储器 WO2023123668A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP22912974.7A EP4276829A1 (en) 2021-12-31 2022-03-08 Control amplification circuit, sense amplifier and semiconductor memory
US17/807,135 US11894048B2 (en) 2021-12-31 2022-06-15 Control amplifying circuit, sense amplifier and semiconductor memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111657770.XA CN116417026A (zh) 2021-12-31 2021-12-31 一种控制放大电路、灵敏放大器和半导体存储器
CN202111657770.X 2021-12-31

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/807,135 Continuation US11894048B2 (en) 2021-12-31 2022-06-15 Control amplifying circuit, sense amplifier and semiconductor memory

Publications (1)

Publication Number Publication Date
WO2023123668A1 true WO2023123668A1 (zh) 2023-07-06

Family

ID=86997288

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/079726 WO2023123668A1 (zh) 2021-12-31 2022-03-08 一种控制放大电路、灵敏放大器和半导体存储器

Country Status (5)

Country Link
US (1) US11894048B2 (zh)
EP (1) EP4276829A1 (zh)
CN (1) CN116417026A (zh)
TW (1) TWI831298B (zh)
WO (1) WO2023123668A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11273346A (ja) * 1998-03-18 1999-10-08 Hitachi Ltd 半導体装置
US20030043668A1 (en) * 2001-09-05 2003-03-06 Sun Microsystems Inc. Dynamic dram sense amplifier
US20060023535A1 (en) * 2004-07-13 2006-02-02 Ki-Chul Chun Circuit and method of driving bitlines of integrated circuit memory using improved precharge scheme and sense-amplification scheme
US20080151664A1 (en) * 2006-12-22 2008-06-26 Kim Myeong-O Sense amplifier circuit of semiconductor memory device and method of operating the same
US20190392873A1 (en) * 2017-03-03 2019-12-26 Sony Semiconductor Solutions Corporation Sense amplifier, semiconductor storage device, information processing apparatus, and reading method
CN111863051A (zh) * 2020-07-27 2020-10-30 安徽大学 灵敏放大器、存储器和灵敏放大器的控制方法
CN112712837A (zh) * 2021-01-05 2021-04-27 长鑫存储技术有限公司 灵敏放大器、灵敏放大器的控制方法及存储器

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950004870B1 (ko) 1992-11-24 1995-05-15 삼성전자 주식회사 번인 모드에서 분리게이트의 신뢰성 개선회로
US5506524A (en) 1995-03-01 1996-04-09 Lin; Jyhfong Low-voltage low-power dynamic folded sense amplifier
JP2000200489A (ja) 1999-01-07 2000-07-18 Mitsubishi Electric Corp 半導体記憶装置
KR100393224B1 (ko) 2001-06-30 2003-07-31 삼성전자주식회사 비트라인 쌍들의 부하를 차단하는 회로를 구비하는 반도체메모리장치
JP2004234729A (ja) 2003-01-29 2004-08-19 Renesas Technology Corp 半導体記憶装置
JP2005322380A (ja) 2004-04-09 2005-11-17 Toshiba Corp 半導体記憶装置
JP5347249B2 (ja) * 2007-08-20 2013-11-20 富士通株式会社 半導体装置
CN101562042B (zh) 2008-04-14 2012-06-13 北京兆易创新科技有限公司 一种适用于随机存储器的灵敏放大器
US8854144B2 (en) 2012-09-14 2014-10-07 General Atomics High voltage amplifiers and methods
CN104078078B (zh) 2014-06-19 2017-01-04 苏州东微半导体有限公司 一种基于半浮栅存储器的读写控制电路
US9520843B2 (en) 2015-01-05 2016-12-13 Music Group Ip Ltd Power amplifiers coupled in series
US10535388B1 (en) 2018-07-17 2020-01-14 Micron Technology, Inc. Apparatuses and methods for reducing row address to column address delay
US10720895B2 (en) 2018-09-24 2020-07-21 Harman International Industries, Incorported Fully-differential programmable gain amplifier
CN111179983A (zh) 2019-12-10 2020-05-19 普冉半导体（上海）有限公司 一种灵敏放大器电路
CN114730586A (zh) * 2020-02-06 2022-07-08 长鑫存储技术有限公司 感测放大器电路、存储器及其操作方法
CN111863049B (zh) 2020-07-27 2022-11-01 安徽大学 灵敏放大器、存储器和灵敏放大器的控制方法
US11929112B2 (en) 2020-07-27 2024-03-12 Anhui University Sense amplifier, memory, and method for controlling sense amplifier
CN112767975B (zh) 2021-02-10 2022-04-12 长鑫存储技术有限公司 灵敏放大器及其控制方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11273346A (ja) * 1998-03-18 1999-10-08 Hitachi Ltd 半導体装置
US20030043668A1 (en) * 2001-09-05 2003-03-06 Sun Microsystems Inc. Dynamic dram sense amplifier
US20060023535A1 (en) * 2004-07-13 2006-02-02 Ki-Chul Chun Circuit and method of driving bitlines of integrated circuit memory using improved precharge scheme and sense-amplification scheme
US20080151664A1 (en) * 2006-12-22 2008-06-26 Kim Myeong-O Sense amplifier circuit of semiconductor memory device and method of operating the same
US20190392873A1 (en) * 2017-03-03 2019-12-26 Sony Semiconductor Solutions Corporation Sense amplifier, semiconductor storage device, information processing apparatus, and reading method
CN111863051A (zh) * 2020-07-27 2020-10-30 安徽大学 灵敏放大器、存储器和灵敏放大器的控制方法
CN112712837A (zh) * 2021-01-05 2021-04-27 长鑫存储技术有限公司 灵敏放大器、灵敏放大器的控制方法及存储器

Also Published As

Publication number Publication date
US20230223071A1 (en) 2023-07-13
EP4276829A1 (en) 2023-11-15
CN116417026A (zh) 2023-07-11
TWI831298B (zh) 2024-02-01
US11894048B2 (en) 2024-02-06
TW202329093A (zh) 2023-07-16

Similar Documents

Publication Publication Date Title
US11854606B2 (en) Sense amplifier and method for controlling the same
WO2022147981A1 (zh) 灵敏放大器、灵敏放大器的控制方法及存储器
US9047980B2 (en) Sense amplifier for static random access memory with a pair of complementary data lines isolated from a corresponding pair of complementary bit lines
US8779800B2 (en) Control signal generation circuit and sense amplifier circuit using the same
US9455002B2 (en) Amplifying circuit and semiconductor memory device including the same
JPH04370596A (ja) 高速センシング動作を実行するセンスアンプ
US7352650B2 (en) External clock synchronization semiconductor memory device and method for controlling same
CN116092549B (zh) 存储结构
US9412424B2 (en) Noise tolerant sense circuit
WO2023123668A1 (zh) 一种控制放大电路、灵敏放大器和半导体存储器
US20230071414A1 (en) Sense amplification circuit and data reading method
WO2023123666A1 (zh) 一种控制放大方法及电路、灵敏放大器和半导体存储器
WO2023123667A1 (zh) 一种控制放大电路、灵敏放大器和半导体存储器
KR20150052632A (ko) 반도체장치
CN115411035A (zh) 读出电路版图、结构以及存储器版图
Kumar et al. Comparative study of different sense amplifiers in submicron CMOS technology
US7940589B2 (en) Bit line sense amplifier of semiconductor memory device and control method thereof
US20230215491A1 (en) Control amplification circuit, sensitive amplifier and semiconductor memory
WO2024045263A1 (zh) 一种控制电路以及半导体存储器
WO2023142208A1 (zh) 放大电路、控制方法和存储器
WO2023142207A1 (zh) 放大电路、控制方法和存储器
TW202411990A (zh) 控制電路以及半導體存儲器
CN115411028A (zh) 读出电路版图、结构以及存储器版图
GB2260839A (en) Data transmission circuit for a semiconductor memory
CN116564371A (zh) 放大电路、控制方法和存储器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22912974

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022912974

Country of ref document: EP

Effective date: 20230810