WO2024045263A1 - 一种控制电路以及半导体存储器 - Google Patents

一种控制电路以及半导体存储器 Download PDF

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Publication number
WO2024045263A1
WO2024045263A1 PCT/CN2022/124024 CN2022124024W WO2024045263A1 WO 2024045263 A1 WO2024045263 A1 WO 2024045263A1 CN 2022124024 W CN2022124024 W CN 2022124024W WO 2024045263 A1 WO2024045263 A1 WO 2024045263A1
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Prior art keywords
power
module
precharge
switch
signal
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PCT/CN2022/124024
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English (en)
French (fr)
Inventor
吴道训
武贤君
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长鑫存储技术有限公司
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Publication of WO2024045263A1 publication Critical patent/WO2024045263A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a control circuit and a semiconductor memory.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the read data signal of each memory unit is read out in sequence through the local data line, global data line and data bus; conversely, in the process of data writing, the write data signal is sequentially read out through The data bus, global data lines, and local data lines write to the memory cells.
  • SA sense amplifier
  • the present disclosure provides a control circuit and a semiconductor memory, which can effectively suppress power supply noise at different stages, increase the reading and writing speed, and thereby improve the performance of the sensitive amplifier.
  • an embodiment of the present disclosure provides a control circuit, which is connected to a sensitive amplifier circuit, and the control circuit includes a precharge control module and a power control module, wherein:
  • the precharge control module includes a precharge drive module and a precharge module, and the precharge drive module is connected to the first power supply and is used to provide a precharge drive signal to the precharge module through the precharge drive module.
  • the precharge drive signal is used to control the precharge drive module.
  • the charging module performs pre-charging processing for the sensitive amplifier circuit;
  • the power control module includes a power drive module and a reference power module, and the power drive module is connected to the second power supply, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to provide power to the sensitive amplifier circuit according to the power drive signal.
  • Reference voltage wherein the first power supply and the second power supply are different.
  • control circuit further includes a power switch module, and the power switch module is connected to a third power supply, wherein: the power switch module is configured to receive a power enable signal, and control the power inside the power switch module according to the power enable signal.
  • the switching tube state is used to provide the second power supply to the power driving module through the third power supply, and the first power supply is different from the third power supply.
  • the third power supply includes a first working power supply and a second working power supply.
  • the first working power supply and the second working power supply are in different voltage domains and/or have different temperature characteristics.
  • the power enable signal includes the first power supply.
  • the power switch module includes a first switch tube and a second switch tube, wherein: the first end of the first switch tube is connected to the first working power supply, and the control of the first switch tube
  • the terminal is connected to the first power enable sub-signal, the first terminal of the second switch tube is connected to the second working power supply, the control terminal of the second switch tube is connected to the second power enable sub-signal, and the second terminal of the first switch tube is connected to the second power enable sub-signal.
  • the terminal is connected to the second terminal of the second switch tube, and the first switch tube and the second switch tube are selectively connected to provide a second power supply for the power drive module.
  • the first switch transistor when the sensitive amplifier circuit operates in the bias elimination stage, the first switch transistor is turned on to provide the second power supply to the power drive module through the first operating power supply; and when the sensitive amplifier circuit operates in the signal amplification stage When, the second switch tube is turned on to provide the second power supply to the power driving module through the second working power supply.
  • the power switch module includes at least one of the following: a pull-up power switch module and a pull-down power switch module; wherein the first switch tube and the second switch tube included in the pull-up power switch module are PMOS tubes, The first switch tube and the second switch tube included in the pull-down power switch module are NMOS tubes, and the first working power supply connected to the pull-up power switch module is different from the first working power supply connected to the pull-down power switch module.
  • the pull-up power switch module is connected to The second working power supply is different from the second working power supply connected to the pull-down power switch module.
  • the control circuit when the number of power switch modules is at least one, the control circuit further includes a power switch control module, wherein: the power switch control module is configured to receive the bias elimination enable signal and the target power enable signal, Generate at least one set of power enable signals based on the bias cancellation enable signal and the target power enable signal; wherein each set of power enable signals includes a first power enable sub-signal and a second power enable sub-signal, and At least one set of power enable signals has a corresponding relationship with at least one power switch module.
  • the power switch control module is configured to receive the bias elimination enable signal and the target power enable signal, Generate at least one set of power enable signals based on the bias cancellation enable signal and the target power enable signal; wherein each set of power enable signals includes a first power enable sub-signal and a second power enable sub-signal, and At least one set of power enable signals has a corresponding relationship with at least one power switch module.
  • the target power enable signal includes a first target power enable signal and a second target power enable signal
  • the power switch control module includes a first logic control module and a second logic control module, wherein: the first logic The control module is configured to receive the offset elimination enable signal and the second target power enable signal, and output at least one first power enable sub-signal; the second logic control module is configured to receive the offset elimination enable signal and the first power enable signal.
  • the target power enable signal outputs at least one second power enable sub-signal; wherein the first target power enable signal and the first power enable sub-signal have the same valid state, and the second target power enable signal and the second The power enable sub-signals have the same valid state.
  • the first logic control module includes a first NOT gate, a first NAND gate, a first level conversion module and a second NOT gate, wherein: the input end of the first NOT gate is used to receive the second target The power enable signal, the output terminal of the first NOT gate is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is used to receive the bias elimination enable signal, the first NAND gate
  • the output end of the first level conversion module is connected to the input end of the first level conversion module.
  • the output end of the first level conversion module is connected to the input end of the second NOT gate.
  • the output end of the second NOT gate is used to output at least one first power source.
  • the second logic control module includes a first NOR gate, a third NOR gate, a second level switching module and a fourth NOR gate, wherein: the first input end of the first NOR gate is used to receive a bias Eliminate the enable signal, the second input terminal of the first NOR gate is used to receive the first target power enable signal, the output terminal of the first NOR gate is connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate The terminal is connected to the input terminal of the second level conversion module, the output terminal of the second level conversion module is connected to the input terminal of the fourth NOT gate, and the output terminal of the fourth NOT gate is used to output at least one second power enabler Signal.
  • the power switch control module further includes a fifth NOT gate, wherein: the input terminal of the fifth NOT gate is used to receive the bias cancellation inverted signal, and the output terminal of the fifth NOT gate is used to output the bias cancellation signal. can signal.
  • the precharge module includes a precharge switch tube, wherein: the first end of the precharge switch tube is connected to the precharge source, the control end of the precharge switch tube is used to receive the precharge drive signal, and the precharge switch tube The second end is connected to the read bit line.
  • the precharge module includes a precharge switch, wherein: a first end of the precharge switch is connected to the readout bit line, a control end of the precharge switch is used to receive a precharge drive signal, and the precharge switch The second end of the tube is connected to the complementary sense bit line.
  • the precharge driving module includes a precharge inverter, wherein: the input end of the precharge inverter is used to receive the precharge enable signal, and the control end of the precharge inverter is connected to the first power supply, The output terminal of the precharge inverter is used to output the precharge driving signal.
  • embodiments of the present disclosure provide a semiconductor memory, which includes a control circuit, a plurality of memory blocks, and a sensitive amplification module disposed between two adjacent memory blocks. There is a switch module installed in the space.
  • the control circuit includes a precharge control module and a power control module.
  • the sensitive amplification module includes a sensitive amplification circuit and a precharge control module.
  • the switch module includes a power control module, in which:
  • the precharge control module includes a precharge drive module and a precharge module, and the precharge drive module is connected to the first power supply, and is used to provide a precharge drive signal to the precharge module through the precharge drive module, and control the precharge according to the precharge drive signal.
  • the module performs precharge processing for the sensitive amplifier circuit;
  • the power control module includes a power drive module and a reference power module, and the power drive module is connected to the second power supply, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to provide power to the sensitive amplifier circuit according to the power drive signal.
  • Reference voltage wherein the first power supply and the second power supply are different.
  • the semiconductor memory further includes a power switch module as in the first aspect and a power switch control module as in the first aspect, wherein: the power switch module and the power switch control module are both located in the switch module; or, the power switch The module is located in the switch module, and the power switch control module is located in the peripheral area of the semiconductor memory; or, the power switch module and the power switch control module are both located in the peripheral area of the semiconductor memory.
  • Embodiments of the present disclosure provide a control circuit and a semiconductor memory.
  • the control circuit is connected to a sensitive amplifier circuit, and the control circuit includes a precharge control module and a power supply control module.
  • the precharge control module includes a precharge drive module and a precharge control module.
  • the control module includes a power drive module and a reference power module, and the power drive module is connected to the second power supply, and is used to provide a power drive signal for the reference power module through the power drive module, and control the reference power module to provide a reference for the sensitive amplification circuit according to the power drive signal. Voltage; wherein the first power supply and the second power supply are different.
  • the precharge drive module and the power drive module use different power supplies, the power supply noise at different stages can be isolated, so that the SA noise suppression and read and write speeds are effectively improved, and the signal amplification process of the sensitive amplification circuit can be optimized, thereby improving Sensitive amplifier performance.
  • Figure 1 is a schematic diagram of the application scenario of a sensitive amplifier
  • Figure 2 is a schematic structural diagram of a control circuit provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram 2 of the composition and structure of a control circuit provided by an embodiment of the present disclosure
  • Figure 4 is a schematic diagram 3 of the composition of a control circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram 4 of the composition and structure of a control circuit provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram 5 of the composition and structure of a control circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of a power switch control module provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram 2 of the composition of a power switch control module provided by an embodiment of the present disclosure
  • Figure 9 is a schematic structural diagram of a pull-up power control module provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of a pull-down power control module provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of a sensitive amplifier circuit provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram 2 of the composition and structure of a sensitive amplifier circuit provided by an embodiment of the present disclosure
  • Figure 13 is a schematic diagram 3 of the composition and structure of a sensitive amplifier circuit provided by an embodiment of the present disclosure
  • Figure 14 is a schematic diagram of an application scenario of a sensitive amplifier provided by an embodiment of the present disclosure.
  • Figure 15 is a schematic signal timing diagram of a sensitive amplifier provided by an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • the high level and low level used in the signals involved in the embodiments of the present disclosure refer to the logic level of the signal. There is a difference between a signal having a high level and a signal having a low level.
  • a high level may correspond to a signal having a first voltage
  • a low level may correspond to a signal having a second voltage.
  • the first voltage is greater than the second voltage.
  • the logic levels of signals may be different or opposite to those described. For example, a signal described as having a logic "high” level may alternatively have a logic "low” level, and a signal described as having a logic "low” level may alternatively have a logic "high” level .
  • FIG. 1 shows a schematic diagram of an application scenario of a sensitive amplifier.
  • the application scenario may include a first signal line 11 , a second signal line 12 , and a sense amplifier 13 .
  • the first signal line 11 has a first switch Sx and a first capacitor C1 for transmitting the signal to be processed Vin+;
  • the second signal line 12 has a second switch Sy and a second capacitor C2 for transmitting the reference signal to be processed.
  • the sense amplifier 13 is used to amplify the signal to be processed Vin+ and the reference signal to be processed Vin-.
  • the first switch Sx and the second switch Sy are used to control the connection between the first signal line 11 and the second signal line 12 and the sense amplifier 13, and the first capacitor C1 and the second capacitor C2 are used to control the signals to be processed Vin+ and Filter with reference to the signal to be processed Vin- to weaken its high-frequency characteristics.
  • the sense amplifier 13 may include a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a fourth switching transistor M4.
  • the control end of the first switch M1, the control end of the second switch M2, the first end of the third switch M3, and the first end of the fourth switch M4 are all connected to the reference signal to be processed Vin-.
  • the first switch The first end of the transistor M1, the first end of the second switching transistor M2, the control end of the third switching transistor M3, and the control end of the fourth switching transistor M4 are all connected to the signal to be processed Vin+.
  • the control terminal of the fifth switching tube 135 is connected to the first control signal SAP.
  • the first terminal of the fifth switching tube M5 is connected to the power signal VBLH.
  • the second end of the fifth switch M5 is connected to the second end of the first switch M1 and the second end of the third switch M3 to form a first reference signal end, represented by PCS;
  • the control end of the sixth switch M6 is connected to
  • the second control signal SAN is connected, the first end of the sixth switch M6 is connected to the ground signal GND, the second end of the sixth switch M6 and the second end of the second switch M2 and the second end of the fourth switch M4
  • the terminals are connected to form the second reference signal terminal, represented by NCS.
  • a precharge circuit may also exist between the first signal line 11 and the second signal line 12, and a precharge circuit may also exist between the second end of the third switch M3 and the second end of the fourth switch M4. path for precharging the first reference signal terminal and the second reference signal terminal.
  • the first switching transistor M1, the third switching transistor M2, and the fifth switching transistor M5 are P-type field effect transistors (PMOSFETs, PMOS transistors for short); the second switching transistors M2 and the fourth switching transistors The switching transistor M4 and the sixth switching transistor M6 are N-type field effect transistors (NMOSFET, referred to as NMOS transistors for short).
  • the first switching tube M1 and the second switching tube M2 form an inverter INV1
  • the third switching tube M3 and the fourth switching tube M4 form another inverter INV2. are connected separately to the outputs, forming a latch.
  • the power signal VBLH provides power for the sense amplifier 13, and is connected to the sense amplifier 13 by the fifth switching tube M5
  • the ground signal GND is the ground wire of the sense amplifier, and is connected to the sense amplifier 13 by the sixth switching tube M6.
  • the working process can be divided into three stages: a precharge (EQ) stage, a small signal input stage and a signal amplification stage.
  • the precharge circuit precharges the sensitive amplifier 13; in the small signal input stage, the small signal can be input from Sx or Sy in Figure 1; in the signal amplification stage, the signal can be amplified through the sensitive amplifier 13.
  • control circuit which is connected to a sensitive amplifier circuit, and the control circuit includes a precharge control module and a power supply control module, wherein: the precharge control module includes a precharge drive module and a precharge control module.
  • the power control module includes a power drive module and a reference power module, and the power drive module is connected to the second power supply, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to provide power to the sensitive amplifier circuit according to the power drive signal.
  • Reference voltage wherein the first power supply and the second power supply are different.
  • the precharge drive module and the power drive module use different power supplies, the power supply noise at different stages can be isolated, so that the SA noise suppression and read and write speeds are effectively improved, and the signal amplification process of the sensitive amplification circuit can be optimized; at the same time, according to The difference between the first power supply and the second power supply can also optimize the sense margin, thereby improving the performance of the sensitive amplifier.
  • FIG. 2 shows a schematic structural diagram of a control circuit provided by an embodiment of the present disclosure.
  • the control circuit 20 may include a precharge control module 21 and a power control module 22, where:
  • the precharge control module 21 includes a precharge drive module 211 and a precharge module 212, and the precharge drive module 211 is connected to the first power supply and is used to provide a precharge drive signal to the precharge module 212 through the precharge drive module 211.
  • the driving signal is used to control the precharge module 212 to perform precharge processing for the sensitive amplifier circuit;
  • the power control module 22 includes a power drive module 221 and a reference power module 222, and the power drive module 221 is connected to the second power supply, and is used to provide a power drive signal to the reference power module 222 through the power drive module 221, and control the reference power supply according to the power drive signal.
  • Module 222 provides a reference voltage for the sensitive amplifier circuit; wherein the first power supply and the second power supply are different.
  • control circuit 20 can be applied in various signal amplification scenarios, such as a sense amplifier in a DRAM.
  • the first power supply can be represented by VDD1
  • the second power supply can be represented by VDD2.
  • the control circuit 20 may be connected to the sensitive amplifier circuit 30 .
  • the precharge drive module 211 provides the precharge drive signal to the precharge module 212, so that the precharge module 212 performs precharge processing for the sensitive amplifier circuit 30; in the signal amplification stage, the precharge module 212 is driven by the power supply.
  • the module 221 provides a power driving signal to the reference power module 222, so that the reference power module 222 provides a reference voltage for the sensitive amplification circuit, thereby enabling signal amplification processing.
  • the control circuit 20 may also include a power switch module 23, and the power switch module 23 is connected to the third power supply, where:
  • the power switch module 23 is configured to receive a power enable signal and control the state of the switch tube inside the power switch module according to the power enable signal to provide a second power supply to the power drive module 221 through a third power supply.
  • the first power supply and the third power supply are The power supply is different.
  • the third power supply may be represented by VDD3.
  • the third power supply can be obtained by the relevant processing of the power switch module 23 at this time, so that different second power supplies can be provided to the power drive module 221 at different stages to achieve the purpose of reducing power supply noise.
  • the power switch module 23 has a voltage adjustment function, and the power switch module 23 can output a different second power supply under the condition that the third power supply VDD3 remains unchanged.
  • the third power supply may include a first working power supply and a second working power supply, and the first working power supply and the third working power supply
  • the two working power supplies are in different voltage domains and/or have different temperature characteristics.
  • the first working power supply is different from the second working power supply.
  • the first working power supply is used to provide the power driving module 221 with the working power required in the first stage
  • the second working power supply is used to provide the power driving module 221 with the working power required in the second stage. required working power supply.
  • the power supply enable signal may include a first power supply enable sub-signal and a second power supply enable sub-signal.
  • the power switch module 23 may include a first switch tube Q1 and a second switch tube Q2; wherein the first switch tube Q1 The first end of the first switch tube Q1 is connected to the first working power supply, the control end of the first switch tube Q1 is connected to the first power enable sub-signal, the first end of the second switch tube Q2 is connected to the second working power supply, and the second switch tube Q2 The control end of is connected to the second power enable sub-signal, the second end of the first switch tube Q1 is connected to the second end of the second switch tube Q2, and the first switch tube Q1 and the second switch tube Q2 are selectively turned on. , used to provide the second power supply to the power driving module 221.
  • the first switching transistor Q1 and the second switching transistor Q2 are not turned on at the same time. Among them, at different stages, the first switching tube Q1 and the second switching tube Q2 are selectively turned on, so that different second power supplies can be provided for the power driving module 221 .
  • the first power enable sub-signal is also used to control the conduction degree of the first switch Q1
  • the second power enable sub-signal is also used to control the conduction degree of the second switch Q2 to adjust The size of the second power supply VDD2.
  • the sensitive amplifier circuit 30 works in the first stage, then for the power switch module 23, the first switch transistor Q1 is controlled to be in a conductive state according to the first power enable sub-signal, The second switch transistor Q2 is controlled to be in an off state according to the second power enable sub-signal to provide the second power supply to the power drive module 221 through the first operating power supply; if the sensitive amplifier circuit 30 works in the second stage, then for the power switch For module 23, the first switch Q1 is controlled to be in an off state according to the first power enable sub-signal, and the second switch Q2 is controlled to be in an on state according to the second power enable sub-signal, so that the second operating power supply is used.
  • the power driving module 221 provides a second power supply.
  • the first stage may be an offset cancellation (Offset Cancel, OC or NC) stage
  • the second stage may be a signal amplification (Develop) stage. Therefore, in some embodiments, when the sensitive amplifying circuit 30 is operating in the bias elimination stage, the first switch Q1 is turned on to provide the second power supply to the power driving module 221 through the first operating power supply; when the sensitive amplifying circuit 30 When working in the signal amplification stage, the second switch transistor Q2 is turned on to provide the second power supply to the power driving module 221 through the second operating power supply.
  • the second power supply is adjusted according to the OC stage and the Develop stage, which can improve SA noise suppression, read and write speed control, sense margin optimization, etc.
  • the first working power supply in the OC stage and the second working power supply in the Develop stage are in different voltage domains and/or have different temperature characteristics; that is, the second power supply required by the power driving module 221 It can be separated according to the OC stage and the Develop stage, and the working power supply of the OC stage and the Develop stage can adjust the corresponding voltage range (voltage trim range) and temperature characteristics respectively, which is more beneficial to the sense margin optimization of the sensitive amplifier circuit 30.
  • the power control module 22 may be a pull-up power control module or a pull-down power control module.
  • the control circuit 20 may also include a pull-up power control module 24 and a pull-down power control module 25, in:
  • the pull-up power control module 24 includes a pull-up power driver module 241 and a pull-up reference power module 242, and the pull-up power driver module 241 is connected to the fourth power supply, and is used to provide the pull-up reference power module 242 through the pull-up power driver module 241. Provide a pull-up power drive signal, and control the pull-up reference power module 242 to provide the first reference voltage for the sensitive amplifier circuit 30 according to the pull-up power drive signal;
  • the pull-down power supply control module 25 includes a pull-down power supply driving module 251 and a pull-down reference power supply module 252, and the pull-down power supply driving module 251 is connected to the fifth power supply and is used to provide a pull-down power driving signal for the pull-down reference power supply module 252 through the pull-down power supply driving module 251.
  • the pull-down reference power module 252 is controlled according to the pull-down power driving signal to provide the second reference voltage for the sensitive amplifier circuit 30 .
  • the first power supply and the fourth power supply are different, and the first power supply and the fifth power supply are also different.
  • the fourth power supply can be represented by VDD4
  • the fifth power supply can be represented by VDD5.
  • the pull-up power control module 24 may be the power control module 22 in FIG. 2
  • the pull-down power control module 25 may be the power control module 22 in FIG. 2 , that is, the pull-up power control module 24 and the pull-down power control module 25 are
  • the internal structure is the same as that of the power control module 22 .
  • the two power control modules may be called the pull-up power control module 24 and the pull-down power control module 25 .
  • the second power supply can be generated by the power switch module and its connected first working power supply and second working power supply
  • the fourth power supply can also be generated by the power switch module.
  • the module and its connected first working power supply and second working power supply; for the pull-down power control module 25, the fifth power supply can also be generated by the power switch module and its connected first working power supply and second working power supply. of.
  • the power switch module 23 includes at least one of the following: a pull-up power switch module and a pull-down power control module. Power switch module;
  • the first switch tube and the second switch tube included in the pull-up power switch module can be PMOS tubes
  • the first switch tube and the second switch tube included in the pull-down power switch module can be NMOS tubes
  • the pull-up power switch module is connected
  • the first working power supply is different from the first working power supply connected to the pull-down power switch module
  • the second working power supply connected to the pull-up power switch module is different from the second working power supply connected to the pull-down power switch module.
  • the control circuit 20 may also include a pull-up power switch module 26 and a pull-down power switch module 27 .
  • the pull-up power switch module 26 is connected to the pull-up power driving module 241, and is used to provide the fourth power supply VDD4 to the pull-up power driving module 241, so that the pull-up power driving module 241 can drive the pull-up reference power module 242, and then Provide the first reference voltage to the sensitive amplifier circuit 30;
  • the pull-down power switch module 27 is connected to the pull-down power drive module 251, and is used to provide the fifth power supply VDD5 to the pull-down power drive module 251, so that the pull-down power drive module 251 can drive the pull-down reference power supply.
  • Module 252 further provides the second reference voltage for the sensitive amplifier circuit 30 .
  • the pull-up power switch module 26 may include a first switch tube P1 and a second switch tube P2.
  • the first end of the first switch tube P1 is connected to the third operating power supply vnocp.
  • the control end of the switch P1 is connected to the first power enable sub-signal
  • the first end of the second switch P2 is connected to the fourth working power supply vpcsg
  • the control end of the second switch P2 is connected to the second power enable sub-signal.
  • the second end of the first switch transistor P1 is connected to the second end of the second switch transistor P2, and the first switch transistor P1 and the second switch transistor P2 are selectively connected to provide the pull-up power drive module 241 with the third terminal.
  • the pull-down power switch module 27 may include a first switch N1 and a second switch N2.
  • the first end of the first switch N1 is connected to the fifth operating power supply vnoc, and the control end of the first switch N1 is connected to the first power enable. sub-signal connection, the first end of the second switch tube N2 is connected to the sixth working power supply vncsgh, the control end of the second switch tube N2 is connected to the second power enable sub-signal, and the second end of the first switch tube N1 is connected to the The second ends of the two switch transistors N2 are connected, and the first switch transistor N1 and the second switch transistor N2 are selectively turned on to provide the fifth power supply VDD5 for the pull-down power driving module 251 .
  • the first switch tube P1 is turned on to provide the pull-up power drive module 241 with the third operating power supply vnocp.
  • different second power supplies can be provided to the pull-up power driving module 241 at different stages; for the pull-down power switch module 27
  • the first switch N1 is turned on to provide the second power supply to the pull-down power driver module 251 through the fifth operating power supply vnoc; in the signal amplification stage, the second switch N2 is turned on to provide the second power supply through the sixth operating power supply vnoc.
  • the working power supply vncsgh provides the second power supply (specifically, the fifth power supply) for the pull-down power driving module 251 . Since the fifth working power supply vnoc and the sixth working power supply vncsgh are in different voltage domains and/or have different temperature characteristics, different second power supplies can be provided to the pull-down power driving module 251 at different stages.
  • the second power supply required for both the pull-up power drive module 241 and the pull-down power drive module 251 can be separated according to the OC stage and the Develop stage, and the working power supplies of the OC stage and the Develop stage can be adjusted to the corresponding voltage range ( voltage trim range) and temperature characteristics, thereby improving SA noise suppression, read and write speed control, and sense margin optimization, etc., ultimately improving the performance of the sensitive amplifier.
  • control circuit 20 may also include a power switch control module 28, wherein:
  • the power switch control module 28 is configured to receive the bias elimination enable signal and the target power enable signal, and generate at least one set of power enable signals according to the bias elimination enable signal and the target power enable signal; wherein, each set of power The enable signals each include a first power enable sub-signal and a second power enable sub-signal, and at least one set of power enable signals has a corresponding relationship with at least one power switch module.
  • the pull-up power switch module 26 and the pull-down power switch module 27 are taken as an example.
  • the power switch control module 28 can Two sets of power enable signals are output, one set of power enable signals is sent to the pull-up power switch module 26 , and the other set of power enable signals is sent to the pull-down power switch module 27 .
  • the target power enable signal may include a first target power enable signal and a second target power enable signal.
  • the power switch control module 28 may include a first logic control module 281 and a second logic control module 282, wherein:
  • the first logic control module 281 is configured to receive the bias cancellation enable signal and the second target power enable signal, and output at least one first power enable sub-signal;
  • the second logic control module 282 is configured to receive the offset cancellation enable signal and the first target power enable signal, and output at least one second power enable sub-signal.
  • the first target power enable signal and the first power enable sub-signal have the same valid state
  • the second target power enable signal and the second power enable sub-signal have the same valid state. That is to say, the first target power enable signal and the effective level of the first power enable sub-signal correspond to the same operating state
  • the second target power enable signal corresponds to the effective level of the second power enable sub-signal. are in the same operating state.
  • the power switch control module 28 can output at least one set of power enable signals, and the number of sets of power enable signals is related to the number of power switch modules 23 .
  • the control circuit 20 includes two power switch modules such as a pull-up power switch module and a pull-down power switch module, then the power switch control module 28 needs to output two sets of power enable signals, each set of power enable signals corresponding to Connect a power switch module.
  • the pull-up power switch module 26 in Figure 6 is connected to one set of power enable signals, and the pull-down power switch module 27 is connected to another set of power enable signals.
  • the first logic control module 281 may include a first NOT gate U1, a first NAND gate U2, a first level conversion module U3, and a second NOT gate U4, wherein:
  • the input terminal of the first NOT gate U1 is used to receive the second target power enable signal.
  • the output terminal of the first NOT gate U1 is connected to the first input terminal of the first NAND gate U2.
  • the second terminal of the first NAND gate U2 The input terminal is used to receive the bias elimination enable signal.
  • the output terminal of the first NAND gate U2 is connected to the input terminal of the first level conversion module U3.
  • the output terminal of the first level conversion module U3 is connected to the second NOT gate U4.
  • the input terminal is connected, and the output terminal of the second NOT gate U4 is used to output at least one first power enable sub-signal;
  • the second logic control module 282 may include a first NOR gate U5, a third NOT gate U6, a second level switching module U7, and a fourth NOT gate U8, where:
  • the first input terminal of the first NOR gate U5 is used to receive the offset elimination enable signal, and the second input terminal of the first NOR gate U5 is used to receive the first target power enable signal.
  • the output terminal is connected to the input terminal of the third NOT gate U6, the output terminal of the third NOT gate U6 is connected to the input terminal of the second level conversion module U7, and the output terminal of the second level conversion module U7 is connected to the fourth NOT gate U8.
  • the input terminal is connected, and the output terminal of the fourth NOT gate U8 is used to output at least one second power enable sub-signal.
  • the first level switching module U3 or the second level switching module U7 can implement voltage domain switching (Level shift), and different voltage domains can correspond to different sets of power enable. signal; after the power switch control module 28 outputs at least one set of power enable signals, these power enable signals can be sent to different power switch modules.
  • Level shift voltage domain switching
  • the power switch control module 28 may also include a fifth non- Gate U9, where:
  • the input terminal of the fifth NOT gate U9 is used to receive the bias elimination inverted signal, and the output terminal of the fifth NOT gate U9 is connected to the second input terminal of the first NAND gate U2 and the first input of the first NOR gate U5 respectively. terminal is connected to provide an offset elimination enable signal for the second input terminal of the first NAND gate U2 and the first input terminal of the first NOR gate U5.
  • the offset cancellation inverted signal and the offset cancellation enable signal are a set of inverted signals.
  • the offset elimination enable signal can be represented by NcEn
  • the offset elimination inversion signal can be represented by NcEnN.
  • the power switch control module 28 serves as a master control circuit and can provide a set of power enable signals (including the first power enable sub-signal and the second power enable sub-signal) for different power switch modules. Power enable sub-signal).
  • the first power enable sub-signal and the second power enable sub-signal in each group are generated based on the bias cancellation inverted signal, and the first power enable sub-signal and the second power enable sub-signal will not be in a valid level state at the same time; that is, there is a timing relationship between the bias cancellation inversion signal and the first power enable sub-signal and the second power enable sub-signal.
  • the pull-up reference power module 242 may include multiple pull-up switch tubes, wherein:
  • the control end (gate) of the pull-up switch is used to receive the pull-up power drive signal.
  • the first end of the pull-up switch is connected to the pull-up reference power supply.
  • the second end of the pull-up switch is used to output the first reference Voltage PCS.
  • the pull-up power driving module 241 may include multiple pull-up inverters, wherein:
  • the control terminal of the pull-up inverter is connected to the pull-up driving power supply, the input terminal of the pull-up inverter is used to receive the pull-up control input signal, and the output terminal of the pull-up inverter is used to output the pull-up power supply driving signal.
  • the number of pull-up switch transistors is consistent with the number of pull-up inverters.
  • the output end of each pull-up inverter is connected to the control end of the corresponding pull-up switch tube, and is used to provide a pull-up power drive signal for the pull-up switch tube.
  • the pull-up power driving module 241 may include a first pull-up inverter I1, a second pull-up inverter I2, and a third pull-up inverter I3.
  • the pull-up reference power module 242 may include a first pull-up switch M1, The second pull-up switch M2 and the third pull-up switch M3, where:
  • the input terminal of the first pull-up inverter I1 is used to receive the first control input signal Vpu1, and the output terminal of the first pull-up inverter I1 is used to output the first pull-up power drive.
  • Signal Pup1; the input terminal of the second pull-up inverter I2 is used to receive the second control input signal Vpu2, and the output terminal of the second pull-up inverter I2 is used to output the second pull-up power drive signal Pup2;
  • the third pull-up inverter I2 is used to receive the second control input signal Vpu2.
  • the input terminal of the pull-up inverter I3 is used to receive the third control input signal Vpu3, and the output terminal of the third pull-up inverter I3 is used to output the third pull-up power drive signal Pup3; the first pull-up inverter I1
  • the control terminal, the control terminal of the second pull-up inverter I2, and the control terminal of the third pull-up inverter I3 are all connected to the pull-up driving power supply vpcsgloc.
  • the pull-up reference power module 242 the first end of the first pull-up switch M1 is connected to the first pull-up reference power supply vblh1, and the first end of the second pull-up switch M2 is connected to the second pull-up reference power supply vblh2.
  • the first end of the third pull-up switch tube M3 is connected to the third pull-up reference power supply vblh3; the control end of the first pull-up switch tube M1 is used to receive the first pull-up power supply driving signal Pup1, and the second pull-up switch tube
  • the control end of M2 is used to receive the second pull-up power drive signal Pup2
  • the control end of the third pull-up switch M3 is used to receive the third pull-up power drive signal Pup3, the second end of the first pull-up switch M1
  • the second end of the second pull-up switch M2 is connected to the second end of the third pull-up switch M3 for outputting the first reference voltage PCS.
  • the first pull-up reference power supply vblh1, the second pull-up reference power supply vblh2 and the third pull-up reference power supply vblh3 may be the same or different, without any limitation here.
  • the pull-up driving power supply vpcsgloc (ie, the fourth power supply described in the previous embodiment) is provided by the pull-up power switch module 26 .
  • the first end of the first switch P1 is connected to the third operating power supply vnocp, and the control end of the first switch P1 is connected to the first power enable sub-signal SCmosOcEn.
  • the first end of the second switch tube P2 is connected to the fourth operating power supply vpcsg
  • the control end of the second switch tube P2 is connected to the second power enable sub-signal SCmosSDTEn
  • the second end of the first switch tube P1 is connected to the second switch
  • the second end of the transistor P2 is connected, and the first switching transistor P1 and the second switching transistor P2 are selectively connected to provide the pull-up driving power supply vpcsgloc to the pull-up power driving module 241 .
  • the pull-down reference power module 252 may include multiple pull-down switch tubes, wherein:
  • the control terminal of the pull-down switch tube is used to receive the pull-down power supply driving signal.
  • the first terminals of the pull-down switch tube are connected to the pull-down reference power supply.
  • the second terminal of the pull-down switch tube is used to output the second reference voltage NCS.
  • the pull-down power driving module 251 may include multiple pull-down inverters, wherein:
  • the control terminal of the pull-down inverter is connected to the pull-down driving power supply, the input terminal of the pull-down inverter is used to receive the pull-down control input signal, and the output terminal of the pull-down inverter is used to output the pull-down power supply driving signal.
  • the number of pull-down switch transistors is consistent with the number of pull-down inverters.
  • the output end of each pull-down inverter is connected to the control end of the corresponding pull-down switch tube, and is used to provide a pull-down power drive signal for the pull-down switch tube.
  • the pull-down power supply driving module 251 including three pull-down inverters, and the pull-down reference power supply module 252 including three pull-down switch transistors.
  • the pull-down power supply driving module 251 It may include a first pull-down inverter I4, a second pull-down inverter I5, and a third pull-down inverter I6.
  • the pull-down reference power module 252 may include a first pull-down switch M4, a second pull-down switch M5, and a third pull-down inverter I6.
  • the input terminal of the first pull-down inverter I4 is used to receive the fourth control input signal Vpd1, and the output terminal of the first pull-down inverter I4 is used to output the first pull-down power driving signal.
  • the input terminal of the second pull-down inverter I5 is used to receive the fifth control input signal Vpd2, and the output terminal of the second pull-down inverter I5 is used to output the second pull-down power drive signal Pdn2; the third pull-down inverter I6
  • the input terminal is used to receive the sixth control input signal Vpd3, the output terminal of the third pull-down inverter I6 is used to output the third pull-down power drive signal Pdn3;
  • the control terminal of the first pull-down inverter I4, the second pull-down inverter I4 The control end of the phase inverter I5 and the control end of the third pull-down inverter I6 are both connected to the pull-down driving power supply vncsgloc.
  • the control end of the first pull-down switch M4 is used to receive the first pull-down power drive signal Pdn1
  • the control end of the second pull-down switch M5 is used to receive the second pull-down power drive signal Pdn2.
  • the control end of the third pull-down switch M6 is used to receive the third pull-down power drive signal Pdn3; the first end of the first pull-down switch M4, the first end of the second pull-down switch M5 and the third pull-down switch M6
  • the first end is connected to output the second reference voltage NCS; the second end of the first pull-down switch M4, the second end of the second pull-down switch M5 and the second end of the third pull-down switch M6 are all connected to the pull-down switch. Refer to power supply VSS connection.
  • the pull-down driving power supply vncsgloc (ie, the fifth power supply described in the previous embodiment) is provided by the pull-down power switch module 27 .
  • the first end of the first switch N1 is connected to the fifth operating power supply vnoc, and the control end of the first switch N1 is connected to the first power enable sub-signal SCmosOcEn.
  • the first end of the second switch N2 is connected to the sixth operating power supply vncsgh
  • the control end of the second switch N2 is connected to the second power enable sub-signal SCmosSDTEn
  • the second end of the first switch N1 is connected to the second switch N1.
  • the second end of N2 is connected, and the first switch transistor N1 and the second switch transistor N2 are selectively connected to provide the pull-down driving power supply vncsgloc to the pull-down power driving module 251 .
  • the third working power supply vnocp and the fourth working power supply vpcsg are in different voltage ranges and/or have different temperature characteristics, so that different pull-ups can be provided for the pull-up power driving module 241 at different stages.
  • the driving power supply vpcsgloc; the fifth working power supply vnoc and the sixth working power supply vncsgh are in different voltage domains and/or have different temperature characteristics, so that different pull-down driving power supplies vncsgloc can be provided for the pull-down power driving module 251 at different stages; thus,
  • the pull-up/pull-down drive power supply can be adjusted according to the OC stage and the Develop stage, which can isolate the power supply noise in the OC stage and the Develop stage, effectively improving the SA noise suppression and reading and writing speed, and at the same time, it is more beneficial to sense margin optimization.
  • the sensitive amplifying circuit 30 may include a seventh switching transistor M7, an eighth switching transistor M8, a ninth switching transistor M8 Switch tube M9, tenth switch tube M10, eleventh switch tube M11, twelfth switch tube M12, thirteenth switch tube M13 and fourteenth switch tube M14.
  • the seventh switch tube M7, the eighth switch tube M8, the ninth switch tube M9 and the tenth switch tube M10 form an amplification module
  • the eleventh switch tube M11 and the twelfth switch tube M12 form an isolation control module.
  • the switch tube M13 and the fourteenth switch tube M14 form an offset elimination module.
  • the first end of the seventh switch M7 is connected to the first end of the eighth switch M8, and both are used to receive the first reference voltage PCS; the second end of the ninth switch M9 is connected to the tenth switch M10.
  • the second end of M7 is connected, and both are used to receive the second reference voltage NCS; the second end of the seventh switch M7, the control end of the eighth switch M8, the first end of the ninth switch M9, the twelfth switch
  • the second end of the transistor M12 and the first end of the thirteenth switch transistor M13 are both connected to the complementary readout bit line saBlb; the second end of the eighth switch transistor M8, the control end of the seventh switch transistor M7, and the tenth switch transistor
  • the first end of M10, the first end of the eleventh switch M11, and the second end of the fourteenth switch M14 are all connected to the readout bit line saBla; the second end of the eleventh switch M11, the thirteenth end of the eleventh switch M11 The second end of the switch
  • the first end of the twelfth switch M12, the first end of the fourteenth switch M14, and the tenth switch M10 The control terminals of are both connected to the complementary bit line Blb; the control terminals of the eleventh switch M11 and the twelfth switch M12 are both used to receive the isolation control signal Iso; the control terminals of the thirteenth switch M13 and the The control terminals of the fourteen switching tubes M14 are all used to receive the bias elimination enable signal NcEn.
  • the ninth switching tube M9, the tenth switching tube M10, the eleventh switching tube M11, the twelfth switching tube M12, the thirteenth switching tube M13 and the fourteenth switching tube M14 can be NMOS tubes.
  • the seventh switching tube M7 and the eighth switching tube M8 can be PMOS tubes.
  • the sensitive amplification circuit 30 is connected to the target memory cells through bit lines, and is connected to the complementary memory cells through complementary bit lines.
  • the potentials on the bit line and the complementary bit line are the same.
  • the target memory cell on the bit line is turned on, the target memory cell shares charges with the bit line, so that the potential on the bit line increases or decreases; the complementary memory cell on the complementary bit line is always off, so the complementary bit line The potential on it remains unchanged.
  • the potential on the bit line increases and decreases, the voltage difference between the bit line and the complementary bit line changes, so that some devices in the sensitive amplification circuit 30 are turned on to perform signal amplification processing.
  • the signal received by the sensitive amplifier circuit 30 from the bit line can be regarded as a signal to be processed, and the signal received by the sensitive amplifier circuit 30 from the complementary bit line can be regarded as a reference signal to be processed.
  • the eleventh switch M11 and the twelfth switch M12 are controlled to be in a conductive state according to the isolation control signal Iso, the transmission speed of the signal to be processed between the target storage unit and the amplification module can be accelerated.
  • the potential of the bit line or the complementary bit line can be quickly raised or lowered, thereby increasing the signal amplification speed.
  • the precharge module 212 may include a precharge switch M15, where:
  • the first end of the precharge switch M15 is connected to the precharge source VAD2, the control end of the precharge switch M15 is used to receive the precharge drive signal PreEQ, and the second end of the precharge switch M15 is connected to the readout bit line saBla.
  • the precharge driving module 211 may include a precharge inverter I7, where:
  • the input terminal of the precharge inverter I7 is used to receive the precharge enable signal eqN, the control terminal of the precharge inverter I7 is connected to the first power supply Vdleq, and the output terminal of the precharge inverter I7 is used to output the precharge drive.
  • the precharge module 212 can be controlled to perform precharge processing for the sensitive amplification circuit 30, so that the read bit line can be The voltage on saBla is precharged to a preset value.
  • the precharge module 212 may include a precharge switch M16, where:
  • the first end of the precharge switch M16 is connected to the readout bit line saBla.
  • the control end of the precharge switch M16 is used to receive the precharge drive signal EQ.
  • the second end of the precharge switch M16 is connected to the complementary readout bit line saBlb. connect.
  • the precharge driving module 211 may include a precharge inverter I8, where:
  • the input terminal of the precharge inverter I8 is used to receive the precharge enable signal eqN, the control terminal of the precharge inverter I8 is connected to the first power supply Vdleq, and the output terminal of the precharge inverter I8 is used to output the precharge drive.
  • the precharge module 212 can be controlled to perform precharge processing for the sensitive amplification circuit 30, so that the bit line can be read out.
  • the voltages of saBla and the complementary sense bit line saBlb are equalized.
  • the first power supply Vdleq, the third working power supply vnocp, and the fourth working power supply vpcsg , the fifth working power supply vnoc, and the sixth working power supply vncsgh are all different, so that the power supply noise at different stages can also be isolated to achieve the purpose of suppressing the power supply noise.
  • different power supplies mean that the power signals have different external sources, not that the specified voltage values must be different.
  • the precharge driving module 211 and the precharge module 212 in FIG. 12 and the precharge driving module 211 and the precharge module 212 in FIG. 13 may exist at the same time.
  • the precharge driving module 211 and the precharge module 212 in Figure 12 are configured to precharge the voltage on the read bit line saBla to a preset value
  • the precharge drive module 211 and the precharge module 212 in Figure 13 It is configured to achieve voltage equalization of the sense bit line saBla and the complementary sense bit line saBlb.
  • the embodiment of the present disclosure provides a control circuit 20, which is connected to a sensitive amplifier circuit, and the control circuit includes a precharge control module and a power control module.
  • the precharge control module includes a precharge drive module and a precharge module, and the precharge drive module is connected to the first power supply;
  • the power control module includes a power drive module and a reference power module, and the power drive module is connected to the second power supply, and The first power source is different from the second power source.
  • the precharge drive module and the power drive module use different power supplies, the power supply noise at different stages can be isolated, so that the SA noise suppression and read and write speeds are effectively improved, and the signal amplification process of the sensitive amplification circuit can be optimized, thereby improving Sensitive amplifier performance.
  • the control circuit 20 based on the previous embodiment is applied to a sense amplifier.
  • Figure 14 a schematic diagram of an application scenario of a sense amplifier provided by an embodiment of the present disclosure is shown. As shown in FIG. 14 , in this application scenario, there are bit line Bla, complementary bit line Blb, sense bit line saBla, complementary sense bit line saBlb and sense amplifier 51 .
  • the first memory cell 52 is provided on the existing bit line Bla
  • the second memory cell 53 is provided on the complementary bit line Blb.
  • both the first storage unit 52 and the second storage unit 53 can each be the object of the preset instruction.
  • the sense amplifier 51 may include a pull-up power supply control circuit 511 , a pull-down power supply control circuit 512 , a sense amplifier circuit 513 and a precharge control circuit 514 .
  • the pull-up power control circuit 511 includes a first pull-up inverter I1, a second pull-up inverter I2, a third pull-up inverter I3, a first pull-up switch M1, and a second pull-up switch M1.
  • the pull-down power control circuit 512 includes a first pull-down inverter I4, a second pull-down inverter I5, a third pull-down inverter I6, a first pull-down switch M4,
  • the second pull-down switch M5 and the third pull-down switch M6 the sensitive amplifier circuit 513 includes a seventh switch M7, an eighth switch M8, a ninth switch M9, a tenth switch M10, an eleventh switch M11,
  • the precharge control circuit 514 includes a precharge switch transistor M15 and a precharge inverter I7.
  • control terminal of the first pull-up inverter I1, the control terminal of the second pull-up inverter I2 and the control terminal of the third pull-up inverter I3 are all connected to the pull-up driving power supply Vpcsg.
  • the control end of the first pull-down inverter I4, the control end of the second pull-down inverter I5 and the control end of the third pull-down inverter I6 are all connected to the pull-down drive power supply Vncsgh, and the control end of the precharge inverter I7 is connected to Precharge drive power Vdleq connection.
  • the precharge driving power supply Vdleq and the pull-down driving power supply Vncsgh share the same power supply. There is noise at different stages of SA operation, which is detrimental to the sense margin; and because the temperature characteristics of the power supply are exactly the same at different stages, This makes the sensitive amplifier lack flexibility.
  • the precharge driving power supply Vdleq and the pull-down driving power supply Vncsgh use different power supplies, and the precharge driving power supply Vdleq and the pull-up driving power supply Vpcsg also use different power supplies. Power supply, thus can isolate the noise of the power bus (power bus) in different stages (such as OC stage and Develop stage).
  • Figure 15 shows a signal timing diagram of a sense amplifier provided by an embodiment of the present disclosure.
  • Iso refers to the aforementioned isolation control signal, which can be the first voltage value and the second voltage value
  • PreEQ refers to the aforementioned precharge driving signal
  • NcEn refers to the aforementioned bias elimination enable signal (also Can be represented by Nc, or called noise elimination signal)
  • SanEn refers to the aforementioned pull-down power drive signal (Pdn1, Pdn2, Pdn3, etc.)
  • SapEn refers to the aforementioned pull-up power drive signal (Pup1, Pup2, Pup3, etc.)
  • WL It refers to the word line turn-on signal.
  • the word line where the target memory unit is located is turned on, so that the target memory unit and the bit line are connected.
  • the target memory unit is turned off.
  • the word line where it is located is closed, so that the target memory cell and the bit line are not connected;
  • PCS/NCS refers to the first reference voltage signal/second reference voltage signal, and the first reference voltage signal has a fourth voltage value and a fifth voltage value, The first reference voltage signal has a fourth voltage value and a sixth voltage value, and the fourth voltage value is between the fifth voltage value and the sixth voltage value;
  • Bla refers to the bit line
  • Blb refers to the complementary bit line
  • saBla is refers to the sense bit line
  • saBlb refers to the complementary sense bit line.
  • the first level state represents a low level state
  • the second level state represents a high level state.
  • the isolation control signal Iso maintains the second voltage value
  • the precharge drive signal PreEQ and the offset elimination enable signal NcEn are in the second level state
  • the pull-up power drive signals SapEn are all in the first level state
  • the word line turn-on signal WL is in the first level state
  • the first reference voltage signal PCS/the second reference voltage signal NCS maintain the fourth voltage value
  • the bit lines Blb are all at the fourth voltage value; at this time, preliminary preparations are made for executing the user's operation instructions.
  • dVt in order to balance the voltages on both sides, after the precharge stage, it needs to enter the bias elimination stage. Under ideal circumstances, dVt tends to be as close to zero as possible.
  • the sensitive amplification circuit 513 enters the bias elimination stage from the standby stage.
  • the isolation control signal Iso changes from the second voltage to The value is adjusted to the first voltage value
  • the precharge drive signal PreEQ is adjusted from the second level state to the first level state
  • the pull-down power drive signal SanEn/pull-up power drive signal SapEn are adjusted from the first level state to the second level state.
  • the first reference voltage signal PCS changes from the fourth voltage value to the fifth voltage value
  • the second reference voltage signal NCS changes from the fourth voltage value to the sixth voltage value
  • the offset elimination enable signal NcEn remains The second level state is maintained, thereby performing offset elimination processing on the sensitive amplification circuit 513 .
  • the pull-down power drive signal SanEn/pull-up power drive signal SapEn switches to the first level state
  • the first reference voltage signal PCS and the second reference voltage signal NCS continue to be powered by the precharge control circuit 514 and return to the fourth voltage value.
  • the word line on signal WL changes to the second level state
  • the word line where the target memory cell is located is adjusted to the on state, so that the sensitive amplification circuit 513 enters the word line on phase, specifically the first In the Charge Sharing (CS) stage
  • the target memory unit for example, the first memory unit 52
  • the voltage of the bit line Bla decreases, that is, a signal to be processed is generated, and the complementary bit line Blb Form a reference signal to be processed.
  • the isolation control signal Iso maintains the first voltage value, so that the bit line Bla and the sense bit line saBla are not connected, and the complementary bit line Blb and the complementary sense bit line saBlb are not connected.
  • the precharge driving signal PreEQ, the offset elimination enable signal NcEn, and the pull-down power driving signal SanEn/pull-up power driving signal SapEn are all in the first level state.
  • the sensitive amplifier circuit 513 After ending the first charge sharing stage, the sensitive amplifier circuit 513 enters the second charge sharing stage.
  • the isolation control signal Iso maintains the second voltage value, so that the bit line Bla is connected to the readout bit line saBla, and the bit line Blb is connected to saBlb, so that the sensitive amplification circuit 513 combines the signal to be processed and the reference signal to be processed.
  • the processing signal is received at the internal node and the voltage of the read bit line saBla is reduced, which can be regarded as bit line Bla/complementary bit line Blb sharing read charges with the read bit line saBla/complementary read bit line saBlb.
  • other signals except the isolation control signal Iso maintain the voltage value of the previous stage.
  • the sensitive amplifier circuit 513 enters the amplification stage, and the pull-down power drive signal SanEn/pull-up power drive signal SapEn is adjusted from the first level state to the second level state, so that the first reference voltage signal PCS From the fourth voltage value to the fifth voltage value, the second reference voltage signal NCS changes from the fourth voltage value to the sixth voltage value, the voltage of the read bit line saBla decreases, causing the seventh switch M7 to turn on, and the first reference voltage signal NCS changes from the fourth voltage value to the sixth voltage value.
  • the voltage signal PCS raises the voltage of the complementary read bit line saBlb, causing the tenth switch M10 to turn on.
  • the second reference voltage signal NCS pulls the voltage of the read bit line saBla low, so that the sensitive amplifier circuit 513 can operate according to the first reference
  • the voltage signal PCS/the second reference voltage signal NCS amplifies the signal to be processed (the signal of the bit line Bla)/the reference signal to be processed (the signal of the complementary bit line Blb), and the isolation control signal Iso still maintains the second voltage value to complete the processing
  • the signal on the processing signal (signal of bit line Bla)/reference signal to be processed (complementary bit line Blb) is amplified.
  • the voltage of the bit line Bla in the first amplification stage will be raised. Since the isolation control signal Iso is at the second voltage value, the bit line Bla/complementary bit line can be suppressed.
  • the rising rate on Blb reduces the noise on the bit line Bla/complementary bit line Blb, but the signal on the sense bit line saBla/complementary sense bit line saBlb inside the sensitive amplifier circuit 513 can quickly reach the high reference potential/low reference potential.
  • the word line on signal WL changes to the first level state
  • the word line where the target memory cell is located is adjusted to the off state.
  • the sensitive amplification circuit 513 enters the word line off stage and isolates the control signal Iso. Maintaining the second voltage value, the precharge drive signal PreEQ and the offset elimination enable signal NcEn maintain the first level state; in addition, during this stage, the pull-down power drive signal SanEn/pull-up power drive signal SapEn will be driven by the second voltage level.
  • the flat state is adjusted to the first level state.
  • the sensitive amplifier circuit 513 enters the precharge stage, and the precharge drive signal PreEQ and the offset elimination enable signal NcEn are adjusted to the second level state.
  • the first reference voltage signal PCS/the second reference voltage signal NCS will After returning to the fourth voltage value, the bit line Bla/complementary bit line Blb and the sense bit line saBla/complementary sense bit line saBlb will return to the same voltage value.
  • the sensitive amplifier circuit 513 After ending the precharge phase, the sensitive amplifier circuit 513 enters the idle phase again to prepare for the next operation.
  • the precharge driving signal PreEQ and the offset elimination enable signal NcEn when they are in the second level state, their corresponding voltage values may be provided by the precharge driving power supply Vdleq;
  • the pull-up power driving signal SapEn when it is in the second level state, its corresponding voltage value may be provided by the pull-up driving power supply Vpcsg (specifically, the third operating power supply vnocp and the fourth operating power supply vpcsg).
  • the pull-down power supply driving signal SanEn when it is in the second level state, its corresponding voltage value may be provided by the pull-down driving power supply Vncsgh (specifically, the fifth working power supply vnoc and the sixth working power supply vncsgh);
  • the pull-down driving power supply Vncsgh specifically, the fifth working power supply vnoc and the sixth working power supply vncsgh
  • the first reference voltage signal PCS/second reference voltage signal NCS bit line Bla/complementary bit line Blb
  • the lowest value is the ground signal, which may be provided by the pull-down reference power supply VSS.
  • FIG. 16 shows a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • the semiconductor memory includes a control circuit, a plurality of memory blocks, and a sensitive amplification circuit module arranged between two adjacent memory blocks.
  • a switch module is arranged between two adjacent sensitive amplification modules.
  • the control circuit includes a precharge control module and a power control module
  • the sensitive amplification module storage block includes a sensitive amplification circuit and a precharge control module
  • the switch module includes a power control module, in which:
  • the precharge control module may include a precharge drive module and a precharge module, and the precharge drive module is connected to the first power supply, and is used to provide a precharge drive signal to the precharge module through the precharge drive module, and control the precharge drive module according to the precharge drive signal.
  • the charging module performs pre-charging processing for the sensitive amplifier circuit;
  • the power control module may include a power drive module and a reference power module, and the power drive module is connected to the second power supply, and is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to be a sensitive amplifier circuit according to the power drive signal.
  • a reference voltage is provided; wherein the first power supply and the second power supply are different.
  • a sensitive amplification module including a sensitive amplification circuit, a precharge module and a precharge drive module is provided between adjacent memory blocks; in the first direction
  • row decoders are arranged between adjacent memory blocks, and switch modules are arranged between adjacent sensitive amplification modules.
  • the switch modules are also located between the adjacent row decoders.
  • the storage block may be a plurality of storage sections (sections) divided by the storage bank in the first direction, that is, each storage block is a storage section.
  • the semiconductor memory may further include the power switch module described in the previous embodiment and the power switch control module described in the previous embodiment, wherein: the power switch module and the power switch control module are both located in the switch module; or , the power switch module is located in the switch module, and the power switch control module is located in the peripheral area of the semiconductor memory; or, the power switch module and the power switch control module are both located in the peripheral area of the semiconductor memory.
  • the power switch module and the power switch control module are both located in the switch module.
  • the above overall control refers to the same power switch control module configured to control the power switch modules corresponding to multiple memory blocks or multiple memory banks, reducing the number of power switch control modules, and the same power switch module Control the power conduction corresponding to multiple memory blocks or multiple memory banks. Further, when the power switch module is disposed in the peripheral area, the corresponding connected power supply is generated in the peripheral area.
  • Embodiments of the present disclosure provide a control circuit and a semiconductor memory.
  • the control circuit is connected to a sensitive amplifier circuit, and the control circuit includes a precharge control module and a power supply control module.
  • the precharge control module includes a precharge drive module and a precharge control module.
  • the control module includes a power drive module and a reference power module, and the power drive module is connected to the second power supply, and is used to provide a power drive signal for the reference power module through the power drive module, and control the reference power module to provide a reference for the sensitive amplification circuit according to the power drive signal. Voltage; wherein the first power supply and the second power supply are different.
  • the precharge drive module and the power drive module use different power supplies, the power supply noise at different stages can be isolated, so that the SA noise suppression and read and write speeds are effectively improved, and the signal amplification process of the sensitive amplification circuit can be optimized, thereby improving Sensitive amplifier performance.

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Abstract

本公开实施例提供了一种控制电路以及半导体存储器，控制电路与灵敏放大电路连接，且该控制电路包括预充控制模块和电源控制模块，其中：预充控制模块包括预充驱动模块和预充模块，且预充驱动模块与第一电源连接，用于通过预充驱动模块为预充模块提供预充驱动信号，预充驱动信号用于控制预充模块为灵敏放大电路进行预充处理；电源控制模块包括电源驱动模块和参考电源模块，且电源驱动模块与第二电源连接，用于通过电源驱动模块为参考电源模块提供电源驱动信号，根据电源驱动信号控制参考电源模块为灵敏放大电路提供参考电压。

Description

一种控制电路以及半导体存储器
相关申请的交叉引用
本公开基于申请号为202211073956.5、申请日为2022年09月02日、发明名称为“一种控制电路以及半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种控制电路以及半导体存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。在数据读取的过程中，每个存储单元的读出数据信号依次经由本地数据线、全局数据线和数据总线进行读出；反之，在数据写入的过程中，则写入数据信号依次经由数据总线、全局数据线和本地数据线向存储单元写入。
目前，存储单元和本地数据线之间设置灵敏放大器(Sense Amplifier，SA)，为提高存储单元内容的信号质量，存储数据需要经过该灵敏放大器放大后读出或写入。但是该灵敏放大器的不同工作阶段容易引入噪声，使得相关技术中数据信号的放大过程仍有不足，导致灵敏放大器的性能有待于提高。
发明内容
本公开提供了一种控制电路以及半导体存储器，能够有效抑制不同阶段的电源噪声，提高读写速度，进而改善灵敏放大器的性能。
第一方面，本公开实施例提供了一种控制电路，该控制电路与灵敏放大电路连接，且控制电路包括预充控制模块和电源控制模块，其中：
预充控制模块包括预充驱动模块和预充模块，且预充驱动模块与第一电源连接，用于通过预充驱动模块为预充模块提供预充驱动信号，预充驱动信号用于控制预充模块为灵敏放大电路进行预充处理；
电源控制模块包括电源驱动模块和参考电源模块，且电源驱动模块与第二电源连接，用于通过电源驱动模块为参考电源模块提供电源驱动信号，根据电源驱动信号控制参考电源模块为灵敏放大电路提供参考电压；其中，第一电源与第二电源不同。
在一些实施例中，该控制电路还包括电源开关模块，且电源开关模块与第三电源连接，其中：电源开关模块，配置为接收电源使能信号，根据电源使能信号控制电源开关模块内部的开关管状态，以通过第三电源向为电源驱动模块提供第二电源，第一电源与第三电源不同。
在一些实施例中，第三电源包括第一工作电源和第二工作电源，第一工作电源与第二工作电源处于不同电压域和/或具有不同的温度特性，电源使能信号包括第一电源使能子信号和第二电源使能子信号；电源开关模块包括第一开关管和第二开关管，其中：第一开关管的第一端与第一工作电源连接，第一开关管的控制端与第一电源使能子信号连接，第二开关管的第一端与第二工作电源连接，第二开关管的控制端与第二电源使能子信号连接，第一开关管的第二端与第二开关管的第二端连接，且第一开关管与第二开关管择一导通，用于为电源驱动模块提供第二电源。
在一些实施例中，在灵敏放大电路工作于偏置消除阶段时，第一开关管导通，以通过第一工作电源为电源驱动模块提供第二电源；以及在灵敏放大电路工作于信号放大阶段时，第二开关管导通，以通过第二工作电源为电源驱动模块提供第二电源。
在一些实施例中，电源开关模块至少包括下述其中一项：上拉电源开关模块和下拉电源开关模块；其中，上拉电源开关模块包括的第一开关管和第二开关管为PMOS管，下拉电源开关模块包括的第一开关管和第二开关管为NMOS管，且上拉电源开关模块连接的第一工作电源与下拉电源开关模块连接的第一工作电源不同，上拉电源开关模块连接的第二工作电源与下拉电源开关模块连接的第二工作电源不同。
在一些实施例中，当电源开关模块的数量为至少一个时，该控制电路还包括电源开关控制模块，其中：电源开关控制模块，配置为接收偏置消除使能信号和目标电源使能信号，根据偏置消除使能信号和目标电源使能信号生成至少一组电源使能信号；其中，每一组电源使能信号均包括第一电源使能子信号和第二电源使能子信号，且至少一组电源使能信号与至少一个电源开关模块具有对应关系。
在一些实施例中，目标电源使能信号包括第一目标电源使能信号和第二目标电源使能信号，电源开关控制模块包括第一逻辑控制模块和第二逻辑控制模块，其中：第一逻辑控制模块，配置为接收偏置消除使能信号和第二目标电源使能信号，输出至少一个第一电源使能子信号；第二逻辑控制模块，配置为接收偏置消除使能信号和第一目标电源使能信号，输出至少一个第二电源使能子信号；其中，第一目标电源使能信号与第一电源使能子信号具有相同的有效状态，第二目标电源使能信号与第二电源使能子信号具有相同的有效状态。
在一些实施例中，第一逻辑控制模块包括第一非门、第一与非门、第一电平转换模块和第二非门，其中：第一非门的输入端用于接收第二目标电源使能信号，第一非门的输出端与第一与非门的第一输入端连接，第一与非门的第二输入端用于接收偏置消除使能信号，第一与非门的输出端与第一电平转换模块的输入端连接，第一电平转换模块的输出端与第二非门的输入端连接，第二非门的输出端用于输出至少一个第一电源使能子信号；第二逻辑控制模块包括第一或非门、第三非门、第二电平切换模块和第四非门，其中：第一或非门的第一输入端用于接收偏置消除使能信号，第一或非门的第二输入端用于接收第一目标电源使能信号，第一或非门的输出端与第三非门的输入端连接，第三非门的输出端与第二电平转换模块的输入端连接，第二电平转换模块的输出端与第四非门的输入端连接，第四非门的输出端用于输出至少一个第二电源使能子信号。
在一些实施例中，电源开关控制模块还包括第五非门，其中：第五非门的输入端用于接收偏置消除反相信号，第五非门的输出端用于输出偏置消除使能信号。
在一些实施例中，预充模块包括预充开关管，其中：预充开关管的第一端与预充电源连接，预充开关管的控制端用于接收预充驱动信号，预充开关管的第二端与读出位线连接。
在一些实施例中，预充模块包括预充开关管，其中：预充开关管的第一端与读出位线连接，预充开关管的控制端用于接收预充驱动信号，预充开关管的第二端与互补读出位线连接。
在一些实施例中，预充驱动模块包括预充反相器，其中：预充反相器的输入端用于接收预充使能信号，预充反相器的控制端与第一电源连接，预充反相器的输出端用于输出预充驱动信号。
第二方面，本公开实施例提供了一种半导体存储器，该半导体存储器包括控制电路、多个存储块以及设置在相邻两个存储块之间的灵敏放大模块，相邻两个灵敏放大模块之间设置有开关模块，控制电路包括预充控制模块和电源控制模块，灵敏放大模块包括灵敏放大电路和预充控制模块，开关模块包括电源控制模块，其中：
预充控制模块包括预充驱动模块和预充模块，且预充驱动模块与第一电源连接，用于通过预充驱动模块为预充模块提供预充驱动信号，根据预充驱动信号控制预充模块为灵敏放大电路进行预充处理；
电源控制模块包括电源驱动模块和参考电源模块，且电源驱动模块与第二电源连接，用于通过电源驱动模块为参考电源模块提供电源驱动信号，根据电源驱动信号控制参考电源模块为灵敏放大电路提供参考电压；其中，第一电源与第二电源不同。
在一些实施例中，该半导体存储器还包括如第一方面的电源开关模块和如第一方面的电源开关控制模块，其中：电源开关模块和电源开关控制模块均位于开关模块中；或者，电源开关模块位于开关模块中，电源开关控制模块位于半导体存储器的外围区域；或者，电源开关模块和电源开关控制模块均位于半导体存储器的外围区域。
本公开实施例提供了一种控制电路以及半导体存储器，控制电路与灵敏放大电路连接，且该控制电路包括预充控制模块和电源控制模块，其中：预充控制模块包括预充驱动模块和预充模块，且预充驱动模块与第一电源连接，用于通过预充驱动模块为预充模块提供预充驱动信号，预充驱动信号用于控制预充模块为灵敏放大电路进行预充处理；电源控制模块包括电源驱动模块和参考电源模 块，且电源驱动模块与第二电源连接，用于通过电源驱动模块为参考电源模块提供电源驱动信号，根据电源驱动信号控制参考电源模块为灵敏放大电路提供参考电压；其中，第一电源与第二电源不同。这样，由于预充驱动模块与电源驱动模块使用的电源不同，从而可以隔离不同阶段的电源噪声，使得SA噪声抑制和读写速度均得到有效提高，能够优化灵敏放大电路的信号放大过程，进而改善灵敏放大器的性能。
附图说明
图1为一种灵敏放大器的应用场景示意图；
图2为本公开实施例提供的一种控制电路的组成结构示意图一；
图3为本公开实施例提供的一种控制电路的组成结构示意图二；
图4为本公开实施例提供的一种控制电路的组成结构示意图三；
图5为本公开实施例提供的一种控制电路的组成结构示意图四；
图6为本公开实施例提供的一种控制电路的组成结构示意图五；
图7为本公开实施例提供的一种电源开关控制模块的组成结构示意图一；
图8为本公开实施例提供的一种电源开关控制模块的组成结构示意图二；
图9为本公开实施例提供的一种上拉电源控制模块的组成结构示意图；
图10为本公开实施例提供的一种下拉电源控制模块的组成结构示意图；
图11为本公开实施例提供的一种灵敏放大电路的组成结构示意图一；
图12为本公开实施例提供的一种灵敏放大电路的组成结构示意图二；
图13为本公开实施例提供的一种灵敏放大电路的组成结构示意图三；
图14为本公开实施例提供的一种灵敏放大器的应用场景示意图；
图15为本公开实施例提供的一种灵敏放大器的信号时序示意图；
图16为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
还需要指出，本公开实施例所涉及信号使用的高电平和低电平指的是信号的逻辑电平。信号具有高电平与其具有低电平时存在不同。例如，高电平可以对应于具有第一电压的信号，而低电平可以对应于具有第二电压的信号。在一些实施例中，第一电压大于第二电压。此外，信号的逻辑电平可以与所描述的逻辑电平不同或相反。例如，被描述为具有逻辑“高”电平的信号可以替选地具有逻辑“低”电平，并且被描述为具有逻辑“低”电平的信号可以替选地具有逻辑“高”电平。
可以理解地，在DRAM的工作过程中，需要利用灵敏放大器实现多种操作过程中的信号放大。参见图1，其示出了一种灵敏放大器的应用场景示意图。如图1所示，该应用场景可以包括第一信号线11、第二信号线12、灵敏放大器13。其中，
第一信号线11上具有第一开关Sx和第一电容C1，用于传入待处理信号Vin+；第二信号线12上具有第二开关Sy和第二电容C2，用于传入参考待处理信号Vin-；灵敏放大器13用于对待处理信号Vin+及参考待处理信号Vin-进行放大，待处理信号Vin+与参考待处理信号Vin-之间具有ΔVin的电压差。其中，第一开关Sx和第二开关Sy用于控制第一信号线11和第二信号线12与灵敏放大器 13的连接通断，第一电容C1和第二电容C2用于对待处理信号Vin+和参考待处理信号Vin-进行滤波，减弱其高频特性。
具体地，灵敏放大器13可以包括第一开关管M1、第二开关管M2、第三开关管M3和第四开关管M4。第一开关管M1的控制端、第二开关管M2的控制端、第三开关管M3的第一端、第四开关管M4的第一端均与参考待处理信号Vin-连接，第一开关管M1的第一端、第二开关管M2的第一端、第三开关管M3的控制端、第四开关管M4的控制端均与所述待处理信号Vin+连接。该应用场景中还存在第五开关管M5和第六开关管M6，第五开关管135的控制端与第一控制信号SAP连接，第五开关管M5的第一端与电源信号VBLH连接，第五开关管M5的第二端与第一开关管M1的第二端和第三开关管M3的第二端连接，形成第一参考信号端，用PCS表示；第六开关管M6的控制端与第二控制信号SAN连接，第六开关管M6的第一端与地信号GND连接，第六开关管M6的第二端和第二开关管M2的第二端和第四开关管M4的第二端连接，形成第二参考信号端，用NCS表示。
另外，在第一信号线11和第二信号线12之间还可以存在预充电路，且第三开关管M3的第二端和第四开关管M4的第二端之间也可以存在预充电路，用于对第一参考信号端和第二参考信号端进行预充处理。
需要说明的是，在图1中，第一开关管M1、第三开关管M2、第五开关管M5为P型场效应管(PMOSFET，简称为PMOS管)；第二开关管M2、第四开关管M4和第六开关管M6为N型场效应管(NMOSFET，简称为NMOS管)。
还需要说明的是，在图1中，第一开关管M1和第二开关管M2组成一个反相器INV1，第三开关管M3和第四开关管M4组成另一个反相器INV2，它们输入与输出分别相连，从而形成一个锁存器。其中，电源信号VBLH为灵敏放大器13提供电源，由第五开关管M5与灵敏放大器13相连接；地信号GND为灵敏放大器的地线，由第六开关管M6与灵敏放大器13相连接。
在本公开实施例中，该工作过程可分为三个阶段：预充(Precharge，EQ)阶段、小信号输入阶段和信号放大阶段。其中，在EQ阶段，预充电路为灵敏放大器13进行预充电；在小信号输入阶段，小信号可以从图1中的Sx或者Sy输入；在信号放大阶段，可以通过灵敏放大器13进行信号放大。
在相关技术中，存储数据需要经过灵敏放大器放大后读出或写入，以提高存储单元内容的信号质量。但是传统灵敏放大器中预充电路和下拉参考电路共用一个电源，在SA的不同工作阶段容易引入噪声，对灵敏度裕量(sense margin)不利，从而影响数据信号的放大过程，导致灵敏放大器的性能有待于提高。基于此，本公开实施例提供了一种控制电路，该控制电路与灵敏放大电路连接，而且该控制电路包括预充控制模块和电源控制模块，其中：预充控制模块包括预充驱动模块和预充模块，且预充驱动模块与第一电源连接，用于通过预充驱动模块为预充模块提供预充驱动信号，预充驱动信号用于控制预充模块为灵敏放大电路进行预充处理；电源控制模块包括电源驱动模块和参考电源模块，且电源驱动模块与第二电源连接，用于通过电源驱动模块为参考电源模块提供电源驱动信号，根据电源驱动信号控制参考电源模块为灵敏放大电路提供参考电压；其中，第一电源与第二电源不同。这样，由于预充驱动模块与电源驱动模块使用的电源不同，从而可以隔离不同阶段的电源噪声，使得SA噪声抑制和读写速度均得到有效提高，能够优化灵敏放大电路的信号放大过程；同时根据第一电源与第二电源的不同，还能够优化sense margin，进而改善灵敏放大器的性能。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图2，其示出了本公开实施例提供的一种控制电路的组成结构示意图。如图2所示，该控制电路20可以包括预充控制模块21和电源控制模块22，其中：
预充控制模块21包括预充驱动模块211和预充模块212，且预充驱动模块211与第一电源连接，用于通过预充驱动模块211为预充模块212提供预充驱动信号，预充驱动信号用于控制预充模块212为灵敏放大电路进行预充处理；
电源控制模块22包括电源驱动模块221和参考电源模块222，且电源驱动模块221与第二电源连接，用于通过电源驱动模块221为参考电源模块222提供电源驱动信号，根据电源驱动信号控制参考电源模块222为灵敏放大电路提供参考电压；其中，第一电源与第二电源不同。
需要说明的是，在本公开实施例中，控制电路20可以应用在多种信号放大的场景中，例如DRAM中的灵敏放大器。
还需要说明的是，在图2中，第一电源可以用VDD1表示，第二电源可以用VDD2表示。另外，控制电路20可以与灵敏放大电路30连接。具体地，在预充阶段，通过预充驱动模块211为预充模块212提供预充驱动信号，以实现该预充模块212为灵敏放大电路30进行预充处理；在信号放大阶段，通过电源驱动模块221为参考电源模块222提供电源驱动信号，以实现参考电源模块222为灵 敏放大电路提供参考电压，从而能够进行信号放大处理。
可以理解地，对于第二电源来说，其可以是直接提供的外部电源，也可以是由外部电源经过相关处理后得到的。在一些实施例中，在图2所示控制电路20的基础上，参见图3，该控制电路20还可以包括电源开关模块23，且电源开关模块23与第三电源连接，其中：
电源开关模块23，配置为接收电源使能信号，根据电源使能信号控制电源开关模块内部的开关管状态，以通过第三电源向为电源驱动模块221提供第二电源，第一电源与第三电源不同。
需要说明的是，在本公开实施例中，第三电源可以用VDD3表示。对于第二电源而言，这时候可以是由第三电源经过电源开关模块23的相关处理得到的，从而能够实现在不同阶段为电源驱动模块221提供不同的第二电源，达到降低电源噪声的目的。也就是说，电源开关模块23具有电压调节功能，电源开关模块23可以在第三电源VDD3不变的条件下输出不同的第二电源。
并列的，为了更好地实现电源开关模块23在不同阶段输出不同的第二电源，在一些实施例中，第三电源可以包括第一工作电源和第二工作电源，而且第一工作电源与第二工作电源处于不同电压域和/或具有不同的温度特性。其中，第一工作电源与第二工作电源不同，第一工作电源用于为电源驱动模块221提供第一阶段所需的工作电源，第二工作电源用于为电源驱动模块221提供第二阶段所需的工作电源。
还需要说明的是，在第三电源包括第一工作电源和第二工作电源时，电源使能信号可以包括第一电源使能子信号和第二电源使能子信号。相应地，在一些实施例中，在图3所示控制电路20的基础上，参见图4，电源开关模块23可以包括第一开关管Q1和第二开关管Q2；其中，第一开关管Q1的第一端与第一工作电源连接，第一开关管Q1的控制端与第一电源使能子信号连接，第二开关管Q2的第一端与第二工作电源连接，第二开关管Q2的控制端与第二电源使能子信号连接，第一开关管Q1的第二端与第二开关管Q2的第二端连接，且第一开关管Q1与第二开关管Q2择一导通，用于为电源驱动模块221提供第二电源。
需要说明的是，在本公开实施例中，第一开关管Q1与第二开关管Q2不会同时导通的。其中，在不同阶段，第一开关管Q1与第二开关管Q2择一导通，从而能够实现为电源驱动模块221提供不同的第二电源。在一些实施例中，第一电源使能子信号还用于控制第一开关管Q1的导通程度，第二电源使能子信号还用于控制第二开关管Q2的导通程度，以调节第二电源VDD2的大小。
具体来说，在本公开实施例中，如果灵敏放大电路30工作于第一阶段，那么对于电源开关模块23来说，根据第一电源使能子信号控制第一开关管Q1处于导通状态，根据第二电源使能子信号控制第二开关管Q2处于关断状态，以通过第一工作电源为电源驱动模块221提供第二电源；如果灵敏放大电路30工作于第二阶段，那么对于电源开关模块23来说，根据第一电源使能子信号控制第一开关管Q1处于关断状态，根据第二电源使能子信号控制第二开关管Q2处于导通状态，以通过第二工作电源为电源驱动模块221提供第二电源。
还需要说明的是，在本公开实施例中，第一阶段可以为偏置消除(Offset Cancel，OC或称为NC)阶段，第二阶段可以为信号放大(Develop)阶段。因此，在一些实施例中，在灵敏放大电路30工作于偏置消除阶段时，第一开关管Q1导通，以通过第一工作电源为电源驱动模块221提供第二电源；在灵敏放大电路30工作于信号放大阶段时，第二开关管Q2导通，以通过第二工作电源为电源驱动模块221提供第二电源。
在本公开实施例中，第二电源根据OC阶段和Develop阶段进行调节，能够改善SA噪声抑制、读写速度控制以及sense margin优化等。另外，在调节过程中，对于OC阶段的第一工作电源和Develop阶段的第二工作电源，两者处于不同电压域和/或具有不同的温度特性；即电源驱动模块221所需的第二电源可以根据OC阶段和Develop阶段进行分开，而且OC阶段和Develop阶段的工作电源可以分别调节对应的电压范围(voltage trim range)和温度特性，从而对灵敏放大电路30的sense margin优化更有利。
还可以理解地，在本公开实施例中，电源控制模块22可以是上拉(pull-up)电源控制模块，也可以是下拉(pull-down)电源控制模块。在一些实施例中，对于电源控制模块22而言，在图2所示控制电路20的基础上，参见图5，该控制电路20还可以包括上拉电源控制模块24和下拉电源控制模块25，其中：
上拉电源控制模块24包括上拉电源驱动模块241和上拉参考电源模块242，且上拉电源驱动模块241与第四电源连接，用于通过上拉电源驱动模块241为上拉参考电源模块242提供上拉电源驱动信号，根据上拉电源驱动信号控制上拉参考电源模块242为灵敏放大电路30提供第一参考电压；
下拉电源控制模块25包括下拉电源驱动模块251和下拉参考电源模块252，且下拉电源驱动模 块251与第五电源连接，用于通过下拉电源驱动模块251为下拉参考电源模块252提供下拉电源驱动信号，根据下拉电源驱动信号控制下拉参考电源模块252为灵敏放大电路30提供第二参考电压。
在本公开实施例中，第一电源与第四电源不同，而且第一电源与第五电源也不同。其中，第四电源可以用VDD4表示，第五电源可以用VDD5表示。另外，上拉电源控制模块24可以是图2中的电源控制模块22，或者下拉电源控制模块25可以是图2中的电源控制模块22，即上拉电源控制模块24和下拉电源控制模块25的内部结构均与电源控制模块22的内部结构相同。
也就是说，在控制电路20包括电源控制模块22的数量为两个时，这两个电源控制模块可以称为上拉电源控制模块24和下拉电源控制模块25。其中，由于第二电源可以是由电源开关模块及其连接的第一工作电源和第二工作电源产生的，相应地，对于上拉电源控制模块24来说，第四电源也可以是由电源开关模块及其连接的第一工作电源与第二工作电源产生的；对于下拉电源控制模块25来说，第五电源也可以是由电源开关模块及其连接的第一工作电源与第二工作电源产生的。
如此，在电源控制模块22可以为上拉电源控制模块和/或下拉电源控制模块的情况下，在一些实施例中，电源开关模块23至少包括下述其中一项：上拉电源开关模块和下拉电源开关模块；
其中，上拉电源开关模块包括的第一开关管和第二开关管可以为PMOS管，下拉电源开关模块包括的第一开关管和第二开关管可以为NMOS管，而且上拉电源开关模块连接的第一工作电源与下拉电源开关模块连接的第一工作电源不同，上拉电源开关模块连接的第二工作电源与下拉电源开关模块连接的第二工作电源不同。
在本公开实施例中，具体参见图5，该控制电路20还可以包括上拉电源开关模块26和下拉电源开关模块27。其中，上拉电源开关模块26与上拉电源驱动模块241连接，用于为上拉电源驱动模块241提供第四电源VDD4，以使上拉电源驱动模块241能够驱动上拉参考电源模块242，进而为灵敏放大电路30提供第一参考电压；下拉电源开关模块27与下拉电源驱动模块251连接，用于为下拉电源驱动模块251提供第五电源VDD5，以使下拉电源驱动模块251能够驱动下拉参考电源模块252，进而为灵敏放大电路30提供第二参考电压。
还需要说明的是，在图5中，上拉电源开关模块26可以包括第一开关管P1和第二开关管P2，第一开关管P1的第一端与第三工作电源vnocp连接，第一开关管P1的控制端与第一电源使能子信号连接，第二开关管P2的第一端与第四工作电源vpcsg连接，第二开关管P2的控制端与第二电源使能子信号连接，第一开关管P1的第二端与第二开关管P2的第二端连接，且第一开关管P1与第二开关管P2择一导通，用于为上拉电源驱动模块241提供第四电源VDD4。
下拉电源开关模块27可以包括第一开关管N1和第二开关管N2，第一开关管N1的第一端与第五工作电源vnoc连接，第一开关管N1的控制端与第一电源使能子信号连接，第二开关管N2的第一端与第六工作电源vncsgh连接，第二开关管N2的控制端与第二电源使能子信号连接，第一开关管N1的第二端与第二开关管N2的第二端连接，且第一开关管N1与第二开关管N2择一导通，用于为下拉电源驱动模块251提供第五电源VDD5。
需要说明的是，在本公开实施例中，对于上拉电源开关模块26来说，在OC阶段，第一开关管P1导通，以通过第三工作电源vnocp为上拉电源驱动模块241提供第二电源；在信号放大阶段，第二开关管P2导通，以通过第四工作电源vpcsg为上拉电源驱动模块241提供第二电源(具体是第四电源)。由于第三工作电源vnocp与第四工作电源vpcsg处于不同电压域和/或具有不同的温度特性，从而在不同阶段能够为上拉电源驱动模块241提供不同的第二电源；对于下拉电源开关模块27来说，在OC阶段，第一开关管N1导通，以通过第五工作电源vnoc为下拉电源驱动模块251提供第二电源；在信号放大阶段，第二开关管N2导通，以通过第六工作电源vncsgh为下拉电源驱动模块251提供第二电源(具体是第五电源)。由于第五工作电源vnoc与第六工作电源vncsgh处于不同电压域和/或具有不同的温度特性，从而在不同阶段还能够为下拉电源驱动模块251提供不同的第二电源。
这样，无论是上拉电源驱动模块241还是下拉电源驱动模块251所需的第二电源都可以根据OC阶段和Develop阶段进行分开，而且OC阶段和Develop阶段的工作电源可以分别调节对应的电压范围(voltage trim range)和温度特性，从而能够改善SA噪声抑制、读写速度控制以及sense margin优化等，最终提升灵敏放大器的性能。
还可以理解地，当电源开关模块23的数量为至少一个时，这时候所需要的电源使能信号对应为至少一组。因此，在图5所示控制电路20的基础上，在一些实施例中，参见图6，该控制电路20还可以包括电源开关控制模块28，其中：
电源开关控制模块28，配置为接收偏置消除使能信号和目标电源使能信号，根据偏置消除使能信号和目标电源使能信号生成至少一组电源使能信号；其中，每一组电源使能信号均包括第一电源 使能子信号和第二电源使能子信号，且至少一组电源使能信号与至少一个电源开关模块具有对应关系。
需要说明的是，在图6中，以上拉电源开关模块26和下拉电源开关模块27为例，这时候电源开关控制模块28在接收到偏置消除使能信号和目标电源使能信号之后，可以输出两组电源使能信号，其中一组电源使能信号发送到上拉电源开关模块26，另一组电源使能信号发送到下拉电源开关模块27。
还需要说明的是，在本公开实施例中，目标电源使能信号可以包括第一目标电源使能信号和第二目标电源使能信号。相应地，在一些实施例中，参见图7，电源开关控制模块28可以包括第一逻辑控制模块281和第二逻辑控制模块282，其中：
第一逻辑控制模块281，配置为接收偏置消除使能信号和第二目标电源使能信号，输出至少一个第一电源使能子信号；
第二逻辑控制模块282，配置为接收偏置消除使能信号和第一目标电源使能信号，输出至少一个第二电源使能子信号。
在这里，第一目标电源使能信号与第一电源使能子信号具有相同的有效状态，第二目标电源使能信号与第二电源使能子信号具有相同的有效状态。也就是说，第一目标电源使能信号与第一电源使能子信号的有效电平对应的是同一运行状态，第二目标电源使能信号与第二电源使能子信号的有效电平对应的是同一运行状态。
还需要说明的是，电源开关控制模块28可以输出至少一组电源使能信号，而电源使能信号的组数与电源开关模块23的数量具有关联关系。具体地，如果控制电路20中包括有上拉电源开关模块和下拉电源开关模块等两个电源开关模块，那么电源开关控制模块28需要输出两组电源使能信号，每一组电源使能信号对应连接一个电源开关模块，如图6中的上拉电源开关模块26连接一组电源使能信号，下拉电源开关模块27连接另一组电源使能信号。
在一些实施例中，如图7所示，第一逻辑控制模块281可以包括第一非门U1、第一与非门U2、第一电平转换模块U3和第二非门U4，其中：
第一非门U1的输入端用于接收第二目标电源使能信号，第一非门U1的输出端与第一与非门U2的第一输入端连接，第一与非门U2的第二输入端用于接收偏置消除使能信号，第一与非门U2的输出端与第一电平转换模块U3的输入端连接，第一电平转换模块U3的输出端与第二非门U4的输入端连接，第二非门U4的输出端用于输出至少一个第一电源使能子信号；
第二逻辑控制模块282可以包括第一或非门U5、第三非门U6、第二电平切换模块U7和第四非门U8，其中：
第一或非门U5的第一输入端用于接收偏置消除使能信号，第一或非门U5的第二输入端用于接收第一目标电源使能信号，第一或非门U5的输出端与第三非门U6的输入端连接，第三非门U6的输出端与第二电平转换模块U7的输入端连接，第二电平转换模块U7的输出端与第四非门U8的输入端连接，第四非门U8的输出端用于输出至少一个第二电源使能子信号。
需要说明的是，在本公开实施例中，第一电平切换模块U3或者第二电平切换模块U7可以实现电压域切换(Level shift)，不同的电压域可以对应不同的一组电源使能信号；在电源开关控制模块28输出至少一组电源使能信号之后，可以将这些电源使能信号发送到不同的电源开关模块。
还需要说明的是，对于电源开关控制模块28而言，在图7所示电源开关控制模块28的基础上，在一些实施例中，参见图8，电源开关控制模块28还可以包括第五非门U9，其中：
第五非门U9的输入端用于接收偏置消除反相信号，第五非门U9的输出端分别与第一与非门U2的第二输入端、第一或非门U5的第一输入端连接，用于为第一与非门U2的第二输入端和第一或非门U5的第一输入端提供偏置消除使能信号。
需要说明的是，在本公开实施例中，偏置消除反相信号与偏置消除使能信号互为一组反相信号。其中，偏置消除使能信号可以用NcEn表示，偏置消除反相信号可以用NcEnN表示。
还需要说明的是，在本公开实施例中，电源开关控制模块28作为一个总控电路，可以为不同的电源开关模块提供一组电源使能信号(包括第一电源使能子信号和第二电源使能子信号)。另外，每一组中的第一电源使能子信号和第二电源使能子信号均是根据偏置消除反相信号生成的，而且第一电源使能子信号和第二电源使能子信号不会同时处于有效电平状态；也就是说，偏置消除反相信号与第一电源使能子信号和第二电源使能子信号之间具有时序关系。
还可以理解地，在上拉电源控制模块24中，对于上拉参考电源模块242来说，上拉参考电源模块242可以包括多个上拉开关管，其中：
上拉开关管的控制端(栅极)用于接收上拉电源驱动信号，上拉开关管的第一端均与上拉参考电源连接，上拉开关管的第二端用于输出第一参考电压PCS。
相应地，对于上拉电源驱动模块241来说，上拉电源驱动模块241可以包括多个上拉反相器，其中：
上拉反相器的控制端与上拉驱动电源连接，上拉反相器的输入端用于接收上拉控制输入信号，上拉反相器的输出端用于输出上拉电源驱动信号。
需要说明的是，在本公开实施例中，上拉开关管的数量与上拉反相器的数量一致。其中，每一个上拉反相器的输出端与对应的上拉开关管的控制端连接，用于为上拉开关管提供上拉电源驱动信号。
示例性地，以上拉电源驱动模块241包括三个上拉反相器，上拉参考电源模块242包括三个上拉开关管为例，具体参见图9，在上拉电源控制模块24中，上拉电源驱动模块241可以包括第一上拉反相器I1、第二上拉反相器I2和第三上拉反相器I3，上拉参考电源模块242可以包括第一上拉开关管M1、第二上拉开关管M2和第三上拉开关管M3，其中：
在上拉电源驱动模块241中，第一上拉反相器I1的输入端用于接收第一控制输入信号Vpu1，第一上拉反相器I1的输出端用于输出第一上拉电源驱动信号Pup1；第二上拉反相器I2的输入端用于接收第二控制输入信号Vpu2，第二上拉反相器I2的输出端用于输出第二上拉电源驱动信号Pup2；第三上拉反相器I3的输入端用于接收第三控制输入信号Vpu3，第三上拉反相器I3的输出端用于输出第三上拉电源驱动信号Pup3；第一上拉反相器I1的控制端、第二上拉反相器I2的控制端、第三上拉反相器I3的控制端均与上拉驱动电源vpcsgloc连接。在上拉参考电源模块242中，第一上拉开关管M1的第一端与第一上拉参考电源vblh1连接，第二上拉开关管M2的第一端与第二上拉参考电源vblh2连接，第三上拉开关管M3的第一端与第三上拉参考电源vblh3连接；第一上拉开关管M1的控制端用于接收第一上拉电源驱动信号Pup1，第二上拉开关管M2的控制端用于接收第二上拉电源驱动信号Pup2，第三上拉开关管M3的控制端用于接收第三上拉电源驱动信号Pup3，第一上拉开关管M1的第二端、第二上拉开关管M2的第二端和第三上拉开关管M3的第二端连接，用于输出第一参考电压PCS。在这里，第一上拉参考电源vblh1、第二上拉参考电源vblh2和第三上拉参考电源vblh3可以相同，也可以不同，这里不作任何限定。
需要注意的是，在图9中，对于上拉驱动电源vpcsgloc(即前述实施例所述的第四电源)来说，是由上拉电源开关模块26提供的。如图9所示，在上拉电源开关模块26中，第一开关管P1的第一端与第三工作电源vnocp连接，第一开关管P1的控制端与第一电源使能子信号SCmosOcEn连接，第二开关管P2的第一端与第四工作电源vpcsg连接，第二开关管P2的控制端与第二电源使能子信号SCmosSDTEn连接，第一开关管P1的第二端与第二开关管P2的第二端连接，且第一开关管P1与第二开关管P2择一导通，用于为上拉电源驱动模块241提供上拉驱动电源vpcsgloc。
还可以理解地，在下拉电源控制模块25中，对于下拉参考电源模块252来说，下拉参考电源模块252可以包括多个下拉开关管，其中：
下拉开关管的控制端用于接收下拉电源驱动信号，下拉开关管的第一端均与下拉参考电源连接，下拉开关管的第二端用于输出第二参考电压NCS。
相应地，对于下拉电源驱动模块251来说，下拉电源驱动模块251可以包括多个下拉反相器，其中：
下拉反相器的控制端与下拉驱动电源连接，下拉反相器的输入端用于接收下拉控制输入信号，下拉反相器的输出端用于输出下拉电源驱动信号。
需要说明的是，在本公开实施例中，下拉开关管的数量与下拉反相器的数量一致。其中，每一个下拉反相器的输出端与对应的下拉开关管的控制端连接，用于为下拉开关管提供下拉电源驱动信号。
示例性地，以下拉电源驱动模块251包括三个下拉反相器，下拉参考电源模块252包括三个下拉开关管为例，具体参见图10，在下拉电源控制模块25中，下拉电源驱动模块251可以包括第一下拉反相器I4、第二下拉反相器I5和第三下拉反相器I6，下拉参考电源模块252可以包括第一下拉开关管M4、第二下拉开关管M5和第三下拉开关管M6，其中：
在下拉电源驱动模块251中，第一下拉反相器I4的输入端用于接收第四控制输入信号Vpd1，第一下拉反相器I4的输出端用于输出第一下拉电源驱动信号Pdn1；第二下拉反相器I5的输入端用于接收第五控制输入信号Vpd2，第二下拉反相器I5的输出端用于输出第二下拉电源驱动信号Pdn2；第三下拉反相器I6的输入端用于接收第六控制输入信号Vpd3，第三下拉反相器I6的输出端用于输 出第三下拉电源驱动信号Pdn3；第一下拉反相器I4的控制端、第二下拉反相器I5的控制端、第三下拉反相器I6的控制端均与下拉驱动电源vncsgloc连接。在下拉参考电源模块252中，第一下拉开关管M4的控制端用于接收第一下拉电源驱动信号Pdn1，第二下拉开关管M5的控制端用于接收第二下拉电源驱动信号Pdn2，第三下拉开关管M6的控制端用于接收第三下拉电源驱动信号Pdn3；第一下拉开关管M4的第一端、第二下拉开关管M5的第一端和第三下拉开关管M6的第一端连接，用于输出第二参考电压NCS；第一下拉开关管M4的第二端、第二下拉开关管M5的第二端和第三下拉开关管M6的第二端均与下拉参考电源VSS连接。
需要注意的是，在图10中，对于下拉驱动电源vncsgloc(即前述实施例所述的第五电源)来说，是由下拉电源开关模块27提供的。如图10所示，在下拉电源开关模块27中，第一开关管N1的第一端与第五工作电源vnoc连接，第一开关管N1的控制端与第一电源使能子信号SCmosOcEn连接，第二开关管N2的第一端与第六工作电源vncsgh连接，第二开关管N2的控制端与第二电源使能子信号SCmosSDTEn连接，第一开关管N1的第二端与第二开关管N2的第二端连接，且第一开关管N1与第二开关管N2择一导通，用于为下拉电源驱动模块251提供下拉驱动电源vncsgloc。
另外，在本公开实施例中，第三工作电源vnocp与第四工作电源vpcsg处于不同电压范围和/或具有不同的温度特性，从而在不同阶段能够为上拉电源驱动模块241提供不同的上拉驱动电源vpcsgloc；第五工作电源vnoc与第六工作电源vncsgh处于不同电压域和/或具有不同的温度特性，从而在不同阶段还能够为下拉电源驱动模块251提供不同的下拉驱动电源vncsgloc；如此，上拉/下拉驱动电源可以根据OC阶段和Develop阶段进行调节，能够隔离OC阶段和Develop阶段的电源噪声，使得SA噪声抑制和读写速度均得到有效提高，同时对sense margin优化更有利。
还可以理解地，在本公开实施例中，对于灵敏放大电路30而言，在一些实施例中，参见图11，灵敏放大电路30可以包括第七开关管M7、第八开关管M8、第九开关管M9、第十开关管M10、第十一开关管M11、第十二开关管M12、第十三开关管M13和第十四开关管M14。其中，第七开关管M7、第八开关管M8、第九开关管M9和第十开关管M10组成放大模块，第十一开关管M11和第十二开关管M12组成隔离控制模块，第十三开关管M13和第十四开关管M14组成偏置消除模块。
在这里，第七开关管M7的第一端与第八开关管M8的第一端连接，且均用于接收第一参考电压PCS；第九开关管M9的第二端与第十开关管M10的第二端连接，且均用于接收第二参考电压NCS；第七开关管M7的第二端、第八开关管M8的控制端、第九开关管M9的第一端、第十二开关管M12的第二端、第十三开关管M13的第一端均与互补读出位线saBlb连接；第八开关管M8的第二端、第七开关管M7的控制端、第十开关管M10的第一端、第十一开关管M11的第一端、第十四开关管M14的第二端均与读出位线saBla连接；第十一开关管M11的第二端、第十三开关管M13的第二端、第九开关管M9的控制端均与位线Bla连接，第十二开关管M12的第一端、第十四开关管M14的第一端、第十开关管M10的控制端均与互补位线Blb连接；第十一开关管M11的控制端和第十二开关管M12的控制端均用于接收隔离控制信号Iso；第十三开关管M13的控制端和第十四开关管M14的控制端均用于接收偏置消除使能信号NcEn。另外，在图11中，第九开关管M9、第十开关管M10、第十一开关管M11、第十二开关管M12、第十三开关管M13和第十四开关管M14可以为NMOS管，第七开关管M7和第八开关管M8可以为PMOS管。
以DRAM为例，灵敏放大电路30通过位线连接目标存储单元，通过互补位线连接互补存储单元。在初始状态，位线和互补位线上的电位是相同的。在位线上的目标存储单元开启后，该目标存储单元与位线进行电荷分享，从而位线上的电位升高或者降低；互补位线上的互补存储单元始终是关闭的，因此互补位线上的电位不变。由于位线上的电位升高和降低，位线和互补位线之间的压差会发生变化，从而灵敏放大电路30中的部分器件导通，执行信号放大处理。此时，灵敏放大电路30从位线上接收的信号可以视为待处理信号，灵敏放大电路30从互补位线上接收的信号可以视为参考待处理信号。这样，在信号放大阶段，根据隔离控制信号Iso控制第十一开关管M11和第十二开关管M12处于导通状态时，可以加快待处理信号在目标存储单元与放大模块之间的传输速度，从而能够快速将位线或互补位线的电位拉高或拉低，提高信号放大速度。
在一些实施例中，对于预充模块212而言，在图11所示灵敏放大电路30的基础上，参见12，预充模块212可以包括预充开关管M15，其中：
预充开关管M15的第一端与预充电源VAD2连接，预充开关管M15的控制端用于接收预充驱动信号PreEQ，预充开关管M15的第二端与读出位线saBla连接。
进一步地，如图12所示，预充驱动模块211可以包括预充反相器I7，其中：
预充反相器I7的输入端用于接收预充使能信号eqN，预充反相器I7的控制端与第一电源Vdleq 连接，预充反相器I7的输出端用于输出预充驱动信号PreEQ。
需要说明的是，在本公开实施例中，根据该预充驱动模块211输出的预充驱动信号PreEQ，可以控制预充模块212为灵敏放大电路30进行预充处理，从而能够将读出位线saBla上的电压预充到一个预设值。
在另一些实施例中，对于预充模块212而言，在图11所示灵敏放大电路30的基础上，参见13，预充模块212可以包括预充开关管M16，其中：
预充开关管M16的第一端与读出位线saBla连接，预充开关管M16的控制端用于接收预充驱动信号EQ，预充开关管M16的第二端与互补读出位线saBlb连接。
进一步地，如图13所示，预充驱动模块211可以包括预充反相器I8，其中：
预充反相器I8的输入端用于接收预充使能信号eqN，预充反相器I8的控制端与第一电源Vdleq连接，预充反相器I8的输出端用于输出预充驱动信号EQ。
需要说明的是，在本公开实施例中，根据该预充驱动模块211输出的预充驱动信号EQ，可以控制预充模块212为灵敏放大电路30进行预充处理，从而能够实现读出位线saBla与互补读出位线saBlb的电压均衡。
另外，无论是图12中的预充驱动模块211和预充模块212还是图13中的预充驱动模块211和预充模块212，第一电源Vdleq与第三工作电源vnocp、第四工作电源vpcsg、第五工作电源vnoc、第六工作电源vncsgh均不相同，从而还可以隔离不同阶段的电源噪声，达到抑制电源噪声的目的。需要说明的是，电源不同指的是电源信号具有不同的外部来源，而并非指定电压值一定不同。
在又一些实施中，对于灵敏放大电路30而言，图12中的预充驱动模块211和预充模块212以及图13中的预充驱动模块211和预充模块212可以同时存在。其中，图12中的预充驱动模块211和预充模块212配置为将读出位线saBla上的电压预充到一个预设值，而图13中的预充驱动模块211和预充模块212配置为实现读出位线saBla与互补读出位线saBlb的电压均衡。
综上可知，本公开实施例提供了一种控制电路20，该控制电路与灵敏放大电路连接，且该控制电路包括预充控制模块和电源控制模块。其中，预充控制模块包括预充驱动模块和预充模块，且预充驱动模块与第一电源连接；电源控制模块包括电源驱动模块和参考电源模块，且电源驱动模块与第二电源连接，而且第一电源与第二电源不同。这样，由于预充驱动模块与电源驱动模块使用的电源不同，从而可以隔离不同阶段的电源噪声，使得SA噪声抑制和读写速度均得到有效提高，能够优化灵敏放大电路的信号放大过程，进而改善灵敏放大器的性能。
在本公开的另一实施例中，基于前述实施例所述的控制电路20，其应用于灵敏放大器。参见图14，其示出了本公开实施例提供的一种灵敏放大器的应用场景示意图。如图14所示，在该应用场景中，存在位线Bla、互补位线Blb、读出位线saBla、互补读出位线saBlb和灵敏放大器51。存在位线Bla上设置有第一存储单元52，在互补位线Blb上设置有第二存储单元53。在这里，第一存储单元52和第二存储单元53均可各自作为预设指令的对象。
另外，灵敏放大器51可以包括上拉电源控制电路511、下拉电源控制电路512、灵敏放大电路513和预充控制电路514。其中，上拉电源控制电路511包括第一上拉反相器I1、第二上拉反相器I2、第三上拉反相器I3、第一上拉开关管M1、第二上拉开关管M2和第三上拉开关管M3，下拉电源控制电路512包括第一下拉反相器I4、第二下拉反相器I5、第三下拉反相器I6、第一下拉开关管M4、第二下拉开关管M5和第三下拉开关管M6，灵敏放大电路513包括第七开关管M7、第八开关管M8、第九开关管M9、第十开关管M10、第十一开关管M11、第十二开关管M12、第十三开关管M13和第十四开关管M14，预充控制电路514包括预充开关管M15和预充反相器I7。在这里，针对图14的电路工作原理具体可参见前述内容，在此不做赘述。
在图14中，第一上拉反相器I1的控制端、第二上拉反相器I2的控制端和第三上拉反相器I3的控制端均与上拉驱动电源Vpcsg连接，第一下拉反相器I4的控制端、第二下拉反相器I5的控制端和第三下拉反相器I6的控制端均与下拉驱动电源Vncsgh连接，预充反相器I7的控制端与预充驱动电源Vdleq连接。
需要说明的是，在相关技术中，预充驱动电源Vdleq与下拉驱动电源Vncsgh共用同一电源，SA工作在不同阶段存在噪声，从而对sense margin不利；而且由于在不同阶段电源的温度特性完全相同，使得灵敏放大器缺少灵活性。而在本公开实施例中，对于图14所示的灵敏放大器来说，预充驱动电源Vdleq与下拉驱动电源Vncsgh使用不同的电源，而且预充驱动电源Vdleq与上拉驱动电源Vpcsg也使用不同的电源，从而可以隔离不同阶段(例如OC阶段和Develop阶段)下电源总线(power bus)的噪声。
在图14的基础上，参见图15，其示出了本公开实施例提供的一种灵敏放大器的信号时序示意图。如图15所示，Iso是指前述的隔离控制信号，可以为第一电压值和第二电压值；PreEQ是指前述的预充驱动信号，NcEn是指前述的偏置消除使能信号(也可用Nc表示，或者称为噪声消除信号)；SanEn是指前述的下拉电源驱动信号(Pdn1、Pdn2、Pdn3等)，SapEn是指前述的上拉电源驱动信号(Pup1、Pup2、Pup3等)；WL是指字线开启信号，在WL为第二电平状态时，目标存储单元所在的字线开启，从而目标存储单元和位线接通，在WL为第一电平状态时，目标存储单元关所在的字线关闭，从而目标存储单元和位线不接通；PCS/NCS是指第一参考电压信号/第二参考电压信号，第一参考电压信号具有第四电压值和第五电压值，第一参考电压信号具有第四电压值和第六电压值，且第四电压值介于第五电压值和第六电压值之间；Bla是指位线，Blb是指互补位线，saBla是指读出位线，saBlb是指互补读出位线。其中，第一电平状态表示低电平状态，第二电平状态表示高电平状态。
如图15所示，在放大电路处于空闲阶段时，隔离控制信号Iso维持第二电压值，预充驱动信号PreEQ和偏置消除使能信号NcEn处于第二电平状态，下拉电源驱动信号SanEn/上拉电源驱动信号SapEn均处于第一电平状态，字线开启信号WL处于第一电平状态，第一参考电压信号PCS/第二参考电压信号NCS维持第四电压值，位线Bla/互补位线Blb均处于第四电压值；此时为执行用户的操作指令做好前期准备。需要注意的是，由于第九开关管M9和第十开关管M10存在工艺偏差等原因，导致两个开关管的性能存在差异使得读出位线saBla/互补读出位线saBlb之间存在电压差dVt，为了使得两边的电压均衡，在预充阶段之后，需要进入偏置消除阶段，在理想情况下，dVt尽可能趋于零。
具体地，假设目标存储单元为第一存储单元52，在用户发送了针对目标存储单元的读指令后，灵敏放大电路513由待机阶段进入偏置消除阶段，此时隔离控制信号Iso由第二电压值调整为第一电压值，预充驱动信号PreEQ由第二电平状态调整为第一电平状态，下拉电源驱动信号SanEn/上拉电源驱动信号SapEn均由第一电平状态调整为第二电平状态，所以第一参考电压信号PCS由第四电压值向第五电压值变化，第二参考电压信号NCS由第四电压值向第六电压值变化，而偏置消除使能信号NcEn仍保持第二电平状态，从而对灵敏放大电路513进行偏置消除处理。之后，下拉电源驱动信号SanEn/上拉电源驱动信号SapEn切换至第一电平状态，第一参考电压信号PCS和第二参考电压信号NCS继续由预充控制电路514供电恢复至第四电压值。
在结束偏置消除阶段后，当字线开启信号WL变化为第二电平状态时，目标存储单元所在的字线调整为开启状态，从而灵敏放大电路513进入字线打开阶段，具体是第一电荷分享(Charge Sharing，CS)阶段，此时对目标存储单元(例如第一存储单元52)进行读取。如图15所示，以第一存储单元52所存储的数据为“0”为例，在第一电荷分享阶段结束后，位线Bla电压降低，即产生了待处理信号，互补位线Blb则形成参考待处理信号。另外，在第一电荷分享阶段，隔离控制信号Iso维持第一电压值，使得位线Bla与读出位线saBla不接通，互补位线Blb与互补读出位线saBlb不接通。预充驱动信号PreEQ、偏置消除使能信号NcEn、下拉电源驱动信号SanEn/上拉电源驱动信号SapEn均处于第一电平状态。
在结束第一电荷分享阶段后，灵敏放大电路513进入第二电荷分享阶段。在第二电荷分享阶段，隔离控制信号Iso维持第二电压值，使得位线Bla与读出位线saBla接通，位线Blb与saBlb接通，从而灵敏放大电路513将待处理信号和参考待处理信号接收到内部节点，将读出位线saBla的电压降低，可以视为位线Bla/互补位线Blb与读出位线saBla/互补读出位线saBlb进行读电荷分享。另外，除隔离控制信号Iso之外的其他信号均维持前一阶段的电压值。
在结束第二电荷分享阶段后，灵敏放大电路513进入放大阶段，下拉电源驱动信号SanEn/上拉电源驱动信号SapEn由第一电平状态调整为第二电平状态，从而第一参考电压信号PCS由第四电压值向第五电压值变化，第二参考电压信号NCS由第四电压值向第六电压值变化，读出位线saBla的电压降低，使第七开关管M7打开，第一参考电压信号PCS对互补读出位线saBlb的电压拉高，使第十开关管M10打开，第二参考电压信号NCS对读出位线saBla的电压拉低，从而灵敏放大电路513能够根据第一参考电压信号PCS/第二参考电压信号NCS对待处理信号(位线Bla的信号)/参考待处理信号(互补位线Blb的信号)进行放大，隔离控制信号Iso仍然维持第二电压值，以完成对待处理信号(位线Bla的信号)/参考待处理信号(互补位线Blb)上的信号放大。
另外，若第一存储单元52所存储的数据为“1”，第一放大阶段位线Bla的电压会拉高，由于隔离控制信号Iso处于第二电压值，能够抑制位线Bla/互补位线Blb上的升高速率，降低位线Bla/互补位线Blb上的噪声，但是处于灵敏放大电路513内部的读出位线saBla/互补读出位线saBlb上的 信号可以很快的达到高参考电位/低参考电位。
在结束放大阶段后，当字线开启信号WL变化为第一电平状态时，目标存储单元所在的字线调整为关闭状态，此时灵敏放大电路513进入字线关闭阶段，同时隔离控制信号Iso维持第二电压值，预充驱动信号PreEQ和偏置消除使能信号NcEn维持第一电平状态；另外，在该阶段期间，下拉电源驱动信号SanEn/上拉电源驱动信号SapEn会由第二电平状态调整为第一电平状态。
进一步地，灵敏放大电路513进入预充阶段，预充驱动信号PreEQ和偏置消除使能信号NcEn调整为第二电平状态，此时，第一参考电压信号PCS/第二参考电压信号NCS将恢复至第四电压值，位线Bla/互补位线Blb、读出位线saBla/互补读出位线saBlb将恢复至相同的电压值。
在结束预充阶段后，灵敏放大电路513再次进入空闲阶段，以准备下一次操作。
在本公开实施例中，对于预充驱动信号PreEQ和偏置消除使能信号NcEn而言，当其处于第二电平状态时，其对应的电压值可以是由预充驱动电源Vdleq提供的；对于上拉电源驱动信号SapEn而言，当其处于第二电平状态时，其对应的电压值可以是由上拉驱动电源Vpcsg(具体为第三工作电源vnocp和第四工作电源vpcsg)提供的；对于下拉电源驱动信号SanEn而言，当其处于第二电平状态时，其对应的电压值可以是由下拉驱动电源Vncsgh(具体为第五工作电源vnoc和第六工作电源vncsgh)提供的；对于第一参考电压信号PCS/第二参考电压信号NCS、位线Bla/互补位线Blb而言，其最低值为地信号，可以是下拉参考电源VSS提供的。
综上可知，基于上述实施例对前述实施例的具体实现进行了详细阐述，从中可以看出，根据前述实施例的技术方案，由于预充控制电路514与上拉电源控制电路511/下拉电源控制电路512使用的电源不同，从而可以隔离不同阶段下的电源噪声，使得SA噪声抑制和读写速度均得到有效提高，能够优化灵敏放大电路的信号放大过程，进而改善灵敏放大器的性能。
在一些实施例中，参见图16，其示出了本公开实施例提供的一种半导体存储器的组成结构示意图。如图16所示，该半导体存储器包括控制电路、多个存储块以及设置在相邻两个存储块之间的灵敏放大电路模块，相邻两个灵敏放大模块之间设置有开关模块。其中，控制电路包括预充控制模块和电源控制模块，灵敏放大模块存储块包括灵敏放大电路和预充控制模块，开关模块包括电源控制模块，其中：
预充控制模块可以包括预充驱动模块和预充模块，且预充驱动模块与第一电源连接，用于通过预充驱动模块为预充模块提供预充驱动信号，根据预充驱动信号控制预充模块为灵敏放大电路进行预充处理；
电源控制模块可以包括电源驱动模块和参考电源模块，且电源驱动模块与第二电源连接，用于通过电源驱动模块为参考电源模块提供电源驱动信号，根据电源驱动信号控制参考电源模块为灵敏放大电路提供参考电压；其中，第一电源与第二电源不同。
以四个存储块为例，根据图16可以看出，在第一方向上，相邻的存储块之间设置有包含灵敏放大电路、预充模块和预充驱动模块的灵敏放大模块；在第二方向上，相邻的存储块之间设置有行解码器，相邻的灵敏放大模块之间还设置有开关模块，所述开关模块还位于相邻所述行解码器之间。在这里，存储块可以为存储体(bank)在第一方向上划分的多个存储部(section)，即每个存储块为一个存储部。
在一些实施例中，该半导体存储器还可以包括前述实施例所述的电源开关模块和前述实施例所述的电源开关控制模块，其中：电源开关模块和电源开关控制模块均位于开关模块中；或者，电源开关模块位于开关模块中，电源开关控制模块位于半导体存储器的外围区域；或者，电源开关模块和电源开关控制模块均位于半导体存储器的外围区域。这样，将电源开关模块和电源开关控制模块置于外围区域，可以实现将同一个存储体中的多个存储块对应的，甚至同一个存储器中的多个存储体对应的电源开关模块和电源开关控制模块合并，执行整体控制，从而节约芯片面积，增加同一块晶圆上的芯片数量(Die Per Wafer，DPW)。
可以理解的是，上述整体控制指的是，同一电源开关控制模块配置为控制多个存储块或多个存储体对应的电源开关模块，减少电源开关控制模块的数量，以及，同一个电源开关模块控制多个存储块或多个存储体对应的电源导通。进一步的，当电源开关模块设置于外围区域时，对应连接的电源在外围区域产生。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更 多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种控制电路以及半导体存储器，控制电路与灵敏放大电路连接，且该控制电路包括预充控制模块和电源控制模块，其中：预充控制模块包括预充驱动模块和预充模块，且预充驱动模块与第一电源连接，用于通过预充驱动模块为预充模块提供预充驱动信号，预充驱动信号用于控制预充模块为灵敏放大电路进行预充处理；电源控制模块包括电源驱动模块和参考电源模块，且电源驱动模块与第二电源连接，用于通过电源驱动模块为参考电源模块提供电源驱动信号，根据电源驱动信号控制参考电源模块为灵敏放大电路提供参考电压；其中，第一电源与第二电源不同。这样，由于预充驱动模块与电源驱动模块使用的电源不同，从而可以隔离不同阶段的电源噪声，使得SA噪声抑制和读写速度均得到有效提高，能够优化灵敏放大电路的信号放大过程，进而改善灵敏放大器的性能。

Claims (14)

  1. 一种控制电路，所述控制电路与灵敏放大电路连接，且所述控制电路包括预充控制模块和电源控制模块，其中：
    所述预充控制模块包括预充驱动模块和预充模块，且所述预充驱动模块与第一电源连接，用于通过所述预充驱动模块为所述预充模块提供预充驱动信号，所述预充驱动信号用于控制所述预充模块为所述灵敏放大电路进行预充处理；
    所述电源控制模块包括电源驱动模块和参考电源模块，且所述电源驱动模块与第二电源连接，用于通过所述电源驱动模块为所述参考电源模块提供电源驱动信号，根据所述电源驱动信号控制所述参考电源模块为所述灵敏放大电路提供参考电压；其中，所述第一电源与所述第二电源不同。
  2. 根据权利要求1所述的控制电路，其中，所述控制电路还包括电源开关模块，且所述电源开关模块与第三电源连接，其中：
    所述电源开关模块，配置为接收电源使能信号，根据所述电源使能信号控制所述电源开关模块内部的开关管状态，以通过所述第三电源向为所述电源驱动模块提供所述第二电源，所述第一电源与所述第三电源不同。
  3. 根据权利要求2所述的控制电路，其中，所述第三电源包括第一工作电源和第二工作电源，所述第一工作电源与所述第二工作电源处于不同电压域和/或具有不同的温度特性，所述电源使能信号包括第一电源使能子信号和第二电源使能子信号；
    所述电源开关模块包括第一开关管和第二开关管；其中，所述第一开关管的第一端与所述第一工作电源连接，所述第一开关管的控制端与所述第一电源使能子信号连接，所述第二开关管的第一端与所述第二工作电源连接，所述第二开关管的控制端与所述第二电源使能子信号连接，所述第一开关管的第二端与所述第二开关管的第二端连接，且所述第一开关管与所述第二开关管择一导通，用于为所述电源驱动模块提供所述第二电源。
  4. 根据权利要求3所述的控制电路，其中，
    在所述灵敏放大电路工作于偏置消除阶段时，所述第一开关管导通，以通过所述第一工作电源为所述电源驱动模块提供所述第二电源；
    在所述灵敏放大电路工作于信号放大阶段时，所述第二开关管导通，以通过所述第二工作电源为所述电源驱动模块提供所述第二电源。
  5. 根据权利要求3所述的控制电路，其中，所述电源开关模块至少包括下述其中一项：上拉电源开关模块和下拉电源开关模块；
    其中，所述上拉电源开关模块包括的第一开关管和第二开关管为PMOS管，所述下拉电源开关模块包括的第一开关管和第二开关管为NMOS管，且所述上拉电源开关模块连接的所述第一工作电源与所述下拉电源开关模块连接的所述第一工作电源不同，所述上拉电源开关模块连接的所述第二工作电源与所述下拉电源开关模块连接的所述第二工作电源不同。
  6. 根据权利要求5所述的控制电路，其中，当所述电源开关模块的数量为至少一个时，所述控制电路还包括电源开关控制模块，其中：
    所述电源开关控制模块，配置为接收偏置消除使能信号和目标电源使能信号，根据所述偏置消除使能信号和所述目标电源使能信号生成至少一组所述电源使能信号；其中，每一组所述电源使能信号均包括所述第一电源使能子信号和所述第二电源使能子信号，且至少一组所述电源使能信号与至少一个所述电源开关模块具有对应关系。
  7. 根据权利要求6所述的控制电路，其中，所述目标电源使能信号包括第一目标电源使能信号和第二目标电源使能信号，所述电源开关控制模块包括第一逻辑控制模块和第二逻辑控制模块，其中：
    所述第一逻辑控制模块，配置为接收所述偏置消除使能信号和所述第二目标电源使能信号，输出至少一个所述第一电源使能子信号；
    所述第二逻辑控制模块，配置为接收所述偏置消除使能信号和所述第一目标电源使能信号，输出至少一个所述第二电源使能子信号；
    其中，所述第一目标电源使能信号与所述第一电源使能子信号具有相同的有效状态，所述第二目标电源使能信号与所述第二电源使能子信号具有相同的有效状态。
  8. 根据权利要求7所述的控制电路，其中，所述第一逻辑控制模块包括第一非门、第一与非门、第一电平转换模块和第二非门，其中：
    所述第一非门的输入端用于接收所述第二目标电源使能信号，所述第一非门的输出端与所述第一与非门的第一输入端连接，所述第一与非门的第二输入端用于接收所述偏置消除使能信号，所述第一与非门的输出端与所述第一电平转换模块的输入端连接，所述第一电平转换模块的输出端与第二非门的输入端连接，所述第二非门的输出端用于输出至少一个所述第一电源使能子信号；
    所述第二逻辑控制模块包括第一或非门、第三非门、第二电平切换模块和第四非门，其中：
    所述第一或非门的第一输入端用于接收所述偏置消除使能信号，所述第一或非门的第二输入端用于接收所述第一目标电源使能信号，所述第一或非门的输出端与所述第三非门的输入端连接，所述第三非门的输出端与所述第二电平转换模块的输入端连接，所述第二电平转换模块的输出端与第四非门的输入端连接，所述第四非门的输出端用于输出至少一个所述第二电源使能子信号。
  9. 根据权利要求7所述的控制电路，其中，所述电源开关控制模块还包括第五非门，其中：
    所述第五非门的输入端用于接收偏置消除反相信号，所述第五非门的输出端用于输出所述偏置消除使能信号。
  10. 根据权利要求1所述的控制电路，其中，所述预充模块包括预充开关管，其中：
    所述预充开关管的第一端与预充电源连接，所述预充开关管的控制端用于接收所述预充驱动信号，所述预充开关管的第二端与读出位线连接。
  11. 根据权利要求1所述的控制电路，其中，所述预充模块包括预充开关管，其中：
    所述预充开关管的第一端与读出位线连接，所述预充开关管的控制端用于接收所述预充驱动信号，所述预充开关管的第二端与互补读出位线连接。
  12. 根据权利要求10或11所述的控制电路，其中，所述预充驱动模块包括预充反相器，其中：
    所述预充反相器的输入端用于接收预充使能信号，所述预充反相器的控制端与所述第一电源连接，所述预充反相器的输出端用于输出所述预充驱动信号。
  13. 一种半导体存储器，所述半导体存储器包括控制电路、多个存储块以及设置在相邻两个所述存储块之间的灵敏放大模块，相邻两个所述灵敏放大模块之间设置有开关模块，所述控制电路包括预充控制模块和电源控制模块，所述灵敏放大模块包括灵敏放大电路和所述预充控制模块，所述开关模块包括所述电源控制模块，其中：
    所述预充控制模块包括预充驱动模块和预充模块，且所述预充驱动模块与第一电源连接，用于通过所述预充驱动模块为所述预充模块提供预充驱动信号，根据所述预充驱动信号控制所述预充模块为所述灵敏放大电路进行预充处理；
    所述电源控制模块包括电源驱动模块和参考电源模块，且所述电源驱动模块与第二电源连接，用于通过所述电源驱动模块为所述参考电源模块提供电源驱动信号，根据所述电源驱动信号控制所述参考电源模块为所述灵敏放大电路提供参考电压；其中，所述第一电源与所述第二电源不同。
  14. 根据权利要求13所述的半导体存储器，其中，所述半导体存储器还包括如权利要求2所述的电源开关模块和如权利要求6所述的电源开关控制模块，其中：
    所述电源开关模块和所述电源开关控制模块均位于所述开关模块中；或者，
    所述电源开关模块位于所述开关模块中，所述电源开关控制模块位于所述半导体存储器的外围区域；或者，
    所述电源开关模块和所述电源开关控制模块均位于所述半导体存储器的外围区域。
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