WO2023123667A1 - 一种控制放大电路、灵敏放大器和半导体存储器 - Google Patents

一种控制放大电路、灵敏放大器和半导体存储器 Download PDF

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Publication number
WO2023123667A1
WO2023123667A1 PCT/CN2022/079712 CN2022079712W WO2023123667A1 WO 2023123667 A1 WO2023123667 A1 WO 2023123667A1 CN 2022079712 W CN2022079712 W CN 2022079712W WO 2023123667 A1 WO2023123667 A1 WO 2023123667A1
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Prior art keywords
signal
control
switch tube
tube
control signal
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PCT/CN2022/079712
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English (en)
French (fr)
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吴道训
尚为兵
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长鑫存储技术有限公司
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Priority to US17/844,259 priority Critical patent/US20230215491A1/en
Publication of WO2023123667A1 publication Critical patent/WO2023123667A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, in particular to a control amplifier circuit, a sensitive amplifier and a semiconductor memory.
  • Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers, consisting of many repeated storage units.
  • DRAM Dynamic Random Access Memory
  • the read data signal of each memory cell is read through the local data line, the global data line and the data bus in turn; otherwise, in the process of data writing, the write data signal is sequentially passed through The data bus, the global data lines and the local data lines write to the memory cells.
  • the disclosure provides a control amplifier circuit, a sensitive amplifier and a semiconductor memory, which can reduce circuit power consumption during signal amplification.
  • an embodiment of the present disclosure provides a control amplifier circuit, including:
  • a power consumption control circuit configured to receive a power consumption control signal, and output a first reference signal according to the power consumption control signal
  • An isolation circuit configured to determine a control command signal, and generate an isolated control signal according to the control command signal
  • An amplifying circuit configured to receive the first reference signal, the isolated control signal and the signal to be processed, and process the signal to be processed based on the first reference signal and the isolated control signal to obtain a target amplified signal .
  • the power consumption control circuit includes a first control circuit and a second control circuit, and the power consumption control signal includes a first power consumption control signal and a second power consumption control signal; wherein, the first A control circuit, configured to receive the first power consumption control signal, and output the first reference control signal with a first voltage value when the first power consumption control signal is in a first level state; the A second control circuit, configured to receive the second power consumption control signal, and output the first reference control signal having a second voltage value when the second power consumption control signal is in a first level state; Wherein, the first voltage value is higher than the second voltage value.
  • the first control circuit includes a plurality of first control subcircuits, and the first control subcircuit includes a first switch tube and a second switch tube; wherein, the first switch tube of the first switch tube The end is used to receive the first power consumption control signal, the third end of the first switch tube, the first end of the second switch tube are connected to the second end of the second switch tube, and the first switch tube is connected to the second end of the second switch tube.
  • the third terminals of the two switching tubes are connected to the ground signal, and the second terminals of the second switching tubes in the plurality of first control sub-circuits are connected to each other; the second terminals of the first switching tubes are used to output the first reference signal.
  • a switch is provided between the third terminal of the first switching tube and the first terminal of the second switching tube, and the control terminal of the switch is connected to the power saving control signal; wherein, in the When the first power consumption control signal is in the first level state, the switch is controlled to be in the closed state by the power saving control signal.
  • the second control circuit includes a plurality of second control subcircuits, and the second control subcircuit includes a third switching tube; wherein, the first end of the third switching tube is used to receive For the second power consumption control signal, the third terminal of the third switching transistor is connected to the ground signal, and the second terminal of the third switching transistor is used to output the first reference signal.
  • the power consumption control circuit further includes a control signal generation circuit; wherein the control signal generation circuit includes a plurality of first inverters, and the first inverters are used to receive an initial control signal, and generating a power consumption control signal; wherein, among the plurality of first inverters, the first power consumption control signal of each of the first control subcircuits is output through one of the first inverters, The second power consumption control signal of each of the second control sub-circuits is output through one of the first inverters.
  • control amplification circuit further includes a reference control circuit; the reference control circuit is configured to determine a reference control signal, and output a second reference signal according to the reference control signal; the amplification circuit also uses for receiving the first reference signal, the second reference signal, the isolation control signal and the signal to be processed, and based on the first reference signal, the second reference signal and the isolation control signal to the The signal to be processed is processed to obtain the target amplified signal.
  • the reference control circuit includes a plurality of third control subcircuits, and the third control subcircuit includes a fourth switching tube; wherein, one end of the fourth switching tube is connected to the reference control signal connected, the second end of the fourth switch tube is connected to the first preset power supply, and the third end of the fourth switch tube is used to output the second reference signal.
  • the reference control circuit includes a plurality of signal processing subcircuits and a plurality of third control subcircuits; wherein, the signal processing subcircuits include a second inverter, and the second inverter uses for receiving an initial reference signal and generating the reference control signal; the third control subcircuit includes a fourth switch tube, the first end of the fourth switch tube is connected to the reference control signal, and the fourth switch The second end of the tube is connected to the first preset power supply, and the third end of the fourth switching tube is used to output the second reference signal; wherein, a plurality of the signal processing sub-circuits and a plurality of the first The three control sub-circuits correspond one by one.
  • the isolation circuit includes a first signal determination circuit, a power output circuit, a second signal determination circuit, and an isolation control circuit; wherein, the first signal determination circuit is configured to receive a preset operation instruction Afterwards, according to the preset operation instruction, a first power switching signal and/or a second power switching signal are output; the power output circuit is configured to switch according to the first power switching signal and/or the second power switching signal to output the isolated power supply value; the second signal determination circuit is used to output the control instruction signal according to the preset operation instruction after receiving the preset operation instruction; the isolation control circuit uses Generate the isolated control signal based on receiving the isolated power supply value and the control instruction signal.
  • the power output circuit is configured to determine the isolated power supply when the first power switching signal has a second level state and the second power switching signal has a first level state value has a third voltage value; or when the first power switching signal has a first level state and the second power signal has a second level state, it is determined that the isolated power supply value has a fourth voltage value; wherein , both the third voltage value and the fourth voltage value belong to the first level state, and the third voltage value is greater than the fourth voltage value.
  • the isolation control circuit is specifically configured to determine that the isolation control signal has a first level state and the isolation power supply value has a third voltage value when the control command signal has a first level state. Three voltage values; or when the control instruction signal has a first level state and the isolated power supply value has a fourth voltage value, determine that the isolated control signal has a fourth voltage value; or in the control instruction When the signal has a second level state, it is determined that the isolation control signal has a fifth voltage value; wherein the fifth voltage value belongs to the second level state, and the fifth voltage value is smaller than the fourth voltage value.
  • the power output circuit includes a second preset power supply, a third preset power supply, a fifth switch tube, and a sixth switch tube; wherein, the first end of the fifth switch tube is connected to the first switch tube.
  • the second end of the switch tube is connected to the third preset power supply; the third end of the fourth switch tube is connected to the third end of the sixth switch tube for outputting the value of the isolated power supply; wherein , the second preset power supply is used to output the third voltage value, and the third preset power supply is used to output the fourth voltage value.
  • the isolation control circuit includes a third inverter, a seventh switch tube, and an eighth switch tube; wherein, the input end of the third inverter is connected to the control instruction signal, and the The output end of the third inverter is respectively connected to the first end of the seventh switching tube and the first end of the eighth switching tube; the second end of the seventh switching tube is connected to the isolated power source, so The third end of the eighth switch transistor is connected to the ground signal; the third end of the seventh switch transistor is connected to the second end of the eighth switch transistor for outputting the isolation control signal.
  • the amplifying circuit includes a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube, a thirteenth switch tube, and a fourteenth switch tube; the ninth switch tube The first end of the tube is connected to the third end of the thirteenth switch tube for receiving the signal to be processed, the second end of the ninth switch tube, the third end of the eleventh switch tube end, the first end of the twelfth switch tube is connected to the second end of the fourteenth switch tube; the first end of the tenth switch tube is connected to the third end of the fourteenth switch tube, For receiving a reference signal to be processed, the second terminal of the tenth switching tube, the third terminal of the twelfth switching tube, the first terminal of the eleventh switching tube and the first terminal of the thirteenth switching tube The two terminals are connected; the third terminal of the ninth switch tube and the third terminal of the tenth switch tube are connected to the first reference signal, the second terminal of the eleventh switch tube, the twel
  • the amplifying circuit further includes a precharging circuit, and the precharging circuit includes a fifteenth switch tube and a sixteenth switch tube; wherein, the first terminal of the fifteenth switch tube, the The first end of the sixteenth switch tube is connected to the pre-charge control signal; the second end of the fifteenth switch tube is connected to the fourth preset power supply, and the third end of the fifteenth switch tube is connected to the The second end of the tenth switch tube is connected; the second end of the sixteenth switch tube is connected to the second end of the tenth switch tube, and the third end of the sixteenth switch tube is connected to the ninth switch tube. The second end of the switch tube is connected.
  • the amplifying circuit further includes a noise elimination circuit
  • the noise elimination circuit includes a seventeenth switch tube and an eighteenth switch tube; wherein, the first terminal of the seventeenth switch tube, the tenth switch tube The first end of the eighth switch tube is connected to the noise elimination signal; the second end of the seventeenth switch tube is connected to the second end of the ninth switch tube, and the third end of the seventeenth switch tube is connected to the The first end of the ninth switching tube is connected; the second end of the eighteenth switching tube is connected to the second end of the tenth switching tube, and the third end of the eighteenth switching tube is connected to the first The first end of ten switching tubes is connected.
  • the amplifying circuit when the amplifying circuit processes the signal to be processed, it includes: a standby phase, a noise elimination phase, a first charge sharing phase, a second charge sharing phase, a signal amplification phase, a signal write-back phase and a pre-charging phase; If the amplifying circuit is in the second charge sharing phase or the signal amplifying phase or the pre-charging phase, then maintain the isolation control signal to have a third voltage value; or if the amplifying circuit is in the standby phase or the In the signal write-back phase, maintain the isolation control signal to have a fourth voltage value; or if the amplifying circuit is in the noise elimination phase or the first charge sharing phase, maintain the isolation control signal to have a fifth voltage value Voltage value.
  • the first power consumption control signal when the amplifying circuit is in the signal write-back phase, the first power consumption control signal is in a first level state, and the second power consumption control signal is in a second level state ; when the amplifying circuit is in the standby phase or the noise elimination phase or the first charge sharing phase or the second charge sharing phase or the signal amplification phase or the pre-charging phase, the first The power consumption control signal is in the second level state.
  • the fifth switch tube, the sixth switch tube, the seventh switch tube, the eleventh switch tube, and the twelfth switch tube are P-type channel field effect tubes; the first switch tube, the second switch tube, The third switching tube, the fourth switching tube, the eighth switching tube, the ninth switching tube, the tenth switching tube, the thirteenth switching tube, the fourteenth switching tube, the fifteenth switching tube, the sixteenth switching tube, the sixth switching tube
  • the seventeenth switch tube and the eighteenth switch tube are N-type channel field effect tubes; wherein, the first end of the P-type channel field effect tube is a gate terminal, and the second end of the P-type channel field effect tube is a source extreme, the third end of the P-type channel field effect transistor is the drain end; the first end of the N-type channel field effect transistor is the gate end, and the second end of the N-type channel field effect transistor is the drain end, The third terminal of the N-type channel field effect transistor is a source terminal.
  • an embodiment of the present disclosure provides a sense amplifier, including the control amplifier circuit according to any one of the first aspect.
  • an embodiment of the present disclosure provides a semiconductor memory, including the sense amplifier as described in the second aspect.
  • An embodiment of the present disclosure provides a control amplifier circuit, a sense amplifier, and a semiconductor memory, including: a power consumption control circuit, configured to receive a power consumption control signal, and output a first reference signal according to the power consumption control signal; an isolation circuit, For determining the control command signal, and generating an isolated control signal according to the control command signal; an amplification circuit, for receiving the first reference signal, the isolated control signal and the signal to be processed, and based on the first reference signal and processing the signal to be processed with the isolation control signal to obtain a target amplified signal.
  • the first reference signal can be adjusted according to the power consumption control signal, thereby reducing power consumption of the circuit.
  • Fig. 1 is a schematic diagram of an application scenario of a sensitive amplifier
  • FIG. 2 is a schematic diagram of the composition and structure of a control amplifier circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of the composition and structure of another control amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 4A is a schematic structural diagram of a power consumption control circuit provided by an embodiment of the present disclosure.
  • FIG. 4B is a schematic structural diagram of another power consumption control circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an inverter provided by an embodiment of the present disclosure.
  • FIG. 6A is a schematic structural diagram of a reference control circuit provided by an embodiment of the present disclosure.
  • FIG. 6B is a schematic structural diagram of another reference control circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an isolation circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of an application scenario of a control amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of an application scenario of another control amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of signal timing of an amplification circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of signal timing of another amplifier circuit provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of the composition and structure of a sense amplifier provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the composition and structure of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific ordering of objects. Understandably, “first ⁇ second ⁇ third 3" where permitted, the specific order or sequence may be interchanged such that the embodiments of the disclosure described herein can be practiced in sequences other than those illustrated or described herein.
  • P-type trench field effect transistor hole type field effect transistor
  • N-type channel field effect tube electronic type field effect tube.
  • FIG. 1 shows a schematic diagram of an application scenario of a sense amplifier.
  • the application scenario includes a first signal line 11 , a second signal line 12 , and a sense amplifier 113 . in,
  • the first signal line 11 has a first switch 111 and a first capacitor 112 for inputting the signal Vin+ to be processed; the second signal line 12 has a second switch 121 and a second capacitor 122 for inputting a reference signal to be processed
  • the voltage difference between the signal Vin-, the signal to be processed Vin+ and the reference signal Vin- to be processed is ⁇ Vin, and the sense amplifier 113 is used to amplify the signal Vin+ to be processed or the reference signal Vin- to be processed.
  • the first switch 111 and the first capacitor 112 can be regarded as a storage unit
  • the second switch 121 and the second capacitor 122 can be regarded as another storage unit.
  • the sense amplifier includes a first switch tube 131 , a second switch tube 132 , a third switch tube 133 and a fourth switch tube 134 . are all connected to the reference signal to be processed Vin-, the third end of the first switching tube 131, the second end of the second switching tube 132, the first end of the third switching tube 133, the first end of the fourth switching tube 134 Both terminals are connected to the signal Vin+ to be processed.
  • a fifth switching tube 135 and a sixth switching tube 136 there are also a fifth switching tube 135 and a sixth switching tube 136, the first end of the fifth switching tube 135 is connected to the first control signal SAP, the second end of the fifth switching tube 135 is connected to the power signal VBLH, The third terminal of the fifth switching transistor 135, the second terminal of the first switching transistor 131 and the second terminal of the third switching transistor 133 are connected to form a first reference signal terminal.
  • the first terminal of the sixth switching tube 136 is connected to the second control signal SAN, the second terminal of the sixth switching tube 136 is connected to the ground signal GND, the second terminal of the sixth switching tube 136, the third terminal of the second switching tube 132 terminal is connected to the third terminal of the fourth switch tube 134 to form a second reference signal terminal.
  • the first switch tube 131, the third switch tube 132, and the fifth switch tube 135 are P-type field effect transistors, the first end of the P-type field effect transistor is a gate pin, and the second end of the P-type field effect transistor is is the source pin, the third end of the P-type field effect transistor is the drain pin; the second switch tube 132, the fourth switch tube 134 and the sixth switch tube 136 are N-type field effect tubes, and the N-type field effect tube
  • the first terminal of the NFET is the gate pin, the second terminal of the NFET is the drain pin, and the third terminal of the NFET is the source pin.
  • pre-charging circuit between the first signal line 11 and the second signal line 12
  • the path is used for precharging the first reference signal terminal and the second reference signal terminal.
  • the signal amplification speed of the sense amplifier 10 is slow, the circuit is prone to noise, and the power consumption is high, which affects the performance of the semiconductor memory.
  • An embodiment of the present disclosure provides a control amplification circuit, including: a power consumption control circuit, configured to receive a power consumption control signal, and output a first reference signal according to the power consumption control signal; an isolation circuit, configured to determine the control instruction signal , and generate an isolation control signal according to the control instruction signal; an amplification circuit, configured to receive the first reference signal, the isolation control signal and the signal to be processed, and based on the first reference signal and the isolation control signal The signal to be processed is processed to obtain a target amplified signal. In this way, by controlling the amplifying circuit, the first reference signal can be adjusted according to the power consumption control signal, thereby reducing power consumption of the circuit.
  • FIG. 2 shows a schematic diagram of the composition and structure of a control amplifier circuit 20 provided by an embodiment of the present disclosure.
  • the control amplifier circuit 20 may include:
  • a power consumption control circuit 21 configured to receive a power consumption control signal, and output a first reference signal according to the power consumption control signal;
  • the isolation circuit 22 is used to determine the control instruction signal, and generate an isolation control signal according to the control instruction signal;
  • the amplifying circuit 23 is configured to receive the first reference signal, the isolated control signal and the signal to be processed, and process the signal to be processed based on the first reference signal and the isolated control signal to obtain a target amplified signal.
  • control amplifier circuit 20 provided by the embodiment of the present disclosure can be applied in various signal amplification scenarios, such as a sense amplifier in a DRAM.
  • the control amplifier circuit 20 receives the power consumption control signal, the control instruction signal and the signal to be processed from the outside, completes the signal amplification process based on the power consumption control signal and the control instruction signal, and finally obtains the target amplified signal.
  • both the power consumption control signal and the control command signal need to be determined according to the specific working stage of the amplifier circuit.
  • the control amplifier circuit 20 through the power consumption control circuit 21, output the first reference signal according to the power consumption control signal; through the isolation circuit 22, output the isolation control signal according to the control command signal and the isolated power supply value;
  • the amplifying circuit 23 amplifies the signal to be processed according to the first reference signal and the isolation control signal, and outputs a target amplified signal.
  • the power consumption control circuit is provided in the control amplifier circuit, the specific voltage value of the first reference signal can be adjusted according to the power consumption control signal, the signal amplification process can be optimized, and the power consumption of the circuit can be reduced.
  • the power consumption control circuit 21 includes a first control circuit 211 and a second control circuit 212, and the power consumption control signal includes a first power consumption control signal and a second power consumption control signal. Two power consumption control signals; where,
  • the first control circuit 211 is configured to receive a first power consumption control signal, and output a first reference control signal having a first voltage value when the first power consumption control signal is in a first level state;
  • the second control circuit 212 is configured to receive a second power consumption control signal, and output a first reference control signal having a second voltage value when the second power consumption control signal is in a first level state;
  • the first voltage value is higher than the second voltage value.
  • the first level state is opposite to the second level state, and the specific voltage range of the first level state (or the second level state) needs to be determined for a specific electronic device.
  • the first level state can make it in an on state, and the second level state can make it in an off state;
  • the first level state can make it in an off state;
  • the level state enables it to be in an off state, and the second level state enables it to be in an on state.
  • the first level states of different switch tubes may be in different voltage ranges.
  • the first level state may be represented by logic "1"
  • the second level state may be represented by logic "0".
  • the first reference signal can be at least the first voltage value or the second voltage value, and can also have more voltage values.
  • the control circuit provides more control means, optimizes the signal amplification process, and reduces circuit power consumption.
  • FIG. 4A is a schematic structural diagram of a power consumption control circuit 21 provided by an embodiment of the present disclosure.
  • the first control circuit 211 includes a plurality of first control subcircuits (such as a first control circuit 211a, a first control subcircuit 211b), and the first control subcircuit includes a first switch tube (such as a first switch tube 301a, the first switch tube 301b) and the second switch tube 302 (such as the second switch tube 302a, the second switch tube 302b); wherein,
  • the first end of the first switch tube is used to receive the first power consumption control signal (such as the first power consumption control signal pdn3, the first power consumption control signal pdn2), the third end of the first switch tube, the second switch tube
  • the first end is connected to the second end of the second switching tube
  • the third end of the second switching tube is connected to the ground signal
  • the second ends of the second switching tubes in the plurality of first control sub-circuits are connected to each other, for example, the first The second end of the second switch tube 302a and the second switch tube 302b is in a connected state;
  • the second end of the first switch tube is used to output the first reference signal NCS.
  • first control subcircuits are shown in FIG. 4A , but there may be more or less first control subcircuits in actual application scenarios.
  • first power consumption control signals there are also multiple first power consumption control signals, and one first power consumption control signal is input into one first control subcircuit.
  • the respective level states of different first power consumption control signals may be the same or different.
  • a first control sub-circuit is independently controlled by a first power consumption control signal.
  • both the first switching transistor and the second switching transistor are N-type field effect transistors.
  • the first terminal of the NFET is a gate pin
  • the second terminal of the NFET is a drain pin
  • the third terminal of the NFET is a source pin.
  • Vt refers to the threshold voltage of the second switch tube 302a and the second switch tube 302b.
  • Vt refers to the higher one of the gate turn-on voltage of the second switch 302a and the threshold voltage of the second switch 302b.
  • the second switch tube Through the setting of the second switch tube, the current flowing through the first switch tube is reduced, and the special connection of the second switch tube causes the current flowing through the second switch tube to be extremely small, the power consumption is very low, and it can provide NCS terminal Stable first voltage value Vt.
  • the speed of voltage pull-down can also be controlled, thereby reducing the noise generated when the signal level drops during the signal amplification process.
  • FIG. 4B is a schematic structural diagram of another power consumption control circuit 21 provided by an embodiment of the present disclosure.
  • a switch is provided between the third end of the first switch tube and the first end of the second switch tube, and the control end of the switch is connected to the power saving control signal; wherein, the first power consumption control signal is In the first level state, the switch is controlled to be in the closed state by the power saving control signal.
  • the second control circuit 212 includes a plurality of second control subcircuits (such as a second control subcircuit 212a, a second control subcircuit 212b), and the second control subcircuit
  • the circuit includes a third switch tube (such as the third switch tube 303a, the third switch tube 303b); wherein,
  • the first end of the third switch tube is used to receive the second power consumption control signal (such as the second power consumption control signal pdn0, the second power consumption control signal pdn1), the third end of the third switch tube is connected to the ground signal, and the second switch tube is connected to the ground signal.
  • the second terminals of the three switch transistors are used to output the first reference signal NCS.
  • FIG. 4A and FIG. 4B each show two second control subcircuits, but in actual application scenarios, there may be more or fewer second control subcircuits.
  • there are multiple second power consumption control signals and one second power consumption control signal is input into one second control subcircuit.
  • the respective level states of different second power consumption control signals may be the same or different.
  • a second control sub-circuit is independently controlled by a second power consumption control signal.
  • the third switching transistors are all N-type field effect transistors.
  • both the third switch tube 303a and the third switch tube 303b are turned on, and the second switch tube 303b is turned on.
  • the potential of a reference signal is pulled down to the second voltage value Vss. Since the third end of the third switch tube is connected to the ground potential, the second voltage value Vss can also be referred to as the ground potential.
  • the speed of voltage pull-down can also be controlled, thereby reducing the noise generated when the signal level drops during the signal amplification process.
  • the power consumption control circuit 21 further includes a control signal generation circuit 213; wherein,
  • the control signal generating circuit includes a plurality of first inverters (such as a first inverter 321a, a first inverter 321b, a first inverter 321c, and a first inverter 321d), and the first inverters are used for Receive initial control signals (such as initial control signal IDD3P0, initial control signal IDD3P1, initial control signal IDD3P2, initial control signal IDD3P3), and generate power consumption control signals (such as first power consumption control signal pdn3, first power consumption control signal pdn2 , the second power consumption control signal pdn1, and the second power consumption control signal pdn0).
  • initial control signals such as initial control signal IDD3P0, initial control signal IDD3P1, initial control signal IDD3P2, initial control signal IDD3P3
  • power consumption control signals such as first power consumption control signal pdn3, first power consumption control signal pdn2 , the second power consumption control signal pdn1, and the second power consumption control signal
  • one first inverter is used to output a first power consumption control signal, or is used to output a second power consumption control signal.
  • the first power consumption control signal of each first control subcircuit is output through one first inverter, and the second power consumption control signal of each second control subcircuit output through a first inverter.
  • first inverters are shown in FIG. 4a , but there may be more or fewer first inverters in actual application scenarios.
  • there are multiple initial control signals and one initial control signal is input into one first inverter.
  • the respective level states of different initial control signals may be different.
  • a first inverter is controlled solely by an initial control signal.
  • the first inverter 321a when both the initial control signal IDD3P0 and the initial control signal IDD3P1 are in the second level state, the first inverter 321a outputs the second power consumption control signal pdn0 in the first level state, and the first inverter 321b outputs the second power consumption control signal pdn1 in the first level state, so that the third switch tube 303a and the third switch tube 303b are turned on, and the first reference signal is pulled down to the second voltage value Vss.
  • the first inverter 321b outputs the first power consumption control signal pdn1 in the second level state
  • the first inverter 321c outputs the first power consumption control signal in the first level state
  • the power consumption control signal pdn2 the first inverter 321d outputs the second power consumption control signal pdn3 in the first level state, so that the first switch tube 301a and the first switch tube 301b are turned on, and the third switch tube 303a and the The third switch tube 303b is turned off, and the first reference signal is pulled down to the first voltage value Vt.
  • the source-drain voltage difference of the first switch tube 301a becomes smaller, and the current flowing through the first switch tube 301a also becomes smaller, and the power of the first switch tube 301a is lower than that of the third switch tube 303a.
  • the power of the first switching tube 301b is also reduced compared to that of the third switching tube 303b.
  • the input end of the first inverter is also connected to the power signal Vncsg.
  • the second inverter When the initial control signal is in the second level state, the second inverter outputs the power consumption control signal in the first level state according to the power signal Vncsg, and in the case that the initial control signal is in the first level state, The second inverter outputs the power consumption control signal in the second level state.
  • FIG. 5 it shows a schematic structural diagram of an inverter provided by an embodiment of the present disclosure.
  • the first inverter 321a can be implemented by an N-type field effect transistor and a P-type field effect transistor.
  • the first reference signal can be controlled to be pulled down to the first voltage value or the second voltage value, so as to subsequently optimize the signal processing process and reduce circuit power consumption.
  • control amplifier circuit 20 further includes a reference control circuit 24;
  • a reference control circuit 24 configured to determine a reference control signal, and output a second reference signal according to the reference control signal
  • the amplification circuit 23 is also used to receive the first reference signal, the second reference signal, the isolated control signal and the signal to be processed, and process the signal to be processed based on the first reference signal, the second reference signal and the isolated control signal to obtain the Target amplified signal.
  • the first reference signal can provide the amplifying circuit 23 with a low reference potential
  • the second reference signal can provide the amplifying circuit 23 with a high reference potential, so that the amplifying circuit 23 can process the signal according to the high reference potential and the low reference potential. Perform magnification.
  • the first reference signal when used as the low reference potential, its specific voltage value may be the first voltage value Vt or the second voltage value Vss. Since the first voltage value Vt is higher than the second voltage value Vss, the source-drain voltage difference of the first switch tube 301a decreases, and the current flowing through the first switch tube 301a will also decrease relative to the current flowing through the third switch tube 303a , so that when one terminal of the amplifying circuit 23 is kept at a low reference potential, the operating current of the first control circuit is reduced, and the amplifying circuit 23 can save a part of power consumption during the signal amplification process.
  • FIG. 6A shows a schematic structural diagram of a reference control circuit 24 provided by an embodiment of the present disclosure.
  • the reference control circuit 24 includes a plurality of third control subcircuits (such as a third control subcircuit 241a, a third control subcircuit 241b, and a third control subcircuit 241c), and the third control subcircuit includes a third control subcircuit.
  • Four switch tubes such as the fourth switch tube 304a, the fourth switch tube 304b, and the fourth switch tube 304c); wherein,
  • One end of the fourth switch tube is connected to the reference control signal (for example, reference control signal pup1, reference control signal pup2, reference control signal pup3), and the second end of the fourth switch tube is connected to the first preset power supply (for example, the first preset power supply Vblh1, the first preset power supply Vblh2, and the first preset power supply Vblh3) are connected, and the third end of the fourth switching transistor is used to output the second reference signal PCS.
  • the reference control signal for example, reference control signal pup1, reference control signal pup2, reference control signal pup3
  • the first preset power supply for example, the first preset power supply Vblh1, the first preset power supply Vblh2, and the first preset power supply Vblh3
  • third control sub-circuits are shown in FIG. 6A , but there may be more or less fourth switch tubes in actual application scenarios.
  • there are multiple reference control signals and one reference control signal corresponds to one third control subcircuit.
  • the level states of the multiple reference control signals may be different, that is, the respective level states of the reference control signal pup1 , the reference control signal pup2 , and the reference control signal pup3 change independently. That is to say, a third control sub-circuit is independently controlled by a reference control signal.
  • the fourth switch transistor may be an N-type field effect transistor. Therefore, taking the fourth switching tube 304a as an example, when the second reference control signal pup1 is at the second level state, the fourth switching tube 304a is turned off; when the first reference control signal pup1 is at the first level In the state, the fourth switch 304a is turned on, and the turned-on fourth switch will charge the second reference signal PCS according to the first preset power supply Vblh1, thereby providing a high voltage for the second level state. reference potential.
  • different fourth switching transistors are respectively connected to a separate third preset power supply, and the voltage values of these third preset power supplies may be different, so as to provide different voltage rising speeds of the second reference signal PCS.
  • the voltage rising speed can also be controlled. In this way, the noise generated when the signal level rises during the signal amplification process can be reduced by controlling the voltage rise speed to be different.
  • FIG. 6B shows a schematic structural diagram of another reference control circuit 24 provided by an embodiment of the present disclosure.
  • the reference control circuit 24 includes a plurality of signal processing subcircuits (such as a signal processing subcircuit 242a, a signal processing subcircuit 242b, and a signal processing subcircuit 242c) and a plurality of third control subcircuits (such as a third control subcircuit subcircuit 241a, the third control subcircuit 241b, the third control subcircuit 241c); wherein,
  • the signal processing subcircuit includes a plurality of second inverters (such as a second inverter 322a, a second inverter 322b, and a second inverter 322c), and the second inverters are used to receive an initial reference signal (such as an initial Reference signal Vpu1, initial reference signal Vpu2, initial reference signal Vpu3), and generate reference control signals (such as reference control signal pup1, reference control signal pup2, reference control signal pup3);
  • an initial reference signal such as an initial Reference signal Vpu1, initial reference signal Vpu2, initial reference signal Vpu3
  • reference control signals such as reference control signal pup1, reference control signal pup2, reference control signal pup3
  • the third control subcircuit includes a fourth switching tube (such as the fourth switching tube 304a, the fourth switching tube 304b, and the fourth switching tube 304c), the first end of the fourth switching tube is connected to the reference control signal, and the fourth switching tube
  • the second terminal is connected to the first preset power supply (such as the first preset power supply Vblh1, the first preset power supply Vblh2, and the first preset power supply Vblh3), and the third terminal of the fourth switching tube is used to output the second reference signal PCS.
  • the multiple signal processing sub-circuits correspond to the multiple third control sub-circuits one-to-one.
  • the reference control signal is obtained through a second inverter according to the initial control signal, so as to match the control logic in different application scenarios.
  • an initial reference signal is input into a second inverter, so that a second inverter outputs a reference control signal, and a reference control signal is independently input into a fourth switch tube.
  • the fourth switching tube 304a when the initial control signal Vpu1 is in the first level state, the reference control signal pup1 is in the second level state, and the fourth switching tube 304a is turned off; the initial control signal Vpu1 is In the case of the second level state, the reference control signal pup1 is in the first level state, and the fifth switch tube 304a is turned on. In this way, the turned-on fourth switch tube will charge the second reference signal PCS according to the first preset power supply Vblh1 , so as to provide a high reference potential for the amplifying circuit 23 .
  • the first reference signal and the second reference signal are also connected to a fourth preset power supply, which can maintain the first reference signal and the second reference signal at the reference voltage when the power consumption control signal and the reference control signal are all in the second level state. value.
  • the first voltage value is lower than the reference voltage value, and the first voltage value is lower than half of the fourth voltage value, so as to ensure the accuracy of data reading.
  • the input end of the third inverter is also connected to the power signal Vpcsg.
  • the second inverter When the initial control signal is in the second level state, the second inverter outputs the reference control signal in the first level state according to the power supply signal; in the case that the initial control signal is in the first level state, the second The inverter outputs the reference control signal in the second level state.
  • the second inverter 322a can be implemented by an N-type field effect transistor and a P-type field effect transistor.
  • the isolation circuit 22 includes a first signal determination circuit 221, a power output circuit 222, a second signal determination circuit 223 and an isolation control circuit 224; wherein,
  • the first signal determination circuit 221 is configured to output the first power switching signal and/or the second power switching signal according to the preset operation instruction after receiving the preset operation instruction;
  • a power supply output circuit 222 configured to output an isolated power supply value according to the first power supply switching signal and/or the second power supply switching signal
  • the second signal determination circuit 223 is configured to output a control instruction signal according to the preset operation instruction after receiving the preset operation instruction;
  • the isolation control circuit 224 is configured to receive an isolation power supply value and a control instruction signal, and generate an isolation control signal.
  • the preset operation command may be a read command, a write command or a refresh command.
  • the isolation control signal is generated according to the isolated power supply value and preset operation instructions, and the voltage of the isolated power supply value can be determined according to the first power switching signal and/or the second power switching signal, the first power switching The signal and/or the second power switching signal is denoted in FIG. 3 as a power switching signal.
  • the isolated power supply value can be controlled by using the power supply switching signal, and the specific voltage value of the isolated power supply value can be adjusted by changing the power supply switching signal, and then the specific voltage value of the isolated control signal can be optimized to optimize the signal amplification process and partially improve the signal
  • the amplification speed is slow and the noise is easy to generate.
  • the power output circuit 222 is provided by taking the power switching signal including both the first power switching signal and the second power switching signal as an example.
  • the power supply output circuit is configured to determine that the isolated power supply value has a third voltage value when the first power supply switching signal has a second level state and the second power supply switching signal has a first level state; or When the first power switching signal has a first level state and the second power signal has a second level state, it is determined that the isolated power supply value has a fourth voltage value.
  • both the third voltage value and the fourth voltage value belong to the first level state, and the third voltage value is greater than the fourth voltage value.
  • the power output circuit 222 can output two isolated power values with different voltage values instead of a power signal with a fixed voltage value.
  • more control means can be provided by adjusting the voltage value of the isolated power supply, thereby partially improving the problems of slow signal amplification speed and large circuit noise.
  • the isolation control circuit is specifically configured to determine that the isolation control signal has a third voltage value when the control instruction signal has a first level state and the isolation power supply value has a third voltage value;
  • the fifth voltage value belongs to the second level state, and the fifth voltage value is smaller than the fourth voltage value.
  • the isolation control signal when the control instruction signal is in the first level state, the isolation control signal is in the first level state, and the isolation control signal has the same voltage value as the isolation voltage value;
  • the control command signal has the second level state, the control command signal is in the second level state, or the control command signal has a fifth voltage value.
  • both the third voltage value and the fourth voltage value may be represented as logic "1", and the fifth voltage value may be represented as logic "0".
  • the above is only a schematic description, and does not have actual limiting content.
  • FIG. 7 shows a schematic structural diagram of an isolation circuit 22 provided by an embodiment of the present disclosure.
  • the power output circuit 222 may include a second preset power supply VisoH, a third preset power supply VisoL, a fifth switch tube 305 and a sixth switch tube 306; wherein,
  • the first end of the fifth switching tube 305 is connected to the first power switching signal, and the first end of the sixth switching tube 306 is connected to the second power switching signal;
  • the second end of the fifth switching tube 305 is connected to the second preset power supply VisoH, and the second end of the sixth switching tube 306 is connected to the third preset power supply VisoL;
  • the third terminal of the fifth switching transistor 305 is connected to the third terminal of the sixth switching transistor 306 for outputting the isolated power supply value VisoInt.
  • the second preset power supply VisoH is used to output the third voltage value
  • the third preset power supply VisoL is used to output the fourth voltage value
  • the fifth switching transistor 305 and the sixth switching transistor 306 are both P-type field effect transistors.
  • the first end of the P-type field effect transistor is a gate pin
  • the second end of the P-type field effect transistor is a source pin
  • the third end of the P-type field effect transistor is a drain pin.
  • the fifth switch tube 305 is turned on and the sixth switch tube 306 is turned off, so the isolated power supply
  • the value VisoInt is the same as the voltage value of the second preset power supply VisoH, that is, the isolated power supply value VisoInt is the third voltage value; when the first power switching signal is in the first level state and the second power switching signal is in the second level state , the fifth switch 305 is turned off and the sixth switch 306 is turned on, so the isolated power supply value VisoInt is the same as the voltage value of the third preset power supply VisoL, that is, the isolated power supply value VisoInt is the fourth voltage value.
  • the isolation control circuit 224 may include a third inverter 323, a seventh switching transistor 307, and an eighth switching transistor 308; wherein,
  • the input end of the third inverter 323 is connected to the output end of the second signal determination circuit 223, and receives the control instruction signal output by the second signal determination circuit 223, and the output end of the third inverter 323 is respectively connected to the seventh switch tube 307
  • the first end of the eighth switch tube 308 is connected to the first end;
  • the second terminal of the seventh switching tube 307 is connected to the isolated power supply value VisoInt, and the third terminal of the eighth switching tube 308 is connected to the ground signal;
  • the third end of the seventh switch tube 307 is connected to the second end of the eighth switch tube 308 for outputting the isolation control signal Iso.
  • the seventh switch transistor 307 is a P-type field effect transistor
  • the eighth switch transistor 308 is an N-type field effect transistor.
  • the seventh switch tube 307 is in the on state, and the eighth switch tube 308 is in the off state, thereby isolating the voltage value of the control signal Iso and the voltage of the isolated power supply value
  • the value VisoInt is the same, that is, the third voltage value or the fourth voltage value; when the control instruction signal is in the second level state, the seventh switch tube 307 is in the off state, and the eighth switch tube 308 is in the conduction state, thus
  • the isolated control signal Iso has a fifth voltage value, which is equivalent to the ground potential.
  • the isolation control signal Iso can also be controlled to a higher voltage (third voltage value) or a lower voltage (fourth voltage value). , to adapt to the voltage requirements and signal transmission speed of different amplification stages, and then optimize the signal amplification process, increase the signal amplification speed, and reduce circuit noise.
  • the amplifier circuit 23 also needs to be connected to the bit line/complementary bit line.
  • the potentials on the bit line and the complementary bit line are the same.
  • the memory cell on the bit line is turned on, the memory cell shares the charge with the bit line, so that the potential on the bit line rises or falls to form a signal to be processed; at the same time, the memory cell on the complementary bit line is always off, so The potential on the complementary bit line remains unchanged, forming a reference signal to be processed. Due to the rise and fall of the potential on the bit line, the voltage difference between the bit line and the complementary bit line will change, so some devices in the amplifying circuit 23 are turned on to amplify the signal to be processed to obtain the target amplified signal.
  • the isolation control signal Iso is set to the fourth voltage value, so that the voltage of the bit line or the complementary bit line rises slowly, and no large noise is generated, thereby affecting the stored data of adjacent memory cells. , so the sensing amplitude of the amplifying circuit 23 can be increased, but the internal nodes of the amplifying circuit 23 can quickly reach the low reference potential or the high reference potential.
  • the isolation control signal Iso is set at the third voltage value, and the voltage flowing through the bit line or the complementary bit line becomes larger. Since the internal node voltage of the amplifying circuit 23 has changed, the bit line or the complementary bit line will be pulled high quickly. Or pull it down to increase the signal amplification speed and suppress the noise when the potential of the bit line or the complementary bit line rises.
  • the amplifying circuit 23 completes the signal amplifying process, for details, refer to the subsequent content.
  • FIG. 8 shows a schematic structural diagram of an amplification circuit 23 provided by an embodiment of the present disclosure.
  • the amplifying circuit 23 may include a ninth switch tube 309, a tenth switch tube 310, an eleventh switch tube 311, and a twelfth switch tube 312, and the control circuit 232 includes a thirteenth switch tube 313 and a tenth switch tube 312.
  • the first end of the ninth switch tube 309 is connected to the third end of the thirteenth switch tube 313 for receiving the signal to be processed, the second end of the ninth switch tube 309, the third end of the eleventh switch tube 311 , the first end of the twelfth switch tube 312 is connected to the second end of the fourteenth switch tube 314;
  • the first end of the tenth switch tube 310 is connected to the third end of the fourteenth switch tube 314 for receiving the reference signal to be processed, the second end of the tenth switch tube 310, the third end of the twelfth switch tube 312
  • the first end of the eleventh switch tube 311 is connected to the second end of the thirteenth switch tube 313;
  • the third terminal of the ninth switching tube 309 and the third terminal of the tenth switching tube 310 are connected to the first reference signal NCS, and the second terminal of the eleventh switching tube 311 and the second terminal of the twelfth switching tube 312 are connected to the first reference signal NCS.
  • the second reference signal PCS is connected, and the first end of the thirteenth switching transistor 313 and the first end of the fourteenth switching transistor 314 are connected to the isolation control signal Iso.
  • the ninth switch tube 309, the tenth switch tube 310, the thirteenth switch tube 313 and the fourteenth switch tube 314 are N-type field effect transistors, and the eleventh switch tube 311 and the twelfth switch tube 312 It is a P-type field effect transistor.
  • the isolation control signal Iso when the isolation control signal Iso is in the first level state (with the third voltage value or the fourth voltage value), the thirteenth switch tube 313 and the fourteenth switch tube 314 are turned on, and the isolation control When the signal Iso is in the second level state (with the fifth voltage value), the thirteenth switch 313 and the fourteenth switch 314 in the control circuit 232 are turned off.
  • the amplifying circuit 23 In the process of signal amplification, the amplifying circuit 23 will be in different working stages, and it is necessary to transmit the signal to be processed and the reference signal to be processed to the amplifying circuit 23 through the isolation control signal Iso to speed up the amplifying process of the amplifying circuit 23, so the isolation control The signal Iso will affect the signal amplification process.
  • the isolation control signal Iso provided in the embodiment of the present disclosure has three voltage values. By adjusting the voltage value of the isolation control signal Iso to be suitable for the amplification circuit 23 in different working stages, the signal amplification process can be optimized, thereby improving the signal amplification. The problem of slow speed and large circuit noise.
  • the amplifying circuit 23 further includes a pre-charging circuit, and the pre-charging circuit includes a fifteenth switch tube 315 and a sixteenth switch tube 316; wherein,
  • the first end of the fifteenth switching tube 315 and the first end of the sixteenth switching tube 316 are connected to the pre-charging signal Eq;
  • the second end of the fifteenth switching tube 315 is connected to the fourth preset power supply, and the third end of the fifteenth switching tube 315 is connected to the second end of the tenth switching tube 310;
  • the third end of the sixteenth switch transistor 316 is connected to the second end of the ninth switch transistor 309 , and the second end of the sixteenth switch transistor 316 is connected to the second end of the tenth switch transistor 310 .
  • the fifteenth switching transistor 315 and the sixteenth switching transistor 316 are both N-type field effect transistors.
  • the pre-charging circuit responds to the pre-charging signal Eq, and performs pre-charging processing for the amplifying circuit 23 according to the fourth preset power source, and makes each circuit node of the amplifying circuit 23 be at the same reference voltage value after the pre-charging processing is completed.
  • the amplifying circuit 23 further includes a noise elimination circuit, and the noise elimination circuit includes a seventeenth switch tube 317 and an eighteenth switch tube 318; wherein,
  • the first end of the seventeenth switch tube 317 and the first end of the eighteenth switch tube 318 are connected to the noise cancellation signal Nc;
  • the second end of the seventeenth switch tube 317 is connected to the second end of the ninth switch tube 309, and the third end of the seventeenth switch tube 317 is connected to the first end of the ninth switch tube 309;
  • the second end of the eighteenth switch transistor 318 is connected to the second end of the tenth switch transistor 310 , and the third end of the eighteenth switch transistor 318 is connected to the first end of the tenth switch transistor 310 .
  • the seventeenth switch transistor 317 and the eighteenth switch transistor 318 are both N-type field effect transistors. Therefore, when the noise canceling signal is in the first level state, the seventeenth switch tube 317 and the eighteenth switch tube 318 are in the on state, so that the first terminal and the third terminal of the ninth switch tube 309 are short-circuited. connected, and the first terminal and the third terminal of the tenth switch tube 310 are short-circuited, and the first reference signal NCS is controlled to be at the first voltage value Vt, and the second reference signal PCS is at a high reference potential, so that the ninth switch tube 309 and the tenth switch tube 310 to perform an offset elimination operation. In this way, the threshold value difference of the switch tube during the signal amplification process can be further eliminated, and the accuracy of sensing the signal to be processed during the amplification process can be improved.
  • FIG. 3-FIG. 9 are only exemplary structures of the control amplifier circuit, wherein the fifth switch tube 305, the sixth switch tube 306, the seventh switch tube 307, the eleventh switch tube 311 and the twelfth switch tube 312 is a P-type trench field effect transistor;
  • the first switching tube 301, the second switching tube 302, the third switching tube 303, the fourth switching tube 304, the eighth switching tube 308, the ninth switching tube 309, the tenth switching tube 310, the thirteenth switching tube 313, the The fourteenth switch tube 314, the fifteenth switch tube 315, the sixteenth switch tube 316, the seventeenth switch tube 317 and the eighteenth switch tube 318 are N-type channel field effect transistors;
  • the first terminal of the P-type channel field effect transistor is the gate terminal
  • the second terminal of the P-type channel field effect transistor is the source terminal
  • the third terminal of the P-type channel field effect transistor is the drain terminal
  • the first end of the N-type field effect transistor is a gate end
  • the second end of the N-type field effect transistor is a drain end
  • the third end of the N-type field effect transistor is a source end.
  • the selection of the above switch tubes does not constitute a limitation of the embodiments of the present disclosure.
  • the aforementioned circuit control logic can be implemented through various types of circuit devices, and specific selection can be made according to the actual application scenarios.
  • An embodiment of the present disclosure provides a control amplifier circuit.
  • the first reference signal can be a larger voltage value (first voltage value Vt) or a smaller voltage value under the premise of being a low reference potential.
  • Voltage value (second voltage value Vss) the voltage value of the first reference signal can be adjusted subsequently according to the working stage of the amplifying circuit, so as to reduce circuit power consumption;
  • the isolated power supply value, and then the isolated control circuit can output the isolated control signal with three different voltage values (third voltage value, fourth voltage value or fifth voltage value) according to the isolated power supply value.
  • the voltage of the isolated power supply value can be lowered to the second voltage value, so as to reduce the leakage phenomenon of the switching tube in the isolated control circuit, avoid the failure of the switching tube, and prolong the service life of the isolated control circuit;
  • the voltage value of the isolation control signal is adjusted to be at the third voltage value or the fourth voltage value, the voltage change speed of the isolation control circuit is accelerated, and the signal amplification process is optimized to improve the slow signal amplification speed, The problem of large circuit noise.
  • FIG. 10 shows a schematic diagram of an application scenario of a control amplifier circuit 20 provided by an embodiment of the present disclosure.
  • a bit line Bla As shown in FIG. 10 , in this application scenario, there are a bit line Bla, a complementary bit line Blb, a read bit line saBla, a complementary read bit line saBlb and a control amplifier circuit 20 .
  • a first memory cell 41 is provided on the bit line B1a, and a second memory cell 42 is provided on the complementary bit line B1b.
  • the control amplifier circuit 20 includes a power consumption control circuit 21 , an isolation circuit 22 , an amplifier circuit 23 and a reference control circuit 24 .
  • the power consumption control circuit 21 includes a plurality of first switching transistors (such as the first switching transistor 301, the first switching transistor 301b), a plurality of second switching transistors (such as the second switching transistor 302a, the second switching transistor 302b), A plurality of switches, a plurality of third switching tubes (such as the third switching tube 303a, a third switching tube 303b), a plurality of first inverters (such as the first inverter 321a, the first inverter 321b, the first inverter 321c, first inverter 321d).
  • the reference control circuit 24 includes a plurality of fourth switching tubes (such as the fourth switching tube 304a, the fourth switching tube 304b, and the fourth switching tube 304c) and multiple second inverters (such as the second inverter 322a, the second inverter 322b, second inverter 322c).
  • the isolation circuit 22 includes a first signal determination circuit 221, a second signal determination circuit 223, a second preset power supply VisoH, a third preset power supply VisoL, a fifth switch tube 305, a sixth switch tube 306, a seventh switch tube 307, The eighth switch tube 308 and the third inverter 323 .
  • the amplifier circuit 23 includes a ninth switch tube 309, a tenth switch tube 310, an eleventh switch tube 311, a twelfth switch tube 312, a thirteenth switch tube 313, a fourteenth switch tube 314, and a fifteenth switch tube 315. , the sixteenth switching tube 316 .
  • the second end of the tenth switch tube 310, the third end of the twelfth switch tube 312, the first end of the eleventh switch tube 311, and the second end of the thirteenth switch tube 313 are all connected to the read bit line On saB1a
  • the second terminal of the ninth switching tube 309, the third terminal of the eleventh switching tube 311, the first terminal of the twelfth switching tube 312 and the second terminal of the fourteenth switching tube 314 are all connected to the complementary reading On the bit line saBlb.
  • the third end of the thirteenth switching transistor 313 is connected to the first end of the ninth switching transistor 309 on the bit line Bla, and the first end of the tenth switching transistor 310 is connected to the third end of the fourteenth switching transistor 314 on the complementary
  • the thirteenth switch tube 313 connects the bit line Bla to the read bit line saBla in response to the isolation control signal Iso
  • the fourteenth switch tube 314 responds to the isolation control signal Iso to connect the complementary bit line Blb to the complementary read bit line
  • the bit line saBlb is connected.
  • the third end of the fifteenth switching transistor 315 is connected to the complementary readout bit line saBlb
  • the third end of the sixteenth switching transistor 316 is connected to the readout bit line saBla
  • the second end of the sixteenth switching transistor 316 is connected to the complementary readout bit line.
  • the bit line saBlb equalizes the bit line Bla, the complementary bit line Blb, the sense bit line saBla and the complementary sense bit line saBlb to a reference voltage value in response to the equalization signal Eq.
  • FIG. 11 shows a schematic diagram of an application scenario of another control amplifier circuit 20 provided by an embodiment of the present disclosure.
  • the amplifying circuit also has a seventeenth switch tube 317 and an eighteenth switch tube 318 .
  • the second end of the seventeenth switch transistor 317 is connected to the complementary read bit line saBlb
  • the third end of the seventeenth switch transistor 317 is connected to the bit line Bla
  • the second end of the eighteenth switch transistor 318 is connected to the read bit line saBla
  • the third end of the eighteenth switch transistor 318 is connected to the complementary bit line Blb.
  • the noise canceling signal Nc by controlling the first reference signal NCS at the first voltage Vt and the second reference signal PCS at a high reference potential, the offset canceling operation is performed on the ninth switch 309 and the tenth switch 310 .
  • the power consumption control circuit 21 is used to output the first reference signal NCS as a low reference potential to the amplifying circuit 23
  • the reference control circuit 24 is used to output the second reference signal PCS as a high reference potential to the amplifying circuit 23 .
  • the isolation circuit 22 is used to output the isolation control signal Iso to the amplification circuit 23 .
  • the amplifying circuit amplifies the signal to be processed according to the isolation control signal Iso, the first reference signal NCS, and the second reference signal PCS to obtain a target amplified signal.
  • the reference control circuit 24 also performs a precharge operation in response to the precharge signal, and performs an offset cancel operation in response to the noise cancel signal.
  • the first reference signal NCS may have a first voltage value Vt or a second voltage value Vss when it is a low reference potential
  • the isolation control signal may be a fourth voltage value or a third voltage value when it is in a first level state.
  • the isolation control signal may be a fifth voltage value when in the second level state.
  • the amplifying circuit 23 has different working phases, and each signal in different working phases (for example, isolation control signal Iso/precharge signal Eq/noise cancellation signal Nc/first reference signal NCS/second The level states of the reference signal PCS, etc.) are different so that the amplifying circuit 23 performs different tasks.
  • the amplifier circuit 23 when the amplifier circuit 23 processes the signal to be processed, it includes: a standby phase, a noise elimination phase, a first charge sharing phase, a second charge sharing phase, a signal amplification phase, and a signal feedback phase.
  • a standby phase when the amplifier circuit 23 processes the signal to be processed, it includes: a standby phase, a noise elimination phase, a first charge sharing phase, a second charge sharing phase, a signal amplification phase, and a signal feedback phase.
  • the amplifying circuit 23 If the amplifying circuit 23 is in the second charge sharing phase or the signal amplification phase or the pre-charging phase, then maintain the isolation control signal with a third voltage value; or
  • the amplifying circuit 23 If the amplifying circuit 23 is in the standby phase or the signal write-back phase, then maintain the isolation control signal with a fourth voltage value; or
  • the isolation control signal is maintained to have a fifth voltage value.
  • the amplifying circuit 23 when the amplifying circuit 23 is in the signal write-back phase, the first power consumption control signal is in the first level state, and the second power consumption control signal is in the second level state; the amplifying circuit 23 is in the standby phase or the noise elimination stage or the first charge sharing stage or the second charge sharing stage or the signal amplification stage or the pre-charging stage, the first power consumption control signal is in the second level state.
  • the isolation control signal can have different voltage values, and the problems of slow signal amplification and large circuit noise can be improved; on the other hand, by first adjusting the power consumption control signal and the second power
  • the power consumption control signal can control the voltage value of the first reference signal and reduce the power consumption of the circuit.
  • FIG. 12 shows a schematic diagram of a signal timing sequence of an amplification circuit provided by an embodiment of the present disclosure.
  • VisoInt refers to the aforementioned isolated power supply value, which can be the third voltage value VisoH and the fourth voltage value VisoL
  • Iso refers to the aforementioned isolated control signal, which can be the fifth voltage value Vss, the third voltage value VisoH , the fourth voltage value VisoL
  • Eq refers to the aforementioned precharge signal
  • Nc refers to the aforementioned noise elimination signal
  • SanEn1 refers to the aforementioned first power consumption control signal
  • SanEn2 refers to the aforementioned second power consumption control signal
  • SapEn Refers to the aforementioned reference control signal
  • WL is the turn-on signal of the storage unit.
  • NCS/PCS refers to the first reference signal/second reference signal
  • the first reference signal has a reference voltage value, the first voltage value Vt or the second voltage value Vss, and the first voltage value Vt or the second voltage value Both Vss can be referred to as a low reference potential
  • the second reference signal has a reference voltage value or a high reference potential
  • Bla refers to a bit line
  • Blb refers to a complementary bit line.
  • the isolated power supply value VisoInt maintains the fourth voltage value VisoL
  • the isolated control signal Iso maintains the fourth voltage value VisoL
  • the precharge signal Eq and the noise elimination signal Nc are in the first level state
  • the first power The power consumption control signal SanEn1, the second power consumption control signal SanEn2, the reference control signal SapEn and the word line enable signal WL are all in the second level state.
  • the thirteenth switching tubes 313 to 18th switching tubes 318 are turned on, so that the fourth preset power supply charges the amplifying circuit 23, so as to realize the voltage of each node in the amplifying circuit 23, the bit line Bla, and the complementary bit line Blb , the readout bit line saBla, the complementary readout bit line saBlb, the first reference signal NCS and the second reference signal PCS are all reference voltage values, and the reference voltage values are at a low reference potential and a high reference potential for subsequent execution of preset operations Command is ready.
  • the amplifying circuit 23 After receiving the preset operation command, the amplifying circuit 23 enters the noise elimination stage, and the isolation control signal Iso is adjusted to the fifth voltage value Vss, so that the thirteenth switch 313 and the fourteenth switch 314 are turned off.
  • the pre-charge signal Eq is adjusted to the second level state
  • the fifteenth switch tube 315 and the sixteenth switch tube 316 are turned off
  • the noise elimination signal Nc is still in the first level state, so the seventeenth switch tube 317 and the The eighteenth switch tube 318 is turned on
  • the reference control signal SapEn and the second power consumption control signal SanEn2 are first adjusted from the second level state to the first level state
  • the third switch tube 303a and the fourth switch tube 304a are turned on, Realize that the first reference signal NCS is at the second voltage value Vt, and the second reference signal PCS is at the high reference potential, thereby performing offset elimination processing on the ninth switching tube 309 and the tenth switching tube 310, eliminating the ninth switching tube 309 and
  • the second power consumption control signal SanEn2 is still in the second level state.
  • the isolation power supply value VisoInt is adjusted to the third voltage value in advance, and then the speed of the isolation control signal Iso when the voltage rises can be accelerated, and the signal processing speed can be improved.
  • the reference control signal SapEn and the second power consumption control signal SanEn2 are first adjusted to the second level state, the first reference signal NCS and the second reference signal PCS are adjusted to the reference voltage value, and the amplifying circuit 23 enters the second level state.
  • the memory cell turn-on signal WL is adjusted to a first level state, instructing to turn on the first memory cell 41 to perform charge sharing with the bit line Bla, and generate a signal to be processed. As shown in FIG.
  • a signal to be processed is generated on the bit line B1a, and at the same time, because the second storage unit 42 will not be turned on, the reference voltage value is still maintained on the complementary bit line Blb, which can be considered as There is a reference pending signal.
  • the isolation control signal Iso maintains the fifth voltage value Vss, the thirteenth switch tube 313 and the fourteenth switch tube 314 are turned off, so that the bit line Bla and the read bit line saBla are not connected, and the complementary bit line Blb is not connected to the complementary readout bit line saBlb, so as to avoid affecting the charge sharing between the first memory cell 41 and the bit line Bla.
  • the precharge signal Eq, the noise cancellation signal Nc, the first power consumption control signal SanEn1, the second power consumption control signal SanEn2 and the reference control signal SapEn are still in the second level state, and the first reference control signal NCS and the second reference The control signals PCS all have reference voltage values.
  • the amplifying circuit 23 After finishing the first charge sharing stage, the amplifying circuit 23 enters the second charge sharing stage, the isolation control signal Iso is adjusted to the third voltage value VisoH, the thirteenth switch tube 313 and the fourteenth switch tube 314 are turned on, so that the bit line Bla is connected to the read bit line saBla, and the complementary bit line Blb is connected to the complementary read bit line saBlb, so that the bit line Bla and the read bit line saBla perform charge sharing, and the complementary bit line Blb and the complementary read bit line saBlb
  • the amplifying circuit 23 receives the signal to be processed from the bit line Bla, and the amplifying circuit 23 receives the reference signal to be processed from the complementary bit line Blb.
  • the precharge signal Eq, the noise cancellation signal Nc, the first power consumption control signal SanEn1, the second power consumption control signal SanEn2 and the reference control signal SapEn are still in the second level state, and the first reference control signal NCS and the second reference The control signals PCS all have reference voltage values.
  • the amplifying circuit 20 is controlled to enter the signal amplification phase, and the second power consumption control signal SanEn2 and the reference control signal SapEn are adjusted to the first level state, so that the first reference signal NCS drops from the reference voltage value to The second voltage value Vss (low reference potential), the second reference signal PCS rises from the reference voltage value to the high reference potential, the amplifying circuit 23 amplifies the signal to be processed according to the first reference signal NCS and the second reference signal PCS, and the The voltage value of the processing signal is pulled up or down for processing to obtain the target amplified signal.
  • Vss low reference potential
  • the second reference signal PCS rises from the reference voltage value to the high reference potential
  • the amplifying circuit 23 amplifies the signal to be processed according to the first reference signal NCS and the second reference signal PCS, and the The voltage value of the processing signal is pulled up or down for processing to obtain the target amplified signal.
  • the isolation control signal Iso rises from the fourth voltage value VisoL to the third voltage value VisoH to increase the charge transmission speed, and both the precharge signal Eq and the noise canceling signal Nc maintain the second level state.
  • the signal voltage difference between the bit line Bla and the complementary bit line Blb increases.
  • the amplifying circuit 23 After the signal amplification stage is finished, the amplifying circuit 23 enters the signal write-back stage, mainly recovering the stored data in the first storage unit 41 through the amplified voltage value of the bit line Bla, so as to avoid data failure. At this time, the isolation power supply value VisoInt decreases from the third voltage value VisoH to the fourth voltage value VisoL, so that the isolation control signal Iso decreases from the third voltage value VisoH to the fourth voltage value VisoL.
  • the first power consumption control signal SanEn1 is adjusted from the second level state to the first level state
  • the second power consumption control signal SanEn2 is adjusted from the first level state to the second level state, that is, the amplifying circuit 23 enters the power saving mode (or called IDD3P mode)
  • the first reference voltage value NCS is adjusted from the second voltage value Vss to the first voltage value Vt to reduce circuit power consumption.
  • the storage unit turn-on signal WL is adjusted to a second level state, indicating that the first storage unit 41 is turned off.
  • the end time of the power saving mode may be earlier than the time when the first storage unit 41 is turned off, which accounts for about 80% of the time period of the write-back phase.
  • the first power consumption control signal SanEn1 is adjusted from the first level state to the second level state
  • the second power consumption control signal SanEn2 is adjusted from the second level state to the first level state.
  • a reference voltage value NCS is adjusted from the first voltage value Vt to the second voltage value Vss. If the target signal is pulled low, because the voltage in the bit line Bla and the first storage unit 41 is relatively low, it can be quickly adjusted from the second voltage value Vss to the first voltage value Vt, and the storage in the first storage unit 41 can be quickly Data restored to a minimum state.
  • the end time of the power-saving mode can be equal to the closing time of the first storage unit 41.
  • the end of the power-saving mode means the end of the write-back phase. If the target signal is pulled low for processing, since the voltage in the first storage unit 41 maintains the first voltage value Vt, it is low The value of the reference voltage will not affect the next data read operation.
  • the amplifying circuit 23 enters the pre-charging stage, the VisoInt isolated power supply value is first adjusted to the third voltage value VisoH and then dropped to the fourth voltage value VisoL, the isolation control signal Iso is first adjusted to the third voltage value VisoH and then dropped to the fourth voltage value VisoL, Save the power consumption of the thirteenth switch tube 303 and the fourteenth switch tube 304, and prolong the life of the device; after the isolation control signal is adjusted to the fourth voltage value VisoL, the precharge signal Eq and the noise elimination signal Nc are adjusted to the first voltage value VisoL At the same time, the first power consumption control signal SanEn1 is adjusted to the second level state, and the second power consumption control signal SanEn2 is first raised to the first level state and then restored to the second level state.
  • the first reference signal NCS drops from the first voltage value Vt to the second voltage value Vss and then rises to the reference voltage value, and the second reference signal PCS recovers from the high reference potential to the fourth voltage value.
  • the bit line Bla/complementary bit line Blb, sense bit line saBla/complementary sense bit line saBlb will return to the reference voltage value.
  • the amplifying circuit 23 After finishing the pre-charging phase, the amplifying circuit 23 enters the standby phase again to prepare for the next operation.
  • FIG. 13 shows a schematic diagram of signal timing provided by the related art.
  • the first reference signal NCS can only be a voltage value Vss (ie, a low reference potential) or a reference voltage value.
  • Vss a voltage value
  • the first reference signal NCS is a low reference potential
  • the first reference signal NCS is a reference voltage value. Indicated by the first reference control signal SanEn.
  • the first reference signal NCS in the related art needs to maintain the second voltage value Vss when it is used as a low reference potential, the power consumption of the circuit cannot be reduced.
  • the value of the isolated power supply (not shown) in the related art is a fixed voltage value, there are two voltage values of the isolated control signal Iso, which respectively belong to the first level state and the second level state, and the signal is amplified Slower speed and more circuit noise.
  • the embodiment of the present disclosure provides a control amplifier circuit and its control method. Through this embodiment, the specific implementation of the foregoing embodiments is described in detail. Decrease to the fourth voltage value VisoL, which can reduce the leakage and failure of the device and prolong the service life of the device; it can enter the power saving mode during the signal write-back stage, which can reduce the leakage and failure of the device and prolong the service life of the device; After the power mode, the first reference signal NCS is the first voltage value Vt, so the amplifying circuit 23 only needs to be pulled down to Vt instead of Vss, which can save circuit power consumption; in addition, the power consumption control circuit can also reduce the voltage during the voltage pull-down process. For example, turning on the sub-circuits in the first power consumption circuit first, and then turning on the sub-circuits in the second power consumption circuit can slow down the voltage pull-down speed and reduce noise.
  • FIG. 14 shows a schematic diagram of the composition and structure of a sense amplifier 60 provided by an embodiment of the present disclosure.
  • the sense amplifier 60 may include the control amplifier circuit 20 described in any one of the foregoing embodiments.
  • the sense amplifier 60 can include the control amplifier circuit 20 described in any one of the preceding embodiments, by setting the power consumption adjustment circuit, the specific voltage value of the first reference signal can be adjusted, thereby reducing the power consumption of the circuit; , can adjust the specific voltage value of the isolated control signal, thereby optimizing the signal amplification process, not only improving the problem of slow signal amplification, but also reducing circuit noise.
  • FIG. 15 shows a schematic structural diagram of a semiconductor memory 70 provided by an embodiment of the present disclosure.
  • the semiconductor memory 70 may include the sense amplifier 60 described in any one of the foregoing embodiments.
  • the semiconductor memory 70 may be a DRAM chip.
  • the semiconductor memory 70 includes the aforementioned sense amplifier 60
  • the sense amplifier 60 may include the control amplifier circuit 20 described in any one of the aforementioned embodiments
  • the specific voltage value of the first reference signal can be adjusted , so as to reduce the power consumption of the circuit; at the same time, through the isolation circuit, the specific voltage value of the isolation control signal can be adjusted to optimize the signal amplification process, which not only improves the problem of slow signal amplification, but also reduces circuit noise.
  • An embodiment of the present disclosure provides a control amplifier circuit, a sense amplifier, and a semiconductor memory, including: a power consumption control circuit, configured to receive a power consumption control signal, and output a first reference signal according to the power consumption control signal; an isolation circuit, For determining the control command signal, and generating an isolated control signal according to the control command signal; an amplification circuit, for receiving the first reference signal, the isolated control signal and the signal to be processed, and based on the first reference signal and processing the signal to be processed with the isolation control signal to obtain a target amplified signal.
  • the first reference signal can be adjusted according to the power consumption control signal, thereby reducing power consumption of the circuit.

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Abstract

本公开实施例提供了一种控制放大电路、灵敏放大器和半导体存储器，该控制放大电路包括：功耗控制电路，用于接收功耗控制信号，并根据所述功耗控制信号输出第一参考信号；隔离电路，用于确定控制指令信号，并根据所述控制指令信号生成隔离控制信号；放大电路，用于接收所述第一参考信号、所述隔离控制信号和待处理信号，并基于所述第一参考信号和所述隔离控制信号对所述待处理信号进行处理，得到目标放大信号。

Description

一种控制放大电路、灵敏放大器和半导体存储器
相关的交叉引用
本公开基于申请号为202111663568.8、申请日为2021年12月31日、发明名称为“一种控制放大电路、灵敏放大器和半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体存储器技术领域，尤其涉及一种控制放大电路、灵敏放大器和半导体存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。在数据读取的过程中，每个存储单元的读出数据信号依次经由本地数据线、全局数据线和数据总线进行读出；反之，在数据写入的过程中，则写入数据信号依次经由数据总线、全局数据线和本地数据线向存储单元写入。
目前，在存储单元和本地数据线之间存在灵敏放大器，以提高存储单元内容的信号质量。存储数据需要经过该灵敏放大器放大后读出或写入，但是信号放大过程的功耗较高。
发明内容
本公开提供了一种控制放大电路、灵敏放大器和半导体存储器，能够降低信号放大过程中的电路功耗。
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种控制放大电路，包括：
功耗控制电路，用于接收功耗控制信号，并根据所述功耗控制信号输出第一参考信号；
隔离电路，用于确定控制指令信号，并根据所述控制指令信号生成隔离控制信号；
放大电路，用于接收所述第一参考信号、所述隔离控制信号和待处理信号，并基于所述第一参考信号和所述隔离控制信号对所述待处理信号进行处理，得到目标放大信号。
在一些实施例中，所述功耗控制电路包括第一控制电路和第二控制电路，所述功耗控制信号包括第一功耗控制信号和第二功耗控制信号；其中，所述第一控制电路，用于接收所述第一功耗控制信号，并在所述第一功耗控制信号为第一电平状态时，输出具有第一电压值的所述第一参考控制信号；所述第二控制电路，用于接收所述第二功耗控制信号，并在所述第二功耗控制信号为第一电平状态时，输出具有第二电压值的所述第一参考控制信号；其中，所述第一电压值高于所述第二电压值。
在一些实施例中，所述第一控制电路包括多个第一控制子电路，所述第一控制子电路包括第一开关管和第二开关管；其中，所述第一开关管的第一端用于接收所述第一功耗控制信号，所述第一开关管的第三端、所述第二开关管的第一端和所述第二开关管的第二端连接，所述第二开关管的第三端与地信号连接，且多个所述第一控制子电路中的第二开关管的第二端相互连接；所述第一开关管的第二端用于输出所述第一参考信号。
在一些实施例中，所述第一开关管的第三端和所述第二开关管的第一端之间设置开关，且所述开关的控制端与省电控制信号连接；其中，在所述第一功耗控制信号为第一电平状态时，通过所述省电控制信号控制所述开关处于闭合状态。
在一些实施例中，所述第二控制电路包括多个第二控制子电路，且所述第二控制子电路包括第三开关管；其中，所述第三开关管的第一端用于接收所述第二功耗控制信号，所述第三开关管的第三端与地信号连接，所述第三开关管的第二端用于输出所述第一参考信号。
在一些实施例中，所述功耗控制电路还包括控制信号生成电路；其中，所述控制信号生成电路包括多个第一反向器，且所述第一反向器用于接收初始控制信号，并生成功耗控制信号；其中，在所述多个第一反向器中，每个所述第一控制子电路的所述第一功耗控制信号通过一个所述第一反向器输出，每个所述第二控制子电路的所述第二功耗控制信号通过一个所述第一反向器输出。
在一些实施例中，所述控制放大电路还包括参考控制电路；所述参考控制电路，用于确定参考控制信号，并根据所述参考控制信号输出第二参考信号；所述放大电路，还用于接收所述第一参考信号、所述第二参考信号、所述隔离控制信号和待处理信号，并基于所述第一参考信号、所述第二参考信号和所述隔离控制信号对所述待处理信号进行处理，得到所述目标放大信号。
在一些实施例中，所述参考控制电路包括多个第三控制子电路，且所述第三控制子电路包括第四开关管；其中，所述第四开关管的一端与所述参考控制信号连接，所述第四开关管的第二端与第一预设电源连接，所述第四开关管的第三端用于输出所述第二参考信号。
在一些实施例中，所述参考控制电路包括多个信号处理子电路和多个第三控制子电路；其中，所述信号处理子电路包括第二反向器，且所述第二反向器用于接收初始参考信号，并生成所述参考控制信号；所述第三控制子电路包括第四开关管，所述第四开关管的第一端与所述参考控制信号连接，所述第四开关管的第二端与第一预设电源连接，所述第四开关管的第三端，用于输出所述第二参考信号；其中，多个所述信号处理子电路和多个所述第三控制子电路一一对应。
在一些实施例中，所述隔离电路包括第一信号确定电路、电源输出电路、第二信号确定电路和隔离控制电路；其中，所述第一信号确定电路，用于在接收到预设操作指令之后，根据所述预设操作指令，输出第一电源切换信号和/或第二电源切换信号；所述电源输出电路，用于根据所述第一电源切换信号和/或所述第二电源切换信号，输出隔离电源值；所述第二信号确定电路，用于在接收到所述预设操作指令之后，根据所述预设操作指令，输出所述控制指令信号；所述隔离控制电路，用于接收隔离电源值和所述控制指令信号，生成所述隔离控制信号。
在一些实施例中，所述电源输出电路，用于在所述第一电源切换信号具有第二电平状态，且所述第二电源切换信号具有第一电平状态时，确定所述隔离电源值具有第三电压值；或者在所述第一电源切换信号具有第一电平状态且所述第二电源信号具有第二电平状态时，确定所述隔离电源值具有第四电压值；其中，所述第三电压值与所述第四电压值均属于所述第一电平状态，所述第三电压值大于所述第四电压值。
在一些实施例中，所述隔离控制电路，具体用于在所述控制指令信号具有第一电平状态且所述隔离电源值具有第三电压值的情况下，确定所述隔离控制信号具有第三电压值；或者在所述控制指令信号具有第一电平状态且所述隔离电源值具有第四电压值的情况下，确定所述隔离控制信号具有第四电压值；或者在所述控制指令信号具有第二电平状态的情况下，确定所述隔离控制信号具有第五电压值；其中，所述第五电压值属于第二电平状态，所述第五电压值小于所述第四电压值。
在一些实施例中，所述电源输出电路包括第二预设电源、第三预设电源、第五开关管和第六开关管；其中，所述第五开关管的第一端与所述第一电源切换信号连接，所述第六开关管的第一端与所述第二电源切换信号连接；所述第五开关管的第二端与所述第二预设电源连接，所述第六开关管的第二端与所述第三预设电源连接；所述第四开关管的第三端，与所述第六开关管的第三端连接，用于输出所述隔离电源值；其中，所述第二预设电源用于输出所述第三电压值，所述第三预设电源用于输出所述第四电压值。
在一些实施例中，所述隔离控制电路包括第三反向器、第七开关管和第八开关管；其中，所述第三反向器的输入端与所述控制指令信号连接，所述第三反向器的输出端分别与所述第七开关管的第一端和第八开关管的第一端连接；所述第七开关管的第二端与所述隔离电源值连接，所述第八开关管的第三端与地信号连接；所述第七开关管的第三端，与所述第八开关管的第二端连接，用于输出所述隔离控制信号。
在一些实施例中，所述放大电路包括第九开关管、第十开关管、第十一开关管、第十二开关管、第十三开关管和第十四开关管；所述第九开关管的第一端，与所述第十三开关管的第三端连接，用于接收所述待处理信号，所述第九开关管的第二端、所述第十一开关管的第三端、所述第十二开关管的第一端与第十四开关管的第二端连接；所述第十开关管的第一端，与所述第十四开关管的第三端连接，用于接收参考待处理信号，所述第十开关管的第二端、所述第十二开关管的第三端、所述第十一开关管的第一端与第十三开关管的第二端连接；所述第九开关管的第三端、所述第十开关管的第三端与第一参考信号连接，所述第十一开关管的第二端、所述第十二开关管的第二端与第二参考信号连接，所述第十三开关管的第一端、所述第十四开关管的第一端与所述隔离控制信号连接。
在一些实施例中，所述放大电路还包括预充电路，且所述预充电路包括第十五开关管和第十六开关管；其中，所述第十五开关管的第一端、所述第十六开关管的第一端与预充控制信号连接；所述第十五开关管的第二端与第四预设电源连接，所述第十五开关管的第三端与所述第十开关管的第二端连接；所述第十六开关管的第二端与所述第十开关管的第二端连接，所述第十六开关管的第三端与所述第九开关管的第二端连接。
在一些实施例中，所述放大电路还包括噪声消除电路，所述噪声消除电路包括第十七开关管和第十八开关管；其中，所述第十七开关管的第一端、第十八开关管的第一端与噪声消除信号连接；所述第十七开关管的第二端与所述第九开关管的第二端连接，所述第十七开关管的第三端与所述第九开关管的第一端连接；所述第十八开关管的第二端与所述第十开关管的第二端连接，所述第十八开关管的第三端与所述第十开关管的第一端连接。
在一些实施例中，所述放大电路对待处理信号进行处理时包括：待机阶段、噪声消除阶段、第一电荷分享阶段、第二电荷分享阶段、信号放大阶段、信号回写阶段和预充阶段；若所述放大电路处于所述第二电荷分享阶段或所述信号放大阶段或预充阶段，则维持所述隔离控制信号具有第三电压值；或者若所述放大电路处于所述待机阶段或所述信号回写阶段，则维持所述隔离控制信号具有第四电压值；或者若所述放大电路处于所述噪声消除阶段或者所述第一电荷分享阶段，则维持所述隔离控制信号具有第五电压值。
在一些实施例中，在所述放大电路处于所述信号回写阶段时，所述第一功耗控制信号处于第一电平状态，且所述第二功耗控制信号处于第二电平状态；所述放大电路处于所述待机阶段或所述噪声消除阶段或所述第一电荷分享阶段或所述第二电荷分享阶段或所述信号放大阶段或所述预充阶段时，所述第一功耗控制信号处于第二电平状态。
在一些实施例中，第五开关管、第六开关管、第七开关管、第十一开关管和第十二开关管为P型沟道场效应管；第一开关管、第二开关管、第三开关管、第四开关管、第八开关管、第九开关管、第十开关管、第十三开关管、第十四开关管、第十五开关管、第十六开关管、第十七开关管和第十八开关管为N型沟道场效应管；其中，所述P型沟道场效应管的第一端为栅极端，所述P型沟道场效应管的第二端为源极端，所述P型沟道场效应管的第三端为漏极端；所述N型沟道场效应管的第一端为栅极端，所述N型沟道场效应管的第二端为漏极端，所述N型沟道场效应管的第三端为源极端。
第二方面，本公开实施例提供了一种灵敏放大器，包括如第一方面任一项所述的控制放大电路。
第三方面，本公开实施例提供了一种半导体存储器，包括如第二方面所述的灵敏放大器。
本公开实施例提供了一种控制放大电路、灵敏放大器和半导体存储器，包括：功耗控制电路，用于接收功耗控制信号，并根据所述功耗控制信号输出第一参考信号；隔离电路，用于确定控制指令信号，并根据所述控制指令信号生成隔离控制信号；放大电路，用于接收所述第一参考信号、所述隔离控制信号和待处理信号，并基于所述第一参考信号和所述隔离控制信号对所述待处理信号进行处理，得到目标放大信号。这样，通过控制放大电路，能够根据功耗控制信号对第一参考信号进行调整，从而降低电路功耗。
附图说明
图1为一种灵敏放大器的应用场景示意图；
图2为本公开实施例提供的一种控制放大电路的组成结构示意图；
图3为本公开实施例提供的另一种控制放大电路的组成结构示意图；
图4A为本公开实施例提供的一种功耗控制电路的结构示意图；
图4B为本公开实施例提供的另一种功耗控制电路的结构示意图；
图5为本公开实施例提供的一种反向器的结构示意图；
图6A为本公开实施例提供的一种参考控制电路的结构示意图；
图6B为本公开实施例提供的另一种参考控制电路的结构示意图；
图7为本公开实施例提供的一种隔离电路的结构示意图；
图8为本公开实施例提供的一种放大电路的结构示意图；
图9为本公开实施例提供的另一种放大电路的结构示意图；
图10为本公开实施例提供的一种控制放大电路的应用场景示意图；
图11为本公开实施例提供的另一种控制放大电路的应用场景示意图；
图12为本公开实施例提供的一种放大电路的信号时序示意图；
图13为本公开实施例提供的另一种放大电路的信号时序示意图；
图14为本公开实施例提供的一种灵敏放大器的组成结构示意图；
图15为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
P型沟道场效应管：空穴型场效应管；
N型沟道场效应管：电子型场效应管。
可以理解，在DRAM的工作过程中，需要利用灵敏放大器实现多种操作过程中的信号放大。参见图1，其示出了一种灵敏放大器的应用场景示意图。如图1所示，该应用场景包括第一信号线11、第二信号线12、灵敏放大器113。其中，
第一信号线11上具有第一开关111和第一电容112，用于传入待处理信号Vin+；第二信号线12上具有第二开关121和第二电容122，用于传入参考待处理信号Vin-，待处理信号Vin+和参考待处理信号Vin-之间的压差为ΔVin，灵敏放大器113用于对待处理信号Vin+或参考待处理信号Vin-进行放大。在这里，第一开关111和第一电容112可视为一个存储单元，第二开关121和第二电容122可视为另一个存储单元。
具体地，灵敏放大器包括第一开关管131、第二开关管132、第三开关管133和第四开关管134。均与所述参考待处理信号Vin-连接，第一开关管131的第三端、第二开关管132的第二端、第三开关管133的第一端、第四开关管134的第一端均与所述待处理信号Vin+连接。该应用场景中还存在第五开关管135和第六开关管136，第五开关管135的第一端与第一控制信号SAP连接，第五开关管135的第二端与电源信号VBLH连接，第五开关管135的第三端、第一开关管131的第二端和第三开关管133的第二端连接，形成第一参考信号端。第六开关管136的第一端与第二控制信号SAN连接，第六开关管136的第二端与地信号GND连接，第六开关管136的第二端、第二开关管132的第三端和第四开关管134的第三端连接，形成第二参考信号端。其中，第一开关管131、第三开关管132、第五开关管135为P型场效应管，P型场效应管的第一端为栅极引脚，P型场效应管的第二端为源极引脚，P型场效应管的第三端为漏极引脚；第二开关管132、第四开关管134和第六开关管136为N型场效应管，N型场效应管的第一端为栅极引脚，N型场效应管的第二端为漏极引脚，N型场效应管的第三端为源极引脚。
另外，在第一信号线11和第二信号线12之间还可以存在预充电路，且第三开关管133的第二端和第四开关管134的第三端之间也可以存在预充电路，用于对第一参考信号端和第二参考信号端进行预充处理。
目前，灵敏放大器10的信号放大速度较慢、电路容易产生噪声，而且功耗较高，影响了半导体存储器的性能。
本公开实施例提供了一种控制放大电路，包括：功耗控制电路，用于接收功耗控制信号，并根据所述功耗控制信号输出第一参考信号；隔离电路，用于确定控制指令信号，并根据所述控制指令信号生成隔离控制信号；放大电路，用于接收所述第一参考信号、所述隔离控制信号和待处理信号，并基于所述第一参考信号和所述隔离控制信号对所述待处理信号进行处理，得到目标放大信号。这样，通过控制放大电路，能够根据功耗控制信号对第一参考信号进行调整，从而降低电路功耗。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图2，其示出了本公开实施例提供的一种控制放大电路20的组成 结构示意图。如图2所示，该控制放大电路20可以包括：
功耗控制电路21，用于接收功耗控制信号，并根据功耗控制信号输出第一参考信号；
隔离电路22，用于确定控制指令信号，并根据控制指令信号生成隔离控制信号；
放大电路23，用于接收第一参考信号、隔离控制信号和待处理信号，并基于第一参考信号和隔离控制信号对待处理信号进行处理，得到目标放大信号。
需要说明的是，本公开实施例提供的控制放大电路20可以应用在多种信号放大的场景中，例如DRAM中的灵敏放大器。
本公开实施例提供的控制放大电路20从外部接收功耗控制信号、控制指令信号和待处理信号，基于功耗控制信号和控制指令信号完成待处理信号放大过程，最终得到目标放大信号。在这里，功耗控制信号和控制指令信号均是需要根据放大电路所处的具体工作阶段进行确定。
具体地，对于控制放大电路20来说，通过功耗控制电路21，根据功耗控制信号，输出第一参考信号；通过隔离电路22，根据控制指令信号和隔离电源值，输出隔离控制信号；通过放大电路23，根据第一参考信号和隔离控制信号对待处理信号进行放大，输出目标放大信号。
这样，由于控制放大电路中设置了功耗控制电路，根据功耗控制信号能够对第一参考信号的具体电压值进行调整，对信号放大过程进行优化，能够减少电路功耗。
在一些实施例中，在图2的基础上，如图3所示，功耗控制电路21包括第一控制电路211和第二控制电路212，功耗控制信号包括第一功耗控制信号和第二功耗控制信号；其中，
第一控制电路211，用于接收第一功耗控制信号，并在第一功耗控制信号为第一电平状态时，输出具有第一电压值的第一参考控制信号；
第二控制电路212，用于接收第二功耗控制信号，并在第二功耗控制信号为第一电平状态时，输出具有第二电压值的第一参考控制信号；
在这里，第一电压值高于第二电压值。
需要说明的是，第一电平状态与第二电平状态相对，且第一电平状态(或第二电平状态)的具体电压范围需要针对具体电子器件确定。示例性地，对于P型场效应管来说，第一电平状态能够使其处于导通状态，第二电平状态能够使其处于关断状态；对于N型场效应管来说，第一电平状态能够使其处于关断状态，第二电平状态能够使其处于导通状态。在这里，由于不同开关管的规格不一样，不同开关管的第一电平状态可能是不相同的电压范围。为方便理解，在一种习惯性的表示方法中，第一电平状态可以用逻辑“1”表示，第二电平状态可以用逻辑“0”进行表示。
应理解，第一参考信号至少可以为第一电压值或者第二电压值，还可以具有更多的电压值。
这样，在第一控制电路接通时，第一参考控制信号的电压值为第一电压值，在第二控制电路接通时，第一参考控制信号的电压值为第二电压值，能够为控制电路提供更多的控制手段，优化信号放大过程，降低电路功耗。
在一些实施例中，在图3的基础上，参见图4A，本公开实施例提供的一种功耗控制电路21的结构示意图。如图4A所示，第一控制电路211包括多个第一控制子电路(例如第一控制电路211a、第一控制子电路211b)，第一控制子电路包括第一开关管(例如第一开关管301a、第一开关管301b)和第二开关管302(例如第二开关管302a、第二开关管302b)；其中，
第一开关管的第一端用于接收第一功耗控制信号(例如第一功耗控制信号pdn3、第一功耗控制信号pdn2)，第一开关管的第三端、第二开关管的第一端和第二开关管的第二端连接，第二开关管的第三端与地信号连接，且多个第一控制子电路中的第二开关管的第二端相互连接，例如第二开关管302a和第二开关管302b的第二端处于连接状态；
第一开关管的第二端用于输出第一参考信号NCS。
需要说明的是，图4A中示出了2个第一控制子电路，但实际应用场景中第一控制子电路可以更多或者更少。另外，第一功耗控制信号的数量也为多个，且一个第一功耗控制信号输入到一个第一控制子电路中。在这里，不同的第一功耗控制信号各自的电平状态可以是相同的，也可以是不同的。换句话说，一个第一控制子电路被一个第一功耗控制信号单独进行控制。
如图4A所示，第一开关管、第二开关管均为N型场效应管。在后续说明中，N型场效应管的第一端为栅极引脚，N型场效应管的第二端为漏级引脚，N型场效应管的第三端为源极引脚。
示例性地，在第一功耗控制信号pdn3和第一功耗控制信号pdn2均为第一电平状态的情况下，第一开关管301a和第二开关管302a均是导通的，将第一参考信号的电位下拉至第一电压值Vt，Vt是指第二开关管302a和第二开关管302b的阈值电压。在这里，如果第二开关管302a和第二开关管302b的阈值电压不同，则Vt指的是第二开关管302a的栅极开启电压和第二开关管302b阈值电压中 较高的一者。
通过第二开关管的设置，降低流经第一开关管的电流，而第二开关管的特殊连接，导致流经第二开关管的电流极小，功耗非常低，并且能够为NCS端提供稳定的第一电压值Vt。
另外，通过控制处于导通状态的第一开关管的数量，还可以控制电压下拉的速度，进而可以减少信号放大过程中信号电平降低时产生的噪声。
在一些实施例中，参见图4B，本公开实施例提供的另一种功耗控制电路21的结构示意图。如图4B所示，第一开关管的第三端和第二开关管的第一端之间设置开关，且开关的控制端与省电控制信号连接；其中，在第一功耗控制信号为第一电平状态时，通过省电控制信号控制开关处于闭合状态。
这样，通过在第一控制子电路中设置开关，并引入省电控制信号进行控制，能够更好地控制第二开关管的工作状态。
在一些实施例中，如图4A或者图4B所示，第二控制电路212包括多个第二控制子电路(例如第二控制子电路212a、第二控制子电路212b)，且第二控制子电路包括第三开关管(例如第三开关管303a、第三开关管303b)；其中，
第三开关管的第一端用于接收第二功耗控制信号(例如第二功耗控制信号pdn0、第二功耗控制信号pdn1)，第三开关管的第三端与地信号连接，第三开关管的第二端用于输出第一参考信号NCS。
需要说明的是，图4A以及图4B中各自示出了2个第二控制子电路，但实际应用场景中第二控制子电路可以更多或者更少。另外，第二功耗控制信号的数量也为多个，且一个第二功耗控制信号输入到一个第二控制子电路中。在这里，不同的第二功耗控制信号各自的电平状态可以是相同的，也可以是不同的。换句话说，一个第二控制子电路被一个第二功耗控制信号单独进行控制。如图5所示，第三开关管均为N型场效应管。
示例性地，在第二功耗控制信号pdn1和第二功耗控制信号pdn0均为第一电平状态的情况下，第三开关管303a和第三开关管303b均是导通的，将第一参考信号的电位下拉至第二电压值Vss。由于第三开关管的第三端与地电位连接，所以第二电压值Vss也可称为地电位。
另外，通过控制处于导通状态的第三开关管的数量，还可以控制电压下拉的速度，进而可以减少信号放大过程中信号电平降低时产生的噪声。
在一些实施例中，如图4A或者图4B所示，功耗控制电路21还包括控制信号生成电路213；其中，
控制信号生成电路包括多个第一反向器(例如第一反向器321a、第一反向器321b、第一反向器321c、第一反向器321d)，且第一反向器用于接收初始控制信号(例如初始控制信号IDD3P0、初始控制信号IDD3P1、初始控制信号IDD3P2、初始控制信号IDD3P3)，并生成功耗控制信号(例如第一功耗控制信号pdn3、第一功耗控制信号pdn2、第二功耗控制信号pdn1、第二功耗控制信号pdn0)。
也就是说，在这些第一反向器中，一个第一反向器用于输出一个第一功耗控制信号，或者用于输出一个第二功耗控制信号。相应地，在多个第一反向器中，每个第一控制子电路的第一功耗控制信号通过一个第一反向器输出，每个第二控制子电路的第二功耗控制信号通过一个第一反向器输出。
需要说明的是，图4a中示出了4个第一反向器，但实际应用场景中第一反向器可以更多或者更少。另外，初始控制信号的数量也为多个，且一个初始控制信号输入到一个第一反向器中。在这里，不同的初始控制信号各自的电平状态可以是不同的。换句话说，一个第一反向器被一个初始控制信号单独进行控制。
示例性地，在初始控制信号IDD3P0和初始控制信号IDD3P1均为第二电平状态时，第一反向器321a输出处于第一电平状态的第二功耗控制信号pdn0，第一反向器321b输出处于第一电平状态的第二功耗控制信号pdn1，从而第三开关管303a和第三开关管303b导通，第一参考信号被下拉至第二电压值Vss。
反之，在初始控制信号IDD3P0和初始控制信号IDD3P1均为第一电平状态，初始控制信号IDD3P2和初始控制信号IDD3P3均为第二电平状态，此时，第一反向器321a输出处于第二电平状态的第二功耗控制信号pdn0，第一反向器321b输出处于第二电平状态的第一功耗控制信号pdn1，第一反向器321c输出处于第一电平状态的第一功耗控制信号pdn2，第一反向器321d输出处于第一电平状态的第二功耗控制信号pdn3，从而第一开关管301a和第一开关管301b导通，且第三开关管303a和第三开关管303b关断，第一参考信号被下拉至第一电压值Vt。此时第一开关管301a的源漏电压差变小，流经第一开关管301a的电流也会变小，第一开关管301a的功率相对于第三开关管303a降低。第一开关管301b相对于第三开关管303b功率同样降低。
还需要说明的是，如图4A或者图4B所示，第一反向器的输入端还与电源信号Vncsg连接。在初始控制信号处于第二电平状态的情况下，第二反向器根据电源信号Vncsg输出处于第一电平状态的功耗控制信号，在初始控制信号处于第一电平状态的情况下，第二反向器输出处于第二电平状态的功耗控制信号。参见图5，其示出了本公开实施例提供的一种反向器的结构示意图。如图5(a)所示，第一反向器321a可以通过一个N型场效应管和一个P型场效应管实现。
这样，通过第一控制电路和第二控制电路，可以控制第一参考信号被下拉至第一电压值或者第二电压值，以便后续优化信号处理过程，减少电路功耗。
在一些实施例中，如图3所示，控制放大电路20还包括参考控制电路24；
参考控制电路24，用于确定参考控制信号，并根据参考控制信号输出第二参考信号；
放大电路23，还用于接收第一参考信号、第二参考信号、隔离控制信号和待处理信号，并基于第一参考信号、第二参考信号和隔离控制信号对待处理信号进行处理，得到所述目标放大信号。
需要说明的是，第一参考信号可以为放大电路23提供低参考电位，第二参考信号可以为放大电路23提供高参考电位，以便于放大电路23可以根据高参考电位和低参考电位对待处理信号进行放大处理。
应理解，在第一参考信号作为低参考电位时，其具体的电压值可以为第一电压值Vt或者第二电压值Vss。由于第一电压值Vt高于第二电压值Vss，导致第一开关管301a源漏电压差减小，并且流经第一开关管301a的电流相对于流经第三开关管303a电流也会降低，使得在维持放大电路23一端处于低参考电位时，降低第一控制电路的工作电流，放大电路23在信号放大过程中能够节省一部分功耗。
在一种具体的实施例中，在图3的基础上，参见图6A，其示出了本公开实施例提供的一种参考控制电路24的结构示意图。如图6A所示，参考控制电路24包括多个第三控制子电路(例如第三控制子电路241a、第三控制子电路241b、第三控制子电路241c)，且第三控制子电路包括第四开关管(例如第四开关管304a、第四开关管304b、第四开关管304c)；其中，
第四开关管的一端与参考控制信号(例如参考控制信号pup1、参考控制信号pup2、参考控制信号pup3)连接，第四开关管的第二端与第一预设电源(例如第一预设电源Vblh1、第一预设电源Vblh2、第一预设电源Vblh3)连接，第四开关管的第三端用于输出第二参考信号PCS。
需要说明的是，图6A中示出了3个第三控制子电路，但实际应用场景中第四开关管可以更多或者更少。另外，参考控制信号的数量也为多个，且一个参考控制信号对应一个第三控制子电路。多个参考控制信号的电平状态可以是不同的，即参考控制信号pup1、参考控制信号pup2、参考控制信号pup3各自的电平状态是单独变化的。也就是说，一个第三控制子电路被一个参考控制信号单独进行控制。
如图6A所示，第四开关管可以为N型场效应管。因此，以第四开关管304a为例，在第二参考控制信号pup1为第二电平状态的情况下，第四开关管304a是关断的；在第一参考控制信号pup1为第一电平状态的情况下，第四开关管304a是导通的，且处于导通的第四开关管将根据第一预设电源Vblh1对第二参考信号PCS进行充电，从而为第二电平状态提供高参考电位。
需要说明的是，不同的第四开关管各自连接一个单独的第三预设电源，这些第三预设电源的电压值可以不相同，以提供第二参考信号PCS不同的电压升高速度。另外，通过控制处于导通状态的第四开关管数量，也可以控制电压升高速度。这样，通过控制电压升高速度不同，可以减少信号放大过程中信号电平升高时产生的噪声。
在另一种具体的实施例中，在图3的基础上，参见图6B，其示出了本公开实施例提供的另一种参考控制电路24的结构示意图。如图6B所示，参考控制电路24包括多个信号处理子电路(例如信号处理子电路242a、信号处理子电路242b、信号处理子电路242c)和多个第三控制子电路(例如第三控制子电路241a、第三控制子电路241b、第三控制子电路241c)；其中，
信号处理子电路包括多个第二反向器(例如第二反向器322a、第二反向器322b、第二反向器322c)，且第二反向器用于接收初始参考信号(例如初始参考信号Vpu1、初始参考信号Vpu2、初始参考信号Vpu3)，并生成参考控制信号(例如参考控制信号pup1、参考控制信号pup2、参考控制信号pup3)；
第三控制子电路包括第四开关管(例如第四开关管304a、第四开关管304b、第四开关管304c)，第四开关管的第一端与参考控制信号连接，第四开关管的第二端与第一预设电源(例如第一预设电源Vblh1、第一预设电源Vblh2、第一预设电源Vblh3)连接，第四开关管的第三端，用于输出第二参考信号PCS。
在这里，多个信号处理子电路和多个第三控制子电路一一对应。
也就是说，参考控制信号是根据初始控制信号经由一个第二反向器后得到的，以匹配不同应用场景下的控制逻辑。换句话说，一个初始参考信号输入到一个第二反向器中，从而一个第二反向器输出一个参考控制信号，一个参考控制信号单独输入到一个第四开关管。
以第四开关管304a为例，在初始控制信号Vpu1为第一电平状态的情况下，参考控制信号pup1为第二电平状态，第四开关管304a是关断的；初始控制信号Vpu1为第二电平状态的情况下，参考控制信号pup1为第一电平状态，第五开关管304a是导通的。这样，处于导通的第四开关管将根据第一预设电源Vblh1对第二参考信号PCS进行充电，从而为放大电路23提供高参考电位。
第一参考信号和第二参考信号还连接有第四预设电源，能够在功耗控制信号和参考控制信号全部处于第二电平状态时，维持第一参考信号和第二参考信号在参考电压值。其中，第一电压值低于参考电压值，第一电压值低于第四电压值的一半，以保障数据读取的准确性。
需要说明的是，如图6B所示，第三反向器的输入端还与电源信号Vpcsg连接。在初始控制信号处于第二电平状态的情况下，第二反向器根据电源信号输出处于第一电平状态的参考控制信号，在初始控制信号处于第一电平状态的情况下，第二反向器输出处于第二电平状态的参考控制信号。如图5(b)所示，第二反向器322a可以通过一个N型场效应管和一个P型场效应管实现。
在一些实施例中，如图3所示，隔离电路22包括第一信号确定电路221、电源输出电路222、第二信号确定电路223和隔离控制电路224；其中，
第一信号确定电路221，用于在接收到预设操作指令之后，根据预设操作指令输出第一电源切换信号和/或第二电源切换信号；
电源输出电路222，用于根据第一电源切换信号和/或第二电源切换信号，输出隔离电源值；
第二信号确定电路223，用于在接收到预设操作指令之后，根据预设操作指令，输出控制指令信号；
隔离控制电路224，用于接收隔离电源值和控制指令信号，生成隔离控制信号。
需要说明的是，以DRAM为例，预设操作指令可以是读指令、写指令或者刷新指令。
需要说明的是，隔离控制信号是根据隔离电源值和预设操作指令生成的，且隔离电源值的电压大小可以根据第一电源切换信号和/或第二电源切换信号进行确定，第一电源切换信号和/或第二电源切换信号在图3中表示为电源切换信号进行确定。
这样，利用电源切换信号能够对隔离电源值进行控制，后续可以通过改变电源切换信号来调整隔离电源值的具体电压值大小，进而隔离控制信号的具体电压值大小，优化信号放大过程，部分改善信号放大速度慢、容易产生噪声的问题。
以下以电源切换信号同时包括第一电源切换信号和第二电源切换信号为例，提供一种电源输出电路222的可行结构。
在一些实施例中，电源输出电路，用于在第一电源切换信号具有第二电平状态，且第二电源切换信号具有第一电平状态时，确定隔离电源值具有第三电压值；或者在第一电源切换信号具有第一电平状态且第二电源信号具有第二电平状态时，确定隔离电源值具有第四电压值。
在这里，第三电压值与第四电压值均属于第一电平状态，第三电压值大于第四电压值。
这样，电源输出电路222可以输出两种不同电压值的隔离电源值，而非一种固定电压值的电源信号。这样，在放大电路23的不同工作阶段，可以通过调整隔离电源值的电压值来提供更多的控制手段，从而部分改善信号放大速度慢、电路噪声大的问题。
在一些实施例中，隔离控制电路，具体用于在控制指令信号具有第一电平状态且隔离电源值具有第三电压值的情况下，确定隔离控制信号具有第三电压值；或者
在控制指令信号具有第一电平状态且隔离电源值具有第四电压值的情况下，确定隔离控制信号具有第四电压值；或者
在控制指令信号具有第二电平状态的情况下，确定隔离控制信号具有第五电压值；
其中，第五电压值属于第二电平状态，第五电压值小于第四电压值。
需要说明的是，对于隔离电路22来说，在控制指令信号处于第一电平状态的情况下，隔离控制信号处于第一电平状态，且隔离控制信号与隔离电压值的电压值相同；在控制指令信号具有第二电平状态的情况下，控制指令信号处于第二电平状态，或者说控制指令信号具有第五电压值。
示例性地，在一种习惯性的表示方法中，第三电压值和第四电压值均可以表示为逻辑“1”，第五电压值可以表示为逻辑“0”。以上仅为示意性说明，并不具有实际限定内容。
这样，隔离控制信号存在三种不同的电压值，可以提供更多的控制手段，以便优化信号放大过 程，改善信号放大速度慢、电路噪声大的问题。
在图3的基础上，参见图7，其示出了本公开实施例提供的一种隔离电路22的结构示意图。如图7所示，电源输出电路222可以包括第二预设电源VisoH、第三预设电源VisoL、第五开关管305和第六开关管306；其中，
第五开关管305的第一端与第一电源切换信号连接，第六开关管306的第一端与第二电源切换信号连接；
第五开关管305的第二端与第二预设电源VisoH连接，第六开关管306的第二端与第三预设电源VisoL连接；
第五开关管305的第三端，与第六开关管306的第三端连接，用于输出隔离电源值VisoInt。
在这里，第二预设电源VisoH用于输出第三电压值，第三预设电源VisoL用于输出第四电压值。
需要说明的是，如图7所示，第五开关管305、第六开关管306均为P型场效应管。在后续说明中，P型场效应管的第一端为栅极引脚，P型场效应管的第二端为源级引脚，P型场效应管的第三端为漏极引脚。
需要说明的是，在第一电源切换信号处于第二电平状态且第二电源切换信号处于第一电平状态时，第五开关管305导通且第六开关管306关断，所以隔离电源值VisoInt与第二预设电源VisoH的电压值相同，即隔离电源值VisoInt为第三电压值；在第一电源切换信号处于第一电平状态且第二电源切换信号处于第二电平状态时，第五开关管305关断且第六开关管306导通，所以隔离电源值VisoInt与第三预设电源VisoL的电压值相同，即隔离电源值VisoInt为第四电压值。
在一些实施例中，如图7所示，隔离控制电路224可以包括第三反向器323、第七开关管307和第八开关管308；其中，
第三反向器323的输入端与第二信号确定电路223的输出端连接，接收第二信号确定电路223输出的控制指令信号，第三反向器323的输出端分别与第七开关管307的第一端和第八开关管308的第一端连接；
第七开关管307的第二端与隔离电源值VisoInt连接，第八开关管308的第三端与地信号连接；
第七开关管307的第三端，与第八开关管308的第二端连接，用于输出隔离控制信号Iso。
需要说明的是，第七开关管307为P型场效应管，第八开关管308为N型场效应管。
这样，在控制指令信号处于第一电平状态的情况下，第七开关管307处于导通状态，第八开关管308处于关断状态，从而隔离控制信号Iso的电压值与隔离电源值的电压值VisoInt相同，即第三电压值或者第四电压值；在控制指令信号处于第二电平状态的情况下，第七开关管307处于关断状态，第八开关管308处于导通状态，从而隔离控制信号Iso具有第五电压值，相当于接地电位。
这样，本公开实施例中，在隔离控制信号Iso处于第一电平状态的前提下，还可以控制隔离控制信号Iso为较高电压(第三电压值)或者较低电压(第四电压值)，以适应不同放大阶段的电压需求和信号传输速度，进而优化信号放大过程，提高信号放大速度，减弱电路噪声。
以DRAM为例，放大电路23还需要与位线/互补位线连接。在初始状态，位线和互补位线上的电位是相同的。在位线上的存储单元开启后，该存储单元与位线进行电荷分享，从而位线上的电位升高或者降低，形成待处理信号；同时互补位线上的存储单元始终是关闭的，因此互补位线上的电位不变，形成参考待处理信号。由于位线上的电位升高和降低，位线和互补位线之间的压差会发生变化，从而放大电路23中的部分器件接通，将待处理信号进行放大，得到目标放大信号。
放大电路23在开始放大的时候，将隔离控制信号Iso设置于第四电压值，导致位线或互补位线的电压升高缓慢，不会产生较大噪声，从而影响相邻存储单元的存储数据，因此能够提高放大电路23的感测幅度，但放大电路23内部节点却能够迅速达到低参考电位或高参考电位。在后续放大阶段将隔离控制信号Iso设置于第三电压值，流经位线或互补位线的电压变大，由于放大电路23内部节点电压已经变化，会快速将位线或互补位线拉高或拉低，提高信号放大速度，抑制位线或互补位线电位升高时的噪声。
后续，放大电路23完成信号放大过程，具体说明参见后续内容。
基于此，在一种具体的实施中，在图3的基础上，参见图8，其示出了本公开实施例提供的一种放大电路23的结构示意图。如图8所示，放大电路23可以包括第九开关管309、第十开关管310、第十一开关管311和第十二开关管312，控制电路232包括第十三开关管313和第十四开关管314；
第九开关管309的第一端，与第十三开关管313的第三端连接，用于接收待处理信号，第九开关管309的第二端、第十一开关管311的第三端、第十二开关管312的第一端与第十四开关管314的第二端连接；
第十开关管310的第一端，与第十四开关管314的第三端连接，用于接收参考待处理信号，第十开关管310的第二端、第十二开关管312的第三端、第十一开关管311的第一端与第十三开关管313的第二端连接；
第九开关管309的第三端、第十开关管310的第三端与第一参考信号NCS连接，第十一开关管311的第二端、第十二开关管312的第二端与第二参考信号PCS连接，第十三开关管313的第一端、第十四开关管314的第一端与隔离控制信号Iso连接。
需要说明的是，第九开关管309、第十开关管310、第十三开关管313和第十四开关管314为N型场效应管，第十一开关管311和第十二开关管312为P型场效应管。
这样，在隔离控制信号Iso处于第一电平状态(具有第三电压值或者第四电压值)的情况下，第十三开关管313和第十四开关管314是导通的，在隔离控制信号Iso处于第二电平状态(具有第五电压值)的情况下，控制电路232中的第十三开关管313和第十四开关管314是关断的。
在信号放大的过程中，放大电路23会处于不同的工作阶段，需要通过隔离控制信号Iso来向放大电路23传输待处理信号和参考待处理信号，以加快放大电路23的放大过程，因此隔离控制信号Iso会对信号放大过程产生影响。而本公开实施例中提供的隔离控制信号Iso具有三个电压值，通过调整隔离控制信号Iso的电压值，以适用于不同的工作阶段的放大电路23，能够优化信号放大过程，进而改善信号放大速度慢、电路噪声大的问题。
在一些实施例中，如图8所示，放大电路23还包括预充电路，且预充电路包括第十五开关管315和第十六开关管316；其中，
第十五开关管315的第一端、第十六开关管316的第一端与预充信号Eq连接；
第十五开关管315的第二端与第四预设电源连接，第十五开关管315的第三端与第十开关管310的第二端连接；
第十六开关管316的第三端与第九开关管309的第二端连接，第十六开关管316的第二端与第十开关管310的第二端连接。
在这里，第十五开关管315和第十六开关管316均为N型场效应管。
这样，预充电路响应于预充信号Eq，根据第四预设电源为放大电路23进行预充处理，在预充处理结束后使得放大电路23的各电路节点处于相同的参考电压值。
在一些实施例中，在图8的基础上，如图9所示，放大电路23还包括噪声消除电路，噪声消除电路包括第十七开关管317和第十八开关管318；其中，
第十七开关管317的第一端、第十八开关管318的第一端与噪声消除信号Nc连接；
第十七开关管317的第二端与第九开关管309的第二端连接，第十七开关管317的第三端与第九开关管309的第一端连接；
第十八开关管318的第二端与第十开关管310的第二端连接，第十八开关管318的第三端与第十开关管310的第一端连接。
在这里，第十七开关管317和第十八开关管318均为N型场效应管。因此，在噪声消除信号处于第一电平状态的情况下，第十七开关管317和第十八开关管318处于接通状态，以使得第九开关管309的第一端和第三端短接，且第十开关管310的第一端和第三端短接，并控制第一参考信号NCS处于第一电压值Vt，第二参考信号PCS处于高参考电位，从而对第九开关管309和第十开关管310进行偏移消除操作。这样，可以进一步消除信号放大过程中的开关管的阈值差异，提高放大过程中对待处理信号感测的准确性。
特别地，图3-图9仅为控制放大电路的示例性结构，其中，第五开关管305、第六开关管306、第七开关管307、第十一开关管311和第十二开关管312为P型沟道场效应管；
第一开关管301、第二开关管302、第三开关管303、第四开关管304、第八开关管308、第九开关管309、第十开关管310、第十三开关管313、第十四开关管314、第十五开关管315、第十六开关管316、第十七开关管317和第十八开关管318为N型沟道场效应管；
其中，所述P型沟道场效应管的第一端为栅极端，所述P型沟道场效应管的第二端为源极端，所述P型沟道场效应管的第三端为漏极端；所述N型沟道场效应管的第一端为栅极端，所述N型沟道场效应管的第二端为漏极端，所述N型沟道场效应管的第三端为源极端。
当然，以上开关管的选型并不构成本公开实施例的限制，在实际应用场景中，可以通过多种类型的电路器件实现前述的电路控制逻辑，可以依据实际应用场景进行具体选择。
本公开实施例提供了一种控制放大电路，一方面，通过增加功耗控制电路，第一参考信号在作为低参考电位的前提下可以为较大电压值(第一电压值Vt)或者较小电压值(第二电压值Vss)，后 续可以根据放大电路的工作阶段调整第一参考信号的电压值，以便减少电路功耗；另一方面，通过增加电源切换电路，从而提供具有两个电压值的隔离电源值，进而隔离控制电路可以根据隔离电源值输出具有三个不同电压值(第三电压值、第四电压值或者第五电压值)的隔离控制信号。在放大电路处于非工作状态时，可以将隔离电源值的电压下降至第二电压值，以减少隔离控制电路中的开关管漏电现象，避免开关管失效，能够延长隔离控制电路的使用寿命；再一方面，在放大电路工作的不同阶段，调整隔离控制信号的电压值处于第三电压值或第四电压值，加快隔离控制电路的电压变化速度，优化信号放大过程，以改善信号放大速度慢、电路噪声大的问题。
在本公开的另一实施例中，参见图10，其示出了本公开实施例提供的一种控制放大电路20的应用场景示意图。如图10所示，在该应用场景中，存在位线Bla、互补位线Blb、读出位线saBla、互补读出位线saBlb和控制放大电路20。在位线Bla上设置有第一存储单元41，在互补位线Blb上设置有第二存储单元42。
控制放大电路20包括功耗控制电路21、隔离电路22、放大电路23和参考控制电路24。其中，功耗控制电路21包括多个第一开关管(例如第一开关管301、第一开关管301b)、多个第二开关管(例如第二开关管302a、第二开关管302b)、多个开关、多个第三开关管(例如第三开关管303a、第三开关管303b)、多个第一反向器(例如第一反向器321a、第一反向器321b、第一反向器321c、第一反向器321d)。参考控制电路24包括多个第四开关管(例如第四开关管304a、第四开关管304b、第四开关管304c)和多个第二反向器(例如第二反向器322a、第二反向器322b、第二反向器322c)。隔离电路22包括第一信号确定电路221、第二信号确定电路223、第二预设电源VisoH、第三预设电源VisoL、第五开关管305、第六开关管306、第七开关管307、第八开关管308和第三反向器323。放大电路23包括第九开关管309、第十开关管310、第十一开关管311、第十二开关管312、第十三开关管313、第十四开关管314、第十五开关管315、第十六开关管316。
第十开关管310的第二端、第十二开关管312的第三端、第十一开关管311的第一端及第十三开关管313的第二端连接均连接在读出位线saBla上，第九开关管309的第二端、第十一开关管311的第三端、第十二开关管312的第一端及第十四开关管314的第二端均连接在互补读出位线saBlb上。
第十三开关管313的第三端与第九开关管309的第一端连接在位线Bla上，第十开关管310的第一端与第十四开关管314的第三端连接在互补位线Blb上，第十三开关管313响应于隔离控制信号Iso将位线Bla与读出位线saBla连接，第十四开关管314响应与隔离控制信号Iso将互补位线Blb与互补读出位线saBlb连接。
第十五开关管315的第三端与互补读出位线saBlb连接，第十六开关管316的第三端连接读出位线saBla，第十六开关管316的第二端连接互补读出位线saBlb，响应于均衡信号Eq，将位线Bla、互补位线Blb、读出位线saBla及互补读出位线saBlb均衡至参考电压值。
在该应用场景中，各器件的类型及连接关系如图9所示，且图9中各符号含义和电路的工作原理具体可参见前述内容，在此不做赘述。
在图10的基础上，参见图11，其示出了本公开实施例提供的另一种控制放大电路20的应用场景示意图。如图11所示，放大电路中还具有第十七开关管317和第十八开关管318。第十七开关管317的第二端连接互补读出位线saBlb，第十七开关管317的第三端连接位线Bla，第十八开关管318的第二端连接读出位线saBla，第十八开关管318的第三端连接互补位线Blb。响应于噪声消除信号Nc，通过控制第一参考信号NCS处于第一电压值Vt，第二参考信号PCS处于高参考电位，对第九开关管309和第十开关管310进行偏移消除操作。
简单来说，功耗控制电路21用于向放大电路23输出作为低参考电位的第一参考信号NCS，参考控制电路24用于向放大电路23输出作为高参考电位的第二参考信号PCS。隔离电路22用于向放大电路23输出隔离控制信号Iso。放大电路根据隔离控制信号Iso、第一参考信号NCS、第二参考信号PCS对待处理信号进行放大，获得目标放大信号。另外，参考控制电路24还会响应于预充信号进行预充操作，以及响应于噪声消除信号进行偏移消除操作。
在这里，第一参考信号NCS在作为低参考电位时可以具有第一电压值Vt或者第二电压值Vss，隔离控制信号在处于第一电平状态时可以为第四电压值或者第三电压值，隔离控制信号在处于第二电平状态时可以为第五电压值。
应理解，在信号放大的过程中，放大电路23具有不同的工作阶段，不同工作阶段中各信号(例如隔离控制信号Iso/预充信号Eq/噪声消除信号Nc/第一参考信号NCS/第二参考信号PCS等等)的 电平状态是不同的，以便放大电路23执行不同的任务。
示例性地，以图11的控制放大电路为例，放大电路23对待处理信号进行处理时包括：待机阶段、噪声消除阶段、第一电荷分享阶段、第二电荷分享阶段、信号放大阶段、信号回写阶段、信号稳定阶段和预充阶段；
若放大电路23处于第二电荷分享阶段或信号放大阶段或预充阶段，则维持隔离控制信号具有第三电压值；或者
若放大电路23处于待机阶段或信号回写阶段，则维持隔离控制信号具有第四电压值；或者
若放大电路23处于噪声消除阶段或者第一电荷分享阶段，则维持隔离控制信号具有第五电压值。
在一些实施例中，在放大电路23处于信号回写阶段时，第一功耗控制信号处于第一电平状态，且第二功耗控制信号处于第二电平状态；放大电路23处于待机阶段或噪声消除阶段或第一电荷分享阶段或第二电荷分享阶段或信号放大阶段或预充阶段时，第一功耗控制信号处于第二电平状态。
这样，一方面，通过调整隔离控制信号具有不同的电压值，能够优化信号处理过程，改善信号放大速度慢、电路噪声大的问题；另一方面，通过第一调整功耗控制信号和第二功耗控制信号，能够控制第一参考信号的电压值，减少电路功耗。
以下对放大电路23在各工作阶段的工作原理和各信号的具体变化情况进行说明。
在图11的基础上，参见图12，其示出了本公开实施例提供的一种放大电路的信号时序示意图。在图12中，VisoInt是指前述的隔离电源值，可以为第三电压值VisoH、第四电压值VisoL；Iso是指前述的隔离控制信号，可以为第五电压值Vss、第三电压值VisoH、第四电压值VisoL；Eq是指前述的预充信号，Nc是指前述的噪声消除信号；SanEn1是指前述的第一功耗控制信号，SanEn2是指前述的第二功耗控制信号，SapEn是指前述的参考控制信号；WL是存储单元的开启信号，在WL为第一电平状态时，存储单元与位线接通，在WL为第二电平状态时，存储单元和位线不接通；NCS/PCS是指第一参考信号/第二参考信号，第一参考信号具有参考电压值、第一电压值Vt或者第二电压值Vss，且第一电压值Vt或者第二电压值Vss均可以称为低参考电位，第二参考信号具有参考电压值或者高参考电位；Bla是指位线，Blb是指互补位线。
在放大电路23处于待机阶段时，隔离电源值VisoInt维持第四电压值VisoL，隔离控制信号Iso维持第四电压值VisoL，预充信号Eq和噪声消除信号Nc处于第一电平状态，第一功耗控制信号SanEn1、第二功耗控制信号SanEn2、参考控制信号SapEn和字线开启信号WL均处于第二电平状态。此时，第十三开关管313～第十八开关管318导通，从而第四预设电源向放大电路23充电，以实现放大电路23中的各节点电压、位线Bla、互补位线Blb、读出位线saBla、互补读出位线saBlb、第一参考信号NCS和第二参考信号PCS均为参考电压值，且参考电压值处于低参考电位和高参考电位，为后续执行预设操作指令作好准备。
在接收到预设操作指令之后，放大电路23进入噪声消除阶段，隔离控制信号Iso调整为第五电压值Vss，从而第十三开关管313、第十四开关管314关断。同时，预充信号Eq调整为第二电平状态，第十五开关管315和第十六开关管316关断，噪声消除信号Nc仍然处于第一电平状态，所以第十七开关管317和第十八开关管318导通，参考控制信号SapEn和第二功耗控制信号SanEn2先由第二电平状态调整为第一电平状态，第三开关管303a和第四开关管304a导通，实现第一参考信号NCS处于第二电压值Vt，第二参考信号PCS处于高参考电位，从而对第九开关管309和第十开关管310进行偏移消除处理，消除第九开关管309和第十开关管310的阈值电压差。另外，在噪声消除阶段，第二功耗控制信号SanEn2仍旧为第二电平状态。特别地，在该阶段中，隔离电源值VisoInt提前调整为第三电压值，后续可以加快隔离控制信号Iso在电压升高时的速度，提高信号处理速度。
以下以预设操作指令信号为针对第一存储单元41的刷新指令为例进行说明。
在结束噪声消除阶段后，参考控制信号SapEn和第二功耗控制信号SanEn2先调整为第二电平状态，第一参考信号NCS和第二参考信号PCS调整至参考电压值，放大电路23进入第一电荷分享阶段，存储单元开启信号WL调整为第一电平状态，指示开启第一存储单元41与位线Bla进行电荷分享，生成待处理信号。如图12所示，在该阶段中，位线Bla上生成了待处理信号，同时由于第二存储单元42不会开启，互补位线Blb上仍然维持参考电压值，可认为互补位线Blb上存在参考待处理信号。在该过程中，隔离控制信号Iso维持第五电压值Vss，第十三开关管313、第十四开关管314关断，从而位线Bla与读出位线saBla不接通，且互补位线Blb与互补读出位线saBlb不接通，避免影响第一存储单元41和位线Bla之间的电荷分享。另外，预充信号Eq、噪声消除信号Nc、第一功耗控制信号SanEn1、第二功耗控制信号SanEn2和参考控制信号SapEn仍处于第二电平状态，第一 参考控制信号NCS和第二参考控制信号PCS均具有参考电压值。
在结束第一电荷分享阶段后，放大电路23进入第二电荷分享阶段，隔离控制信号Iso调整为第三电压值VisoH，第十三开关管313、第十四开关管314导通，从而位线Bla与读出位线saBla接通，且互补位线Blb与互补读出位线saBlb接通，从而位线Bla与读出位线saBla进行电荷分享，互补位线Blb与互补读出位线saBlb进行电荷分享，放大电路23从位线Bla处接收待处理信号，且放大电路23从互补位线Blb处接收参考待处理信号。另外，预充信号Eq、噪声消除信号Nc、第一功耗控制信号SanEn1、第二功耗控制信号SanEn2和参考控制信号SapEn仍处于第二电平状态，第一参考控制信号NCS和第二参考控制信号PCS均具有参考电压值。
在结束第二电荷分享阶段后，控制放大电路20进入信号放大阶段，第二功耗控制信号SanEn2和参考控制信号SapEn调整为第一电平状态，从而第一参考信号NCS由参考电压值下降至第二电压值Vss(低参考电位)，第二参考信号PCS由参考电压值升高至高参考电位，放大电路23依据第一参考信号NCS和第二参考信号PCS对待处理信号进行放大处理，将待处理信号的电压值拉高或拉低处理，得到目标放大信号。另外，隔离控制信号Iso由第四电压值VisoL升高至第三电压值VisoH，提高电荷传输速度，预充信号Eq和噪声消除信号Nc均维持第二电平状态。如图12所示，在信号放大阶段，位线Bla和互补位线Blb之间的信号压差增大。
在结束信号放大阶段后，放大电路23进入信号回写阶段，主要通过放大后的位线Bla的电压值恢复第一存储单元41内的存储数据，避免数据失效。此时，隔离电源值VisoInt从第三电压值VisoH降低为第四电压值VisoL从而隔离控制信号Iso从第三电压值VisoH降低为第四电压值VisoL。第一功耗控制信号SanEn1从第二电平状态调整为第一电平状态，第二功耗控制信号SanEn2从第一电平状态调整为第二电平状态，即放大电路23进入省电模式(或称为IDD3P模式)，此时第一参考电压值NCS由第二电压值Vss调整为第一电压值Vt，减少电路功耗。
在结束信号回写阶段后，存储单元开启信号WL调整为第二电平状态，指示第一存储单元41关闭。
省电模式结束时间可早于第一存储单元41关闭时间，约占回写阶段的80％时间段。省电模式结束后第一功耗控制信号SanEn1从第一电平状态调整为第二电平状态，第二功耗控制信号SanEn2从第二电平状态调整为第一电平状态，此时第一参考电压值NCS由第一电压值Vt调整为第二电压值Vss。若将目标信号拉低处理，由于位线Bla及第一存储单元41内的电压较低，能够迅速从第二电压值Vss调整为第一电压值Vt，迅速将第一存储单元41内的存储数据恢复至最低状态。
省电模式结束时间可等于第一存储单元41关闭时间，省电模式结束即回写阶段结束，若将目标信号拉低处理，由于第一存储单元41内的电压维持第一电压值Vt，低于参考电压值，不影响下一次数据读取操作。
放大电路23进入预充阶段，VisoInt隔离电源值先调整为第三电压值VisoH后下降为第四电压值VisoL，隔离控制信号Iso先调整为第三电压值VisoH后下降至第四电压值VisoL，节省第十三开关管303和第十四开关管304的功耗，并延长器件寿命；在隔离控制信号调整为第四电压值VisoL之后，预充信号Eq、噪声消除信号Nc调整为第一电平状态，同时第一功耗控制信号SanEn1调整为第二电平状态，第二功耗控制信号SanEn2先升高为第一电平状态再恢复为第二电平状态，这样，第一参考信号NCS由第一电压值Vt下降至第二电压值Vss再上升至参考电压值，第二参考信号PCS从高参考电位恢复至第四电压值。位线Bla/互补位线Blb、读出位线saBla/互补读出位线saBlb将恢复至的参考电压值。
在结束预充阶段后，放大电路23再次进入待机阶段，以准备下一次操作。
在相关技术中，参见图13，其示出了相关技术提供的一种信号时序示意图。由于相关技术中的控制放大电路缺少功耗控制电路，此时第一参考信号NCS仅能够为电压值Vss(即低参考电位)或者参考电压值。在图12中，SanEn为第一参考控制信号，在第一参考控制信号SanEn处于第一电平状态，第一参考信号NCS为低参考电位，在第一参考控制信号SanEn处于第二电平状态时，第一参考信号NCS为参考电压值。由第一参考控制信号SanEn指示。图13其他各信号含义及各信号的变化原理可参照图12理解，不作赘述。如图13所示，一方面，由于相关技术中的第一参考信号NCS在作为低参考电位时需要维持第二电压值Vss，所以无法降低电路功耗。另一方面，由于相关技术中的隔离电源值(未示出)为一固定电压值，所以隔离控制信号Iso存在两个电压值，分别属于第一电平状态和第二电平状态，信号放大速度较慢和电路噪声较大。
本公开实施例提供了一种控制放大电路及其控制方法，通过本实施例对前述实施例的具体实现进行详细阐述，从中可以看出，一方面，在预充阶段和待机阶段，隔离电源值下降为第四电压值VisoL， 能够减少器件漏电及失效问题，延长器件的使用寿命；在信号回写阶段可以进入省电模式，能够减少器件漏电及失效问题，延长器件的使用寿命；在进入省电模式后，第一参考信号NCS为第一电压值Vt，所以放大电路23仅需要下拉至Vt而非Vss，能够节省电路功耗；另外，通过功耗控制电路还可以降低电压拉低过程中的噪声，例如，先打开第一功耗电路中的子电路，再打开第二功耗电路的子电路，能够减缓电压下拉的速度，减少噪声。
在本公开的又一实施例中，参见图14，其示出了本公开实施例提供的一种灵敏放大器60的组成结构示意图。如图14所示，灵敏放大器60可以包括前述实施例任一项所述的控制放大电路20。
这样，由于灵敏放大器60可以包括前述实施例任一项所述的控制放大电路20，通过设置功耗调整电路，能够调整第一参考信号的具体电压值，从而降低电路功耗；同时通过隔离电路，能够调整隔离控制信号的具体电压值，从而优化信号放大过程，不仅改善信号放大速度较慢的问题，而且可以降低电路噪声。
在本公开的再一实施例中，参见图15，其示出了本公开实施例提供的一种半导体存储器70的组成结构示意图。如图15所示，半导体存储器70可以包括前述实施例任一项所述的灵敏放大器60。
在本公开实施例中，半导体存储器70可以为DRAM芯片。
这样，由于半导体存储器70包括前述的灵敏放大器60，由于灵敏放大器60可以包括前述实施例任一项所述的控制放大电路20，通过设置功耗调整电路，能够调整第一参考信号的具体电压值，从而降低电路功耗；同时通过隔离电路，能够调整隔离控制信号的具体电压值，从而优化信号放大过程，不仅改善信号放大速度较慢的问题，而且可以降低电路噪声。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种控制放大电路、灵敏放大器和半导体存储器，包括：功耗控制电路，用于接收功耗控制信号，并根据所述功耗控制信号输出第一参考信号；隔离电路，用于确定控制指令信号，并根据所述控制指令信号生成隔离控制信号；放大电路，用于接收所述第一参考信号、所述隔离控制信号和待处理信号，并基于所述第一参考信号和所述隔离控制信号对所述待处理信号进行处理，得到目标放大信号。这样，通过控制放大电路，能够根据功耗控制信号对第一参考信号进行调整，从而降低电路功耗。

Claims (22)

  1. 一种控制放大电路，包括：
    功耗控制电路，用于接收功耗控制信号，并根据所述功耗控制信号输出第一参考信号；
    隔离电路，用于确定控制指令信号，并根据所述控制指令信号生成隔离控制信号；
    放大电路，用于接收所述第一参考信号、所述隔离控制信号和待处理信号，并基于所述第一参考信号和所述隔离控制信号对所述待处理信号进行处理，得到目标放大信号。
  2. 根据权利要求1所述的控制放大电路，其中，所述功耗控制电路包括第一控制电路和第二控制电路，所述功耗控制信号包括第一功耗控制信号和第二功耗控制信号；其中，
    所述第一控制电路，用于接收所述第一功耗控制信号，并在所述第一功耗控制信号为第一电平状态时，输出具有第一电压值的所述第一参考控制信号；
    所述第二控制电路，用于接收所述第二功耗控制信号，并在所述第二功耗控制信号为第一电平状态时，输出具有第二电压值的所述第一参考控制信号；
    其中，所述第一电压值高于所述第二电压值。
  3. 根据权利要求2所述的控制放大电路，其中，所述第一控制电路包括多个第一控制子电路，所述第一控制子电路包括第一开关管和第二开关管；其中，
    所述第一开关管的第一端用于接收所述第一功耗控制信号，所述第一开关管的第三端、所述第二开关管的第一端和所述第二开关管的第二端连接，所述第二开关管的第三端与地信号连接，且多个所述第一控制子电路中的第二开关管的第二端相互连接；
    所述第一开关管的第二端用于输出所述第一参考信号。
  4. 根据权利要求3所述的控制放大电路，其中，所述第一开关管的第三端和所述第二开关管的第一端之间设置开关，且所述开关的控制端与省电控制信号连接；
    其中，在所述第一功耗控制信号为第一电平状态时，通过所述省电控制信号控制所述开关处于闭合状态。
  5. 根据权利要求3所述的控制放大电路，其中，所述第二控制电路包括多个第二控制子电路，且所述第二控制子电路包括第三开关管；其中，
    所述第三开关管的第一端用于接收所述第二功耗控制信号，所述第三开关管的第三端与地信号连接，所述第三开关管的第二端用于输出所述第一参考信号。
  6. 根据权利要求5所述的控制放大电路，其中，所述功耗控制电路还包括控制信号生成电路；其中，
    所述控制信号生成电路包括多个第一反向器，且所述第一反向器用于接收初始控制信号，并生成功耗控制信号；其中，
    在所述多个第一反向器中，每个所述第一控制子电路的所述第一功耗控制信号通过一个所述第一反向器输出，每个所述第二控制子电路的所述第二功耗控制信号通过一个所述第一反向器输出。
  7. 根据权利要求1所述的控制放大电路，其中，所述控制放大电路还包括参考控制电路；
    所述参考控制电路，用于确定参考控制信号，并根据所述参考控制信号输出第二参考信号；
    所述放大电路，还用于接收所述第一参考信号、所述第二参考信号、所述隔离控制信号和待处理信号，并基于所述第一参考信号、所述第二参考信号和所述隔离控制信号对所述待处理信号进行处理，得到所述目标放大信号。
  8. 根据权利要求7所述的控制放大电路，其中，所述参考控制电路包括多个第三控制子电路，且所述第三控制子电路包括第四开关管；其中，
    所述第四开关管的一端与所述参考控制信号连接，所述第四开关管的第二端与第一预设电源连接，所述第四开关管的第三端用于输出所述第二参考信号。
  9. 根据权利要求7所述的控制放大电路，其中，所述参考控制电路包括多个信号处理子电路和多个第三控制子电路；其中，
    所述信号处理子电路包括第二反向器，且所述第二反向器用于接收初始参考信号，并生成所述参考控制信号；
    所述第三控制子电路包括第四开关管，所述第四开关管的第一端与所述参考控制信号连接，所述第四开关管的第二端与第一预设电源连接，所述第四开关管的第三端，用于输出所述第二参考信号；
    其中，多个所述信号处理子电路和多个所述第三控制子电路一一对应。
  10. 根据权利要求1-9任一项所述的控制放大电路，其中，所述隔离电路包括第一信号确定电路、电源输出电路、第二信号确定电路和隔离控制电路；其中，
    所述第一信号确定电路，用于在接收到预设操作指令之后，根据所述预设操作指令，输出第一电源切换信号和/或第二电源切换信号；
    所述电源输出电路，用于根据所述第一电源切换信号和/或所述第二电源切换信号，输出隔离电源值；
    所述第二信号确定电路，用于在接收到所述预设操作指令之后，根据所述预设操作指令，输出所述控制指令信号；
    所述隔离控制电路，用于接收隔离电源值和所述控制指令信号，生成所述隔离控制信号。
  11. 根据权利要求10所述的控制放大电路，其中，
    所述电源输出电路，用于在所述第一电源切换信号具有第二电平状态，且所述第二电源切换信号具有第一电平状态时，确定所述隔离电源值具有第三电压值；或者
    在所述第一电源切换信号具有第一电平状态且所述第二电源信号具有第二电平状态时，确定所述隔离电源值具有第四电压值；
    其中，所述第三电压值与所述第四电压值均属于所述第一电平状态，所述第三电压值大于所述第四电压值。
  12. 根据权利要求11所述的控制放大电路，其中，
    所述隔离控制电路，具体用于在所述控制指令信号具有第一电平状态且所述隔离电源值具有第三电压值的情况下，确定所述隔离控制信号具有第三电压值；或者
    在所述控制指令信号具有第一电平状态且所述隔离电源值具有第四电压值的情况下，确定所述隔离控制信号具有第四电压值；或者
    在所述控制指令信号具有第二电平状态的情况下，确定所述隔离控制信号具有第五电压值；
    其中，所述第五电压值属于第二电平状态，所述第五电压值小于所述第四电压值。
  13. 根据权利要求12所述的控制放大电路，其中，所述电源输出电路包括第二预设电源、第三预设电源、第五开关管和第六开关管；其中，
    所述第五开关管的第一端与所述第一电源切换信号连接，所述第六开关管的第一端与所述第二电源切换信号连接；
    所述第五开关管的第二端与所述第二预设电源连接，所述第六开关管的第二端与所述第三预设电源连接；
    所述第四开关管的第三端，与所述第六开关管的第三端连接，用于输出所述隔离电源值；
    其中，所述第二预设电源用于输出所述第三电压值，所述第三预设电源用于输出所述第四电压值。
  14. 根据权利要求12述的控制放大电路，其中，所述隔离控制电路包括第三反向器、第七开关管和第八开关管；其中，
    所述第三反向器的输入端与所述控制指令信号连接，所述第三反向器的输出端分别与所述第七开关管的第一端和第八开关管的第一端连接；
    所述第七开关管的第二端与所述隔离电源值连接，所述第八开关管的第三端与地信号连接；
    所述第七开关管的第三端，与所述第八开关管的第二端连接，用于输出所述隔离控制信号。
  15. 根据权利要求12所述的控制放大电路，其中，所述放大电路包括第九开关管、第十开关管、第十一开关管、第十二开关管、第十三开关管和第十四开关管；
    所述第九开关管的第一端，与所述第十三开关管的第三端连接，用于接收所述待处理信号，所述第九开关管的第二端、所述第十一开关管的第三端、所述第十二开关管的第一端与第十四开关管的第二端连接；
    所述第十开关管的第一端，与所述第十四开关管的第三端连接，用于接收参考待处理信号，所述第十开关管的第二端、所述第十二开关管的第三端、所述第十一开关管的第一端与第十三开关管的第二端连接；
    所述第九开关管的第三端、所述第十开关管的第三端与第一参考信号连接，所述第十一开关管的第二端、所述第十二开关管的第二端与第二参考信号连接，所述第十三开关管的第一端、所述第十四开关管的第一端与所述隔离控制信号连接。
  16. 根据权利要求15所述的控制放大电路，其中，所述放大电路还包括预充电路，且所述 预充电路包括第十五开关管和第十六开关管；其中，
    所述第十五开关管的第一端、所述第十六开关管的第一端与预充控制信号连接；
    所述第十五开关管的第二端与第四预设电源连接，所述第十五开关管的第三端与所述第十开关管的第二端连接；
    所述第十六开关管的第二端与所述第十开关管的第二端连接，所述第十六开关管的第三端与所述第九开关管的第二端连接。
  17. 根据权利要求15所述的控制放大电路，其中，所述放大电路还包括噪声消除电路，所述噪声消除电路包括第十七开关管和第十八开关管；其中，
    所述第十七开关管的第一端、第十八开关管的第一端与噪声消除信号连接；
    所述第十七开关管的第二端与所述第九开关管的第二端连接，所述第十七开关管的第三端与所述第九开关管的第一端连接；
    所述第十八开关管的第二端与所述第十开关管的第二端连接，所述第十八开关管的第三端与所述第十开关管的第一端连接。
  18. 根据权利要求12-17任一项所述的控制放大电路，其中，所述放大电路对所述待处理信号进行处理时包括：待机阶段、噪声消除阶段、第一电荷分享阶段、第二电荷分享阶段、信号放大阶段、信号回写阶段和预充阶段；
    若所述放大电路处于所述第二电荷分享阶段或所述信号放大阶段或预充阶段，则维持所述隔离控制信号具有第三电压值；或者
    若所述放大电路处于所述待机阶段或所述信号回写阶段，则维持所述隔离控制信号具有第四电压值；或者
    若所述放大电路处于所述噪声消除阶段或者所述第一电荷分享阶段，则维持所述隔离控制信号具有第五电压值。
  19. 根据权利要求18所述的控制放大电路，其中，
    在所述放大电路处于所述信号回写阶段时，所述第一功耗控制信号处于第一电平状态，且所述第二功耗控制信号处于第二电平状态；
    所述放大电路处于所述待机阶段或所述噪声消除阶段或所述第一电荷分享阶段或所述第二电荷分享阶段或所述信号放大阶段或所述预充阶段时，所述第一功耗控制信号处于第二电平状态。
  20. 根据权利要求3-17任一项所述的控制放大电路，其中，第五开关管、第六开关管、第七开关管、第十一开关管和第十二开关管为P型沟道场效应管；
    第一开关管、第二开关管、第三开关管、第四开关管、第八开关管、第九开关管、第十开关管、第十三开关管、第十四开关管、第十五开关管、第十六开关管、第十七开关管和第十八开关管为N型沟道场效应管；
    其中，所述P型沟道场效应管的第一端为栅极端，所述P型沟道场效应管的第二端为源极端，所述P型沟道场效应管的第三端为漏极端；所述N型沟道场效应管的第一端为栅极端，所述N型沟道场效应管的第二端为漏极端，所述N型沟道场效应管的第三端为源极端。
  21. 一种灵敏放大器，包括如权利要求1至20任一项所述的控制放大电路。
  22. 一种半导体存储器，包括如权利要求21所述的灵敏放大器。
PCT/CN2022/079712 2021-12-31 2022-03-08 一种控制放大电路、灵敏放大器和半导体存储器 WO2023123667A1 (zh)

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* Cited by examiner, † Cited by third party
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US5506524A (en) * 1995-03-01 1996-04-09 Lin; Jyhfong Low-voltage low-power dynamic folded sense amplifier
CN101562042A (zh) * 2008-04-14 2009-10-21 北京芯技佳易微电子科技有限公司 一种适用于随机存储器的灵敏放大器
CN104078078A (zh) * 2014-06-19 2014-10-01 苏州东微半导体有限公司 一种基于半浮栅存储器的读写控制电路
CN111179983A (zh) * 2019-12-10 2020-05-19 普冉半导体（上海）有限公司 一种灵敏放大器电路
CN111863051A (zh) * 2020-07-27 2020-10-30 安徽大学 灵敏放大器、存储器和灵敏放大器的控制方法

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US5506524A (en) * 1995-03-01 1996-04-09 Lin; Jyhfong Low-voltage low-power dynamic folded sense amplifier
CN101562042A (zh) * 2008-04-14 2009-10-21 北京芯技佳易微电子科技有限公司 一种适用于随机存储器的灵敏放大器
CN104078078A (zh) * 2014-06-19 2014-10-01 苏州东微半导体有限公司 一种基于半浮栅存储器的读写控制电路
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