WO2023122509A1 - Thermoelectric cooling for die packages - Google Patents

Thermoelectric cooling for die packages Download PDF

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Publication number
WO2023122509A1
WO2023122509A1 PCT/US2022/081849 US2022081849W WO2023122509A1 WO 2023122509 A1 WO2023122509 A1 WO 2023122509A1 US 2022081849 W US2022081849 W US 2022081849W WO 2023122509 A1 WO2023122509 A1 WO 2023122509A1
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WO
WIPO (PCT)
Prior art keywords
thermoelectric element
integrated device
microelectronic device
device die
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2022/081849
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English (en)
French (fr)
Inventor
Belgacem Haba
Rajesh Katkar
Patrick Variot
Hong Shen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Bonding Technologies Inc
Original Assignee
Adeia Semiconductor Bonding Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Adeia Semiconductor Bonding Technologies Inc filed Critical Adeia Semiconductor Bonding Technologies Inc
Priority to JP2024537071A priority Critical patent/JP2025500315A/ja
Priority to KR1020247024306A priority patent/KR20240128904A/ko
Priority to EP22912608.1A priority patent/EP4454011A4/en
Priority to CN202280090243.1A priority patent/CN118661254A/zh
Publication of WO2023122509A1 publication Critical patent/WO2023122509A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N19/00—Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/253—Semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/259—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/28—Arrangements for cooling comprising Peltier coolers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general

Definitions

  • the field relates to dissipating heat in microelectronics, and particularly in microelectronic devices including directly bonded elements.
  • microelectronics With the miniaturization and the high density integration of electronic components, the heat flux density in microelectronics is increasing.
  • the microelectronic components are typically operated below certain rated temperature to ensure optimal operation.
  • a heat spreader or heat sink may be mounted using thermal interface material (TIM) on top of the hot microelectronic component or semiconductor die to extract heat from the top of the die.
  • TIM thermal interface material
  • the microelectronics may not operate reliably, its performance may be affected, and it may even shut down or burn out.
  • thermal dissipation and extraction is a serious problem in high-power devices, and the problem worsens with chip stacking.
  • FIG. 1A schematically illustrates a cross-sectional view of an example microelectronic system.
  • FIG. IB schematically illustrates a plan view of the example microelectronic system shown in FIG. 1A.
  • FIGs. 2A-2F schematically illustrate a method of forming a thermoelectric element in a die stack according to an embodiment of the disclosed technology.
  • FIGs. 3A-3C schematically illustrate a portion of another method of forming a thermoelectric element in a die stack according to an embodiment of the disclosed technology.
  • FIGs. 4A-4D schematically illustrate yet another method of forming a thermoelectric element in a die stack according to an embodiment of the disclosed technology.
  • FIGs. 5A-5C schematically illustrate still another method of forming a thermoelectric element in a die stack according to an embodiment of the disclosed technology.
  • FIG. 6A schematically illustrates a cross-sectional view of another example microelectronic system.
  • FIG. 6A-2 schematically illustrates a plan view of the example microelectronic system shown in FIG. 6A.
  • FIG. 6B schematically illustrates a cross-sectional view of yet another example microelectronic system.
  • FIG. 7A schematically illustrates a cross-sectional view of yet another example microelectronic system.
  • FIG. 7B schematically illustrates a cross-sectional view of yet another example microelectronic system.
  • FIG. 8A schematically illustrates a cross-sectional view of yet another example microelectronic system.
  • FIG. 8B schematically illustrates a plan view of the example microelectronic system shown in FIG. 8A.
  • FIG. 9 schematically illustrates a cross-sectional view of yet another example microelectronic system.
  • FIG. 10 schematically illustrates a cross-sectional view of yet another example microelectronic system.
  • Microelectronic elements e.g., dies/chips
  • chip joining methods such as adhesive bonding, flip chip interconnections, etc.
  • the adhesives may reduce or insulate heat transfer from one die to another or from bottom die towards the top die (towards the direction of the heat spreader).
  • heat dissipation is typically aided by heat sinks at the top of the stack, but efficiently extracting heat from lower dies in the die stack (especially the lowest die of a stack) is challenging. Accordingly, there remains a continuing need for improved techniques to dissipate heat in microelectronic devices.
  • a microelectronic device 100 may include a thermoelectric element 103 which can help remove heat from the device 100 and actively redirect the heat flow within the device 100, for example actively lower the temperature of a certain chip in the device 100, of a certain location of a chip or of a certain hot spot in a chip.
  • the thermoelectric element 103 may comprise a Peltier element which includes two materials with different Peltier coefficients joined together at a junction.
  • the Peltier element may utilize the Peltier effect to create a net heat flux at the junction of the two different materials when supplied with electrical energy (e.g., a DC electric current), due to the imbalance of the Peltier heat flowing in and out of the junction.
  • the Peltier element may include a plurality of pairs 1030 of p-type and n-type semiconductor pellets or chips, etc. connected electrically in series and thermally in parallel, such as in the configuration shown in FIG. 1A. In this configuration, the charge carriers and heat may all flow in the same direction through the pellets 1034 and 1036 (bottom to top, or top to bottom, depending on the applied voltage bias). For example, in FIG. 1A, the pellets 1034 and 1036 can be biased such that heat flux flows upwardly, as indicated by the arrows, from the lower active chip 101 through the Peltier element and the carrier element 105 to the heat sink 107.
  • the thermoelectric element 103 is not bonded to other elements of the device 100 by an adhesive or thermal interface material (TIM), which may interfere with heat transfer. Rather, the thermoelectric element 103 may be directly bonded to another element in the device 100, thus improving heat transfer efficiency.
  • a plurality of p-type and n-type semiconductor pellet pairs 1030 or a structure (e.g., a wafer, die, etc.) comprising a plurality of p-type and n-type semiconductor pellet pairs 1030 may be directly bonded to an active chip 101.
  • the thermoelectric element 103 may be grown onto an active chip 101 or die.
  • An active chip 101 may be a die comprising active circuitry, e.g., the active circuitry can include one or more transistors.
  • a plurality of p-type and n-type semiconductor thermoelectric pellet pairs 1030 can be divided into many groups, and each group may be controlled independently.
  • a sensor e.g., diode
  • the group of thermoelectric pellet pairs 1030 associated with that location may be activated by applying an electrical current through one or more pairs of electrical contact pins/pads 117.
  • thermoelectric pellet pairs 1030 may be locally monitored and controlled.
  • the ability to independently operate each or a selected group of thermoelectric pellet pairs 1030 may also allow the thermoelectric element to consume less power.
  • FIG. 1A schematically illustrates a cross-sectional view of an example microelectronic system 100 having stacked semiconductor elements (e.g., dies/chips/carriers) and a thermoelectric element 103 which may direct heat to a heat sink 107 (e.g., a metal heat sink or a heat pipe with fluid coolant) at the top of the stack.
  • a heat sink 107 e.g., a metal heat sink or a heat pipe with fluid coolant
  • the heat generated by a lower semiconductor element 101 e.g., an active chip
  • thermoelectric element 103 may be bonded to an element (e.g., a lower active chip 101 or an upper carrier 105) at bonding inferfaces 1077 by way of direct bonding without an intervening adhesive, such as hybrid direct bonding processes described below and commercially available fromAdeia of San Jose, CA. In some embodiments, the thermoelectric element 103 may be bonded to the lower active chip
  • thermoelectric element 103 may be connected directly or via conductive traces to TSVs (through-substrate vias) 1015 extending in the element 101 for powering of the thermoelectric element.
  • the electrical contacts 117 of thermoelectric element 103 may be directly bonded to the TSVs 1015 in the element 101.
  • the thermoelectric element 103 may be grown on the lower active chip
  • FIG. IB schematically illustrates a plan view of the example microelectronic system 100 shown in FIG. 1A.
  • the thermoelectric element 103 may be configured for zoned control of cooling the lower active chip 101.
  • a plurality of electrical contacts 117 are used for multi-zonal control/positional control of different groups of thermoelectric pellet pairs 1030 in the thermoelectric element 103 during cooling operation, providing local thermal dissipation in response to measured hot spot distribution.
  • signals measured by temperature sensors may be used to control the thermoelectric element 103, and the temperature sensors may be located in the lower active chip 101 or within the thermoelectric element 103.
  • control of the thermoelectric element 103 may be done by the lower active chip 101, within the thermoelectric element 103, or by an external chip on the system board.
  • FIGs. 2A-2F schematically illustrates a method of forming a thermoelectric element 103 in a die stack.
  • FIG. 2A shows a first step including forming N- or P-doped regions (2034 and 2036, respectively) in a suitable thermoelectric substrate 2010 (e.g., a Bi2Te3 wafer), where the N- or P-doped regions are separated by physical gaps 2015 or wide (e.g. >1 pm) intrinsic regions 2017.
  • the physical gap 2015 may be filled with one or more sutable organic or inorganic dielectric materials.
  • the widths of P or N regions (2036 or 2034) may vary from tens of pm to several mm in one or both planar directions.
  • the metallization may be one or more conductive traces 2031 between each P and N regions (2036 and 2034, respectively).
  • another metallization may also be formed to act as a hot or cold plate.
  • several conductive traces 2031 may be implemented for uniform carrier flow/distribution effectively creating uniform thermal gradient between hot and cold plates.
  • metallization layers connecting P and N regions (2036 and 2034, respectively) is followed by dielectric 2032 deposition.
  • the dielectric layer 2032 is prepared (e.g., cleaning, chemical-mechanical polishing or CMP, plasma activation, etc.) for direct bonding (e.g., by direct insulator-to-insulator bonds or by direct hybrid bonds).
  • FIG. 2C shows a third step including attaching the formed thermoelectric element 103 to a carrier 105 (e.g., by way of dielectric-to-dielectric direct bonding, such as ZIBOND®, commercially available from Adeia).
  • the carrier 105 may be a permanent carrier that is not subsequently removed and may be formed of a suitable good thermally conductive material (e.g., Si, ceramic, Aluminum, Aluminum Nitride, Silicon Carbide, etc., or a material having a thermal conductivity greater than 1 W/cm/°C). In other embodiments, during later processing the carrier 105 may be removed.
  • FIG. 2D shows a fourth step including grinding or polishing or any other suitable process to remove the thermoelectric substrate 2010 (e.g., the Bi2Te3 wafer) and reveal the N/P pairs 2030.
  • FIG. 2E shows a fifth step including dielectric 2042 deposition, metallization to create electrical contacts 117, and forming a bonding layer 2051 (e.g., a layer configured for hybrid bonding such as DBI® bonding commercially available from Adeia).
  • FIG. 2F shows a sixth step including attaching (e.g., by direct hybrid bonding) the thermoelectric element 103 to an active chip 101 or wafer (face-to-face, F2F, or face-to-back, F2B), which may include TSVs.
  • the thermoelectric element 103 is direct bonded to an active chip 101 or wafer without electrical coonections between them. The method described in connection with FIGs.
  • 2A-2F may be utilized to manufacture the devices and systems, and/or to operate in conjunction with the devices and systems, that are described in U.S. Provisional Application No. 63/265,770, filed December 20, 2021, titled “THERMOELECTRIC COOLING IN MICROELECTRONICS”, the content of which is incorporated herein by reference.
  • FIGs. 3A-3C schematically illustrates a portion of another method of forming a thermoelectric element 103 in a die stack.
  • FIG. 3A shows starting from a carrier wafer 105 (which may have a high thermal conductivity, e.g., a thermal conductivity greater than 1 W/cm/°C).
  • the material may be Si or ceramic, if used as a permanent carrier.
  • Other carrier materials like Aluminum, Aluminum Nitride, Silicon Carbide, may be used in some examples.
  • FIG. 3B shows subsequently forming small cavities 3033 in the wafer 105 (with or without also depositing a layer of dielectric/insulator in the cavity 3033).
  • 3C shows subsequently filling the cavities with Bi and Te mix 3039, followed by high temp sintering.
  • Bi2Te3 (doped) wafer is cruched and the powder is compressed into the cavities/pockets and sintered.
  • the cavities 3033 may be filled by deposition, stenciling or 3D printing of the doped materials 3039 in them.
  • the method may proceed with the steps as described in connection with FIGs. 2B-2F.
  • the method described in connection with FIGs. 3A-3C may be utilized to manufacture the devices and systems, and/or to operate in conjunction with the devices and systems, that are described in U.S. Provisional Application No.
  • FIGs. 4A-4D schematically illustrates yet another method of forming a thermoelectric element 103 in a die stack.
  • FIG. 4A shows a first step including starting with a carrier 105 (or or interposer).
  • FIG. 4B shows a second step including metallization to create electrical connections 4031, then depositing, stenciling, or 3D printing doped Bi2Te3 onto the carrier 105 to form features/pellets 4034 and 4036 that will become thermoelectric N/P pairs 4030.
  • FIG. 4A shows a first step including starting with a carrier 105 (or or interposer).
  • FIG. 4B shows a second step including metallization to create electrical connections 4031, then depositing, stenciling, or 3D printing doped Bi2Te3 onto the carrier 105 to form features/pellets 4034 and 4036 that will become thermoelectric N/P pairs 4030.
  • FIG. 4C shows a third step including filling the gaps 4015 between the Bi2Te3 features with dielectric 4017, metallization to create electrical connections 4033 and contacts 117, and forming a bonding layer 4051 (e.g., a layer configured for direct hybrid bonding, such as DBI® bonding, available commercially from Adeia).
  • FIG. 4D shows a fourth step including attaching (e.g., by direct hybrid bonding) the formed thermoelectric element 103 to an active chip 101 or wafer (F2F or F2B), which may include TSVs.
  • the thermoelectric element 103 is direct bonded to an active chip 101 or wafer without electrical coonections between them.
  • the thermoelectric element 103 may span a region of about 1-3 mm in size.
  • the pitch for the N-P pairs 4030 may be about 0.5 mm to several mm, or may be about tens of microns. In some embodiments, the pitch for the N-P pairs 4030 may be about 0.1 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm, 5 mm or therebetween, or may be about 10 microns, 30 microns, 50 microns, 70 microns, 90 microns or therebetween.
  • the method described in connection with FIGs. 4A-4D may be utilized to manufacture the devices and systems, and/or to operate in conjunction with the devices and systems, that are described in U.S. Provisional Application No. 63/265,770, filed December 20, 2021, titled “THERMOELECTRIC COOLING IN MICROELECTRONICS”, the content of which is incorporated herein by reference.
  • FIGs. 5A-5C schematically illustrates still another method of forming a thermoelectric element 103 in a die stack by directly growing the thermoelectric element 103 on an active wafer/chip 101.
  • FIG. 5A shows a first step including starting with an active wafer/chip 101.
  • FIG. 5B shows a second step including metallization to create electrical connections 5031, then deposition/stenciling/3D printing doped Bi2Te3 onto the backside 5010 of the active wafer/chip 101 to form pellets 5034 and 5036 that will become thermoelectric N/P pairs 5030.
  • FIG. 5C shows a third step including filling the gaps 5015 between the Bi2Te3 features with dielectric 5017, and metallization to create electrical connections 5033.
  • the thermoelectric element 103 may span a region of about 0.5-3 mm in size.
  • the pitch for the N-P pairs 5030 may be about 0.5-1 mm, or may be about tens of microns.
  • the pitch for the N-P pairs 4030 may be about 0.1 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm, 5 mm or therebetween, or may be about 10 microns, 30 microns, 50 microns, 70 microns, 90 microns or therebetween.
  • the method described in connection with FIGs. 5A-5C may be utilized to manufacture the devices and systems, and/or to operate in conjunction with the devices and systems, that are described in U.S. Provisional Application No. 63/265,770, filed December 20, 2021, titled “THERMOELECTRIC COOLING IN MICROELECTRONICS”, the content of which is incorporated herein by reference.
  • FIG. 6A schematically illustrates a cross-sectional view of an example microelectronic system 600A having stacked semiconductor elements (e.g., carrier element 605 and active dies 601A, 6001A and 6002A) and a thermoelectric element 603A which directs heat from a bottom chip (601 A) to a heat sink 607 A at the top of the stack.
  • the thermoelectric element 603A and a plurality of chips e.g., 6001Aand 6002A
  • the thermoelectric element 603A may be direct bonded (e.g., by way of insulator- to-insulator direct bonding or by hybrid direct bonding) to the bottom chip 601 A .
  • thermoelectric element 603A may be adjacent to at least one chip (e.g., at least 6001A and/or 6002 A) and thus reducing heat flow through the at least one chip 6001 A and/or 6002 A.
  • the thermoelectric element 603 A may be powered by electrical contacts 617A connecting to the bottom chip 601A.
  • FIG. 6A-2 schematically illustrates a plan view of the example microelectronic system 600A shown in FIG. 6A.
  • thermoelectric element 603B schematically illustrates a cross- sectional view of another example microelectronic system 600B having stacked semiconductor elements (e.g., carrier element 605 and active dies 601B, 6001B and 6002B) and a thermoelectric element 603B which directs heat from a bottom chip (601B) to a heat sink 607B at the top of the stack.
  • the thermoelectric element may be mounted on the bottom chip (601B), and a plurality of chips (e.g., 6001Band 6002B) may be mounted on the thermoelectric element 603 B.
  • the thermoelectric element 603 B may be powered and controlled via electrical contacts 617B connecting to the bottom chip (60 IB) in response to temperature detection by sensors disposed in any of the neighboring chips (e.g., 601B, 6001B or 6002B).
  • FIG. 7A schematically illustrates a cross-sectional view of an example microelectronic system 700A similar to that shown in FIG. 6A, where like features are referenced by like reference numbers, but using bondwires 799A to power the thermoelectric element 603 A from the backside.
  • the thermoelectric element 603 A may be direct bonded (e.g. , by direct hybrid bonding or by insulator-to-insulator direct bonding) to the bottom chip 601A.
  • FIG. 7B schematically illustrates a cross-sectional view of an example microelectronic system 700B similar to that shown in FIG.
  • thermoelectric element 603 A or 603B can control the operation of the thermoelectric element 603 A or 603B.
  • a chip or die on the system board (not shown) can control the operation of the thermoelectric element 603 A or 603B.
  • FIG. 8A schematically illustrates a cross-sectional view of an example microelectronic system 800 similar to that shown in FIG. 6B, where like features are referenced by like reference numbers, but additionally or alternatively has temperature sensors 826 embedded in the thermoelectric element 603 B to control the temperature distribution and chip activities.
  • the sensors 826 detect a temperature
  • the sensors 826 will send a signal to circuitry in die 60 IB, 600 IB and/or 6002B
  • the die 60 IB, 600 IB and/or 6002B can send a control signal to the thermoelectric element 603B.
  • FIG. 8B schematically illustrates a plan view of the example microelectronic system 800 shown in FIG. 8A, showing that each group of thermoelectric N/P pellets is monitored by a temperature sensor 826 and powered by a pair of electrical contacts 817.
  • FIG. 9 schematically illustrates a cross-sectional view of an example microelectronic system 900 similar to that shown in FIG. 6A, where like features are referenced by like reference numbers,.
  • the thermoelectric element 603A is controlled by an adjacent chip (e.g., 6001 A or 6002A) via an electrical pathway 909 (e.g., a trace) through the bottom chip 601 A.
  • FIG. 10 schematically illustrates a cross-sectional view of an example microelectronic system 1000 having stacked semiconductor elements (e.g., active dies 10020 and 1020 and carrier elements 10051) and multiple thermoelectric elements 10003 which can be used to actively redirect heat within and out of the system 1000 (e.g., through a heat sink 10077 at the top of the stack).
  • stacked semiconductor elements e.g., active dies 10020 and 1020 and carrier elements 10051
  • thermoelectric elements 10003 which can be used to actively redirect heat within and out of the system 1000 (e.g., through a heat sink 10077 at the top of the stack).
  • thermoelectric element 603A, 603B or 10003 may be grown on an carrier (e.g., 605 or 10051) or active chip (e.g., 601 A, 601B, 10020 or 1020). In some embodiments, the thermoelectric element 603 A, 603B or 10003 may be grown on or directly bonded to the backside of an active chip (e.g., 601A, 601B, 10020 or 1020). In some embodiments, the stacked semiconductor elements can be directly bonded to each other without an intervening adhesive.
  • 6001A, 6001B, 6002A, 6002B and/or 10020 may be directly bonded to the bottom chip (e.g., 601 A, 60 IB or 1020) or to the thermoelectric element 603B.
  • the top heat sink 607A, 607B or 10077 may be directly bonded to the semiconductor elements (e.g., 6001A, 6001B, 6002A, 6002B or 10020 ) and/or the carrier 605 or 10051 associated with the thermoelectric element 603 A, 603B or 10003.
  • the direct bonding process may include the ZIBOND® and DBI® processes configured for room temperature, atmospheric pressure direct bonding or the DBI® Ultra process configured for low-temperature hybrid bonding, which are commercially available from Adeia of San Jose, CA.
  • the direct bonds can be between dielectric materials of the bonded elements and can also include conductive materials at or near the bond interface for direct hybrid bonding.
  • the conductive materials at the bonding interface may be bonding pads formed in or over a redistribution layer (RDL) over a die, and/or passive electronic components.
  • RDL redistribution layer
  • a die can refer to any suitable type of integrated device die.
  • the integrated device dies can comprise an electronic component such as an integrated circuit (such as a processor die, a controller die, or a memory die), a microelectromechanical systems (MEMS) die, an optical device, or any other suitable type of device die.
  • the electronic component can comprise a passive device such as a capacitor, inductor, or other surface-mounted device.
  • Circuitry (such as active components like transistors) can be patterned at or near active surface(s) of the die in various embodiments. The active surface may be on a side of the die which is opposite the backside of the die. The backside may or may not include any active circuitry or passive devices.
  • An integrated device die can comprise a bonding surface and a back surface opposite the bonding surface.
  • the bonding surface can have a plurality of conductive bond pads including a conductive bond pad, and a non-conductive material proximate to the conductive bond pad.
  • the conductive bond pads of the integrated device die can be directly bonded to the corresponding conductive pads of the substrate or wafer without an intervening adhesive
  • the non-conductive material of the integrated device die can be directly bonded to a portion of the corresponding non-conductive material of the substrate or wafer without an intervening adhesive. Directly bonding without an adhesive is described throughout U.S. Patent Nos.
  • Various embodiments disclosed herein relate to directly bonded structures in which two elements can be directly bonded to one another without an intervening adhesive.
  • Two or more electronic elements which can be semiconductor elements (such as integrated device dies, wafers, etc.), may be stacked on or bonded to one another to form a bonded structure.
  • Conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked in the bonded structure.
  • the contact pads may comprise metallic pads formed in a nonconductive bonding region, and may be connected to underlying metallization, such as a redistribution layer (RDL).
  • RDL redistribution layer
  • the elements are directly bonded to one another without an adhesive.
  • a non-conductive or dielectric material of a first element can be directly bonded to a corresponding non-conductive or dielectric field region of a second element without an adhesive.
  • the non-conductive material can be referred to as a nonconductive bonding region or bonding layer of the first element.
  • the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-to-dielectric bonding techniques.
  • dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Patent Nos.
  • Suitable dielectric materials for direct bonding include but are not limited to inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon oxycarbonitride, silicon carbonitride or diamond-like carbon. In some embodiments, the dielectric materials do not comprise polymer materials, such as epoxy, resin or molding materials.
  • hybrid direct bonds can be formed without an intervening adhesive.
  • dielectric bonding surfaces can be polished to a high degree of smoothness.
  • the bonding surfaces can be cleaned and exposed to a plasma and/or etchants to activate the surfaces.
  • the surfaces can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes).
  • the activation process can be performed to break chemical bonds at the bonding surface, and the termination process can provide additional chemical species at the bonding surface that improves the bonding energy during direct bonding.
  • the activation and termination are provided in the same step, e.g., a plasma or wet etchant to activate and terminate the surfaces.
  • the bonding surface can be terminated in a separate treatment to provide the additional species for direct bonding.
  • the terminating species can comprise nitrogen.
  • the bonding surfaces can be exposed to fluorine. For example, there may be one or multiple fluorine peaks near layer and/or bonding interfaces. Thus, in the directly bonded structures, the bonding interface between two dielectric materials can comprise a very smooth interface with higher nitrogen content and/or fluorine peaks at the bonding interface. Additional examples of activation and/or termination treatments may be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
  • conductive contact pads of the first element can also be directly bonded to corresponding conductive contact pads of the second element.
  • a hybrid direct bonding technique can be used to provide conductor-to-conductor direct bonds along a bond interface that includes covalently direct bonded dielectric-to- dielectric surfaces, prepared as described above.
  • the conductor-to- conductor (e.g., contact pad to contact pad) direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
  • dielectric bonding surfaces can be prepared and directly bonded to one another without an intervening adhesive as explained above.
  • Conductive contact pads (which may be surrounded by nonconductive dielectric field regions) may also directly bond to one another without an intervening adhesive.
  • the respective contact pads can be recessed below exterior (e.g., upper) surfaces of the dielectric field or nonconductive bonding regions, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm.
  • the nonconductive bonding regions can be directly bonded to one another without an adhesive at room temperature in some embodiments in the bonding tool described herein and, subsequently, the bonded structure can be annealed. Annealing can be performed in a separate apparatus. Upon annealing, the contact pads can expand and contact one another to form a metal-to-metal direct bond.
  • hybrid bonding techniques such as Direct Bond Interconnect, or DBI®, available commercially from Adeia of San Jose, CA, can enable high density of pads connected across the direct bond interface (e.g., small or fine pitches for regular arrays).
  • the pitch of the bonding pads, or conductive traces embedded in the bonding surface of one of the bonded elements may be less 40 microns or less than 10 microns or even less than 2 microns.
  • the ratio of the pitch of the bonding pads to one of the dimensions of the bonding pad is less than 5, or less than 3 and sometimes desirably less than 2.
  • the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range between 0.3 to 5 microns.
  • the contact pads and/or traces can comprise copper, although other metals may be suitable.
  • a first element can be directly bonded to a second element without an intervening adhesive.
  • the first element can comprise a singulated element, such as a singulated integrated device die.
  • the first element can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies.
  • the first element can be considered a host substrate and is mounted on a support in the bonding tool to receive the second element from a pick-and-place or robotic end effector.
  • the second element of the illustrated embodiments comprises a die.
  • the second element can comprise a carrier or a flat panel.or substrate (e.g., a wafer).
  • the first and second elements can be directly bonded to one another without an adhesive, which is different from a deposition process.
  • a width of the first element in the bonded structure can be similar to a width of the second element.
  • a width of the first element in the bonded structure can be different from a width of the second element.
  • the width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element.
  • the first and second elements can accordingly comprise non-deposited elements.
  • directly bonded structures unlike deposited layers, can include a defect region along the bond interface in which nanovoids are present.
  • the nanovoids may be formed due to activation of the bonding surfaces (e.g., exposure to a plasma).
  • the bond interface can include concentration of materials from the activation and/or last chemical treatment processes.
  • a nitrogen peak can be formed at the bond interface.
  • an oxygen peak can be formed at the bond interface.
  • the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride.
  • the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds.
  • the bonding layers can also comprise polished surfaces that are planarized to a high degree of smoothness.
  • the bonding layers may have a surface roughness of less than 2 nm root mean square (RMS) per micron, or less than 1 nm RMS per micron.
  • RMS root mean square
  • metal-to-metal bonds between the contact pads in direct hybrid bonded structures can be joined such that conductive features grains, for example copper grains on the conductive features grow into each other across the bond interface.
  • the copper can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface.
  • the bond interface can extend substantially entirely to at least a portion of the bonded contact pads, such that there is substantially no gap between the nonconductive bonding regions at or near the bonded contact pads.
  • a barrier layer may be provided under the contact pads (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the contact pads, for example, as described in US 2019/0096741, which is incorporated by reference herein in its entirety and for all purposes.
  • the disclosed technology relates to a microelectronic device comprising: a first integrated device die; a thermoelectric element bonded to the first integrated device die; and a heat sink disposed over at least the thermoelectric element, wherein the thermoelectric element is configured to transfer heat from the first integrated device die to the heat sink, the thermoelectric element directly bonded to the first integrated device die without an adhesive.
  • the first integrated device die comprises active circuitry.
  • thermoelectric element is directly bonded to the backside of the first integrated device die.
  • the interface between the first integrated device die and the thermoelectric element comprises conductor-to-conductor direct bonds.
  • the interface between the first integrated device die and the thermoelectric element further comprises non-conductor to non-conductor direct bonds.
  • a carrier element is disposed between the thermoelectric element and the heat sink.
  • the carrier element is devoid of active circuitry.
  • the carrier element comprises silicon, ceramic, Aluminum, Aluminum Nitride, or Silicon Carbide.
  • the carrier element comprises a material having a thermal conductivity greater than 1 W/cm/°C.
  • thermoelectric element is grown on the carrier element by a stenciling or printing process.
  • thermoelectric element is grown into cavities in the carrier element by a sintering process.
  • thermoelectric element is directly bonded to the carrier element without an adhesive.
  • the interface between thermoelectric element and the carrier element comprises dielectric-to-dielectric direct bonds.
  • heat is transfered from the first integrated device die to the heat sink during operation of the thermoelectric element.
  • a second integrated device die is disposed on the thermoelectric element and contacting the heat sink.
  • a second integrated device die is disposed on the first integrated device die and adjacent to the thermoelectric element.
  • thermoelectric element is electrically connected with the second integrated device die through the first integrated device die.
  • thermoelectric element is attached to bondwires for connecting to an external electrical power source.
  • thermoelectric element is electrically connected with the first integrated device die by way of metal contacts.
  • thermoelectric element is electrically connected with through-substrate vias in the first integrated device die.
  • thermoelectric element is configured for zoned control of cooling the first integrated device die.
  • a plurality of temperature sensors is disposed in the first integrated device die or the thermoelectric element, wherein each temperature sensor is associated with two electrical contacts for actuating a portion of the thermoelectric element.
  • the microelectronic device further comprises a plurality of electrical contact pairs, each electrical contact pair independently controlling a portion of the thermoelectric element.
  • thermoelectric element is actuated by the first integrated device die, the thermoelectric element, or an external chip.
  • the disclosed technology relates to a microelectronic device comprising: a first integrated device die; a thermoelectric element formed on the first integrated device die; and a heat sink disposed over at least the thermoelectric element, wherein the thermoelectric element is configured to transfer heat from the first integrated device die to the heat sink.
  • the thermoelectric element is grown on the first integrated device die.
  • thermoelectric element is deposited on the first integrated device die.
  • the first integrated device die comprises active circuitry.
  • thermoelectric element is grown on the backside of the first integrated device die.
  • thermoelectric element is grown on the first integrated device die by a stenciling or printing process.
  • heat is transfered from the first integrated device die to the heat sink during operation of the thermoelectric element.
  • a second integrated device die is disposed on the thermoelectric element and contacting the heat sink.
  • a second integrated device die is disposed on the first integrated device die and adjacent to the thermoelectric element.
  • thermoelectric element is electrically connected with the second integrated device die through the first integrated device die.
  • thermoelectric element is attached to bondwires for connecting to an external electrical power source.
  • thermoelectric element is electrically connected with the first integrated device die by way of metal contacts.
  • thermoelectric element is electrically connected with through-substrate vias in the first integrated device die.
  • thermoelectric element is configured for zoned control of cooling the first integrated device die.
  • a plurality of temperature sensors is disposed in the first integrated device die or the thermoelectric element, wherein each temperature sensor is associated with two electrical contacts for actuating a portion of the thermoelectric element.
  • the microelectronic device further comprises a plurality of electrical contact pairs, each electrical contact pair independently controlling a portion of the thermoelectric element.
  • thermoelectric element is actuated by the first integrated device die, the thermoelectric element, or an external chip.
  • the disclosed technology relates to a microelectronic device comprising: a first integrated device die; a thermoelectric element disposed on the first integrated device die; and a carrier element disposed on the thermoelectric element, wherein the thermoelectric element is configured for zoned control of cooling the first integrated device die.
  • the first integrated device die comprises a plurality of zones, and wherein at least one of the zones is activated by a temperature trigger, the temperature trigger received from a thermal sensor.
  • the thermal sensor is disposed in the first integrated device die or the thermoelectric element.
  • the carrier element is devoid of active circuitry.
  • thermoelectric element is grown on the backside of the first integrated device die by a stenciling or printing process.
  • thermoelectric element is directly bonded to the backside of the first integrated device die.
  • the disclosed technology relates to a microelectronic device comprising: a first integrated device die; a thermoelectric element disposed on the first integrated device die; a carrier element disposed on the thermoelectric element; and a heat sink disposed over at least the carrier element, wherein the thermoelectric element is configured to transfer heat from the first integrated device die to the heat sink.
  • the carrier element is devoid of active circuitry.
  • the microelectronic device comprises an additional carrier element disposed between the first integrated device die and the thermoelectric element.
  • the first integrated device die comprises active circuitry, and wherein the the thermoelectric element is grown on the backside of the first integrated device die by a stenciling or printing process.
  • the first integrated device die comprises active circuitry, and wherein the the thermoelectric element is directly bonded to the backside of the first integrated device die.
  • the carrier element comprises silicon or ceramic.
  • thermoelectric element is grown on the carrier element by a stenciling or printing process.
  • thermoelectric element is grown into cavities in the carrier element by a sintering process.
  • thermoelectric element is directly bonded to the carrier element without an adhesive.
  • heat is transfered from the first integrated device die to the heat sink through the carrier element during operation of the thermoelectric element.
  • a second integrated device die is disposed on the thermoelectric element and contacting the heat sink.
  • a second integrated device die is disposed on the first integrated device die and adjacent to the thermoelectric element.
  • thermoelectric element is electrically connected with the second integrated device die through the first integrated device die.
  • thermoelectric element is attached to bondwires for connecting to an external electrical power source.
  • thermoelectric element is electrically connected with the first integrated device die by way of metal contacts.
  • thermoelectric element is electrically connected with through-substrate vias in the first integrated device die.
  • thermoelectric element a plurality of temperature sensors is disposed in the thermoelectric element, wherein each temperature sensor is associated with two electrical contacts for actuating a portion of the thermoelectric element.
  • yhe microelectronic device further comprises a plurality of electrical contact pairs, each electrical contact pair independently controlling a portion of the thermoelectric element.
  • the disclosed technology relates to a microelectronic device configured for direct bonding, comprising: a carrier element, the carrier element devoid of active circuitry; and a thermoelectric element grown on the carrier element by a stenciling or printing process, the thermoelectric element comprising a surface configured for direct hybrid bonding.
  • the disclosed technology relates to a microelectronic device configured for direct bonding, comprising: a carrier element, the carrier element devoid of active circuitry; and a thermoelectric element grown into cavities in the carrier element by a sintering process, the thermoelectric element comprising a surface configured for direct hybrid bonding.
  • the disclosed technology relates to a microelectronic device configured for direct bonding, comprising: a carrier element, the carrier element devoid of active circuitry; and a thermoelectric element, comprising a surface directly bonded to the carrier element without an adhesive and an opposite surface configured for direct hybrid bonding.
  • the disclosed technology relates to a method for forming a microelectronic device, the method comprising: providing a first integrated device die comprising active circuitry; and growing a thermoelectric element on the backside of the first integrated device die.
  • thermoelectric element is grown on the first integrated device die by a stenciling or printing process.
  • thermoelectric element is electrically connected with the first integrated device die by way of metal contacts.
  • the disclosed technology relates to a method for forming a microelectronic device, the method comprising: providing a carrier element devoid of active circuitry; growing a thermoelectric element on the carrier element; and preparing a surface of the thermoelectric element for direct hybrid bonding.
  • thermoelectric element is grown on the first integrated device die by a stenciling or printing process.
  • the carrier element comprises silicon or ceramic.
  • a method for forming a microelectronic device comprising: providing a carrier element devoid of active circuitry; forming cavities in the carrier element; growing a thermoelectric element on the carrier element and into the cavities; and preparing a surface of the thermoelectric element for direct hybrid bonding.
  • thermoelectric element is grown by a sintering process.
  • the carrier element comprises silicon or ceramic.
  • the disclosed technology relates to a method for forming a microelectronic device, the method comprising: providing a wafer comprising a thermoelectric element; directly bonding a side of the wafer to a carrier element; thinning the wafter from an opposite side to reveal the thermoelectric element; and preparing a surface of the thermoelectric element for direct hybrid bonding.
  • the carrier element is devoid of active circuitry.
  • the carrier element comprises silicon or ceramic.
  • the disclosed technology relates to a microelectronic device comprising: a first integrated device die; a thermoelectric element bonded to the first integrated device die; and a heat sink disposed over at least the thermoelectric element, wherein the thermoelectric element is configured to transfer heat from the first integrated device die to the heat sink, and wherein the thermoelectric element is actuated by the first integrated device die.
  • thermoelectric element is directly bonded to the first integrated device die without an adhesive.
  • the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.”
  • the word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements.
  • the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements.
  • the words “herein,” “above,” “below,” and words of similar import when used in this application, shall refer to this application as a whole and not to any particular portions of this application.
  • first element when a first element is described as being “on” or “over” a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements.
  • words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively.
  • the word “or” in reference to a list of two or more items that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
  • conditional language used herein such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.

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  • Engineering & Computer Science (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
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EP22912608.1A EP4454011A4 (en) 2021-12-20 2022-12-16 THERMOELECTRIC COOLING FOR CHIP BOXES
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