WO2023108785A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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WO2023108785A1
WO2023108785A1 PCT/CN2021/140813 CN2021140813W WO2023108785A1 WO 2023108785 A1 WO2023108785 A1 WO 2023108785A1 CN 2021140813 W CN2021140813 W CN 2021140813W WO 2023108785 A1 WO2023108785 A1 WO 2023108785A1
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layer
region
electrode layer
substrate
germanium
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PCT/CN2021/140813
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English (en)
French (fr)
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黄伟兴
朱慧珑
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北京超弦存储器研究院
中国科学院微电子研究所
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Priority to US17/783,627 priority Critical patent/US20240164110A1/en
Publication of WO2023108785A1 publication Critical patent/WO2023108785A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

Definitions

  • the present application relates to the field of semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof.
  • non-volatile memory devices and dynamic random access memory (Dynamic Random Access Memory, DRAM) devices are one of the most concerned devices in memory devices.
  • DRAM Dynamic Random Access Memory
  • the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, so as to improve the performance of the storage device.
  • An embodiment of the present application provides a semiconductor device, including:
  • a first electrode layer located on one side of the substrate
  • a functional layer located on the side of the first electrode layer away from the substrate, the functional layer includes a first region and a second region of a U-shaped structure surrounding the first region, the U of the second region The direction of the opening is parallel to the substrate and away from the first region, the material of the first region includes at least germanium, and the second region includes a U-shaped ferroelectric layer and a U-shaped gate stacked in sequence;
  • the second electrode layer is located on the side of the functional layer away from the substrate, the first electrode layer is one of the source layer or the drain layer, and the second electrode layer is the source layer or the drain layer Another type of polar layer.
  • the second region of the U-shaped structure is arc-shaped, and the radial length of the U-shaped opening gradually increases along a direction parallel to the substrate and away from the first region.
  • the material of the first region is germanium or silicon germanium.
  • the doping ratio of the germanium first increases and then decreases.
  • the germanium doping ratio ranges from 10% to 70%.
  • the material of the ferroelectric layer is HfZrO, and the thickness of the ferroelectric layer is in the range of 3-30 nanometers.
  • the substrate has an isolation layer surrounding the first electrode layer, the functional layer, and the second electrode layer, and the first contact, the second contact, and the gate contact penetrate through the isolation layer, respectively. It is electrically connected with the first electrode layer, the second electrode layer and the gate.
  • An embodiment of the present application provides a method for manufacturing a semiconductor device, including:
  • a first electrode layer, a semiconductor layer comprising at least germanium, and a second electrode layer are sequentially formed on one side of the substrate; the first electrode layer is one of a source layer or a drain layer, and the second electrode The layer is the other of the source layer or the drain layer;
  • a ferroelectric layer and a gate are sequentially formed in the U-shaped opening, the ferroelectric layer and the gate form a second region, and the second region surrounds the first region.
  • the material of the semiconductor layer including at least germanium is silicon germanium, and in a direction perpendicular to the substrate, the doping ratio of the germanium first increases and then decreases;
  • the etching the semiconductor layer from the sidewall of the semiconductor layer to form a U-shaped opening includes:
  • the material of the semiconductor layer including at least germanium is germanium
  • the etching the semiconductor layer from the sidewall of the semiconductor layer to form a U-shaped opening includes:
  • the semiconductor layer is etched from the sidewall of the semiconductor layer by atomic layer etching and an etchant having crystal plane selectivity to the germanium, so as to form a U-shaped opening.
  • An embodiment of the present application provides a semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer, the first electrode layer is one of a source layer or a drain layer, and the second electrode layer is The other of the source layer or the drain layer, the functional layer is located between the first electrode layer and the second electrode layer, the functional layer includes a first area and a second area of U-shaped structure surrounding the first area, the second area The direction of the U-shaped opening is parallel to the substrate and away from the first region, that is, the U-shaped opening faces outside, the material of the first region includes at least germanium, and the second region includes a U-shaped ferroelectric layer and a U-shaped gate stacked in sequence.
  • a ferroelectric layer with a U-shaped structure is used as the storage layer of the storage device.
  • the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing the electric field of the entire semiconductor device. storage window, and while keeping the storage window of the entire semiconductor device unchanged, the gate voltage can also be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the storage device.
  • FIG. 1 shows a schematic structural diagram of a semiconductor device provided by an embodiment of the present application
  • FIG. 2 shows a schematic structural diagram of another semiconductor device provided by an embodiment of the present application
  • FIG. 3 is a schematic top view of the semiconductor device shown in FIG. 2;
  • Fig. 4 is a schematic structural view obtained along the AA' direction section of the semiconductor device shown in Fig. 3;
  • FIG. 5 shows a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application
  • 6 to 18 are schematic structural diagrams of a semiconductor device manufactured according to the method for manufacturing a semiconductor device provided in an embodiment of the present application.
  • an embodiment of the present application provides a semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer, the first electrode layer being one of a source layer or a drain layer, The second electrode layer is the other of the source layer or the drain layer.
  • the functional layer is located between the first electrode layer and the second electrode layer.
  • the functional layer includes a first region and a second U-shaped structure surrounding the first region. region, the direction of the U-shaped opening in the second region is parallel to the substrate and away from the first region, that is, the U-shaped opening faces to the outside, the material of the first region includes at least germanium, and the second region includes U-shaped ferroelectric layers and U-shaped grid.
  • a ferroelectric layer with a U-shaped structure is used as the storage layer of the storage device.
  • the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing the electric field of the entire semiconductor device. storage window, and while keeping the storage window of the entire semiconductor device unchanged, the gate voltage can also be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the storage device.
  • FIG. 1 it is a schematic structural diagram of a semiconductor device provided by the embodiment of the present application.
  • the semiconductor device provided by the embodiment of the present application is a storage device, and the storage device can be, for example, a non-volatile storage device and a dynamic random access storage (DRAM) Dynamic Random Access Memory, DRAM) devices.
  • the semiconductor device provided in the embodiment of the present application may be a vertical transistor device, such as a vertical field effect transistor (Field Effect Transistor, FET).
  • FET Field Effect Transistor
  • the semiconductor device provided by the embodiment of the present application includes a substrate 110 , a first electrode layer 120 , a functional layer 130 and a second electrode layer 140 , as shown in FIG. 1 .
  • the substrate 110 may be a semiconductor substrate, such as a silicon substrate.
  • the first electrode layer 120 is located on one side of the substrate 110
  • the functional layer 130 is located on the side of the first electrode layer 120 away from the substrate 110
  • the second electrode layer 140 is located on the side of the functional layer 130 away from the substrate 110, that is to say , the first electrode layer 120, the functional layer 130 and the second electrode layer 140 are stacked sequentially, wherein the first electrode layer 110 is one of the source layer or the drain layer, and the second electrode layer 140 is the source layer or the drain layer.
  • Another type of polar layer is another type of polar layer.
  • the thickness of the first electrode layer 120 and the second electrode layer 140 is about 10-50 nanometers (nm), the first electrode layer 120 and the second electrode layer 140 are doped semiconductor layers, the first electrode layer 120 and the second electrode layer
  • the doping type of the layer 140 is the same, which can be N-type doping or P-type doping.
  • the first electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-2e20/cm 3 .
  • the second electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-2e20/cm 3 .
  • the first electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-2e20/cm 3 .
  • the second electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-2e20/cm 3 .
  • the functional layer 130 is located between the first electrode layer 120 and the second electrode layer 140, the functional layer 130 includes a first region 131 and a second region 132 of a U-shaped structure surrounding the first region 131, The U-shaped opening of the second region 132 is oriented parallel to the substrate 110 and away from the first region 131 , that is, the U-shaped opening of the second region 132 faces outward.
  • the U-shaped opening of the second region 132 includes a U-shaped ferroelectric layer 1321 and a U-shaped gate 1322 stacked in sequence.
  • the width of the first region 131 gradually decreases and then increases, that is, it presents a structure in which the upper and lower widths are larger than the middle width, similar to the letter X structure.
  • the U-shaped structure of the second region 132 is arc-shaped, and the radial length of the U-shaped opening increases gradually along a direction parallel to the substrate 110 and away from the first region 131 . That is to say, the U-shaped opening of the second region 132 has a curvature, and the curvature changes slowly in a direction approaching the first region 131 .
  • the arc-shaped U-shaped structure can subsequently form a U-shaped ferroelectric layer 1321 in the U-shaped opening, so that the U-shaped ferroelectric layer 1321 can improve the performance of the storage device.
  • the material of the first region 131 includes at least germanium, such as germanium or silicon germanium, and a U-shaped opening can be formed by using the material including germanium, so as to form a U-shaped ferroelectric layer 1321 in the U-shaped opening.
  • the doping ratio of germanium first increases and then decreases. That is to say, in a direction perpendicular to the substrate 110 , the doping ratio of germanium in the central region is greater than that in the upper and lower regions, so as to form the opening of the U-shaped structure.
  • the doping ratio of germanium can be gradually and slowly changed, which helps to form a U-shaped opening with a uniform curvature change.
  • the doping ratio of germanium ranges from 10% to 70%. If the doping ratio is too small, the opening of the U-shaped structure cannot be formed. If the doping ratio is too high, the lattice defects will increase, which may reduce the performance of the storage device. .
  • the arc shape of the opening of the U-shaped structure finally formed can be controlled by controlling the doping ratio of germanium.
  • the doping ratio of germanium from the central region to the upper and lower regions The greater the variation, the deeper the opening of the formed U-shaped structure is in the direction parallel to the substrate 110 .
  • the material of the ferroelectric layer 1321 may be a ferroelectric material, such as HfZrO, that is, HfxZr1-xO2. That is to say, the storage device of the present application uses ferroelectric materials to store data.
  • the thickness of the ferroelectric layer 1321 is in the range of 3-30 nm. If the ferroelectric layer 1321 is too thick, the ferroelectric properties will be lost, so choosing an appropriate thickness range can improve the performance of the storage device.
  • the material of the gate 1322 may be a material with good conductivity, such as TiN, TaN, W and so on.
  • the ferroelectric layer of U-shaped structure is used as the storage layer of the storage device.
  • the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing The storage window of the entire semiconductor device, and under the condition of keeping the storage window of the entire semiconductor device unchanged, the gate voltage can also be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the storage device.
  • the source, functional layer, and drain are stacked in sequence to form a channel structure perpendicular to the substrate surface, which is a vertical storage device and can be applied to 3D integration scenarios, which can further increase integration density and reduce device power consumption.
  • the semiconductor device further includes an isolation layer 150 , a first contact 161 , a second contact 162 and a gate contact 163 , as shown in FIG. 2 .
  • the isolation layer 150 is located on the substrate 110 and surrounds the first electrode layer 120 , the functional layer 130 and the second electrode layer 140 to isolate and protect devices.
  • the material of the isolation layer 150 may be a dielectric material with better insulation, such as silicon oxide.
  • the first contact 161, the second contact 162 and the gate contact 163 penetrate the isolation layer 150 to be electrically connected to the first electrode layer 120, the second electrode layer 140 and the gate 1322 respectively, so as to carry out the first electrode layer 120, the second electrode layer 140 and grid 1322 electrical extraction.
  • the doped well layer 170 there is a well layer 170 between the first electrode layer 120 and the substrate 110, as shown in FIG.
  • the doped well layer 170 has higher conductivity and can form a good electrical contact with the first electrode layer 120 .
  • the doping can be N-type doping, the doping element is As or P, and the doping concentration is 1e17-2e19/cm 3 .
  • the doping can also be P-type doping, the doping element is B or In, and the doping concentration is 1e17-2e19/cm 3 .
  • the second electrode layer 140 is covered with an etching stopper layer 180 and a dielectric layer 190 .
  • the etch stop layer 180 covers the second electrode layer 140 for protecting the second electrode layer 140 below it, and can also serve as an etch stop layer to avoid etching damage when forming the second contact 162 of the second electrode layer 140
  • the second electrode layer 140 .
  • the material of the etch stop layer 180 may be silicon oxide.
  • the etch stop layer 180 may have a thickness of 2-5 nm.
  • the etch stop layer 180 is also covered with a dielectric layer 190 .
  • the dielectric layer 190 is used to isolate the hard mask layer and the second electrode layer 140 when manufacturing the device, and can also be used to isolate the second contact 162 after forming the second contact 162 of the second electrode layer 140 to ensure that the second contact 162 is only electrically connected to the second electrode layer 140 in the semiconductor device.
  • the material of the dielectric layer 190 may be silicon nitride or a low-K material, and the thickness of the dielectric layer 190 may be 10-100 nanometers.
  • the second region 132 also includes an interface layer (not shown), the interface layer is located between the first region 131 and the second region 132, and the interface layer is used to improve the interface quality and further improve the semiconductor device. performance, the material of the interface layer can be silicon oxide.
  • the schematic structural diagrams of the semiconductor device provided in Fig. 1 and Fig. 2 are obtained by taking a cross-section along the BB' direction of the semiconductor device provided in Fig. 3 .
  • FIG. 4 it is a schematic diagram of a semiconductor structure obtained by taking a cross-section along the AA' direction of the semiconductor device provided in FIG. 3 . It can be seen from FIG. 4 that openings of the U-shaped structure exist on each side wall of the semiconductor device.
  • the semiconductor device includes a substrate, a first electrode layer, a functional layer and a second electrode layer, the first electrode layer is one of the source layer or the drain layer, and the second The electrode layer is another one of the source layer or the drain layer, the functional layer is located between the first electrode layer and the second electrode layer, and the functional layer includes a first region and a second region of a U-shaped structure surrounding the first region, The direction of the U-shaped opening in the second region is parallel to the substrate and away from the first region, that is, the U-shaped opening faces the outside, the material of the first region includes at least germanium, and the second region includes U-shaped ferroelectric layers and U-shaped ferroelectric layers stacked in sequence. grid.
  • a ferroelectric layer with a U-shaped structure is used as the storage layer of the storage device.
  • the U-shaped channel can increase the electric field of the ferroelectric layer, thereby increasing the electric field of the entire semiconductor device. storage window, and while keeping the storage window of the entire semiconductor device unchanged, the gate voltage can also be reduced, thereby reducing the power consumption of the semiconductor device and improving the performance of the storage device.
  • the embodiment of the present application further provides a method for manufacturing the semiconductor device.
  • FIG. 5 it is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. The method includes the following steps:
  • the first electrode layer 120 , the semiconductor layer 101 including at least germanium, and the second electrode layer 140 may be sequentially formed on one side surface of the substrate 110 .
  • the first electrode layer 120 , the semiconductor layer 101 including at least germanium, and the second electrode layer 140 may be formed by means of epitaxial growth.
  • the substrate 110 may be a semiconductor substrate, such as a silicon substrate.
  • a well layer 170 can also be firstly formed in the substrate 110, as shown in FIG. Compared with the substrate 110 formed later, the doped well layer 170 has higher conductivity and can form a good electrical contact with the first electrode layer 120 .
  • the doping can be N-type doping, the doping element is As or P, and the doping concentration is 1e17-2e19/cm 3 .
  • the doping can also be P-type doping, the doping element is B or In, and the doping concentration is 1e17-2e19/cm 3 .
  • the well layer 170 may be formed on the silicon substrate by implanting dopant ions and performing an annealing process.
  • an N-type field effect transistor (Field Effect Transistor, FET) is implanted with P-type impurities to form the well layer 170
  • a P-type field effect transistor (Field Effect Transistor, FET) is implanted with N-type impurities to form the well layer 170 .
  • the thickness of the first electrode layer 120 and the second electrode layer 140 is about 10-50 nanometers, and the first electrode layer 120
  • the second electrode layer 140 is a doped semiconductor layer, and the doping types of the first electrode layer 120 and the second electrode layer 140 are the same, which can be N-type doping or P-type doping. Since the first electrode layer 110 is one of the source layer or the drain layer, and the second electrode layer 140 is the other of the source layer or the drain layer, the first electrode layer 120 and the second electrode layer can be made The conductivity of the second electrode layer 140 is better, specifically, in-situ doping can be used for doping.
  • the first electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-2e20/cm 3 .
  • the second electrode layer 120 is a P-type doped silicon layer, the doping element is B or In, and the doping concentration is 1e18-2e20/cm 3 .
  • the first electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-2e20/cm 3 .
  • the second electrode layer 120 is an N-type doped silicon layer, the doping element is As or P, and the doping concentration is 1e18-2e20/cm 3 .
  • the semiconductor layer 101 including at least germanium may be epitaxially grown on the first electrode layer 120 .
  • the material of the semiconductor layer 101 includes at least germanium, such as germanium or silicon germanium.
  • the thickness of the semiconductor layer 101 may range from 5-500 nm.
  • the material of the semiconductor layer 101 is germanium Ge, refer to FIG. 6 .
  • the doping ratio of germanium first increases and then decreases, that is, the Ge composition in the middle region is greater than Upper and lower regions of Ge composition. Since the Ge composition is high in the middle region and the Ge composition is low in the upper and lower regions, the etching rate of the high Ge composition is greater than that of the low Ge composition, so the U-shaped opening can be formed by subsequent etching.
  • the doping ratio of germanium ranges from 10% to 70%. If the doping ratio is too small, the opening of the U-shaped structure cannot be formed. If the doping ratio is too high, the lattice defects will increase, which may reduce the performance of the storage device. .
  • the doping ratio of germanium is increased from 10% in the upper and lower regions to 30% in the middle region, so that the doping ratio of germanium gradually changes in the direction perpendicular to the substrate 110 .
  • the semiconductor layer 101 with a changed germanium composition multiple layers of SiGe may be epitaxially formed, approximately 5-100 layers, each layer having a thickness of 1-5 nm.
  • the arc shape of the opening of the finally formed U-shaped structure can be controlled by controlling the doping ratio of germanium.
  • the greater the change in the doping ratio of germanium from the central region to the upper and lower regions, the U-shaped The opening of the structure is deeper in a direction parallel to the substrate 110 .
  • the doping ratio of germanium can be gradually and slowly changed, which helps to form a U-shaped opening with uniform arc changes. Therefore, in the actual manufacturing process, the variation range of the germanium composition, the number of epitaxial SiGe layers, and the variation trend of the Ge composition can be controlled as required.
  • the second electrode layer 140 is epitaxially formed on the semiconductor layer 101 , and then the etch stop layer 180 and the dielectric layer 190 are sequentially formed on the second electrode layer 140 .
  • the etch stop layer 180 and the dielectric layer 190 can be formed by a deposition process.
  • the etch stop layer 180 covers the second electrode layer 140 for protecting the second electrode layer 140 below it, and can also serve as an etch stop layer to avoid etching damage when forming the second contact 162 of the second electrode layer 140
  • the second electrode layer 140 The material of the etch stop layer 180 may be silicon oxide, or silicon oxide with high crystalline quality formed by a high temperature process, so as to improve the performance of the semiconductor device.
  • the etch stop layer 180 may have a thickness of 2-5 nm.
  • the etch stop layer 180 is also covered with a dielectric layer 190 .
  • the dielectric layer 190 is used to isolate the hard mask layer and the second electrode layer 140 when manufacturing the device, and can also be used to isolate the second contact 162 after forming the second contact 162 of the second electrode layer 140 to ensure that the second contact 162 is only electrically connected to the second electrode layer 140 in the semiconductor device.
  • the material of the dielectric layer 190 may be silicon nitride or a low-K material, and the thickness of the dielectric layer 190 may be 10-100 nanometers.
  • FIG. 8 is a schematic top view of the semiconductor device during the manufacturing process
  • FIG. 9 is a schematic view of the semiconductor structure obtained by taking a cross-section along the AA' direction of the semiconductor device provided in FIG. 8 .
  • the patterned photoresist layer 102 uses the patterned photoresist layer 102 to etch the dielectric layer 190 , the etch barrier layer 180 , the second electrode layer 140 , the semiconductor layer 101 , the first electrode layer 120 and part of the well layer 170 , as shown in FIG. 10 .
  • the photoresist layer 102 is removed, the dielectric material is deposited until covering all the semiconductor devices, and then a chemical mechanical polishing (CMP) process and an etching process are used to form shallow trench isolation (shallow trench isolation, STI) layer 103, as shown in FIG. 11 , FIG. 12 and FIG. 13 .
  • CMP chemical mechanical polishing
  • Figure 11 is a schematic diagram of a three-dimensional structure of a semiconductor device during the manufacturing process
  • Figure 12 is a schematic diagram of a semiconductor structure obtained by taking a cross-section along the AA' direction of the semiconductor device provided in Figure 11
  • Figure 13 is a schematic diagram of the semiconductor device provided along Figure 11 Schematic diagram of the semiconductor structure obtained by cross-sectioning in the BB' direction.
  • a shallow trench isolation (shallow trench isolation, STI) layer 103 is used to isolate the semiconductor device from other semiconductor devices that are simultaneously manufactured during integrated circuit manufacturing.
  • the dielectric material may be silicon oxide.
  • the etching process can be wet etching or dry etching.
  • the semiconductor layer 101 is etched to form a U-shaped opening 104, and the remaining semiconductor layer 101 is etched to form a first region 131.
  • the direction of the U-shaped opening 104 is parallel to the substrate 110 and away from the first region 131, that is, U-shaped.
  • the opening 104 faces outward, as shown in FIG. 14 , FIG. 15 and FIG. 16 .
  • 14 and 15 are schematic diagrams of the semiconductor structure obtained by taking a cross section along the AA' direction of the semiconductor device, and Fig.
  • FIG. 16 is a schematic diagram of the semiconductor structure obtained by taking a cross section along the BB' direction of the semiconductor device. It can be seen that, in the embodiment of the present application, etching is performed on the four sidewalls of the semiconductor device to form the U-shaped opening 104 .
  • the width of the first region 131 gradually decreases and then increases in the direction perpendicular to the substrate 110, that is, it presents a structure whose upper and lower widths are larger than the middle width, similar to the letter X structure.
  • the U-shaped opening 104 is arc-shaped, and the radial length of the U-shaped opening 104 gradually increases along a direction parallel to the substrate 110 and away from the first region 131 . That is to say, the U-shaped opening 104 has a curvature, and the curvature changes slowly in a direction approaching the first region 131 .
  • the arc-shaped U-shaped opening 104 can subsequently form a U-shaped ferroelectric layer 1321 in the U-shaped opening 104, so that the U-shaped ferroelectric layer 1321 can improve the performance of the memory device.
  • the doping ratio of germanium first increases and then decreases, the semiconductor layer 101 is etched from the sidewall of the semiconductor layer 101 by atomic layer etching, Since the Ge composition is high in the middle region and the Ge composition is low in the upper and lower regions, the etching rate of the high Ge composition is greater than the low etching rate of the Ge composition, so the etching process can be precisely controlled by atomic layer etching to form a U-shaped opening 104, as shown in FIG. 14 and FIG. 16.
  • the semiconductor layer 101 is etched from the sidewall of the semiconductor layer 101 by atomic layer etching, and an etchant with crystal plane selectivity to germanium is selected during etching, for example compared to The etching rate of (111) crystal plane, (100), (110) crystal plane is fast, and the angle difference between (111) crystal plane and (110) crystal plane is 54.7 degrees, so it can be precisely controlled by atomic layer etching An etching process to form a U-shaped opening 104 , as shown in FIG. 15 and FIG. 16 .
  • the first electrode layer 120 and the second electrode layer 140 When performing etching specifically, it is also necessary to select an etchant having a selective ratio to the first electrode layer 120 and the second electrode layer 140, so that the first electrode layer 120 and the first electrode layer 120 will not be damaged when the U-shaped opening 104 is formed by etching.
  • the second electrode layer 140 When performing etching specifically, it is also necessary to select an etchant having a selective ratio to the first electrode layer 120 and the second electrode layer 140, so that the first electrode layer 120 and the first electrode layer 120 will not be damaged when the U-shaped opening 104 is formed by etching.
  • the second electrode layer 140 When performing etching specifically, it is also necessary to select an etchant having a selective ratio to the first electrode layer 120 and the second electrode layer 140, so that the first electrode layer 120 and the first electrode layer 120 will not be damaged when the U-shaped opening 104 is formed by etching.
  • the second electrode layer 140 When performing etching specifically, it is also necessary to select an etchant
  • the ferroelectric layer 1321 and the gate 1322 are sequentially formed in the U-shaped opening 104.
  • the ferroelectric layer 1321 and the gate The pole 1322 constitutes the second region 132, and the second region 132 surrounds the first region 131, and the second region 132 has a U-shaped structure, and correspondingly, the ferroelectric layer 1321 and the grid 1322 are also U-shaped, and the first region 131 and the second Region 132 forms functional layer 130 .
  • Fig. 17 is a schematic diagram of a semiconductor structure obtained by taking a cross section along the direction AA' of the semiconductor device
  • Fig. 18 is a schematic diagram of a semiconductor structure obtained by taking a cross section along the direction BB' of the semiconductor device.
  • the ferroelectric layer 1321 and the gate 1322 may be formed by deposition and etching.
  • the material of the ferroelectric layer 1321 may be a ferroelectric material, such as HfZrO, that is, HfxZr1-xO2. That is to say, the storage device of the present application uses ferroelectric materials to store data.
  • the thickness of the ferroelectric layer 1321 is in the range of 3-30 nm. If the ferroelectric layer 1321 is too thick, the ferroelectric properties will be lost, so choosing an appropriate thickness range can improve the performance of the storage device.
  • the material of the gate 1322 may be a material with good conductivity, such as TiN, TaN, W and so on.
  • an interface layer (not shown) may be formed in the U-shaped opening, and the interface layer is located in the first region 131 between the second region 132 and the second region 132 , the interface layer is used to improve the interface quality and further improve the performance of the semiconductor device, and the material of the interface layer may be silicon oxide.
  • the process of forming the interface layer may be to oxidize the remaining part of the first region 131 of the semiconductor layer 101 with ozone.
  • the isolation layer 150 is finally formed, and the isolation layer 150 is located on the substrate 110 and surrounds the first electrode layer 120 , the functional layer 130 and the second electrode layer 140 to isolate and protect the device.
  • the material of the isolation layer 150 may be a dielectric material with better insulation, such as silicon oxide.
  • a first contact 161, a second contact 162 and a gate contact 163 that penetrate the isolation layer 150 and are electrically connected to the first electrode layer 120, the second electrode layer 140 and the gate 1322 are formed using a through hole process, referring to FIGS. Figure 4 shows.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to the part of the description of the structural embodiments.

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Abstract

本申请实施例提供了一种半导体器件及其制造方法，包括衬底、第一电极层、功能层和第二电极层，功能层位于第一电极层和第二电极层中间，功能层包括第一区域和包围第一区域的U型结构的第二区域，第二区域的U型开口的朝向平行于衬底且远离第一区域，即U型开口朝向外侧，第一区域的材料至少包括锗，第二区域包括依次层叠的U型铁电层和U型栅极。本申请实施例利用U型结构的铁电层作为存储器件的存储层，在保持栅极电压不变的情况下，U型沟道可以增大铁电层的电场，从而增大整个半导体器件的存储窗口，并且在保持整个半导体器件的存储窗口不变的情况下，还可以降低栅极电压，从而降低半导体器件的功耗，提升存储器件的性能。

Description

一种半导体器件及其制造方法
本申请要求于2021年12月15日提交中国国家知识产权局、申请号为CN202111535097.2、发明名称为“一种半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件领域，特别涉及一种半导体器件及其制造方法。
背景技术
随着半导体技术的快速发展，存储器件受到广泛关注。例如非易失性存储器件和动态随机存取存储(Dynamic Random Access Memory，DRAM)器件都是存储器件中备受关注的器件之一。
但是随着计算机技术等其他技术的急速发展，对于高性能的存储器件的需求也越来越大，因此，现在亟需高性能的存储器件。
发明内容
有鉴于此，本申请的目的在于提供一种半导体器件及其制造方法，提高存储器件的性能。
为实现上述目的，本申请有如下技术方案：
本申请实施例提供一种半导体器件，包括：
衬底；
第一电极层，位于所述衬底的一侧；
功能层，位于所述第一电极层远离所述衬底的一侧，所述功能层包括第一区域和包围所述第一区域的U型结构的第二区域，所述第二区域的U型开口的朝向平行于所述衬底且远离所述第一区域，所述第一区域的材料至少包括锗，所述第二区域包括依次层叠的U型铁电层和U型栅极；
第二电极层，位于所述功能层远离所述衬底的一侧，所述第一电极层为源极层或漏极层中的一种，所述第二电极层为源极层或漏极层中的另一种。
可选地，所述U型结构的第二区域为弧形，沿着平行于所述衬底且远离所述第一区域的方向，所述U型开口的径向长度逐渐增大。
可选地，所述第一区域的材料为锗或硅锗。
可选地，当所述第一区域的材料为硅锗时，在垂直于所述衬底的方向上，所述锗的掺杂比例先增大后减小。
可选地，所述锗的掺杂比例范围为10％-70％。
可选地，所述铁电层的材料为HfZrO，所述铁电层的厚度范围为3-30纳米。
可选地，所述衬底上具有包围所述第一电极层、所述功能层和所述第二电极层的隔离 层，第一接触、第二接触和栅极接触贯穿所述隔离层分别与所述第一电极层、所述第二电极层和所述栅极电连接。
本申请实施例提供一种半导体器件的制造方法，包括：
在衬底的一侧上依次形成第一电极层、至少包括锗的半导体层和第二电极层；所述第一电极层为源极层或漏极层中的一种，所述第二电极层为源极层或漏极层中的另一种；
从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口，剩余的半导体层为第一区域，所述U型开口的朝向平行于所述衬底且远离所述第一区域；
在所述U型开口内依次形成铁电层和栅极，所述铁电层和所述栅极构成第二区域，所述第二区域包围所述第一区域。
可选地，至少包括锗的半导体层的材料为硅锗，在垂直于所述衬底的方向上，所述锗的掺杂比例先增大后减小；
所述从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口包括：
利用原子层刻蚀从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口。
可选地，至少包括锗的半导体层的材料为锗；
所述从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口包括：
利用原子层刻蚀以及对所述锗具有晶面选择性的刻蚀剂，从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口。
本申请实施例提供了一种半导体器件，包括衬底、第一电极层、功能层和第二电极层，第一电极层为源极层或漏极层中的一种，第二电极层为源极层或漏极层中的另一种，功能层位于第一电极层和第二电极层中间，功能层包括第一区域和包围第一区域的U型结构的第二区域，第二区域的U型开口的朝向平行于衬底且远离第一区域，即U型开口朝向外侧，第一区域的材料至少包括锗，第二区域包括依次层叠的U型铁电层和U型栅极。本申请实施例利用U型结构的铁电层作为存储器件的存储层，在保持栅极电压不变的情况下，U型沟道可以增大铁电层的电场，从而增大整个半导体器件的存储窗口，并且在保持整个半导体器件的存储窗口不变的情况下，还可以降低栅极电压，从而降低半导体器件的功耗，提升存储器件的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1示出了本申请实施例提供的一种半导体器件的结构示意图；
图2示出了本申请实施例提供的另一种半导体器件的结构示意图；
图3为图2所示的半导体器件的俯视结构示意图；
图4为沿着图3所示的半导体器件的AA’方向截面得到的结构示意图；
图5示出了本申请实施例提供的一种半导体器件的制造方法的流程图；
图6-图18示出了根据本申请实施例提供的半导体器件的制造方法制造的半导体器件的结构示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是本申请还可以采用其它不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施例的限制。
其次，本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
目前，对于高性能的存储器件的需求也越来越大，因此，现在亟需高性能的存储器件。
基于以上技术问题，本申请实施例提供了一种半导体器件，包括衬底、第一电极层、功能层和第二电极层，第一电极层为源极层或漏极层中的一种，第二电极层为源极层或漏极层中的另一种，功能层位于第一电极层和第二电极层中间，功能层包括第一区域和包围第一区域的U型结构的第二区域，第二区域的U型开口的朝向平行于衬底且远离第一区域，即U型开口朝向外侧，第一区域的材料至少包括锗，第二区域包括依次层叠的U型铁电层和U型栅极。本申请实施例利用U型结构的铁电层作为存储器件的存储层，在保持栅极电压不变的情况下，U型沟道可以增大铁电层的电场，从而增大整个半导体器件的存储窗口，并且在保持整个半导体器件的存储窗口不变的情况下，还可以降低栅极电压，从而降低半导体器件的功耗，提升存储器件的性能。
为了更好地理解本申请的技术方案和技术效果，以下将结合附图对具体的实施例进行详细的描述。
参考图1所示，为本申请实施例提供的一种半导体器件的结构示意图，本申请实施例提供的半导体器件为存储器件，存储器件例如可以是非易失性存储器件和动态随机存取存储(Dynamic Random Access Memory，DRAM)器件。本申请实施例提供的半导体器件可以为垂直结构的晶体管器件，例如垂直结构的场效应晶体管(Field Effect Transistor，FET)。
本申请实施例提供的半导体器件包括衬底110、第一电极层120、功能层130和第二电极层140，参考图1所示。
衬底110可以是半导体衬底，例如硅衬底。第一电极层120位于衬底110的一侧，功能层130位于第一电极层120远离衬底110的一侧，第二电极层140位于功能层130远离衬底110的一侧，也就是说，第一电极层120、功能层130和第二电极层140依次层叠，其中，第一电极层110为源极层或漏极层中的一种，第二电极层140为源极层或漏极层中的另一种。
第一电极层120和第二电极层140的厚度约为10-50纳米(nm)，第一电极层120和第 二电极层140为掺杂的半导体层，第一电极层120和第二电极层140的掺杂类型相同，可以为N型掺杂，也可以为P型掺杂。
作为一种示例，第一电极层120为P型掺杂的硅层，掺杂元素为B或In，掺杂浓度为1e18-2e20/cm 3。第二电极层120为P型掺杂的硅层，掺杂元素为B或In，掺杂浓度为1e18-2e20/cm 3。
作为另一种示例，第一电极层120为N型掺杂的硅层，掺杂元素为As或P，掺杂浓度为1e18-2e20/cm 3。第二电极层120为N型掺杂的硅层，掺杂元素为As或P，掺杂浓度为1e18-2e20/cm 3。
在本申请的实施例中，功能层130位于第一电极层120和第二电极层140之间，功能层130包括第一区域131和包围第一区域131的U型结构的第二区域132，第二区域132的U型开口的朝向平行于衬底110且远离第一区域131，即第二区域132的U型开口朝向外侧。第二区域132的U型开口内包括依次层叠的U型铁电层1321和U型栅极1322。
第一区域131在垂直于衬底110所在的方向上，宽度逐渐减小后增大，即呈现上下宽度大于中部宽度的结构，类似字母X结构。
作为一种可能的实现方式，第二区域132的U型结构为弧形，沿着平行于衬底110且远离第一区域131的方向，U型开口的径向长度逐渐增大。也就是说，第二区域132的U型开口是具有弧度的，在靠近第一区域131的方向上，弧度缓慢变化。弧形的U型结构能够使得后续在该U型开口内形成U型结构的铁电层1321，以便U型结构的铁电层1321能够提升存储器件的性能。
第一区域131的材料至少包括锗，例如可以是锗或硅锗，利用包括锗的材料可以形成U型开口，以便在U型开口内形成U型结构的铁电层1321。
具体的，若第一区域131的材料为硅锗时，在垂直于衬底110的方向上，锗的掺杂比例先增大后减小。也就是说，在垂直于衬底110的方向上，中部区域的锗掺杂比例大于上下区域的锗掺杂比例，以便形成U型结构的开口。
在垂直于衬底110的方向上，锗的掺杂比例可以是逐渐缓慢变化的，有助于形成弧度变化均匀的U型开口。
锗的掺杂比例范围为10％-70％，若掺杂比例过小，则不能形成U型结构的开口，若掺杂比例过多，则晶格缺陷变多，可能会降低存储器件的性能。
在本申请的实施例中，在垂直于衬底110的方向上，可以通过控制锗的掺杂比例控制最终形成的U型结构的开口的弧形，从中部区域到上下区域锗的掺杂比例变化越大，形成的U型结构的开口在平行于衬底110方向上的深度越深。
铁电层1321的材料可以是铁电材料，例如HfZrO，即HfxZr1-xO2，也就是说，本申请的存储器件利用铁电材料实现数据的存储。
铁电层1321的厚度范围为3-30纳米。铁电层1321太厚会失去铁电特性，因此选用适宜的厚度范围能够提高存储器件的性能。
栅极1322的材料可以是导电性较好的材料，例如TiN、TaN和W等。
在本申请的实施例中，利用U型结构的铁电层作为存储器件的存储层，在保持栅极电 压不变的情况下，U型沟道可以增大铁电层的电场，从而增大整个半导体器件的存储窗口，并且在保持整个半导体器件的存储窗口不变的情况下，还可以降低栅极电压，从而降低半导体器件的功耗，提升存储器件的性能。并且本申请中源极、功能层和漏极依次层叠，形成垂直于衬底表面的沟道结构，为纵向存储器件，能够应用于3D集成的场景，可进一步增加集成密度，降低器件功耗。
在本申请的实施例中，半导体器件还包括隔离层150、第一接触161、第二接触162和栅极接触163，参考图2所示。
隔离层150位于衬底110上，并且包围第一电极层120、功能层130和第二电极层140，以隔离和保护器件。隔离层150的材料可以是绝缘性较好的介质材料，例如氧化硅。
第一接触161、第二接触162和栅极接触163贯穿隔离层150分别与第一电极层120、第二电极层140和栅极1322电连接，以便进行第一电极层120、第二电极层140和栅极1322的电引出。
在本申请的实施例中，第一电极层120和衬底110之间具有阱层170，参考图2所示，阱层170是对衬底110的部分区域进行掺杂后形成的，相较于衬底110，掺杂后的阱层170的导电性更高，能够与第一电极层120形成良好的电接触。掺杂可以是N型掺杂，掺杂元素为As或P，掺杂浓度为1e17-2e19/cm 3。掺杂也可以是P型掺杂，掺杂元素为B或In，掺杂浓度为1e17-2e19/cm 3。
在本申请的实施例中，第二电极层140上覆盖有刻蚀阻挡层180和介质层190。
刻蚀阻挡层180覆盖第二电极层140，用于保护其下的第二电极层140，还能作为刻蚀阻挡层，避免在形成第二电极层140的第二接触162时，刻蚀损伤第二电极层140。刻蚀阻挡层180的材料可以是氧化硅。刻蚀阻挡层180的厚度可以是2-5纳米。
在刻蚀阻挡层180上还覆盖有介质层190。介质层190用于在制造器件时，隔离硬掩膜层和第二电极层140，还能用于在形成第二电极层140的第二接触162后，隔离第二接触162，保证第二接触162仅与半导体器件中的第二电极层140形成电连接。介质层190的材料可以是氮化硅或低K材料，介质层190的厚度可以是10-100纳米。
在本申请的实施例中，第二区域132还包括界面层(图未示出)，界面层位于第一区域131和第二区域132之间，界面层用于改善界面质量，进一步提高半导体器件的性能，界面层的材料可以为氧化硅。
在本申请的实施例中，图1和图2提供的半导体器件的结构示意图是沿着图3提供的半导体器件的BB’方向进行截面获得的。
参考图4所示，为沿着图3提供的半导体器件的AA’方向进行截面获得的半导体结构示意图。由图4可以看出，U型结构的开口在半导体器件的每个侧壁都有。
综上所述，本申请实施例提供的半导体器件，包括衬底、第一电极层、功能层和第二电极层，第一电极层为源极层或漏极层中的一种，第二电极层为源极层或漏极层中的另一种，功能层位于第一电极层和第二电极层中间，功能层包括第一区域和包围第一区域的U型结构的第二区域，第二区域的U型开口的朝向平行于衬底且远离第一区域，即U型开口朝向外侧，第一区域的材料至少包括锗，第二区域包括依次层叠的U型铁电层和U型栅极。 本申请实施例利用U型结构的铁电层作为存储器件的存储层，在保持栅极电压不变的情况下，U型沟道可以增大铁电层的电场，从而增大整个半导体器件的存储窗口，并且在保持整个半导体器件的存储窗口不变的情况下，还可以降低栅极电压，从而降低半导体器件的功耗，提升存储器件的性能。
基于以上实施例提供的半导体器件，本申请实施例还提供了一种半导体器件的制造方法。参考图5所示，为本申请实施例提供的一种半导体器件的制造方法的流程图，该方法包括以下步骤：
S101，在衬底110的一侧上依次形成第一电极层120、至少包括锗的半导体层101和第二电极层140，参考图6所示。
在本申请的实施例中，可以在衬底110的一侧表面上依次形成第一电极层120、至少包括锗的半导体层101和第二电极层140。具体的，可以利用外延生长的方式形成第一电极层120、至少包括锗的半导体层101和第二电极层140。
衬底110可以是半导体衬底，例如硅衬底。在衬底110的一侧表面上形成第一电极层120之前，还可以首先在衬底110中形成阱层170，参考图6所示，阱层170是对衬底110的部分区域进行掺杂后形成的，相较于衬底110，掺杂后的阱层170的导电性更高，能够与第一电极层120形成良好的电接触。掺杂可以是N型掺杂，掺杂元素为As或P，掺杂浓度为1e17-2e19/cm 3。掺杂也可以是P型掺杂，掺杂元素为B或In，掺杂浓度为1e17-2e19/cm 3。具体可以是在硅衬底上通过注入掺杂离子并进行退火工艺形成阱层170。
作为一种示例，N型场效应晶体管(Field Effect Transistor，FET)注入P型杂质形成阱层170，P型场效应晶体管(Field Effect Transistor，FET)注入N型杂质形成阱层170。
在本申请的实施例中，在外延生长形成第一电极层120和第二电极层140之后，第一电极层120和第二电极层140的厚度约为10-50纳米，第一电极层120和第二电极层140为掺杂的半导体层，第一电极层120和第二电极层140的掺杂类型相同，可以为N型掺杂，也可以为P型掺杂。由于第一电极层110为源极层或漏极层中的一种，第二电极层140为源极层或漏极层中的另一种，可以通过掺杂使得第一电极层120和第二电极层140的导电性能更好，具体可以利用原位掺杂进行掺杂。
作为一种示例，针对P型FET器件，第一电极层120为P型掺杂的硅层，掺杂元素为B或In，掺杂浓度为1e18-2e20/cm 3。第二电极层120为P型掺杂的硅层，掺杂元素为B或In，掺杂浓度为1e18-2e20/cm 3。
作为另一种示例，针对N型FET器件，第一电极层120为N型掺杂的硅层，掺杂元素为As或P，掺杂浓度为1e18-2e20/cm 3。第二电极层120为N型掺杂的硅层，掺杂元素为As或P，掺杂浓度为1e18-2e20/cm 3。
在本申请的实施例中，在外延生长形成第一电极层120之后，可以在第一电极层120上外延生长至少包括锗的半导体层101。半导体层101的材料至少包括锗，例如可以是锗或硅锗。半导体层101的厚度范围可以是5-500纳米。
作为一种可能的实现方式，若半导体层101的材料为锗Ge时，则参考图6所示。
作为另一种可能的实现方式，若半导体层101的材料为硅锗SiGe时，在垂直于衬底110的方向上，锗的掺杂比例先增大后减小，即中部区域Ge组分大于上下区域Ge组分。由于中部区域Ge组分高，上下区域Ge组分低，Ge组分高的刻蚀速率大于Ge组分低的刻蚀速率，因而可以通过后续的刻蚀形成U型开口。
锗的掺杂比例范围为10％-70％，若掺杂比例过小，则不能形成U型结构的开口，若掺杂比例过多，则晶格缺陷变多，可能会降低存储器件的性能。
作为一种示例，参考图7所示，锗的掺杂比例从上下区域的10％增加到中部区域的30％，实现在垂直于衬底110的方向上，锗的掺杂比例逐渐进行变化。
具体形成锗组分变化的半导体层101时，可以外延多层SiGe，大约为5-100层，每层厚度1-5nm。在垂直于衬底110的方向上，可以通过控制锗的掺杂比例控制最终形成的U型结构的开口的弧形，从中部区域到上下区域锗的掺杂比例变化越大，形成的U型结构的开口在平行于衬底110方向上的深度越深。锗的掺杂比例可以是逐渐缓慢变化的，有助于形成弧度变化均匀的U型开口。因此可以在实际制造过程中，根据需要控制锗组分的变化范围、外延SiGe的层数及Ge组分变化趋势。
在本申请的实施例中，在外延形成半导体层101之后，继续在半导体层101外延形成第二电极层140，而后在第二电极层140继续依次形成刻蚀阻挡层180和介质层190。具体可以利用沉积工艺形成刻蚀阻挡层180和介质层190。
刻蚀阻挡层180覆盖第二电极层140，用于保护其下的第二电极层140，还能作为刻蚀阻挡层，避免在形成第二电极层140的第二接触162时，刻蚀损伤第二电极层140。刻蚀阻挡层180的材料可以是氧化硅，可以是利用高温工艺形成的结晶质量较高的氧化硅，以便提高半导体器件的性能。刻蚀阻挡层180的厚度可以是2-5纳米。
在刻蚀阻挡层180上还覆盖有介质层190。介质层190用于在制造器件时，隔离硬掩膜层和第二电极层140，还能用于在形成第二电极层140的第二接触162后，隔离第二接触162，保证第二接触162仅与半导体器件中的第二电极层140形成电连接。介质层190的材料可以是氮化硅或低K材料，介质层190的厚度可以是10-100纳米。
在本申请的实施例中，在依次形成阱层170、第一电极层120、半导体层101、第二电极层140、刻蚀阻挡层180和介质层190之后，还可以在介质层190上形成图案化的光刻胶层102，图案化的光刻胶层102定义半导体器件的有源区，半导体器件的有源区在衬底110上的投影在阱层170内，参考图8或图9所示，图8为半导体器件在制造过程中的俯视结构示意图，图9为沿着图8提供的半导体器件的AA’方向进行截面获得的半导体结构示意图。
而后利用图案化的光刻胶层102刻蚀介质层190、刻蚀阻挡层180、第二电极层140、半导体层101、第一电极层120和部分阱层170，参考图10所示。在刻蚀完毕后，去除光刻胶层102，沉积介质材料直至覆盖全部的半导体器件，而后使用化学机械研磨(Chemical Mechanical Polishing，CMP)工艺和刻蚀工艺形成浅沟槽隔离(shallow trench isolation，STI)层103，参考图11、图12和图13所示。图11为半导体器件在制造过程中的3维结 构示意图，图12为沿着图11提供的半导体器件的AA’方向进行截面获得的半导体结构示意图，图13为沿着图11提供的半导体器件的BB’方向进行截面获得的半导体结构示意图。浅沟槽隔离(shallow trench isolation，STI)层103用于隔离该半导体器件和在集成电路统一制造时同时制造形成的其他半导体器件。介质材料可以是氧化硅。刻蚀工艺可以是湿法刻蚀或干法刻蚀。
S102，从所述半导体层101的侧壁刻蚀所述半导体层101，以形成U型开口104，参考图14、图15和图16所示。
在本申请的实施例中，在刻蚀完毕介质层190、刻蚀阻挡层180、第二电极层140、半导体层101、第一电极层120和部分阱层170之后，从半导体层101的侧壁刻蚀所述半导体层101，以形成U型开口104，刻蚀剩余的半导体层101为第一区域131，U型开口104的朝向平行于衬底110且远离第一区域131，即U型开口104朝向外侧，参考图14、图15和图16所示。图14和图15为沿着半导体器件的AA’方向进行截面获得的半导体结构示意图，图16为沿着半导体器件的BB’方向进行截面获得的半导体结构示意图。由此可见，本申请实施例在半导体器件的4个侧壁均进行刻蚀形成U型开口104。
参考图14、图15和图16所示，第一区域131在垂直于衬底110所在的方向上，宽度逐渐减小后增大，即呈现上下宽度大于中部宽度的结构，类似字母X结构。
作为一种可能的实现方式，U型开口104为弧形，沿着平行于衬底110且远离第一区域131的方向，U型开口104的径向长度逐渐增大。也就是说，U型开口104是具有弧度的，在靠近第一区域131的方向上，弧度缓慢变化。弧形的U型开口104能够使得后续在该U型开口104内形成U型结构的铁电层1321，以便U型结构的铁电层1321能够提升存储器件的性能。
在从半导体层101的侧壁刻蚀半导体层101形成U型开口104时，不同的半导体层101的材料刻蚀工艺不同：
当半导体层101的材料为硅锗，在垂直于衬底110的方向上，锗的掺杂比例先增大后减小时，利用原子层刻蚀从半导体层101的侧壁刻蚀半导体层101，由于中部区域Ge组分高，上下区域Ge组分低，Ge组分高的刻蚀速率大于Ge组分低的刻蚀速率，因而可以通过原子层刻蚀精准控制刻蚀工艺，形成U型开口104，参考图14和图16所示。在具体进行刻蚀时，选用对第一电极层120和第二电极层140具有选择比的刻蚀剂，以便在刻蚀形成U型开口104时，不会损伤第一电极层120和第二电极层140。
当半导体层101的材料为锗时，利用原子层刻蚀从半导体层101的侧壁刻蚀半导体层101，并且在刻蚀时选用对锗具有晶面选择性的刻蚀剂，例如相较于(111)晶面，(100),(110)晶面的刻蚀速率快，(111)晶面和(110)晶面之间的角度差为54.7度，因而可以通过原子层刻蚀精准控制刻蚀工艺，形成U型开口104，参考图15和图16所示。在具体进行刻蚀时，还需要选用对第一电极层120和第二电极层140具有选择比的刻蚀剂，以便在刻蚀形成U型开口104时，不会损伤第一电极层120和第二电极层140。
S103，在所述U型开口104内依次形成铁电层1321和栅极1322，参考图17和图18所示。
在本申请的实施例中，在刻蚀得到U型开口104之后，在U型开口104内依次形成铁电层1321和栅极1322，参考图17和图18所示，铁电层1321和栅极1322构成第二区域132，第二区域132包围第一区域131，第二区域132呈U型结构，相应地，铁电层1321和栅极1322也呈U形，第一区域131和第二区域132构成功能层130。图17为沿着半导体器件的AA’方向进行截面获得的半导体结构示意图，图18为沿着半导体器件的BB’方向进行截面获得的半导体结构示意图。
铁电层1321和栅极1322可以是利用沉积工艺并进行刻蚀形成的。铁电层1321的材料可以是铁电材料，例如HfZrO，即HfxZr1-xO2，也就是说，本申请的存储器件利用铁电材料实现数据的存储。铁电层1321的厚度范围为3-30纳米。铁电层1321太厚会失去铁电特性，因此选用适宜的厚度范围能够提高存储器件的性能。栅极1322的材料可以是导电性较好的材料，例如TiN、TaN和W等。
在本申请的实施例中，在U型开口104中形成铁电层1321和栅极1322之前，还可以先在U型开口内形成界面层(图未示出)，界面层位于第一区域131和第二区域132之间，界面层用于改善界面质量，进一步提高半导体器件的性能，界面层的材料可以为氧化硅。形成界面层的工艺可以是利用臭氧氧化半导体层101的剩余部分第一区域131。
在本申请的实施例中，最后形成隔离层150，隔离层150位于衬底110上，并且包围第一电极层120、功能层130和第二电极层140，以隔离和保护器件。隔离层150的材料可以是绝缘性较好的介质材料，例如氧化硅。之后利用通孔工艺形成贯穿隔离层150并且分别与第一电极层120、第二电极层140和栅极1322电连接的第一接触161、第二接触162和栅极接触163，参考图2和图4所示。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于结构实施例，所以描述得比较简单，相关之处参见结构实施例的部分说明即可。
上述各个附图对应的流程或结构的描述各有侧重，某个流程或结构中没有详述的部分，可以参见其他流程或结构的相关描述。
以上所述仅是本申请的优选实施方式，虽然本申请已以较佳实施例披露如上，然而并非用以限定本申请。任何熟悉本领域的技术人员，在不脱离本申请技术方案范围情况下，都可利用上述揭示的方法和技术内容对本申请技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本申请技术方案保护的范围内。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。

Claims (10)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    第一电极层，位于所述衬底的一侧；
    功能层，位于所述第一电极层远离所述衬底的一侧，所述功能层包括第一区域和包围所述第一区域的U型结构的第二区域，所述第二区域的U型开口的朝向平行于所述衬底且远离所述第一区域，所述第一区域的材料至少包括锗，所述第二区域包括依次层叠的U型铁电层和U型栅极；
    第二电极层，位于所述功能层远离所述衬底的一侧，所述第一电极层为源极层或漏极层中的一种，所述第二电极层为源极层或漏极层中的另一种。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述U型结构的第二区域为弧形，沿着平行于所述衬底且远离所述第一区域的方向，所述U型开口的径向长度逐渐增大。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述第一区域的材料为锗或硅锗。
  4. 根据权利要求3所述的半导体器件，其特征在于，当所述第一区域的材料为硅锗时，在垂直于所述衬底的方向上，所述锗的掺杂比例先增大后减小。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述锗的掺杂比例范围为10％-70％。
  6. 根据权利要求1-5任意一项所述的半导体器件，其特征在于，所述铁电层的材料为HfZrO，所述铁电层的厚度范围为3-30纳米。
  7. 根据权利要求1-5任意一项所述的半导体器件，其特征在于，所述衬底上具有包围所述第一电极层、所述功能层和所述第二电极层的隔离层，第一接触、第二接触和栅极接触贯穿所述隔离层分别与所述第一电极层、所述第二电极层和所述栅极电连接。
  8. 一种半导体器件的制造方法，其特征在于，包括：
    在衬底的一侧上依次形成第一电极层、至少包括锗的半导体层和第二电极层；所述第一电极层为源极层或漏极层中的一种，所述第二电极层为源极层或漏极层中的另一种；
    从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口，剩余的半导体层为第一区域，所述U型开口的朝向平行于所述衬底且远离所述第一区域；
    在所述U型开口内依次形成铁电层和栅极，所述铁电层和所述栅极构成第二区域，所述第二区域包围所述第一区域。
  9. 根据权利要求8所述的制造方法，其特征在于，至少包括锗的半导体层的材料为硅锗，在垂直于所述衬底的方向上，所述锗的掺杂比例先增大后减小；
    所述从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口包括：
    利用原子层刻蚀从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口。
  10. 根据权利要求8所述的制造方法，其特征在于，至少包括锗的半导体层的材料为锗；
    所述从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口包括：
    利用原子层刻蚀以及对所述锗具有晶面选择性的刻蚀剂，从所述半导体层的侧壁刻蚀所述半导体层，以形成U型开口。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210036019A1 (en) * 2019-08-02 2021-02-04 Sandisk Technologies Llc Three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same
CN113178455A (zh) * 2020-05-05 2021-07-27 台湾积体电路制造股份有限公司 存储器器件和用于形成存储器器件的方法
CN113690247A (zh) * 2020-05-19 2021-11-23 爱思开海力士有限公司 包含铁电层的三维结构的半导体器件
WO2021236166A1 (en) * 2020-05-18 2021-11-25 Sandisk Technologies Llc Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210036019A1 (en) * 2019-08-02 2021-02-04 Sandisk Technologies Llc Three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same
CN113178455A (zh) * 2020-05-05 2021-07-27 台湾积体电路制造股份有限公司 存储器器件和用于形成存储器器件的方法
WO2021236166A1 (en) * 2020-05-18 2021-11-25 Sandisk Technologies Llc Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same
CN113690247A (zh) * 2020-05-19 2021-11-23 爱思开海力士有限公司 包含铁电层的三维结构的半导体器件

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