WO2023108703A1 - 显示面板和电子装置 - Google Patents

显示面板和电子装置 Download PDF

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Publication number
WO2023108703A1
WO2023108703A1 PCT/CN2021/139869 CN2021139869W WO2023108703A1 WO 2023108703 A1 WO2023108703 A1 WO 2023108703A1 CN 2021139869 W CN2021139869 W CN 2021139869W WO 2023108703 A1 WO2023108703 A1 WO 2023108703A1
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WIPO (PCT)
Prior art keywords
layer
display panel
thin film
film transistor
via hole
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Application number
PCT/CN2021/139869
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English (en)
French (fr)
Inventor
杨国强
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/623,275 priority Critical patent/US20240038766A1/en
Publication of WO2023108703A1 publication Critical patent/WO2023108703A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and an electronic device.
  • the under-screen camera technology is to place the front camera under the display panel, and it is not difficult to place the front camera under the display panel.
  • the difficulty is how to solve the problem of light transmission in the under-screen camera area.
  • the substrate material of the display panel can be transparent polyimide (Clear Polyimide, CPI), but transparent polyimide has the problems of large thermal stress, water absorption and large thermal expansion coefficient, which will lead to local uneven brightness (Mura) near the display panel bending (Bending) area.
  • CPI transparent Polyimide
  • the present application provides a display panel and an electronic device, so as to alleviate the technical problem of local uneven brightness at a position close to a bending area of an existing display panel.
  • An embodiment of the present application provides a display panel, which includes a display area and a bending area located on one side of the display area, and the display panel further includes:
  • a barrier layer located on one side of the first transparent substrate, at least including a first barrier portion located in the bending region;
  • the second inorganic layer is formed with a first via hole in the bending region, the first via hole penetrates the second inorganic layer and the first inorganic layer, and the first via hole
  • the orthographic projection of the bottom of the hole on the first transparent substrate falls within the range of the orthographic projection of the first blocking portion on the first transparent substrate.
  • the barrier layer further includes a plurality of second barrier portions arranged at intervals in the display area, and the second barrier portions are at least partially overlapped with the semiconductor layer.
  • a shielding layer located between the barrier layer and the first inorganic layer is further included, and the shielding layer includes: a first shielding layer corresponding to the first barrier portion part and a second shielding part corresponding to the second blocking part.
  • the bottom surface of the first via hole extends to the shielding layer and exposes the first shielding portion.
  • the second shielding portion is at least partially overlapped with the semiconductor layer.
  • the first shielding part is arranged overlapping with the first blocking part
  • the second shielding part is arranged overlapping with the second blocking part
  • a first groove is provided on a side of the first shielding portion away from the first blocking portion.
  • the second inorganic layer includes a gate insulating layer and an interlayer insulating layer stacked in sequence, and the gate insulating layer covers the semiconductor layer and the first inorganic layer. layer; the display panel also includes:
  • the gate layer is disposed on the gate insulating layer, the interlayer insulating layer covers the gate layer and the gate insulating layer, and the interlayer insulating layer is patterned to form the first a via hole, and forming a second via hole in the display area, the second via hole exposing part of the second shielding portion;
  • the first source-drain layer is disposed on the interlayer insulating layer, a power line is formed in the display area, and the power line is connected to the second shielding portion through the second via hole.
  • the display panel further includes a functional area disposed adjacent to the display area, and a first thin film transistor and a second thin film transistor disposed in the display area, the first thin film The transistor is arranged close to the functional area, and the display panel further includes:
  • the conductive electrode layer is arranged on the side of the first thin film transistor and the second thin film transistor away from the first transparent substrate, and a first pixel electrode is formed in the functional area, and a first pixel electrode is formed in the display area There is a second pixel electrode, the first pixel electrode is connected to the first thin film transistor, and the second pixel electrode is connected to the second thin film transistor;
  • the semiconductor layer forms the channel region of the first thin film transistor and the second thin film transistor and the source region and the drain region on both sides of the channel region in the display region;
  • the gates of the first thin film transistor and the second thin film transistor are formed in the display area, and a first signal transfer line is formed in the bending area, and the gate is arranged correspondingly to the channel area;
  • the first source-drain layer forms the first source and the first drain of the first thin film transistor and the second thin film transistor in the display area, and a second signal transition is formed in the bending area wiring, wherein the first source is connected to the source region, the first drain is connected to the drain region, and the first signal transition line is connected to the second signal transition line.
  • the display panel further includes a bridging layer located between the first thin film transistor and the conductive electrode layer, and the bridging layer forms a first Bridge electrodes, and form a second bridge electrode in the display area, the first pixel electrode is connected to the first thin film transistor through the first bridge electrode, and the second pixel electrode is connected to the first thin film transistor through the second bridge electrode connected with the second thin film transistor.
  • the display panel further includes:
  • the second source-drain layer is disposed on the first planarization layer, the second sources of the first thin film transistor and the second thin film transistor are formed in the display area, and are formed in the bending area There are multiple bonded traces formed;
  • a second planarization layer overlaid on the second source-drain layer and the first planarization layer, and the bridging layer is disposed on the second planarization layer;
  • a third planarization layer covering the bridging layer and the second planarization layer, and the conductive electrode layer is disposed on the third planarization layer;
  • first bridging electrode and the second bridging electrode are respectively connected to the corresponding second source, and the bonding wiring is connected to the second signal transfer wire.
  • a second groove is provided on a side of the first blocking portion away from the first transparent substrate.
  • the embodiment of the present application also provides an electronic device, which includes a functional element and a display panel, and the display panel includes a display area, a bending area located on one side of the display area, and a functional area arranged adjacent to the display area.
  • the functional elements are set corresponding to the functional areas; the display panel includes the display panel of one of the foregoing embodiments.
  • the display panel includes a barrier layer, a first inorganic layer, a semiconductor layer and a second inorganic layer which are sequentially arranged on the first transparent substrate, and the second inorganic layer is bent on the display panel.
  • a first via hole is formed in the region, the first via hole penetrates the first inorganic layer of the second inorganic layer, and the orthographic projection of the bottom of the first via hole on the first transparent substrate falls on the first barrier part Within the range of the orthographic projection on the first transparent substrate, the first via hole is exposed to the barrier portion, which can protect the first transparent substrate, avoiding damage to the first transparent substrate caused by water vapor and the etching process of the first via hole. In turn, the problem of uneven brightness near the bending area caused by the exposure of the first transparent substrate is avoided, thereby solving the problem of local uneven brightness of the existing display panel near the bending area.
  • FIG. 1 is a schematic top view structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a first cross-sectional structure of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a partial cross-sectional structure of the display panel in FIG. 2 .
  • FIG. 4 and FIG. 5 are detailed views of the first via hole provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of a second cross-sectional structure of a display panel provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a third cross-sectional structure of a display panel provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a fourth cross-sectional structure of a display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a partial cross-sectional structure of the display panel in FIG. 8 .
  • FIG. 10 is a schematic diagram of a fifth cross-sectional structure of a display panel provided by an embodiment of the present application.
  • Figure 1 is a schematic top view of the display panel provided by the embodiment of the present application
  • Figure 2 is a schematic cross-sectional view of the first type of display panel provided by the embodiment of the present application.
  • a schematic diagram of a partial cross-sectional structure of the display panel, and FIG. 4 and FIG. 5 are detailed views of the first via hole provided by the embodiment of the present application.
  • the display panel 100 includes a display area AA, a functional area FA disposed adjacent to the display area AA, and a bending area PA located on one side of the display area AA, and the bending area PA can be bent to the display panel. 100 for narrow bezels or no bezels.
  • the functional area FA can be located at any position in the display area AA, and the functional area FA can be used to realize various functions such as fingerprint recognition under the screen, face recognition, and a camera under the screen, and can also be used for the display function. Realize the true full screen.
  • the display panel 100 further includes a first transparent substrate 11 , a barrier layer 10 , a first inorganic layer 12 , a semiconductor layer 50 and a second inorganic layer 20 .
  • the barrier layer 10 is located on one side of the first transparent substrate 11, and at least includes a first barrier portion 10-1 located in the bending area PA, and the first inorganic layer 12 covers the first transparent substrate.
  • the semiconductor layer 50 is disposed on the side of the first inorganic layer 12 away from the first transparent substrate 11, and the second inorganic layer 20 covers the on the semiconductor layer 50 and the first inorganic layer 12 .
  • the second inorganic layer 20 is formed with a first via hole 21 in the bending area PA, the first via hole 21 penetrates the second inorganic layer 20 and the first inorganic layer 12, and the first via hole 21
  • the orthographic projection of the hole bottom of a via hole 21 on the first transparent substrate 11 falls within the range of the orthographic projection of the first barrier portion 10-1 on the first transparent substrate 11, so that the The first blocking portion 10 - 1 blocks the first transparent substrate 11 corresponding to the first via hole 21 , preventing the first opening 21 from exposing the first transparent substrate 11 .
  • the material of the first transparent substrate 11 includes transparent polyimide (Clear Polyimide, CPI), etc., and the transparent polyimide is compared with light yellow polyimide (Yellow Polyimide, YPI) has high transmittance, so the use of the transparent polyimide can improve the light transmittance of the functional area FA.
  • the use of the transparent polyimide will bring many undesirable results. For example, due to the high water vapor transmission rate of the transparent polyimide, water vapor will enter the first via hole 21 when preparing the first via hole 21. In the first transparent substrate 11; for example, the thermal stress of the transparent polyimide is large, which will cause the stress in the bending area PA to expand to the display area AA.
  • a sacrificial layer (such as SiOx/a-Si) is usually formed on the glass substrate first, and then the sacrificial layer Coating transparent polyimide on top to make a transparent substrate.
  • the etching gas CF4/O2 under the action of an electric field will cause an oxidation reaction to occur at the interface between the sacrificial layer in the DH area and the transparent polyimide, resulting in the sacrificial layer in the area near the DH
  • the interface with transparent polyimide is significantly different from that of the normal display area, so when the sacrificial layer is peeled off, this obvious difference in the interface will lead to a difference in the laser energy threshold when peeling off, and the difference in the laser energy threshold will cause the corresponding thin film
  • the degree of shrinkage of the transparent substrate at the transistor device is different, which will affect the stress state of the semiconductor layer, resulting in different semiconductor lattice defects, which will lead to the deterioration of the characteristics of the thin film transistor device near the DH region, and then lead to the display near the DH region. Brightness unevenness occurs in the area.
  • the DH process refers to the deep hole process, for example, the first
  • the first shielding part can block the first The via hole 21, so that when the first via hole 21 is formed in the bending area PA, the first via hole 21 penetrates the second inorganic layer 20 and the first inorganic layer 12, but due to the The existence of the first barrier part 10-1 prevents the first via hole 21 from exposing the first transparent substrate 11, thereby avoiding the problem caused by the use of transparent polyimide in the first transparent substrate 11. Brightness unevenness.
  • the material of the barrier layer 10 includes one of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), or other organic materials with good water and oxygen barrier properties.
  • inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), or other organic materials with good water and oxygen barrier properties.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • the material of the barrier layer 10 is preferably an inorganic material.
  • the display panel 100 includes the first transparent substrate 11, a barrier layer 10 disposed on one side of the first transparent substrate 11, and a barrier layer covering the barrier layer 10 and the first transparent substrate 11.
  • the display panel 100 further includes a third inorganic layer 14 and a second transparent substrate 13, the third inorganic layer 14 is located on the side of the first transparent substrate 11 away from the first inorganic layer 12 , the second transparent substrate 13 is located on the side of the third inorganic layer 14 away from the first transparent substrate 11 .
  • the material of the second transparent substrate 13 is the same as that of the first transparent substrate 11, and the material of the third inorganic layer 14 is the same as that of the first inorganic layer 12, so as to achieve better barrier Water vapor performance.
  • both the first transparent substrate 11 and the second transparent substrate 13 can be wet-film coated by coating, and high vacuum drying (High Vacuum Dry, HVCD) to remove the solvent, and then cure to form a film by curing (Curing).
  • HVCD High Vacuum Dry
  • the high vacuum drying can be carried out under the conditions of temperature ranging from 40° C. to 80° C. and bottom pressure ranging from 0-10 Pa for 250 seconds to 550 seconds. Curing can be carried out at a temperature of 400° C. to 450° C. for 30 minutes.
  • an inorganic film such as SiOx or SiNx or SiNx/SiOx/SiNx stack or SiOx/SiNx/SiOx/SiNx stack is formed on the first transparent substrate 11, and the formed inorganic film is etched to The bending area PA forms the first barrier portion 10-1.
  • the thickness of the barrier layer 10 is in the range of 500 angstroms to 6000 angstroms, when the barrier layer 10 is a SiNx/SiOx/SiNx stack structure, wherein the thickness of the first layer of SiNx is in the range of 50 angstroms to 2000 angstroms, SiOx The thickness ranges from 50 angstroms to 2000 angstroms, and the thickness of the second layer of SiNx is 50 angstroms to 2000 angstroms.
  • the thickness of the first layer of SiOx ranges from 50 angstroms to 500 angstroms
  • the thickness of the first layer of SiNx ranges from 500 angstroms to 2000 angstroms
  • the thickness of the second layer of SiOx The thickness of SiNx is in the range of 500 angstroms to 2000 angstroms
  • the thickness of the second layer of SiNx is in the range of 500 angstroms to 2000 angstroms.
  • the first inorganic layer 12 covers the barrier layer 10 and the first transparent substrate 11, and the material of the first inorganic layer 12 includes silicon oxide (SiOx), silicon nitride (SiNx) , silicon oxynitride (SiON) and other inorganic materials.
  • the semiconductor layer 50 is formed on the first inorganic layer 12 and disposed corresponding to the display area AA.
  • the second inorganic layer 20 covers the semiconductor layer 50 and the first inorganic layer 12 .
  • the second inorganic layer 20 includes a gate insulating layer 22 and an interlayer insulating layer 23 stacked in sequence, and the gate insulating layer 22 is disposed facing the semiconductor layer 50 .
  • the display panel 100 further includes a first thin film transistor T1 and a second thin film transistor T2 arranged in the second inorganic layer 20, and a first thin film transistor T1 and a second thin film transistor T2 arranged in the second inorganic layer 20
  • the conductive electrode layer 30 on the side away from the first transparent substrate 11 .
  • the first thin film transistor T1 and the second thin film transistor T2 are disposed on the same layer, and the first thin film transistor T1 is disposed close to the functional area FA.
  • the conductive electrode layer 30 is formed with a first pixel electrode 31 in the functional area FA, and a second pixel electrode 32 is formed in the display area AA.
  • the first pixel electrode 31 is connected to the first thin film transistor T1 connected, the second pixel electrode 32 is connected to the second thin film transistor T2.
  • a bridging layer 40 is also provided between the first thin film transistor T1 and the conductive electrode layer 30, and the bridging layer 40 forms a first bridging electrode 41 in the functional area FA, and forms a first bridging electrode 41 in the display area FA.
  • Area AA forms the second bridging electrode 42 .
  • the first bridging electrode 41 extends from the functional area FA to the display area AA, and is connected to the first thin film transistor T1, and the first pixel electrode 31 is connected to the first pixel electrode 31 through the first bridging electrode 41.
  • the first thin film transistor T1 is connected, and the second pixel electrode 32 is connected to the second thin film transistor T2 through the second bridge electrode 42 .
  • the display panel 100 further includes a gate layer 60 , a first source-drain layer 70 , a second source-drain layer 80 and a multi-layer planarization layer.
  • the semiconductor layer 50 is disposed on the first inorganic layer 12.
  • a buffer layer 15 may also be disposed between the first inorganic layer 12 and the semiconductor layer 50, and the semiconductor layer 50 is disposed on the semiconductor layer 50. on the buffer layer 15.
  • the material of the buffer layer 15 may include inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., and the buffer layer 15 can prevent unwanted impurities or pollutants (such as moisture , oxygen, etc.) diffuse from the first transparent substrate 11 into devices that may be damaged by these impurities or contaminants, while also providing a flat top surface.
  • inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc.
  • the semiconductor layer 50 forms the channel region 51 of the first thin film transistor T1 and the second thin film transistor T2 in the display area AA, and the source region 52 and the drain region 53 located on both sides of the channel region 51, so
  • the gate insulating layer 22 covers the semiconductor layer 50 and the first inorganic layer 12.
  • the display surface 100 also includes a buffer layer 15, the gate insulating layer 22 covers the on the semiconductor layer 50 and the buffer layer 15 .
  • the gate layer 60 is disposed on the gate insulating layer 22, and the gate layer 60 forms the gates 61 of the first thin film transistor T1 and the second thin film transistor T2 in the display area AA,
  • the gate 61 is disposed corresponding to the channel region 51 , and of course, the gate layer 60 can also form signal lines such as the gate scan line 63 in the display region AA.
  • the gate layer 60 also has a first signal transfer line 62 formed in the bending area PA, and the first signal transfer line 62 is connected to the gate scan line 63 for providing the gate 61 with scanning signals to control the corresponding turn-off of the first thin film transistor T1 and the second thin film transistor T2.
  • the interlayer insulating layer 23 covers the gate layer 60 and the gate insulating layer 22, and the interlayer insulating layer 23 is patterned to form the first via hole 21 in the bending area PA. , and form a third via hole 231 in the display area AA.
  • the first via hole 21 includes a first sub-hole 211 and a second sub-hole 212 , the opening of the first sub-hole 211 is larger than the second sub-hole 212 .
  • the first sub-hole 211 and the third via hole 231 are formed under the same process conditions, and the first sub-hole 211 and the third via hole 231 both penetrate the interlayer insulating layer 23 and part of the In the gate insulating layer 22 , the third via holes 231 respectively expose the corresponding source region 52 and the drain region 53 , as shown in FIG. 4 .
  • a fourth via hole 232 is also formed in the bending area PA, and the fourth via hole 232 also passes through the interlayer
  • the insulating layer 23 and part of the gate insulating layer 22 are used to expose the first signal transfer wire 62 .
  • first sub-hole 211 After forming the first sub-hole 211, dry etching is used to etch the film layer at the bottom of the first sub-hole 211 to form the second sub-hole 212, and the second sub-hole 212 runs through the The gate insulating layer 22 , buffer layer 15 and part of the first inorganic layer 12 at the bottom of the first sub-hole 211 are shown in FIG. 5 .
  • second sub-hole 212 When forming the second sub-hole 212 .
  • the first source-drain layer 70 is disposed on the interlayer insulating layer 23, and the first source-drain layer 70 forms the first thin film transistor T1 and the second thin film transistor in the display area AA.
  • the first source 71 and the first drain 72 of T2 pass through different third via holes 231 and correspond to the source region 52 and the corresponding The drain region 53 is connected.
  • the first source-drain layer 70 also has signal lines such as data lines 74 formed in the display area AA.
  • the first source-drain layer 70 is formed with a second signal transfer line 73 in the bending area PA, and a part of the second signal transfer line 73 is connected to the corresponding data line 74 for providing the corresponding data line 74.
  • the first thin film transistor T1 and the second thin film transistor T2 provide data signals.
  • Another part of the second signal transfer wire 73 is connected to the corresponding first signal transfer wire 62 through the fourth via hole 232 .
  • the first planarization layer 91 covers the first source-drain layer 70 and the interlayer insulating layer 23 and fills the first via hole 21 .
  • the first planarization layer 91 is an organic material, filling the first planarization layer 91 in the first via hole 21 can improve the bending performance of the bending area PA, and can simplify the The process of filling other organic materials in the first via hole 21 is described above.
  • the organic material solution when preparing the first planarization layer 91 formed of organic materials, the organic material solution is usually prepared on other film layers by coating, inkjet printing and other processes and solidified to form a film, and the The first barrier part 10-1 corresponding to the bottom of the first via hole 21 can effectively prevent the organic material solution from entering the first transparent substrate 11, and generate free charges in the first transparent substrate 11. .
  • the yellow light process of preparing the first via hole 21 it usually includes a dry etching process and a photoresist stripping process.
  • the bottom of the first via hole 21 corresponds to the first barrier part 10-1 It can also prevent the stripping liquid used for dry etching gas and stripping the photoresist from entering the first transparent substrate 11 , thereby avoiding uneven brightness in the display area AA close to the bending area PA.
  • the second source-drain layer 80 is disposed on the first planarization layer 91, and the second source-drain layer 80 forms the first thin film transistor T1 and the second thin film transistor T2 in the display area AA.
  • the second source 81 is connected to the first drain 72 through the via hole in the first planarization layer 91 .
  • the second source-drain layer 80 is also formed with a plurality of bonding wires 82 in the bending area PA, and the bonding wires 82 pass through the via holes of the first planarization layer 91 and the second The two signal transfer lines 73 are connected.
  • the second planarization layer 92 covers the second source-drain layer 80 and the first planarization layer 91, the bridge layer 40 is disposed on the second planarization layer 92, and the bridge layer 40 is The transparent conductive electrode layer is used to improve the transmittance of the functional area FA.
  • the material of the bridging layer 40 includes transparent conductive oxide (Transparent Conductive Oxide, TCO) materials such as ITO, IZO, ZnO or In2O3.
  • TCO Transparent Conductive Oxide
  • the first bridging electrodes 41 and the second bridging electrodes 42 formed in the bridging layer 40 are respectively connected to the corresponding second source electrodes 81 through different via holes in the second planarization layer 92 .
  • the third planarization layer 93 covers the bridging layer 40 and the second planarization layer 92, the conductive electrode layer 30 is disposed on the third planarization layer 93, and the conductive electrode layer 30 forms The first pixel electrode 31 and the second pixel electrode 32 are respectively connected to the corresponding first bridge electrode 41 and the second bridge electrode 42 through different via holes in the third planarization layer 93 .
  • the material of the conductive electrode layer 30 can be the same as that of the bridging layer 40, or the material of the conductive electrode layer 30 can also be selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd , Ir, Cr and other electrode materials.
  • the display panel 100 further includes a pixel definition layer 94 disposed on the conductive electrode layer 30 and the third planarization layer 93, and the pixel definition layer 94 corresponds to the first pixel electrode 31 and The second pixel electrode 32 is provided with a pixel opening 941 to expose the first pixel electrode 31 and the second pixel electrode 32 .
  • FIG. 6 is a second cross-sectional schematic diagram of a display panel provided by an embodiment of the present application.
  • the difference from the above embodiment is that in the display panel 101 of this embodiment, the The side of the first barrier 10-1 away from the first transparent substrate 11 is provided with a second groove 1011, the second groove 1011 can prolong the diffusion and infiltration path of water vapor, and reduce the first process.
  • the stress expansion caused by the thermal stress of the first transparent substrate 11 in the hole area of the hole 21 can achieve the purpose of releasing water vapor and stress, so that the appearance of the display area AA close to the bending area PA can be further improved.
  • the problem of uneven brightness is a second cross-sectional schematic diagram of a display panel provided by an embodiment of the present application.
  • the second groove 1011 can prolong the diffusion and infiltration path of water vapor, and reduce the first process.
  • the stress expansion caused by the thermal stress of the first transparent substrate 11 in the hole area of the hole 21 can achieve the purpose of releasing water vapor and stress, so that the appearance of
  • the provision of the second groove 1011 can also reduce the bending stress of the bending area PA and improve the bending reliability of the bending area PA of the display panel 100 .
  • the cross-sectional shape of the second groove 1011 includes square, trapezoid, triangle and so on. For other descriptions, please refer to the above-mentioned embodiments, which will not be repeated here.
  • FIG. 7 is a schematic cross-sectional structure diagram of a third display panel provided by the embodiment of the present application.
  • the difference from the above embodiment is that in the display panel 102 of this embodiment, the The display panel 102 further includes a shielding layer 16 between the barrier layer 10 and the first inorganic layer 12, and the barrier layer 10 further comprises a plurality of second barrier layers arranged at intervals in the display area AA. 10-2, the shielding portion 16 includes a first shielding portion 16-1 corresponding to the first blocking portion 10-1 and a second shielding portion 16 corresponding to the second blocking portion 10-2 -2.
  • the second barrier part 10-2 and the first barrier part 10-1 are arranged at intervals in the same layer, and part of the second barrier part 10-2 is arranged corresponding to the semiconductor layer 50, so that the first barrier part
  • the second barrier portion 10 - 2 is at least partially overlapped with the semiconductor layer 50 , that is, the first transistor T1 and the second transistor T2 both correspond to the second barrier portion 10 - 2 .
  • the shielding layer 16 is disposed on a side of the barrier layer 10 away from the first transparent substrate 11, wherein the first shielding portion 16-1 is disposed corresponding to the first barrier portion 10-1, The bottom surface of the first via hole 21 extends to the shielding layer 16 and exposes the first shielding portion 16 - 1 .
  • the second shielding portion 16 - 2 is disposed corresponding to the second blocking portion 10 - 2 , so that the second shielding portion 16 - 2 is at least partially overlapped with the semiconductor layer 50 .
  • first shielding portion 16-1 is overlapped with the first blocking portion 10-1
  • second shielding portion 16-2 is overlapped with the second blocking portion 10-2, as described
  • the shielding layer 16 and the barrier layer 10 can be formed through the same photomask. Specifically, after forming an inorganic thin film or an organic thin film on the first transparent substrate 11 , continue to prepare a metal thin film on the inorganic thin film or organic thin film, and the metal thin film may be a metal thin film such as molybdenum or aluminum.
  • the thickness of the shielding layer 16 is smaller than the thickness of the barrier layer 10 , the thickness of the shielding layer 16 ranges from 50 angstroms to 500 angstroms.
  • the shielding layer 16 is also formed when the barrier layer 10 is formed, and there is no need to add a photomask, which saves costs. More importantly, the shielding layer 16 can also shield the charges in the first transparent substrate 11 and the second transparent substrate 13 to prevent them from affecting the transistor characteristics of the display area AA .
  • the charges in the first transparent substrate 11 and the second transparent substrate 13 will be polarized, and after the charges are polarized, they are equivalent to the channels in the semiconductor layer 50 A dummy gate is formed on the back, which is similar to the back channel effect, which will cause the threshold voltage shift (Vth Shift) of the transistor, which in turn will cause image sticking (IS) to appear in the entire display area AA of the display panel 102 .
  • the charges in the first transparent substrate 11 and the second transparent substrate 13 mainly come from the electron transfer of dianhydride and diamine and the charges at the interface of the transparent substrates.
  • a constant voltage signal can be passed to the shielding layer 16 .
  • the first via hole 21 is formed by patterning the interlayer insulating layer 23
  • a second via hole 233 is also formed in the display area AA, and the second via hole 233 exposes part of the Describe the second shielding portion 16-2.
  • the first source-drain layer 70 is also formed with a power line (VDD) 75 in the display area AA, the power line 75 is also set on the same layer as the first source 71, and the power line 75
  • the second shielding part 16-2 is connected to the second shielding part 16-2 through the second via hole 233, and there is a constant DC voltage on the power line 75, so the second shielding part 16-2 connected to the power line 75 also has a constant DC voltage.
  • the present application is not limited thereto, and the second shielding part 16-2 of the present application may not be connected to the power line 75.
  • the shielding layer 16 may also be located on the barrier layer 10 facing the first One side of a transparent substrate 11.
  • the above-mentioned embodiments please refer to the above-mentioned embodiments, which will not be repeated here.
  • FIG. 8 is a schematic diagram of a fourth cross-sectional structure of a display panel provided by an embodiment of the present application
  • FIG. 9 is a schematic diagram of a partial cross-sectional structure of the display panel in FIG. 8 .
  • this embodiment adopts a double-gate structure, while the bridging layer 40 adopts multi-layer bridging, and the conductive electrode layer 30 adopts a laminated structure.
  • the gate layer 60 includes a first gate layer 60-1 and a second gate layer 60-2, and correspondingly, the gate insulating layer 22 also includes a first gate insulating layer 22-1 and a second gate insulating layer 22-2, the first gate insulating layer 22-1 is located between the semiconductor layer 50 and the first gate layer 60-1, the second gate insulating layer 22-2 is located between the first gate layer 60-1 and the second gate layer 60-2.
  • the first gate layer 60-1 forms the first gates 61-1 of the first thin film transistor T1 and the second thin film transistor T2 in the display area AA, and simultaneously forms corresponding gate scanning Line 63.
  • the first gate layer 60 - 1 has a first signal transition line 62 formed in the bending area PA.
  • the second gate layer 60-2 forms the second gate 61-2 of the first thin film transistor T1 and the second thin film transistor T2 in the display area AA.
  • the second gate The layer 60 - 2 may also form other signal lines in the display area AA, and form other corresponding signal transfer lines in the bending area PA.
  • the bridging layer 40 includes a first bridging layer 40-1 and a second bridging layer 40-2, the first bridging layer 40-1 is disposed on the second planarization layer 92, and accordingly, it is also necessary to set The fourth planarization layer 95, the fourth planarization layer 95 covers the first bridge layer 40-1 and the second planarization layer 92, the second bridge layer 40-2 is disposed on the On the fourth planarization layer 95 , the third planarization layer 93 covers the second bridging layer 40 - 2 and the fourth planarization layer 95 .
  • the first bridging layer 40-1 forms a first bridging electrode 41 in the functional area FA, and forms a second bridging electrode 42 in the display area AA.
  • the second bridging layer 40-2 has a third bridging electrode 43 formed in the functional area FA, and a fourth bridging electrode 44 formed in the display area AA.
  • the first bridging electrode 41 extends from the functional area FA to the display area AA, and is connected to the second source 81 of the first thin film transistor T1, and the third bridging electrode 43 is connected to the first thin film transistor T1.
  • a bridge electrode 41 is connected.
  • the second bridge electrode 42 is connected to the second source 81 of the second thin film transistor T2 , and the fourth bridge electrode 44 is connected to the second bridge electrode 42 .
  • the conductive electrode layer 30 is disposed on the third planarization layer 93, and the conductive electrode layer 30 includes a stacked first conductive electrode layer 30-1 and a second conductive electrode layer 30-2, so The first conductive electrode layer 30-1 forms a first auxiliary electrode 33 in the functional area FA, and forms a second auxiliary electrode 34 in the display area AA. The first auxiliary electrode 33 and the third bridging electrode 43, the second auxiliary electrode 34 is connected to the fourth bridging electrode 44.
  • the second conductive electrode layer 30-2 forms the first pixel electrode 31 in the functional area FA, and forms the second pixel electrode 32 in the display area AA.
  • the first pixel electrode 31 and the The first auxiliary electrode 33 is connected, and the second pixel electrode 32 is connected to the second auxiliary electrode 34 .
  • FIG. 10 is a schematic diagram of a fifth cross-sectional structure of a display panel provided by an embodiment of the present application.
  • the difference from the above embodiment is that in the display panel 104 of this embodiment, the A first groove 161 is disposed on a side of the first shielding portion 16-1 away from the first blocking portion 10-1.
  • the cross-sectional shape of the first groove 161 includes square, trapezoid, triangle and so on.
  • the display panel 104 of the present application also includes a light-emitting functional layer 200 disposed on the pixel definition layer 94, and in order to protect the light-emitting functional layer 200, the present application
  • the display panel 104 further includes an encapsulation layer 300 disposed on the light emitting functional layer 200 .
  • the light-emitting functional layer 200 includes a light-emitting unit 201 and a cathode 202 .
  • the light-emitting unit 201 is formed by the light-emitting material printed in the pixel opening of the pixel definition layer 94.
  • the light-emitting material of different colors forms light-emitting units of different colors, and the light-emitting units of different colors emit light of different colors, thereby realizing the display Color display of the panel.
  • the light-emitting unit 201 may include a red light-emitting unit formed of a red light-emitting material, a green light-emitting unit formed of a green light-emitting material, and a blue light-emitting unit formed of a blue light-emitting material.
  • the red light-emitting unit emits red light
  • the green light-emitting unit emits green light
  • light the blue light-emitting unit emits blue light.
  • the cathode 202 covers the light emitting unit 201 and the pixel definition layer 94 .
  • the light emitting unit 201 emits light under the cooperation of the corresponding pixel electrode (such as the first pixel electrode 31 or the second pixel electrode 32 ) and the cathode 202 .
  • the light emitting functional layer 200 may also include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the light emitting unit 201 and the pixel electrode; An electron injection layer (EIL) and an electron transport layer (ETL) between the unit 201 and the cathode 202 .
  • HIL hole injection layer
  • HTL hole transport layer
  • EIL electron injection layer
  • ETL electron transport layer
  • the hole injection layer receives the holes transported by the pixel electrode, the holes are transported to the light emitting unit 201 through the hole transport layer, the electron injection layer receives the electrons transported by the cathode 202, and the electrons are transported to the light emitting unit 201 through the electron transport layer, the holes and electrons Excitons are generated after the light-emitting unit 201 is combined, and the excitons transition from the excited state to the ground state to release energy and emit light.
  • the encapsulation layer 300 covers the light-emitting functional layer 200 and is used to protect the light-emitting unit 201 of the light-emitting functional layer 200 and prevent the light-emitting unit 201 from failing due to water vapor intrusion.
  • the encapsulation layer 300 can be encapsulated with a thin film, for example, the encapsulation layer 300 can be a laminated structure formed by sequentially laminating three layers of thin films of a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer or more Multilayer laminated structure.
  • the display panel 104 of the present application may also include structures such as a touch electrode layer, a polarizer, and a cover plate disposed on a side of the encapsulation layer 300 away from the light-emitting functional layer 200 .
  • structures such as a touch electrode layer, a polarizer, and a cover plate disposed on a side of the encapsulation layer 300 away from the light-emitting functional layer 200 .
  • the present application further provides an electronic device, the electronic device includes a functional element and the display panel according to one of the foregoing embodiments, and the functional element includes a camera, a fingerprint sensor, and the like.
  • the electronic devices include mobile phones, tablets, wearable electronic devices, and the like.
  • the present application provides a display panel and an electronic device.
  • the display panel includes a display area and a bending area located on one side of the display area.
  • the display panel also includes a first transparent substrate, a first inorganic layer located on one side of the transparent substrate, and The second inorganic layer located on the side of the first inorganic layer away from the first transparent substrate, the second inorganic layer is formed with a first via hole in the bending area, and the first via hole penetrates through the second inorganic layer and part of the first inorganic layer , so that the first inorganic layer retains a certain thickness of the entire film layer in the area corresponding to the first via hole, so as to protect the first transparent substrate and avoid the influence of water vapor and the etching process of the first via hole on the first transparent substrate, Furthermore, the problem of uneven brightness near the bending area caused by the exposure of the first transparent substrate is avoided, thereby solving the problem of local uneven brightness in the position near the bending area of the existing display panel.

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Abstract

一种显示面板（100）和电子装置；显示面板（100,101,102,103,104）包括显示区（AA）和位于显示区（AA）一侧的弯折区（PA），显示面板（100）还包括第一透明衬底（11）、位于第一透明衬底（11）一侧的阻挡层（10）、第一无机层（12）以及第二无机层（20），第二无机层（20）在弯折区（PA）形成有第一过孔（21）以裸露出阻挡部，阻挡部能够保护第一透明衬底（11），以缓解现有显示面板（100）在靠近弯折区（PA）的位置存在局部亮度不均的问题。

Description

显示面板和电子装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和电子装置。
 背景技术
随着显示技术的发展，市场对于高屏占比的显示面板的需求越来越迫切，显示面板正朝着全面屏、轻薄化方向发展，而全面屏的实现离不开屏下摄像头技术。顾名思义，屏下摄像头技术即是把前置摄像头放在显示面板的下面，而把前置摄像头放在显示面板的下面并不困难，困难的是如何解决屏下摄像头区的透光问题。为了很好的提高屏下摄像头区的透过率，显示面板的基板材料可采用透明聚酰亚胺（Clear Polyimide，CPI），但是透明聚酰亚胺存在热应力大、吸水以及热膨胀系数大的问题，如此会导致在靠近显示面板弯折（Bending）区的位置出现局部亮度不均（Mura）。
因此，现有显示面板在靠近弯折区的位置存在局部亮度不均的问题需要解决。
 技术问题
本申请提供一种显示面板和电子装置，以缓解现有显示面板在靠近弯折区的位置存在局部亮度不均的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，其包括显示区和位于所述显示区一侧的弯折区，所述显示面板还包括：
第一透明衬底；
阻挡层，位于所述第一透明衬底的一侧，至少包括位于所述弯折区的第一阻挡部；
第一无机层，覆于所述第一透明衬底以及所述阻挡层上；
半导体层，设置于所述第一无机层远离所述第一透明衬底的一侧；以及
第二无机层，覆于所述半导体层及所述第一无机层上；
其中，所述第二无机层在所述弯折区形成有第一过孔，所述第一过孔贯穿所述第二无机层和所述第一无机层，且所述第一过孔的孔底在所述第一透明衬底上的正投影落在所述第一阻挡部在所述第一透明衬底上的正投影范围内。
在本申请实施例提供的显示面板中，所述阻挡层还包括位于所述显示区的多个间隔排布的第二阻挡部，所述第二阻挡部至少与所述半导体层部分重叠设置。
在本申请实施例提供的显示面板中，还包括位于所述阻挡层和所述第一无机层之间的屏蔽层，所述屏蔽层包括：与所述第一阻挡部对应设置的第一屏蔽部和与所述第二阻挡部对应设置的第二屏蔽部。
在本申请实施例提供的显示面板中，所述第一过孔的底面延伸至所述屏蔽层，并暴露所述第一屏蔽部。
在本申请实施例提供的显示面板中，所述第二屏蔽部与所述半导体层至少部分重叠设置。
在本申请实施例提供的显示面板中，所述第一屏蔽部与所述第一阻挡部重叠设置，所述第二屏蔽部与所述第二阻挡部重叠设置。
在本申请实施例提供的显示面板中，所述第一屏蔽部远离所述第一阻挡部的一侧设置有第一凹槽。
在本申请实施例提供的显示面板中，所述第二无机层包括依次层叠设置的栅极绝缘层、层间绝缘层，所述栅极绝缘层覆于所述半导体层及所述第一无机层上；所述显示面板还包括：
栅极层，设置于所述栅极绝缘层上，所述层间绝缘层覆于所述栅极层及所述栅极绝缘层上，且所述层间绝缘层图案化形成所述第一过孔，并在所述显示区形成第二过孔，所述第二过孔裸露出部分所述第二屏蔽部；
第一源漏极层，设置于所述层间绝缘层上，在所述显示区形成电源线，所述电源线通过所述第二过孔与所述第二屏蔽部连接。
在本申请实施例提供的显示面板中，所述显示面板还包括临近所述显示区设置的功能区，以及设置在所述显示区的第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管靠近所述功能区设置，所述显示面板还包括：
导电电极层，设置于所述第一薄膜晶体管和所述第二薄膜晶体管远离所述第一透明衬底的一侧，且在所述功能区形成有第一像素电极，在所述显示区形成有第二像素电极，所述第一像素电极与所述第一薄膜晶体管连接，所述第二像素电极与所述第二薄膜晶体管连接；
其中，所述半导体层在所述显示区形成所述第一薄膜晶体管和所述第二薄膜晶体管的沟道区以及位于沟道区两侧的源区和漏区；所述栅极层在所述显示区形成所述第一薄膜晶体管和所述第二薄膜晶体管的栅极，并在所述弯折区形成有第一信号转接线，所述栅极与所述沟道区对应设置；所述第一源漏极层在所述显示区形成所述第一薄膜晶体管和所述第二薄膜晶体管的第一源极和第一漏极，并在所述弯折区形成有第二信号转接线，其中所述第一源极与所述源区连接，所述第一漏极与所述漏区连接，所述第一信号转接线与所述第二信号转接线连接。
在本申请实施例提供的显示面板中，所述显示面板还包括位于所述第一薄膜晶体管和所述导电电极层之间还设置有桥接层，所述桥接层在所述功能区形成第一桥接电极，并在所述显示区形成第二桥接电极，所述第一像素电极通过所述第一桥接电极与所述第一薄膜晶体管连接，所述第二像素电极通过所述第二桥接电极与所述第二薄膜晶体管连接。
在本申请实施例提供的显示面板中，所述显示面板还包括：
第一平坦化层，覆于所述第一源漏极层及所述层间绝缘层上，并填充所述第一过孔；
第二源漏极层，设置于所述第一平坦化层上，在所述显示区形成所述第一薄膜晶体管和所述第二薄膜晶体管的第二源极，并在所述弯折区形成有多个绑定走线；
第二平坦化层，覆于所述第二源漏极层及所述第一平坦化层上，所述桥接层设置所述第二平坦化层上；
第三平坦化层，覆于所述桥接层及所述第二平坦化层上，所述导电电极层设置于所述第三平坦化层上；
其中，所述第一桥接电极和所述第二桥接电极分别与对应的所述第二源极连接，所述绑定走线与所述第二信号转接线连接。
在本申请实施例提供的显示面板中，所述第一阻挡部远离所述第一透明衬底的一侧设置有第二凹槽。
本申请实施例还提供一种电子装置，其包括功能元件和显示面板，所述显示面板包括显示区、位于所述显示区一侧的弯折区以及临近所述显示区设置的功能区，所述功能元件对应所述功能区设置；所述显示面板包括前述实施例其中之一的显示面板。
 有益效果
本申请提供的显示面板和电子装置中，显示面板包括依次设置于第一透明衬底上的阻挡层、第一无机层、半导体层以及第二无机层，第二无机层在显示面板的弯折区形成有第一过孔，第一过孔贯穿第二无机层的所述第一无机层，且第一过孔的孔底在第一透明衬底上的正投影落在第一阻挡部在第一透明衬底上的正投影范围内，使第一过孔裸露出阻挡部，阻挡部能够保护第一透明衬底，避免了水汽以及第一过孔的蚀刻制程对第一透明衬底的影响，进而避免了第一透明衬底裸露引起的靠近弯折区出现亮度不均的问题，从而解决了现有显示面板在靠近弯折区的位置存在局部亮度不均的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的俯视结构示意图。
图2为本申请实施例提供的显示面板的第一种剖面结构示意图。
图3为图2中显示面板的局部剖面结构示意图。
图4和图5为本申请实施例提供的第一过孔的细节图。
图6为本申请实施例提供的显示面板的第二种剖面结构示意图。
图7为本申请实施例提供的显示面板的第三种剖面结构示意图。
图8为本申请实施例提供的显示面板的第四种剖面结构示意图。
图9为图8中显示面板的局部剖面结构示意图。
图10为本申请实施例提供的显示面板的第五种剖面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请结合参照图1至图5，图1为本申请实施例提供的显示面板的俯视结构示意图，图2为本申请实施例提供的显示面板的第一种剖面结构示意图，图3为图2中显示面板的局部剖面结构示意图，图4和图5为本申请实施例提供的第一过孔的细节图。所述显示面板100包括显示区AA、临近所述显示区AA设置的功能区FA以及位于所述显示区AA一侧的弯折区PA，所述弯折区PA可弯折到所述显示面板100的背面，以实现窄边框或无边框。所述功能区FA可位于所述显示区AA内的任意位置，所述功能区FA可用于实现屏下指纹识别、人脸识别、屏下摄像头等各种功能，且还可用于显示功能，以实现真正意义的全面屏。
具体地，所述显示面板100还包括第一透明衬底11、阻挡层10、第一无机层12、半导体层50以及第二无机层20。所述阻挡层10位于所述第一透明衬底11的一侧，且至少包括位于所述弯折区PA的第一阻挡部10-1，所述第一无机层12覆于所述第一透明衬底11以及所述阻挡层10上，所述半导体层50设置于所述第一无机层12远离所述第一透明衬底11的一侧，所述第二无机层20覆于所述半导体层50以及所述第一无机层12上。所述第二无机层20在所述弯折区PA形成有第一过孔21，所述第一过孔21贯穿所述第二无机层20和所述第一无机层12，且所述第一过孔21的孔底在所述第一透明衬底11上的正投影落在所述第一阻挡部10-1在所述第一透明衬底11上的正投影范围内，使所述第一阻挡部10-1遮挡对应所述第一过孔21处的第一透明衬底11，避免所述第一开孔21裸露出所述第一透明衬底11。
所述第一透明衬底11的材料包括透明聚酰亚胺（Clear Polyimide，CPI）等，所述透明聚酰亚胺相较于淡黄色聚酰亚胺（Yellow Polyimide，YPI）具有较高的透过率，故使用所述透明聚酰亚胺能够提高所述功能区FA的透光性。但是使用所述透明聚酰亚胺还会带来诸多不期望的结果，比如由于所述透明聚酰亚胺的水汽透过率大，会导致制备所述第一过孔21时水汽进入到所述第一透明衬底11内；又比如所述透明聚酰亚胺的热应力大，会导致所述弯折区PA的应力向所述显示区AA扩展。
更重要的是，在使用所述透明聚酰亚胺制备所述第一透明衬底11时，通常要在玻璃基板上先做一层牺牲层（如SiOx/a-Si），随后在牺牲层上涂布（Coating）透明聚酰亚胺，进而制作透明衬底基板。但在DH（Deep Hole，挖孔）制程时，刻蚀气体CF4/O2在电场作用下，会导致DH区域的牺牲层和透明聚酰亚胺的界面发生氧化反应，导致DH附近区域的牺牲层和透明聚酰亚胺的界面与正常显示区的有明显差异，如此在剥离牺牲层时，这种界面的明显差异会导致剥离时的激光能量阈值差异，而激光能量阈值的差异会导致对应薄膜晶体管器件处的透明衬底皱缩程度不同，进而会影响到半导体层的受力状态，导致半导体晶格缺陷不同，从而导致靠近DH区域的薄膜晶体管器件特性发生恶化，进而导致靠近DH区域的显示区出现亮度不均。其中DH制程是指挖深孔制程，比如本申请的所述第一过孔21即是该制程形成的。
而本申请通过在所述第一透明衬底11上设置阻挡层10，并在所述弯折区PA形成所述第一阻挡部10-1，所述第一遮挡部能够遮挡所述第一过孔21，如此在所述弯折区PA形成所述第一过孔21时，所述第一过孔21贯穿所述第二无机层20以及所述第一无机层12，但由于所述第一阻挡部10-1的存在，使所述第一过孔21不会裸露出所述第一透明衬底11，进而可避免所述第一透明衬底11使用透明聚酰亚胺导致的亮度不均现象。可选地，所述阻挡层10的材料包括氧化硅（SiOx）、氮化硅（SiNx）等无机材料中的一种，或者还可以为其他阻隔水氧性能好的有机材料，当然地，由于无机材料具有比较优异的阻隔水氧性能，故所述阻挡层10的材料可优选无机材料。
下面将具体阐述所述显示面板100上各区域的膜层结构：
所述显示面板100包括所述第一透明衬底11、设置在所述第一透明衬底11一侧的阻挡层10、覆于所述阻挡层10和所述第一透明衬底11上的第一无机层12、设置于所述第一无机层12上的半导体层50以及覆于所述半导体层50和所述第一无机层12上的所述第二无机层20。
可选地，所述显示面板100还包括第三无机层14和第二透明衬底13，所述第三无机层14位于所述第一透明衬底11远离所述第一无机层12一侧，所述第二透明衬底13位于所述第三无机层14远离所述第一透明衬底11的一侧。所述第二透明衬底13的材料和所述第一透明衬底11的材料相同，所述第三无机层14的材料和所述第一无机层12的材料相同，以实现更好的阻隔水汽性能。
可选地，所述第一透明衬底11和所述第二透明衬底13均可通过涂布（Coating）的方式进行湿膜涂布，湿膜涂布完成后进行高真空干燥（High Vacuum Dry，HVCD）以去除溶剂，然后通过固化（Curing）的方式进行固化成膜。其中，高真空干燥可采用在温度为40℃至80℃，底压为0-10Pa的条件下，干燥250秒至550秒。固化可采用在温度为400℃至450℃的条件下，固化30分钟。
具体地，在所述第一透明衬底11上形成SiOx或SiNx或SiNx/SiOx/SiNx叠构或SiOx/SiNx/SiOx/SiNx叠构等无机薄膜，并对形成的无机薄膜进行蚀刻以在所述弯折区PA形成所述第一阻挡部10-1。其中所述阻挡层10的厚度在500埃至6000埃的范围内，当所述阻挡层10为SiNx/SiOx/SiNx叠构时，其中第一层SiNx的厚度范围为50埃至2000埃，SiOx的厚度范围为50埃至2000埃，第二层SiNx厚度50埃至2000埃。当所述阻挡层10为SiOx/SiNx/SiOx/SiNx叠构时，其中第一层SiOx的厚度范围为50埃至500埃，第一层SiNx的厚度范围500埃至2000埃，第二层SiOx的厚度范围为500埃至2000埃，第二层SiNx的厚度范围为500埃至2000埃。
进一步地，所述第一无机层12覆于所述阻挡层10和所述第一透明衬底11上，所述第一无机层12的材料包括氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料。所述半导体层50形成在所述第一无机层12上，且对应所述显示区AA设置。所述第二无机层20覆于所述半导体层50和所述第一无机层12上。所述第二无机层20包括依次层叠设置的栅极绝缘层22、层间绝缘层23，所述栅极绝缘层22面向所述半导体层50设置。
进一步地，所述显示面板100还包括设置于所述第二无机层20内的第一薄膜晶体管T1和第二薄膜晶体管T2、设置于所述第一薄膜晶体管T1和所述第二薄膜晶体管T2远离所述第一透明衬底11一侧的导电电极层30。所述第一薄膜晶体管T1和所述第二薄膜晶体管T2同层设置，且所述第一薄膜晶体管T1靠近所述功能区FA设置。所述导电电极层30在所述功能区FA形成有第一像素电极31，并在所述显示区AA形成有第二像素电极32，所述第一像素电极31与所述第一薄膜晶体管T1连接，所述第二像素电极32与所述第二薄膜晶体管T2连接。
可选地，所述第一薄膜晶体管T1和所述导电电极层30之间还设置有桥接层40，所述桥接层40在所述功能区FA形成第一桥接电极41，并在所述显示区AA形成第二桥接电极42。其中所述第一桥接电极41从所述功能区FA延伸至所述显示区AA内，并于所述第一薄膜晶体管T1连接，所述第一像素电极31通过所述第一桥接电极41与所述第一薄膜晶体管T1连接，所述第二像素电极32通过所述第二桥接电极42与所述第二薄膜晶体管T2连接。
具体地，所述显示面板100还包括栅极层60、第一源漏极层70、第二源漏极层80以及多层平坦化层。所述半导体层50设置于所述第一无机层12上，可选地，所述第一无机层12和所述半导体层50之间还可设置缓冲层15，所述半导体层50设置于所述缓冲层15上。所述缓冲层15的材料可包括氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料，所述缓冲层15可以防止不期望的杂质或污染物（例如湿气、氧气等）从所述第一透明衬底11扩散至可能因这些杂质或污染物而受损的器件中，同时还可以提供平坦的顶表面。
所述半导体层50在所述显示区AA形成所述第一薄膜晶体管T1和所述第二薄膜晶体管T2的沟道区51以及位于沟道区51两侧的源区52和漏区53，所述栅极绝缘层22覆于所述半导体层50及所述第一无机层12上，当然地，如果所述显示面100还包括缓冲层15时，所述栅极绝缘层22覆于所述半导体层50及所述缓冲层15上。
所述栅极层60设置于所述栅极绝缘层22上，所述栅极层60在所述显示区AA形成所述第一薄膜晶体管T1和所述第二薄膜晶体管T2的栅极61，所述栅极61与所述沟道区51对应设置，当然地，所述栅极层60还可在所述显示区AA形成栅极扫描线63等信号线。所述栅极层60还在所述弯折区PA形成有第一信号转接线62，所述第一信号转接线62与所述栅极扫描线63连接，用于给所述栅极61提供扫描信号，以控制对应的所述第一薄膜晶体管T1和所述第二薄膜晶体管T2的关断。
所述层间绝缘层23覆于所述栅极层60及所述栅极绝缘层22上，且图案化所述层间绝缘层23在所述弯折区PA形成所述第一过孔21，并在所述显示区AA形成第三过孔231。
所述第一过孔21包括第一子孔211和第二子孔212，所述第一子孔211的开口大于所述第二子孔212。所述第一子孔211和所述第三过孔231在同一工艺条件下形成，所述第一子孔211和所述第三过孔231均贯穿所述层间绝缘层23以及部分所述栅极绝缘层22，所述第三过孔231分别裸露出对应的所述源区52和所述漏区53，如图4所示。当然地，在形成第一子孔211和所述第三过孔231的同时，在所述弯折区PA还形成有第四过孔232，所述第四过孔232也贯穿所述层间绝缘层23以及部分所述栅极绝缘层22，以裸露出所述第一信号转接线62。
在形成所述第一子孔211后，采用干法蚀刻对所述第一子孔211孔底的膜层进行蚀刻以形成所述第二子孔212，所述第二子孔212贯穿所述第一子孔211孔底的所述栅极绝缘层22、缓冲层15以及部分所述第一无机层12，如图5所示。在形成所述第二子孔212时。
所述第一源漏极层70设置于所述层间绝缘层23上，所述第一源漏极层70在所述显示区AA形成所述第一薄膜晶体管T1和所述第二薄膜晶体管T2的第一源极71和第一漏极72，所述第一源极71和所述第一漏极72分别通过不同的所述第三过孔231与对应的所述源区52和所述漏区53连接。当然地，所述第一源漏极层70在所述显示区AA还形成有数据线74等信号线。
所述第一源漏极层70在所述弯折区PA形成有第二信号转接线73，一部分所述第二信号转接线73与对应的所述数据线74连接，用于给对应的所述第一薄膜晶体管T1和所述第二薄膜晶体管T2提供数据信号。另一部分所述第二信号转接线73通过所述第四过孔232与对应的所述第一信号转接线62连接。
所述第一平坦化层91覆于所述第一源漏极层70及所述层间绝缘层23上，并填充所述第一过孔21。所述第一平坦化层91为有机材料，把所述第一平坦化层91填充在所述第一过孔21内，能够提高所述弯折区PA的弯折性能，且可以简化在所述第一过孔21内填充其他有机材料的制程。
可以理解的是，在制备由有机材料形成的所述第一平坦化层91时，通常会采用涂布、喷墨打印等工艺把有机材料溶液制备在其他膜层上并固化成膜，而所述第一过孔21孔底对应的所述第一阻挡部10-1能够有效阻挡有机材料溶液进入所述第一透明衬底11内，在所述第一透明衬底11内产生游离的电荷。同时在制备所述第一过孔21的黄光工艺中，通常包括有干法蚀刻制程以及剥离光阻的制程，所述第一过孔21孔底对应的所述第一阻挡部10-1还能够阻挡用于干刻气体以及剥离光阻的剥离液进入所述第一透明衬底11，进而避免靠近所述弯折区PA的所述显示区AA出现亮度不均现象。
第二源漏极层80设置于所述第一平坦化层91上，所述第二源漏极层80在所述显示区AA形成所述第一薄膜晶体管T1和所述第二薄膜晶体管T2的第二源极81，所述第二源极81通过所述第一平坦化层91的过孔与所述第一漏极72连接。所述第二源漏极层80还在所述弯折区PA形成有多个绑定走线82，所述绑定走线82通过所述第一平坦化层91的过孔与所述第二信号转接线73连接。
第二平坦化层92覆于所述第二源漏极层80及所述第一平坦化层91上，所述桥接层40设置所述第二平坦化层92上，所述桥接层40为透明导电电极层，以提高所述功能区FA的透过率。所述桥接层40的材料包括ITO、IZO、ZnO或In2O3等透明导电氧化物（Transparent Conductive Oxide，TCO）材料。所述桥接层40形成的所述第一桥接电极41和所述第二桥接电极42分别通过所述第二平坦化层92的不同过孔与对应的所述第二源极81连接。
第三平坦化层93覆于所述桥接层40及所述第二平坦化层92上，所述导电电极层30设置于所述第三平坦化层93上，所述导电电极层30形成的所述第一像素电极31和所述第二像素电极32分别通过所述第三平坦化层93的不同过孔与对应的所述第一桥接电极41和所述第二桥接电极42连接。通过把所述第一薄膜晶体管T1设置在靠近所述功能区FA的显示区AA内，并通过所述第一桥接电极41与所述第一像素电极31连接，在满足所述功能区FA显示功能的前提下，还可提高所述功能区FA的透过率。可选地，所述导电电极层30的材料可与所述桥接层40的材料相同，或者所述导电电极层30的材料也可选用Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr等电极材料。
当然地，所述显示面板100还包括设置于所述导电电极层30以及所述第三平坦化层93上的像素定义层94，所述像素定义层94在对应所述第一像素电极31和所述第二像素电极32的位于设置有像素开口941，以裸露出所述第一像素电极31和所述第二像素电极32。
在一种实施例中，请参照图6，图6为本申请实施例提供的显示面板的第二种剖面结构示意图，与上述实施例不同的是，在本实施例的显示面板101中，所述第一阻挡部10-1远离所述第一透明衬底11的一侧设置有第二凹槽1011，第二凹槽1011能够延长水汽的扩散和渗入路径，并减小所述第一过孔21孔区的所述第一透明衬底11的热应力带来的应力扩展，从而达到实现释放水汽和应力的目的，如此可进一步改善靠近所述弯折区PA的所述显示区AA出现亮度不均的问题。同时通过设置所述第二凹槽1011还能减小所述弯折区PA的弯折应力，提高所述显示面板100弯折区PA弯折的可靠性。可选地，所述第二凹槽1011的截面形状包括方形、梯形、三角形等。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图7，图7为本申请实施例提供的显示面板的第三种剖面结构示意图，与上述实施例不同的是，在本实施例的显示面板102中，所述显示面板102还包括位于所述阻挡层10和所述第一无机层12之间的屏蔽层16，所述阻挡层10还包括位于所述显示区AA的多个间隔排布的第二阻挡部10-2，所述屏蔽部16包括与所述第一阻挡部10-1对应设置的第一屏蔽部16-1和与所述第二阻挡部10-2对应设置的第二屏蔽部16-2。
具体地，所述第二阻挡部10-2和所述第一阻挡部10-1同层间隔设置，其中部分所述第二阻挡部10-2对应所述半导体层50设置，使得所述第二阻挡部10-2至少与所述半导体层50部分重叠设置，也即所述第一晶体管T1和所述第二晶体管T2均对应有所述第二阻挡部10-2。
进一步地，所述屏蔽层16设置在所述阻挡层10远离所述第一透明衬底11的一侧，其中所述第一屏蔽部16-1对应所述第一阻挡部10-1设置，使得所述第一过孔21的底面延伸至所述屏蔽层16，并暴露所述第一屏蔽部16-1。所述第二屏蔽部16-2对应所述第二阻挡部10-2设置，使得所述第二屏蔽部16-2与所述半导体层50至少部分重叠设置。
进一步地，所述第一屏蔽部16-1与所述第一阻挡部10-1重叠设置，所述第二屏蔽部16-2与所述第二阻挡部10-2重叠设置，如此所述屏蔽层16和所述阻挡层10可通过同一道光罩形成。具体地，在所述第一透明衬底11上形成无机薄膜或有机薄膜后，继续在该无机薄膜或有机薄膜上制备一层金属薄膜，所述金属薄膜可以为钼、铝等金属薄膜。然后使用一道光罩对所述金属薄膜和无机薄膜同时进行曝光、显影、蚀刻等制程，以形成图案化的所述第一屏蔽部16-1、所述第二屏蔽部16-2、所述第一阻挡部10-1以及所述第二阻挡部10-2。其中所述屏蔽层16的厚度小于所述阻挡层10的厚度，所述屏蔽层16的厚度范围为50埃至500埃。
如此，在形成所述阻挡层10的同时还形成了所述屏蔽层16，且无需增加光罩，节约了成本。更重要的是，所述屏蔽层16还能屏蔽所述第一透明衬底11和所述第二透明衬底13中的电荷（charge），避免其对所述显示区AA的晶体管特性产生影响。因为在电场力作用下，所述第一透明衬底11和所述第二透明衬底13中的电荷会被极化，而电荷被极化后即相当于在所述半导体层50的沟道背面形成一个假栅极，类似于背沟道效应，如此会引起晶体管的阈值电压漂移（Vth Shift），进而会导致所述显示面板102整个所述显示区AA出现残像（Image Sticking，IS）。其中所述第一透明衬底11和所述第二透明衬底13中电荷主要来源于二酐和二胺的电子转移以及透明衬底界面的电荷。
进一步地，为了使所述屏蔽层16具有更好的屏蔽电荷的效果，可以给所述屏蔽层16通一恒定的电压信号。具体地，所述层间绝缘层23在图案化形成所述第一过孔21的同时，还在所述显示区AA形成有第二过孔233，所述第二过孔233裸露出部分所述第二屏蔽部16-2。而所述第一源漏极层70还在所述显示区AA形成有电源线（VDD）75，所述电源线75也和所述第一源极71同层设置，且所述电源线75通过所述第二过孔233与所述第二屏蔽部16-2连接，所述电源线75上为恒定的直流电压，则与所述电源线75相连的所述第二屏蔽部16-2上也具有恒定的直流电压。当然地，本申请不限于此，本申请的所述第二屏蔽部16-2也可不与所述电源线75连接，此时所述屏蔽层16也可位于所述阻挡层10面向所述第一透明衬底11的一侧。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请结合参照图8和图9，图8为本申请实施例提供的显示面板的第四种剖面结构示意图，图9为图8中显示面板的局部剖面结构示意图。与上述实施例不同的是，在本实施例的显示面板103中，本实施例采用双栅结构，同时所述桥接层40采用多层桥接，且所述导电电极层30采用叠层结构。
具体地，所述栅极层60包括第一栅极层60-1和第二栅极层60-2，则相应地，所述栅极绝缘层22也包括第一栅极绝缘层22-1和第二栅极绝缘层22-2，所述第一栅极绝缘层22-1位于所述半导体层50与所述第一栅极层60-1之间，所述第二栅极绝缘层22-2位于所述第一栅极层60-1与所述第二栅极层60-2之间。所述第一栅极层60-1在所述显示区AA形成所述第一薄膜晶体管T1和所述第二薄膜晶体管T2的第一栅极61-1，并同时形成有对应的栅极扫描线63。所述第一栅极层60-1在所述弯折区PA形成有第一信号转接线62。所述第二栅极层60-2在所述显示区AA形成所述第一薄膜晶体管T1和所述第二薄膜晶体管T2的第二栅极61-2，当然地，所述第二栅极层60-2还可在所述显示区AA形成有其他信号线，并在所述弯折区PA形成对应的其他信号转接线。
进一步地，把所述桥接层40设置为多层，能够更好的调整所述弯折区PA的应力中心层。所述桥接层40包括第一桥接层40-1和第二桥接层40-2，所述第一桥接层40-1设置于所述第二平坦化层92上，则相应地，还需要设置第四平坦化层95，所述第四平坦化层95覆于所述第一桥接层40-1以及所述第二平坦化层92上，所述第二桥接层40-2设置于所述第四平坦化层95上，所述第三平坦化层93覆于所述第二桥接层40-2以及所述第四平坦化层95上。所述第一桥接层40-1在所述功能区FA形成第一桥接电极41，并在所述显示区AA形成第二桥接电极42。所述第二桥接层40-2在所述功能区FA形成有第三桥接电极43，并在所述显示区AA形成有第四桥接电极44。其中所述第一桥接电极41由所述功能区FA延伸到所述显示区AA，并与所述第一薄膜晶体管T1的第二源极81连接，所述第三桥接电极43与所述第一桥接电极41连接。所述第二桥接电极42与所述第二薄膜晶体管T2的第二源极81连接，所述第四桥接电极44与所述第二桥接电极42连接。
进一步地，所述导电电极层30设置于所述第三平坦化层93上，所述导电电极层30包括层叠设置的第一导电电极层30-1和第二导电电极层30-2，所述第一导电电极层30-1在所述功能区FA形成第一辅助电极33，并在所述显示区AA形成第二辅助电极34，所述第一辅助电极33与所述第三桥接电极43连接，所述第二辅助电极34与所述第四桥接电极44连接。所述第二导电电极层30-2在所述功能区FA形成所述第一像素电极31，并在所述显示区AA形成所述第二像素电极32，所述第一像素电极31与所述第一辅助电极33连接，所述第二像素电极32与所述第二辅助电极34连接。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图10，图10为本申请实施例提供的显示面板的第五种剖面结构示意图，与上述实施例不同的是，在本实施例的显示面板104中，所述第一屏蔽部16-1远离所述第一阻挡部10-1的一侧设置有第一凹槽161。通过设置所述第一凹槽161能够减小所述弯折区PA的弯折应力，提高所述显示面板弯折区弯折的可靠性。可选地，所述第一凹槽161的截面形状包括方形、梯形、三角形等。
另外需要说明的是，为了实现显示面板104的显示功能，本申请的显示面板104还包括设置于所述像素定义层94上的发光功能层200，而为了保护所述发光功能层200，本申请的所述显示面板104还包括设置于所述发光功能层200上的封装层300。
具体地，所述发光功能层200包括发光单元201以及阴极202。所述发光单元201是由打印在所述像素定义层94的像素开口内的发光材料形成，不同颜色的发光材料形成不同颜色的发光单元，不同颜色的发光单元发射不同颜色的光，进而实现显示面板的彩色显示。比如发光单元201可以包括由红色发光材料形成的红色发光单元，由绿色发光材料形成的绿色发光单元，由蓝色发光材料形成的蓝色发光单元，红色发光单元发出红光，绿色发光单元发出绿光，蓝色发光单元发出蓝光。
所述阴极202覆于所述发光单元201以及所述像素定义层94上。所述发光单元201在对应的像素电极（如所述第一像素电极31或所述第二像素电极32）与所述阴极202的共同作用下发光。
可选地，所述发光功能层200还可包括设置于所述发光单元201与所述像素电极之间的空穴注入层(HIL)、空穴传输层(HTL)；以及设置于所述发光单元201与所述阴极202之间的电子注入层(EIL)、电子传输层(ETL)。空穴注入层接收像素电极传输的空穴，空穴经由空穴传输层传输至发光单元201，电子注入层接收阴极202传输的电子，电子经由电子传输层传输至发光单元201，空穴和电子在发光单元201位置结合后产生激子，激子由激发态跃迁至基态释放能量并发光。
所述封装层300覆于所述发光功能层200上，用于保护所述发光功能层200的发光单元201，避免水汽入侵导致发光单元201失效。可选地，所述封装层300可采用薄膜封装，比如所述封装层300可以为由第一无机封装层、有机封装层、第二无机封装层三层薄膜依次层叠形成的叠层结构或更多层的叠层结构。
当然地，本申请的所述显示面板104还可包括设置于所述封装层300远离所述发光功能层200一侧的触控电极层、偏光片、盖板等结构。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，本申请还提供一种电子装置，所述电子装置包括功能元件以及前述实施例其中之一的显示面板，所述功能元件包括摄像头、指纹传感器等。所述电子装置包括手机、平板、可穿戴电子设备等。
根据上述实施例可知：
本申请提供一种显示面板和电子装置，该显示面板包括显示区和位于显示区一侧的弯折区，显示面板还包括第一透明衬底、位于透明衬底一侧的第一无机层以及位于第一无机层远离第一透明衬底的一侧的第二无机层，第二无机层在弯折区形成有第一过孔，第一过孔贯穿第二无机层及部分第一无机层，使得第一无机层在对应第一过孔的区域保留一定厚度的整面膜层，以保护第一透明衬底，避免了水汽以及第一过孔的蚀刻制程对第一透明衬底的影响，进而避免了第一透明衬底裸露引起的靠近弯折区出现亮度不均的问题，从而解决了现有显示面板在靠近弯折区的位置存在局部亮度不均的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括显示区和位于所述显示区一侧的弯折区，所述显示面板还包括：
    第一透明衬底；
    阻挡层，位于所述第一透明衬底的一侧，至少包括位于所述弯折区的第一阻挡部；
    第一无机层，覆于所述第一透明衬底以及所述阻挡层上；
    半导体层，设置于所述第一无机层远离所述第一透明衬底的一侧；以及
    第二无机层，覆于所述半导体层及所述第一无机层上；
    其中，所述第二无机层在所述弯折区形成有第一过孔，所述第一过孔贯穿所述第二无机层和所述第一无机层，且所述第一过孔的孔底在所述第一透明衬底上的正投影落在所述第一阻挡部在所述第一透明衬底上的正投影范围内。
  2. 根据权利要求1所述的显示面板，其中，所述阻挡层还包括位于所述显示区的多个间隔排布的第二阻挡部，所述第二阻挡部至少与所述半导体层部分重叠设置。
  3. 根据权利要求2所述的显示面板，其中，还包括位于所述阻挡层和所述第一无机层之间的屏蔽层，所述屏蔽层包括：与所述第一阻挡部对应设置的第一屏蔽部和与所述第二阻挡部对应设置的第二屏蔽部。
  4. 根据权利要求3所述的显示面板，其中，所述第一过孔的底面延伸至所述屏蔽层，并暴露所述第一屏蔽部。
  5. 根据权利要求3所述的显示面板，其中，所述第二屏蔽部与所述半导体层至少部分重叠设置。
  6. 根据权利要求3所述的显示面板，其中，所述第一屏蔽部与所述第一阻挡部重叠设置，所述第二屏蔽部与所述第二阻挡部重叠设置。
  7. 根据权利要求3所述的显示面板，其中，所述第一屏蔽部远离所述第一阻挡部的一侧设置有第一凹槽。
  8. 根据权利要求3所述的显示面板，其中，所述第二无机层包括依次层叠设置的栅极绝缘层、层间绝缘层，所述栅极绝缘层覆于所述半导体层及所述第一无机层上；所述显示面板还包括：
    栅极层，设置于所述栅极绝缘层上，所述层间绝缘层覆于所述栅极层及所述栅极绝缘层上，且所述层间绝缘层图案化形成所述第一过孔，并在所述显示区形成第二过孔，所述第二过孔裸露出部分所述第二屏蔽部；
    第一源漏极层，设置于所述层间绝缘层上，在所述显示区形成电源线，所述电源线通过所述第二过孔与所述第二屏蔽部连接。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括临近所述显示区设置的功能区，以及设置在所述显示区的第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管靠近所述功能区设置，所述显示面板还包括：
    导电电极层，设置于所述第一薄膜晶体管和所述第二薄膜晶体管远离所述第一透明衬底的一侧，且在所述功能区形成有第一像素电极，在所述显示区形成有第二像素电极，所述第一像素电极与所述第一薄膜晶体管连接，所述第二像素电极与所述第二薄膜晶体管连接；
    其中，所述半导体层在所述显示区形成所述第一薄膜晶体管和所述第二薄膜晶体管的沟道区以及位于沟道区两侧的源区和漏区；所述栅极层在所述显示区形成所述第一薄膜晶体管和所述第二薄膜晶体管的栅极，并在所述弯折区形成有第一信号转接线，所述栅极与所述沟道区对应设置；所述第一源漏极层在所述显示区形成所述第一薄膜晶体管和所述第二薄膜晶体管的第一源极和第一漏极，并在所述弯折区形成有第二信号转接线，其中所述第一源极与所述源区连接，所述第一漏极与所述漏区连接，所述第一信号转接线与所述第二信号转接线连接。
  10. 根据权利要求9所述的显示面板，其中，所述显示面板还包括位于所述第一薄膜晶体管和所述导电电极层之间还设置有桥接层，所述桥接层在所述功能区形成第一桥接电极，并在所述显示区形成第二桥接电极，所述第一像素电极通过所述第一桥接电极与所述第一薄膜晶体管连接，所述第二像素电极通过所述第二桥接电极与所述第二薄膜晶体管连接。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    第一平坦化层，覆于所述第一源漏极层及所述层间绝缘层上，并填充所述第一过孔；
    第二源漏极层，设置于所述第一平坦化层上，在所述显示区形成所述第一薄膜晶体管和所述第二薄膜晶体管的第二源极，并在所述弯折区形成有多个绑定走线；
    第二平坦化层，覆于所述第二源漏极层及所述第一平坦化层上，所述桥接层设置所述第二平坦化层上；
    第三平坦化层，覆于所述桥接层及所述第二平坦化层上，所述导电电极层设置于所述第三平坦化层上；
    其中，所述第一桥接电极和所述第二桥接电极分别与对应的所述第二源极连接，所述绑定走线与所述第二信号转接线连接。
  12. 根据权利要求1所述的显示面板，其中，所述第一阻挡部远离所述第一透明衬底的一侧设置有第二凹槽。
  13. 一种电子装置，其包括功能元件和显示面板，所述显示面板包括显示区、位于所述显示区一侧的弯折区以及临近所述显示区设置的功能区，所述功能元件对应所述功能区设置；所述显示面板还包括：
    第一透明衬底；
    阻挡层，位于所述第一透明衬底的一侧，至少包括位于所述弯折区的第一阻挡部；
    第一无机层，覆于所述第一透明衬底以及所述阻挡层上；
    半导体层，设置于所述第一无机层远离所述第一透明衬底的一侧；以及
    第二无机层，覆于所述半导体层及所述第一无机层上；
    其中，所述第二无机层在所述弯折区形成有第一过孔，所述第一过孔贯穿所述第二无机层和所述第一无机层，且所述第一过孔的孔底在所述第一透明衬底上的正投影落在所述第一阻挡部在所述第一透明衬底上的正投影范围内。
  14. 根据权利要求13所述的电子装置，其中，所述阻挡层还包括位于所述显示区的多个间隔排布的第二阻挡部，所述第二阻挡部至少与所述半导体层部分重叠设置。
  15. 根据权利要求14所述的电子装置，其中，所述显示面板还包括位于所述阻挡层和所述第一无机层之间的屏蔽层，所述屏蔽层包括：与所述第一阻挡部对应设置的第一屏蔽部和与所述第二阻挡部对应设置的第二屏蔽部。
  16. 根据权利要求15所述的电子装置，其中，所述第一过孔的底面延伸至所述屏蔽层，并暴露所述第一屏蔽部。
  17. 根据权利要求15所述的电子装置，其中，所述第二屏蔽部与所述半导体层至少部分重叠设置。
  18. 根据权利要求15所述的电子装置，其中，所述第一屏蔽部与所述第一阻挡部重叠设置，所述第二屏蔽部与所述第二阻挡部重叠设置。
  19. 根据权利要求15所述的电子装置，其中，所述第一屏蔽部远离所述第一阻挡部的一侧设置有第一凹槽。
  20. 根据权利要求15所述的电子装置，其中，所述第二无机层包括依次层叠设置的栅极绝缘层、层间绝缘层，所述栅极绝缘层覆于所述半导体层及所述第一无机层上；所述显示面板还包括：
    栅极层，设置于所述栅极绝缘层上，所述层间绝缘层覆于所述栅极层及所述栅极绝缘层上，且所述层间绝缘层图案化形成所述第一过孔，并在所述显示区形成第二过孔，所述第二过孔裸露出部分所述第二屏蔽部；
    第一源漏极层，设置于所述层间绝缘层上，在所述显示区形成电源线，所述电源线通过所述第二过孔与所述第二屏蔽部连接。
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