WO2023002929A1 - 発光デバイス、表示デバイス、電子機器、並びに発光デバイスの製造方法および製造装置 - Google Patents
発光デバイス、表示デバイス、電子機器、並びに発光デバイスの製造方法および製造装置 Download PDFInfo
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Classifications
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
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- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0041—Processes relating to semiconductor body packages relating to wavelength conversion elements
Definitions
- the present disclosure relates to light emitting devices and the like.
- Patent Document 1 discloses a method of forming a plurality of LEDs (light emitting diodes) on a substrate.
- a light-emitting device includes a semiconductor substrate including a main substrate, a mask positioned above the main substrate and including a mask portion and an opening, and a base semiconductor portion positioned above the mask; a compound semiconductor portion positioned above a substrate and having a first light emitting portion, the semiconductor substrate penetrating the main substrate in a thickness direction and communicating with the first light emitting portion below the first light emitting portion; Includes overlapping first holes.
- FIG. 1 is a cross-sectional view along the X direction of a light-emitting device according to Example 1.
- FIG. 1 is a cross-sectional view along the Y direction of a light-emitting device according to Example 1.
- FIG. 1 is a plan view of a light-emitting device according to Example 1.
- FIG. 4 is a plan view showing another configuration of the light emitting device according to Example 1.
- FIG. 4 is a plan view showing another configuration of the light emitting device according to Example 1.
- FIG. 5 is a flow chart showing an example of a method for manufacturing a light emitting device according to Example 1.
- FIG. FIG. 13 is a cross-sectional view showing a method of manufacturing the light emitting device of FIG. 12;
- FIG. 4 is a cross-sectional view showing an example of lateral growth of a base semiconductor portion;
- 3 is a schematic cross-sectional view showing configurations of a base semiconductor portion and a compound semiconductor portion;
- FIG. 1 is a cross-sectional view showing the configuration of a display device according to Example 1;
- FIG. 1 is a cross-sectional view showing the configuration of a display device according to Example 1;
- FIG. 1 is a block diagram showing the configuration of a display device according to Example 1;
- FIG. 4 is a cross-sectional view showing an example of a drive substrate;
- FIG. 10 is a cross-sectional view along the X direction of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view along the Y direction of the light-emitting device according to Example 2;
- FIG. 10 is a plan view of a light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing the configuration of a display device according to Example 1;
- FIG. 1 is a cross-sectional view showing the configuration of a display device according to Example 1;
- FIG. 1 is a block diagram showing the configuration of a display device according to Example
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device
- FIG. 10 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2;
- FIG. 10 is a cross-sectional view along the X direction of the light-emitting device according to Example 3;
- FIG. 11 is a cross-sectional view along the Y direction of the light-emitting device according to Example 3;
- FIG. 11 is a plan view of a light-emitting device according to Example 3;
- FIG. 11 is a cross-sectional view showing another configuration of the light emitting device according to Example 3;
- FIG. 11 is a cross-sectional view showing another configuration of the light emitting device according to Example 3;
- FIG. 11 is a cross-sectional view showing another configuration of the light emitting device according to Example 3;
- FIG. 11 is a cross-sectional view showing another configuration of the light emitting device according to Example 3;
- FIG. 11 is a cross-sectional view showing another configuration of the light emitting device according to Example 3;
- FIG. 10 is
- FIG. 11 is a plan view showing another configuration of the light emitting device according to Example 3;
- FIG. 11 is a cross-sectional view showing another configuration of the light emitting device according to Example 4;
- FIG. 11 is a cross-sectional view showing another configuration of the light emitting device according to Example 4;
- 11 is a flow chart showing a method for manufacturing a light emitting device according to Example 5.
- FIG. FIG. 11 is a cross-sectional view showing the configuration of a light-emitting device according to Example 5; 14 is a flow chart showing another method for manufacturing a light-emitting device according to Example 5.
- FIG. FIG. 12 is a cross-sectional view showing another configuration of the light-emitting device according to Example 5;
- FIG. 12 is a cross-sectional view showing another configuration of the light-emitting device according to Example 5;
- FIG. 11 is a schematic plan view showing a display device of Example 7;
- FIG. 12 is a schematic diagram showing the configuration of an electronic device according to
- FIG. 1 is a cross-sectional view showing the configuration of a light-emitting device according to this embodiment.
- the light emitting device 30 includes a main substrate 1, a mask 6 including a mask portion 5 and an opening K1, and a mask 6 above the main substrate 1.
- a semiconductor substrate 10 having a base semiconductor portion 8 positioned thereon, and a compound semiconductor portion 9 positioned above the semiconductor substrate 10 and having a first light emitting portion L1.
- the semiconductor substrate 10 only needs to include the main substrate 1 (for example, a free-standing bulk crystal substrate) and a semiconductor portion (for example, a semiconductor layer), and the main substrate 1 may be a semiconductor or a non-semiconductor. good too.
- the direction from the main substrate 1 (for example, a free-standing bulk crystal substrate) to the base semiconductor portion 8 is the upward direction (therefore, it may differ from the vertically upward direction or the upward direction in the drawings).
- Mask 6 may be a mask pattern including mask portion 5 and opening K1.
- the opening K ⁇ b>1 is a region where the mask portion 5 does not exist, and the opening K ⁇ b>1 may not be surrounded by the mask portion 5 .
- the semiconductor substrate 10 includes a first hole H1 that penetrates the main substrate 1 in the thickness direction and overlaps the first light emitting portion L1 below the first light emitting portion L1.
- the first hole H1 overlaps the first light emitting portion L1 in a plan view (visual recognition in the normal direction of the main substrate 1). That two components overlap in plan view means that at least a part of one component overlaps the other component when viewed in the normal direction of the main substrate 1 (including perspective recognition). Two components may be spaced apart (e.g., vertically) and overlapping.
- a first electrode E ⁇ b>1 can be provided above the compound semiconductor portion 9 .
- the first hole H1 has an opening KR on the back surface 1U (lower surface) of the main substrate 1, which serves as a light emitting surface.
- Threading dislocations are dislocations (defects) that extend from the base semiconductor portion 8 to the compound semiconductor portion 9, inhibit charge transfer, and cause heat generation.
- the light emitting device 30 has rigidity because it includes the main substrate 1 . Further, by providing the first wavelength conversion layer J1 in the first hole H1, light having a longer wavelength (for example, visible light region) than the light generated in the first light emitting portion L1 can be emitted from the opening KR.
- the base semiconductor portion 8 and the compound semiconductor portion 9 contain, for example, a nitride semiconductor.
- a GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.
- the base semiconductor portion 8 may be of a doped type (for example, n-type containing donors) or non-doped type.
- the base semiconductor portion 8 containing a nitride semiconductor can be formed by an ELO (Epitaxial Lateral Overgrowth) method, but another method may be used as long as it can achieve low defects.
- ELO Epi Lateral Overgrowth
- a heterogeneous substrate having a lattice constant different from that of the base semiconductor portion 8 is used as the main substrate 1
- a nitride semiconductor is used as the base portion 4
- an inorganic compound film is used as the mask portion 5
- a base portion is used as the opening K1.
- the base semiconductor portion 8 can be grown laterally (Y direction) on the mask portion 5 .
- the main substrate 1 and the underlying portion 4 are collectively referred to as the underlying substrate, and the main substrate 1, the underlying portion 4 and the mask 6 are sometimes referred to as the template substrate 7 .
- the base semiconductor portion formed by the ELO method is sometimes referred to as an ELO semiconductor layer.
- the template substrate 7 including the main substrate 1 and the mask 6 on the main substrate 1 may be used.
- the template substrate 7 may have a growth suppression region (for example, a region that suppresses crystal growth in the Z direction) corresponding to the mask portion 5 and a seed region corresponding to the opening K1.
- a growth suppression region and a seed region can be formed on the main substrate 1, and the base semiconductor section 8 can be formed on the growth suppression region and the seed region using the ELO method.
- FIG. 2 is a flow chart showing an example of a method for manufacturing a light emitting device according to this embodiment.
- the step of preparing the template substrate (ELO growth substrate) 7 the step of forming the base semiconductor portion 8 using the ELO method is performed to obtain the semiconductor substrate 10.
- FIG. 3 is a block diagram showing an example of a light-emitting device manufacturing apparatus according to this embodiment.
- the light-emitting device manufacturing apparatus 70 of FIG. 3 includes a semiconductor forming section 72 for forming the base semiconductor section 8 and the compound semiconductor section 9 on the template substrate 7, and a substrate processing section for etching the main substrate 1 from the back surface 1U. 73 and a control unit 74 that controls the semiconductor forming unit 72 and the substrate processing unit 73 .
- the semiconductor formation unit 72 may include a MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and memory.
- the control unit 74 may be configured to control the semiconductor forming unit 72 and the substrate processing unit 73 by executing a program stored in an internal memory, a communicable communication device, or an accessible network, for example.
- the above program and a recording medium storing the above program are also included in this embodiment.
- FIG. 4 is a cross-sectional view showing the configuration of the display device according to this embodiment.
- the display device 50 includes the light emitting device 30 and a drive substrate TK arranged on the opposite side of the main substrate 1 of the light emitting device 30 and electrically connected to the first electrode E1.
- a pixel circuit included in the drive substrate TK controls the light emission intensity of the first light emitting unit L1 (described later).
- the driving substrate TK may have a structure in which a pixel circuit including a plurality of transistors is formed on a glass substrate or a resin substrate, or a structure in which a pixel circuit including a plurality of transistors is formed on a silicon substrate.
- the pixel circuit may include a CMOS (Complementary Metal Oxide Semiconductor) circuit.
- CMOS Complementary Metal Oxide Semiconductor
- FIG. 5 is a cross-sectional view along the X direction of the light-emitting device according to Example 1.
- FIG. 6 is a cross-sectional view along the Y direction of the light-emitting device according to Example 1.
- FIG. 7 is a plan view of a light-emitting device according to Example 1.
- the light emitting device 30 according to Example 1 includes a semiconductor substrate 10, a compound semiconductor portion 9 located on the semiconductor substrate 10, and first and second electrodes E1 and E2.
- a semiconductor substrate 10 includes a main substrate 1, a base portion 4 positioned on the main substrate 1, a mask 6 positioned on the base portion 4 and including a mask portion 5 and openings K1 and K2, and a mask 6 positioned on the mask 6. and a base semiconductor portion 8 that
- the compound semiconductor portion 9 has a first light emitting portion L1.
- the first electrode E1 is positioned above the compound semiconductor portion 9, and the second electrode E2 is positioned above the base semiconductor portion 8.
- the base semiconductor portion 8 and the compound semiconductor portion 9 contain a nitride semiconductor (for example, a GaN-based semiconductor).
- the X direction is the ⁇ 11-20> direction (a-axis direction) of the base semiconductor portion 8
- the Y direction is the ⁇ 1-100> direction (m-axis direction) of the base semiconductor portion 8
- the Z direction is the ⁇ 0001> direction of the base semiconductor portion 8. > direction (c-axis direction).
- the X direction is the ⁇ 11-20> direction in the crystal structure of the nitride semiconductor (eg, GaN-based semiconductor)
- the Y direction is the ⁇ 1-100> direction in the crystal structure of the nitride semiconductor (eg, GaN-based semiconductor).
- the direction, the Z direction is the ⁇ 0001> direction in the crystal structure of a nitride semiconductor (for example, a GaN-based semiconductor).
- a structure below the mask 6 may be referred to as a base substrate UK.
- the underlying substrate and the mask 6 may be collectively referred to as a template substrate 7 .
- the base portion 4 may be a base layer.
- Mask 6 may be a mask layer.
- the base semiconductor portion 8 may be a base semiconductor layer.
- the compound semiconductor portion 9 may be a compound semiconductor layer or a device layer.
- the main substrate 1 is a heterogeneous substrate having a lattice constant different from that of the base semiconductor portion 8 .
- the main substrate 1 may be a light shielding substrate, for example a silicon substrate.
- the main substrate 1 includes a first hole H1 that penetrates between the lower surface and the upper surface and overlaps the first light emitting portion L1 in plan view.
- the first hole H1 may have a tapered shape that tapers toward the base semiconductor portion 8 side.
- a first wavelength conversion layer J1 that emits light having a longer wavelength than the light receiving wavelength is provided in the first hole H1.
- the first wavelength conversion layer J1 converts light (for example, ultraviolet light) received from the first light emitting unit L1 into visible light by, for example, photoluminescence. The converted visible light is emitted to the outside through the first hole H1.
- the first wavelength conversion layer J1 may contain at least one of a fluorescent substance and a phosphorescent substance.
- the first hole H1 has an opening KR on the rear surface (lower surface) 1U of the main substrate 1, which serves as a visible light emitting surface.
- the shape of the opening KR may be rectangular (see FIG. 7), rhombic, circular, elliptical, or the like, but is not limited to these.
- at least part of the bottom of the first hole H1 is included in the base portion 4 . As shown in FIG. 5, the entire bottom portion of the first hole H1 may be positioned within the underlying portion 4 .
- the base semiconductor portion 8 includes a first portion HD located above the opening K1, and a second portion SD (low-defect portion) located above the mask portion 5 and having a threading dislocation density lower than that of the first portion HD. , the second portion SD overlaps the first light emitting portion L1 in plan view.
- the threading dislocation density of the second portion SD is, for example, 5 ⁇ 10 6 /cm 2 or less. Thereby, the luminous efficiency of the 1st light emission part L1 can be improved.
- a threading dislocation extends in the thickness direction of the base semiconductor portion 8 and reaches its surface layer.
- the first and second electrodes E1 and E2 are arranged in the Y direction.
- the first electrode E1 is, for example, an anode (p-electrode)
- the second electrode E2 is, for example, a cathode (n-electrode).
- the first electrode E1 overlaps the first light emitting section L1 in plan view. This shortens the current path between the first electrode E1 and the first light emitting portion L1.
- the first and second electrodes E1 and E2 are light reflective. As a result, the light traveling from the first light emitting portion L1 toward the first electrode E1 is reflected toward the main substrate 1, so that the light utilization efficiency is enhanced.
- the light emitting device 30 includes a first pad P1 connected to the first electrode E1 and a second pad P2 connected to the second electrode E2. At least a portion of the second pad P2 does not overlap the first hole H1 in plan view. Therefore, when the driving substrate TK and the light-emitting device 30 are bonded together, the pressing force on the second pads P2 affects the compound semiconductor portion 9 and the base semiconductor portion 8 (for example, the cracks and other defects inside the base semiconductor portion 8). occurrence) is reduced. In addition, since the positions of the upper surfaces of the first and second pads P1 and P2 are aligned, mounting on the drive substrate TK (see FIG. 4) is facilitated. The first and second electrodes E1 and E2 are not in contact with the base semiconductor section 8, and the insulating film DF is positioned between the first and second electrodes E1 and E2 and the base semiconductor section 8. FIG. The insulating film DF may be transparent.
- the second electrode E2 is in contact with the base semiconductor portion 8.
- the base semiconductor portion 8 can be made of an n-type semiconductor.
- the second electrode E2 may have a concave portion EH, and the insulating layer DL may be provided in the concave portion EH. By providing the insulating layer DL in the recess EH, the upper surface of the second pad P2 can be planarized.
- the first electrode E1 and the second electrode E2 may be used as a set, and a light shielding layer QY may be provided in the gap between two sets that are adjacent in the Y direction. A portion of the light shielding layer QY may be located within the base semiconductor portion 8 .
- the light shielding layer QY may be light absorbing or may have a lower refractive index than the base semiconductor portion 8 .
- the compound semiconductor portion 9 has a second light emitting portion L2 and a third light emitting portion L3, and the main substrate 1 is a through hole in the thickness direction (Z direction), and has a second light emitting portion L2 overlapping the second light emitting portion L2 in plan view. It includes a hole H2 and a third hole H3 which is a through hole in the thickness direction and overlaps the third light emitting portion L3 in plan view.
- the first to third light emitting parts L1 to L3 are arranged in the X direction, and the first to third holes H1 to H3 are also arranged in the X direction.
- the emission peak wavelength of each of the first to third light emitting portions L1 to L3 may be in the wavelength range (visible light range) of 430 to 640 [nm].
- the light-emitting device 30 includes a third electrode E3 and a fourth electrode E4. In a plan view, the third electrode E3 overlaps the second light-emitting portion L2, and the first and third electrodes E1 and E3 are arranged in the X direction.
- the third and fourth electrodes E3 and E4 are arranged in the Y direction, and the second and fourth electrodes E2 and E4 are arranged in the X direction.
- the light emitting device 30 includes a first partition wall portion QF positioned between the first and second light emitting portions L1 and L2 in plan view.
- the first partition wall portion QF has a light shielding property (for example, a property of absorbing light of the emission wavelengths of the first and second light emitting portions L1 and L2), and overlaps the opening portion K1 of the mask 6 in plan view.
- the first partition portion (light shielding layer) QF may have a lower refractive index than the base semiconductor portion 8 .
- the light-emitting device 30 includes a second partition QS positioned between the second and third light-emitting portions L2 and L3 in plan view.
- the second partition QS has a light shielding property (for example, a property of absorbing light of the emission wavelengths of the second and third light emitting portions L2 and L3), and overlaps the center of the mask portion 5 in plan view.
- the first and second partitions QF and QS have a shape whose longitudinal direction is the Y direction.
- the second partition portion (light shielding layer) QS may have a lower refractive index than the base semiconductor portion 8 .
- the base semiconductor portion 8 includes a first region 8F and a second region 8S that are separated from each other.
- the first area 8F overlaps the opening K1 in plan view
- the second area 8S overlaps the opening K2 in plan view.
- Each of the first and second regions 8F and 8S has a longitudinal shape, and a second partition QS is arranged between the first and second regions 8F and 8S.
- the first and second partitions QF and QS cause light generated in the light emitting portion L1 to enter a hole other than the hole H1 (for example, the hole H2), or enter another light emitting portion (for example, the light emitting portion L2). It has a function of reducing the crosstalk phenomenon that is incident on the active layer of the From this point of view, the first and second partition walls QF and QS may be films with low translucency (not only films with light absorption properties but also films with light reflection properties). , Ag, Cu, Cr, Au, etc., or a semiconductor film, a dielectric film, a resin film (for example, a light-absorbing black photoresist), or the like.
- FIG. 8 is a plan view showing another configuration of the light emitting device according to Example 1.
- the plurality of first light emitting portions L1 are arranged in a straight line in the Y direction, but the present invention is not limited to this.
- a plurality of first light emitting units L1 may be arranged in a staggered manner in the Y direction.
- a plurality of first light emitting units L1 may emit light of the same color.
- the openings K1 and K3 are arranged in a staggered manner in the Y direction.
- 9 is a plan view showing another configuration of the light emitting device according to Example 1.
- FIG. 1 is arranged in a straight line in the Y direction, but the present invention is not limited to this.
- a plurality of first light emitting units L1 may be arranged in a staggered manner in the Y direction.
- a plurality of first light emitting units L1 may emit light of the same color.
- the openings K1 and K3 are arranged in a
- the present invention is not limited to this.
- the first to third light emitting portions L1 to L3 may be arranged in the Y direction (the ⁇ 1-100> direction of the base semiconductor portion 8).
- a third partition wall portion (light shielding layer) QT may be provided in the gap between the first light emitting portion L1 and the second light emitting portion L2 and the gap between the second light emitting portion L2 and the third light emitting portion L3 arranged in the Y direction.
- the third partition wall portion QT may be light absorbing or may have a lower refractive index than the base semiconductor portion 8 .
- FIG. 10 is a flowchart illustrating an example of a method for manufacturing a light-emitting device according to Example 1.
- FIG. 11A and 11B are cross-sectional views illustrating an example of a method for manufacturing a light-emitting device according to Example 1.
- FIG. 10 and 11 after the step of preparing the template substrate 7, the step of forming the base semiconductor portion 8 using the ELO method is performed to obtain the semiconductor substrate 10.
- FIG. 10 and 11 after the step of preparing the template substrate 7, the step of forming the base semiconductor portion 8 using the ELO method is performed to obtain the semiconductor substrate 10.
- FIG. Next, a step of forming the compound semiconductor portion 9 is performed, followed by a step of forming the first and second electrodes E1 and E2, and then a step of forming the first and second pads P1 and P2.
- the semiconductor substrate 10 is etched from the back surface 1U of the main substrate 1 to form the first holes H1 penetrating through the main substrate 1 in the semiconductor substrate 10 .
- a step of forming the first wavelength conversion layer J1 in the first hole H1 is performed.
- through-holes such as the 1st hole H1, in the main board
- it can form by methods, such as wet etching or dry etching, for example. More specifically, for example, the through holes may be formed by the Bosch method.
- Through holes such as the second hole H2 and the third hole H3 can also be formed by the above method.
- FIG. 12 is a flow chart showing another example of the method for manufacturing the light-emitting device according to the first embodiment.
- 13A and 13B are cross-sectional views illustrating a method of manufacturing the light emitting device of FIG.
- the step of bonding the driving substrate TK may be performed, and then the etching of the main substrate 1 may be performed.
- a silicon substrate generally having a thickness of about 300 ⁇ m to 2.0 mm
- the silicon substrate (main substrate 1) is thinned (for example, thickness 300 ⁇ m or less) by wet etching, dry etching, polishing, CMP (Chemical Mechanical Polishing), etc., and then through holes having openings KR are formed. You may
- a heterosubstrate having a lattice constant different from that of the GaN-based semiconductor can be used for the main substrate 1 .
- hetero-substrates include single-crystal silicon (Si) substrates, sapphire (Al 2 O 3 ) substrates, silicon carbide (SiC) substrates, and the like.
- the plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H—SiC (0001) plane of a SiC substrate. These are just examples, and any main substrate and plane orientation that allow the ELO base semiconductor portion 8 to grow by the ELO method may be used.
- the buffer portion 2 and the seed portion 3 can be provided in order from the main substrate 1 side.
- the buffer section 2 may be a buffer layer.
- the seed portion 3 may be a seed layer.
- the buffer portion 2 has a function of reducing, for example, the direct contact between the main substrate 1 and the seed portion 3 and the mutual melting. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portion 3, both (the main substrate and the seed portion) melt together. By providing a buffer portion 2 containing one side, melting is reduced.
- An AlN layer which is an example of the buffer section 2, can be formed to a thickness of about 10 nm to about 5 ⁇ m using, for example, an MOCVD apparatus.
- the buffer portion 2 may have at least one of the effect of increasing the crystallinity of the seed portion 3 and the effect of relieving the internal stress of the base semiconductor portion 8 (relieving the warpage of the light emitting device 30).
- the main substrate 1 that does not melt with the seed portion 3 it is possible to configure without the buffer portion 2 (that is, configure the underlying portion 4 with the seed portion).
- the structure is not limited to the configuration in which the base portion 4 overlaps the entire mask portion 5 in a plan view as shown in FIG. 5 .
- the underlying portion 4 may be exposed from the openings K1 and K2 of the mask 6, the underlying portion 4 is locally formed so as to overlap the openings K1 and K2 in plan view (for example, in a slit shape extending in the Y direction). may be formed (described later).
- At least one of the buffer portion 2 (e.g., aluminum nitride or silicon carbide) and the seed portion 3 (e.g., GaN-based semiconductor) is deposited using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).
- a sputtering apparatus has merits such as low-temperature film formation and large-area film formation and cost reduction.
- the openings K1 and K2 of the mask 6 expose the seed portion 3 and function as growth start holes for starting the growth of the base semiconductor portion 8.
- the mask portion 5 of the mask 6 extends the base semiconductor portion 8 laterally. It has the function of a selective growth mask for directional growth.
- the openings K1 and K2 are portions where the mask portion 5 does not exist, and the openings K1 and K2 may not be surrounded by the mask portion 5 .
- a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (for example, 1000° C. or higher) are used.
- a single layer film containing either one or a laminated film containing at least two of these can be used.
- a silicon oxide film having a thickness of about 100 nm to 4 ⁇ m (preferably about 150 nm to 2 ⁇ m) is formed on the underlying portion 4 by sputtering, and a resist is applied to the entire surface of the silicon oxide film.
- the resist is patterned by photolithography to form a resist having a plurality of striped openings.
- a portion of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings (including K1 and K2), and the resist is removed by organic cleaning.
- a mask 6 is formed.
- a silicon nitride film may be formed using a sputtering device or a PECVD (Plasma Enhanced Chemical Vapor Deposition) device.
- the silicon nitride film can withstand the deposition temperature of about 1000° C. of the base semiconductor portion 8 even if it is thinner than the silicon oxide film.
- the film thickness of the silicon nitride film can be about 20 nm to 4 ⁇ m.
- the openings K1 and K2 have a longitudinal shape (slit shape) and are arranged periodically in the a-axis direction (X direction) of the ELO base semiconductor portion 8 .
- the width of the openings K1 and K2 is about 0.1 ⁇ m to 20 ⁇ m. The smaller the width of each opening, the smaller the number of threading dislocations propagating from each opening to the ELO base semiconductor portion 8 . Also, the second portion LD can be enlarged.
- a small amount of the silicon oxide film decomposes and evaporates during the film formation of the ELO base semiconductor portion 8 and may be taken into the ELO base semiconductor portion 8.
- the silicon nitride film and the silicon oxynitride film decompose at a high temperature. , has the advantage of being difficult to evaporate.
- the mask 6 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed on the base portion 4 in this order.
- a laminated film may be formed by forming a silicon nitride film and a silicon oxide film in this order thereon, or a laminated film may be formed by forming a silicon nitride film, a silicon oxide film and a silicon nitride film in this order on an underlying portion.
- Abnormal portions such as pinholes in the mask portion 5 can be eliminated by performing organic cleaning after film formation, introducing the film into the film forming apparatus again, and forming the same type of film.
- a good quality mask 6 can also be formed by using a general silicon oxide film (single layer) and using such a film formation method.
- a silicon substrate having a (111) plane was used as the main substrate 1, and the buffer portion 2 of the underlying portion 4 was an AlN layer (approximately 30 nm to 300 nm, eg, 150 nm).
- the seed portion 3 of the base portion 4 is formed by a first layer of Al 0.6 Ga 0.4 N layer (for example, 300 nm) and a second layer of GaN layer (for example, 1 to 2 ⁇ m), which are formed in this order. and graded layer.
- a laminate was used in which a silicon oxide film (SiO 2 ) and a silicon nitride film (SiN) were formed in this order.
- the thickness of the silicon oxide film is, for example, 0.3 ⁇ m, and the thickness of the silicon nitride film is, for example, 70 nm.
- a plasma-enhanced chemical vapor deposition (CVD) method was used to form each of the silicon oxide film and the silicon nitride film.
- Example 1 (Base semiconductor part) In Example 1, a GaN layer was used as the base semiconductor portion 8, and an ELO film of gallium nitride (GaN) was formed on the aforementioned template substrate 7 using an MOCVD apparatus.
- the first and second regions 8F and 8S are selectively grown (vertically grown) on the seed portion 3 (the GaN layer as the second layer) exposed in the openings K1 and K2, Subsequently, it grows laterally on the mask portion 5 . Then, the lateral growth of the first and second regions 8F and 8S (base semiconductor portion 8) laterally growing from both sides of the mask portion 5 is stopped before they meet.
- the width (size in the X direction) of the mask portion 5 is 50 ⁇ m, the width (size in the X direction) of the openings K1 and K2 is 5 ⁇ m, the lateral width (size in the X direction) of the ELO base semiconductor portion 8 is 53 ⁇ m, and the second portion LD was 24 ⁇ m, and the layer thickness of the ELO base semiconductor portion 8 was 5 ⁇ m.
- the width of the mask portion 5 can be set according to the specifications of the compound semiconductor portion 9 (for example, about 10 ⁇ m to 200 ⁇ m).
- the lateral film formation rate is increased.
- a technique for increasing the lateral film formation rate is as follows. First, a vertical growth layer growing in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the openings K1 and K2, and then a lateral growth layer growing in the X direction (a-axis direction) is formed. do. At this time, by setting the thickness of the vertical growth layer to 10 ⁇ m or less, preferably 5 ⁇ m or less, and more preferably 3 ⁇ m or less, the thickness of the horizontal growth layer can be kept low and the horizontal film formation rate can be increased.
- FIG. 14 is a cross-sectional view showing an example of lateral growth of the base semiconductor portion (ELO semiconductor layer).
- ELO semiconductor layer the base semiconductor portion
- the initial growth layer SL serves as a starting point for lateral growth of the base semiconductor portions 8A and 8B.
- By appropriately controlling the ELO film forming conditions it is possible to control growth of the base semiconductor portions 8A and 8B in the Z direction (c-axis direction) or in the X direction (a-axis direction).
- the initial growth is performed immediately before the edge of the initial growth layer SL climbs over the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or immediately after it climbs over the upper surface of the mask portion 5. It is preferable to stop the film formation of the layer SL (that is, switch the ELO film formation conditions from the c-axis direction film formation conditions to the a-axis direction film formation conditions at this timing). In this way, since the lateral film formation is performed in a state where the initial growth layer SL slightly protrudes from the mask portion 5, consumption of material for growth in the thickness direction of the base semiconductor portion 8 can be reduced.
- the semiconductor portions 8A and 8B can be laterally grown at high speed.
- the initial growth layer SL can be formed with a thickness of, for example, 0.1 ⁇ m or more and 4.0 ⁇ m or less.
- FIG. 15 is a schematic cross-sectional view showing configurations of a base semiconductor portion and a compound semiconductor portion.
- a compound semiconductor portion 9 forming an LED (light emitting diode) is deposited on a base semiconductor portion 8 .
- the base semiconductor portion 8 is of n-type doped with silicon or the like, for example.
- the compound semiconductor section 9 includes an active layer 34, an electron blocking layer 35, and a p-type semiconductor layer 36 in order from the lower layer side.
- the active layer 34 is an MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer.
- the first light emitting part L1 is included in the active layer 34 .
- the electron blocking layer 35 is, for example, an AlGaN layer.
- the p-type semiconductor layer 36 is, for example, a p-type GaN layer.
- a first electrode E1, which is an anode, is arranged so as to be in contact with the p-type semiconductor layer 36, and a second electrode E2, which is a cathode, is arranged so as to be in contact with the base semiconductor portion 8.
- the first electrode E1, the base semiconductor portion 8, the active layer 34, the electron blocking layer 35, the p-type semiconductor layer 36 and the second electrode E2 constitute the light emitting element ED (so-called micro LED).
- An n-type semiconductor layer may be provided between the base semiconductor portion 8 and the active layer 34 .
- At least one of Al, Ag, Cr, Pd, Pt, Au, Ni, Ti, V, W, Cu, Zn, Sn and In may be a single layer structure or a multi-layer structure. It may have a layered structure and may contain an alloy layer.
- Ag is included in at least one of the first and second electrodes E1 and E2 to emit light. Reflectance can be improved.
- At least one of the first and second electrodes E1 and E2 is a light-transmitting conductive film (ITO (Indium Tin Oxide), etc.) on the compound semiconductor portion 9 and a light-reflecting metal film (Ag, Al, Ti, etc.). can also be a laminated structure.
- ITO Indium Tin Oxide
- the protective layer DF has the function of electrically isolating the first and second electrodes E1 and E2.
- the protective layer DF may have the effect of treating the side surface caused by removing part of the compound semiconductor portion 9 by etching or the like, or the damaged layer formed on the side surface.
- the base semiconductor portion 8 (ELO semiconductor layer) and the compound semiconductor portion 9 can be continuously formed by the same film forming apparatus (for example, MOCVD apparatus). It is also possible to temporarily take out the substrate from the film forming apparatus and then form the compound semiconductor portion 9 using another apparatus. In this case, the compound semiconductor portion 9 may be formed after an n-type GaN layer (for example, about 0.1 ⁇ m to 3 ⁇ m thick) is formed on the base semiconductor portion 8 as a buffer during re-growth. good.
- n-type GaN layer for example, about 0.1 ⁇ m to 3 ⁇ m thick
- a material containing at least one of a fluorescent material and a phosphorescent material can be used for the first to third wavelength conversion layers J1 to J3.
- a material that converts ultraviolet light into blue light is used as the first wavelength conversion layer J1
- a material that converts ultraviolet light into green light is used as the second wavelength conversion layer J2
- ultraviolet light is used as the third wavelength conversion layer J3.
- red light is emitted from the opening (light emitting surface) KR of the first hole H1
- green light is emitted from the opening (light emitting surface) KG of the second hole H2
- the third hole Blue light is emitted from the opening (light emitting surface) KB of H3.
- the first to third wavelength conversion layers J1 to J3 can be formed using a photolithography method, an inkjet method, or the like.
- the first hole H1 formed in the semiconductor substrate 10 functions as a container that holds the first wavelength conversion layer J1 (including at least one of the fluorescent material and the phosphorescent material) within the first hole H1.
- Light from the active layer 34 is converted into a desired wavelength by the first wavelength conversion layer J1 in the first hole H1.
- the minimum film thickness of the first wavelength conversion layer J1 is determined by the characteristics of the phosphor and phosphor (for example, particle shape, size, conversion efficiency) used in the first wavelength conversion layer J1.
- the main substrate 1 can be polished and thinned after the base semiconductor portion 8 and the compound semiconductor portion 9 are formed, but the final thickness of the main substrate 1 is greater than the minimum film thickness of the first wavelength conversion layer J1. should be thicker.
- FIGS. 16 and 17 are cross-sectional views showing the configuration of the display device according to Example 1.
- FIG. 18 is a block diagram illustrating the configuration of the display device according to the first embodiment; FIG. As shown in FIGS. 16 to 18, the display device 50 is arranged on the opposite side of the main substrate 1 of the light emitting device 30 and the light emitting device 30, and is electrically connected to the first and second pads P1 and P2. and a substrate TK.
- the drive substrate TK includes a high-potential power supply PH, a low-potential power supply PL, a plurality of pixel circuits XC, first and second driver circuits D1 and D2, and a control circuit DC.
- the pixel circuit XC includes, for example, a conductive pad PK, a write transistor WT, a drive transistor DT, and a capacitor CP. be done.
- the high-potential power supply PH of the drive substrate TK is connected to the conductive pad PK through the channel of the drive transistor DT, and the conductive pad PK is connected through the first pad P1.
- the first electrode E1 (anode) is connected to the first electrode E1 (anode) through the second pad P2
- the low potential side power supply PL of the drive substrate TK is connected to the second electrode E2 (cathode) through the second pad P2.
- the display voltage (corresponding to the gradation data DT) from the data line YL connected to the second driver D2 (data driver) is applied while the scanning line GL is selected by the first driver D1 (scan driver).
- voltage is written into the capacitor CP via the write transistor WT, and a current corresponding to this display voltage is passed through the channel of the drive transistor DT, the conductive pad PK, the first pad P1, the first electrode E1, and the active layer 34.
- the first light emitting portion L1 of the active layer 34 emits light with an intensity corresponding to the gradation data DT (video data input to the control circuit DC).
- the light (for example, ultraviolet light) emitted from the first light emitting unit L1 is converted into visible light by the first wavelength conversion layer J1, as a result, visible light (for example, red light) having an intensity corresponding to the gradation data DT is emitted.
- visible light for example, red light
- the drive substrate TK may include a silicon substrate, and the pixel circuits XC may be formed on the silicon substrate.
- the channel of each transistor (DT, WT, etc.) may comprise silicon (eg amorphous silicon, polysilicon).
- FIG. 19 is a cross-sectional view showing an example of a drive substrate.
- pixel circuit XC of drive substrate TK may include CMOS circuit 27 including n-channel MOS transistor 25 and p-channel MOS transistor 26 formed on substrate 24 .
- the material of the main substrate 1 of the light emitting device 30 and the substrate 24 of the driving substrate TK may be the same.
- a silicon substrate is used for each of the light emitting device 30 and the driving substrate TK (that is, the main substrate 1 and the substrate 24 of the driving substrate TK have the same coefficient of thermal expansion)
- bonding the light emitting device 30 to the driving substrate TK Accuracy (bonding accuracy) is increased, and yield is improved. It is also possible to bond the light emitting device 30 having a large light emitting surface (display surface) and the drive substrate TK.
- the opening KR of the first hole H1 is the light-emitting surface of the red sub-pixel
- the opening KG of the second hole H2 is the light-emitting surface of the green sub-pixel
- the opening KB of the third hole H3 is the blue sub-pixel.
- these three sub-pixels constitute one pixel.
- the width of the first region 8F (base semiconductor portion 8) is about 53 ⁇ m
- the sub-pixel pitch in the X direction is about 28 ⁇ m
- the sub-pixel pitch in the Y direction is about 84 ⁇ m
- the number of pixels per inch (PPI ) can form a display device (micro LED display) of the order of 900.
- Example 1 even if a different substrate is used for the main substrate 1, for example, the crystallinity of the first light emitting portion L1 located above the first hole H1 formation region is improved, and the light emission efficiency of the first light emitting portion L1 is improved. can increase Furthermore, by forming, for example, a part of the first hole H1 in the main substrate 1, which is a substrate for growth, the first hole H1 can function as a container for holding the first wavelength conversion layer J1. , the main substrate 1 (for example, a silicon substrate) with low translucency can function as a light shielding structure for alleviating the crosstalk phenomenon (light interference between adjacent light emitting portions). This simplifies the structure for extracting light generated in the first light emitting portion L1, and enhances the extraction efficiency.
- the main substrate 1 for example, a silicon substrate
- FIG. 20 is a cross-sectional view along the X direction of the light-emitting device according to Example 2.
- FIG. FIG. 21 is a cross-sectional view along the Y direction of the light-emitting device according to Example 2.
- FIG. 22 is a plan view of a light-emitting device according to Example 2.
- the transparent resin layer TL and the first wavelength conversion layer J1 are in contact with each other, and the contact surface between the transparent resin layer TL and the first wavelength conversion layer J1 is located inside the main substrate 1 .
- a material having a smaller refractive index than that of the underlying portion 4 can be used for the transparent resin layer TL.
- Example 2 as shown in FIGS. 21 and 22, at least a portion of the first pad P1 does not overlap the first hole H1 in plan view. By doing so, it is possible to reduce the influence of pressing on the first pad P1 on the compound semiconductor portion 9 and the base semiconductor portion 8 . At least a portion of the first pad P1 does not overlap the first light emitting section L1. By doing so, it is possible to reduce the influence of the pressure applied to the first pad P1 on the first light-emitting portion L1 of the compound semiconductor portion 9 .
- the first pad P1 does not come into contact with the base semiconductor section 8, and the insulating film DF is positioned between the first pad P1 and the base semiconductor section 8. As shown in FIG. This prevents the formation of short-circuit paths.
- the insulating film DF may be transparent.
- FIG. 23 and 24 are cross-sectional views showing another configuration of the light-emitting device according to Example 2.
- the first hole H1 penetrates the mask 6 and at least part of the bottom of the first hole H1 is included in the base semiconductor portion 8.
- the bottom of the first hole H1 may be the lower surface of the base semiconductor portion 8 .
- a material having a smaller refractive index than that of the mask 6 can be used for the transparent resin layer TL. By doing so, it is possible to suppress the light (stray light) propagated in the mask 6 from entering the first to third wavelength conversion layers J1 to J3. Further, for example, there is no change in the refractive index in the optical path from the first light emitting section L1 to the bottom of the hole H1. Therefore, the light emitted from the first light emitting section L1 is less likely to be reflected or scattered in this optical path and efficiently reaches the hole H1, so that the light extraction efficiency is enhanced.
- FIG. 25 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2.
- FIG. 20 and the like the bottom surface of the first partition QF is positioned on the base semiconductor portion 8 and the bottom surface of the second partition QS is positioned on the upper surface of the mask portion 5, but the present invention is not limited to this.
- the first and second partition wall portions QF and QS with light shielding properties may penetrate the mask 6 and the underlying portion 4 and reach the upper surface of the main substrate 1.
- FIG. 20 the bottom surface of the first partition QF is positioned on the base semiconductor portion 8 and the bottom surface of the second partition QS is positioned on the upper surface of the mask portion 5, but the present invention is not limited to this.
- the first and second partition wall portions QF and QS with light shielding properties may penetrate the mask 6 and the underlying portion 4 and reach the upper surface of the main substrate 1.
- FIG. 20 and the like the bottom surface of the first partition QF is positioned on the base semiconductor portion 8 and the bottom surface of the second partition Q
- FIG. 26 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2.
- the first and second partitions QF and QS are light shielding, but the present invention is not limited to this.
- the first and second partitions QF and QS may be made of a translucent material having a lower refractive index than the base semiconductor section 8 with respect to the emission wavelength of each light emitting section. In this way, light incident on the first and second partition wall portions QF and QS at an angle exceeding the critical angle is totally reflected, so that light propagation (stray light) in the base semiconductor portion 8 can be suppressed. .
- FIG. 27 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2.
- the first to third wavelength conversion layers J1 to J3 are provided in FIG. 20 and the like, the present invention is not limited to this.
- the emission wavelengths of the first to third light emitting portions L1 to L3 are in the blue region, and the third hole H3 is not provided with a wavelength conversion layer, and the blue light from the third light emitting portion L3 is emitted.
- a configuration in which light is emitted from the third hole H3 is also possible.
- a transparent resin layer TL may be provided in the third hole H3.
- FIG. 28 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2.
- a third electrode E3 (light reflecting electrode) overlapping the second light emitting portion L2 in plan view is provided, and the distance between the first electrode E1 (light reflecting electrode) and the first wavelength conversion layer J1 is set to It can be made larger than the distance between the third electrode E3 and the second wavelength conversion layer J2.
- the transparent resin layer TL of the first hole H1 may be thicker than the transparent resin layer TL of the second hole H2, or the depth of the first hole H1 ⁇ the depth of the second hole H2.
- a fifth electrode E5 (light reflecting electrode) overlapping the third light emitting portion L3 in a plan view is provided, and the distance between the third electrode E3 and the second wavelength conversion layer J2 is set to the distance between the fifth electrode E5 and the third wavelength conversion layer. It can be larger than the distance to J3. In this way, an optical resonance effect can be obtained when the emission wavelength of the first wavelength conversion layer J1>the emission wavelength of the second wavelength conversion layer J2>the emission wavelength of the third wavelength conversion layer J3.
- FIG. 29 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2.
- an optical layer CL may be provided in the first hole H1, positioned closer to the light exit surface than the first wavelength converter J1.
- the optical layer CL may have at least one of a light diffusing function and a polarizing function.
- the optical layer CL has a light diffusion function, the viewing angle characteristics are improved (luminance change due to viewing angle is reduced).
- the optical layer CL has a polarizing function (for example, a circular polarizing function), it is possible to reduce the influence of external light.
- FIG. 30 is a cross-sectional view showing another configuration of the light-emitting device according to Example 2.
- a light reflecting film LF for example, a metal film
- the hole wall positioned closer to the light exit surface than the first wavelength converter J1. In this way, the light utilization efficiency can be improved.
- Example 3 31 is a cross-sectional view along the X direction of the light-emitting device according to Example 3.
- FIG. 32 is a cross-sectional view along the Y direction of the light-emitting device according to Example 3.
- FIG. 33 is a plan view of a light-emitting device according to Example 3.
- the first and second light emitting portions L1 and L2 are adjacent to each other in the X direction, and the first electrode E1 is an anode (p electrode) overlapping the first light emitting portion L1 in plan view.
- the second electrode E2 is a cathode (n-electrode) adjacent to the first electrode E1 in the X direction
- the third electrode E3 is an anode overlapping the second light-emitting portion L2 in plan view
- the fourth electrode E4 is the third electrode. 3 It is a cathode adjacent to the electrode E3 in the X direction.
- the first electrode E1, the second electrode E2, the third electrode E3, and the fourth electrode E4 are arranged in the X direction, that is, in the ⁇ 11-20> direction of the base semiconductor portion 8 containing a GaN-based semiconductor. They are arranged in order, and the anodes are not adjacent to each other in the X direction.
- the first electrode E1 overlaps the second portion SD (the portion located on the mask portion 5) of the base semiconductor portion 8, and at least part of the first pad P1 connected to the first electrode E1 is It does not overlap with the first hole H1.
- the opening K1 of the mask 6 is positioned between the first and second light emitting parts L1 and L2, the first partition wall QF is positioned so as to overlap with the opening K1, and the first partition walls QF are positioned adjacent to each other in the Y direction.
- a third partition wall portion QT extending in the X direction is positioned between the light emitting portions L1.
- the third partition wall portion QT may have a light shielding property, or may have a lower refractive index than the base semiconductor portion 8 .
- FIG. 34 and 35 are cross-sectional views showing another configuration of the light-emitting device according to Example 3.
- FIG. 34 the first electrode E1, the second electrode E2, the fourth electrode E4, and the third electrode E3 are arranged in this order in the X direction, and the cathodes are adjacent to each other in the X direction.
- FIG. 35 the second electrode E2, the first electrode E1, the third electrode E3, and the fourth electrode E4 are arranged in this order in the X direction, and the anodes are adjacent to each other in the X direction.
- FIG. 36 is a cross-sectional view showing another configuration of the light-emitting device according to Example 3.
- FIG. 37 is a plan view showing another configuration of the light emitting device according to Example 3.
- the second electrode E2 which is a cathode, may be provided so as to overlap the opening K1 of the mask 6 in plan view.
- the first light emitting portion L1 overlaps the second portion LD in plan view, and the first electrode E1 overlaps the first light emitting portion L1 in plan view.
- the first and second electrodes E1 and E2 are arranged in the X direction.
- the first and second electrodes E1 and E2 are light reflective. Further, in plan view, at least a portion of the first pad P1 does not overlap the first hole H1, and at least a portion of the second pad P2 does not overlap the first hole H1.
- Example 4 38 and 39 are cross-sectional views showing another configuration of the light-emitting device according to Example 4.
- FIG. 38 the underlying portion 4 is locally provided so as to overlap the opening K1 of the mask 6 in plan view.
- the patterning shape overlaps with the opening K1, such as a slit extending in the Y direction.
- a bottom portion of the first hole H1 is included in the base semiconductor portion 8 .
- the main substrate 1 may be a silicon substrate, and the local underlying portion 4 may include a buffer portion (eg, including at least one of AlN and SiC) and a seed portion (GaN-based semiconductor).
- the substrate 1 may be a silicon substrate and the local underlayer 4 may contain a seed portion (eg AlN, 6H—SiC). Note that, as shown in FIG. 39, the bottom surface of the base semiconductor portion 8 may be the bottom portion of the first hole H1.
- Example 5 40 is a flow chart showing a method for manufacturing a light emitting device according to Example 5.
- FIG. 41 is a cross-sectional view showing the configuration of a light-emitting device according to Example 5.
- light emitting device 30 includes mask 6, but is not so limited. As shown in FIG. 40, the mask can be removed after the compound semiconductor portion 9 is formed on the semiconductor substrate 10 including the mask. The mask can be removed by wet etching using an etchant such as hydrofluoric acid or buffered hydrofluoric acid.
- etchant such as hydrofluoric acid or buffered hydrofluoric acid.
- a base substrate UK including a main substrate 1, a semiconductor substrate 10 having a base semiconductor portion 8 positioned above the base substrate UK, a semiconductor substrate 10 positioned above the semiconductor substrate 10, and a first substrate UK. and a compound semiconductor portion 9 having a light emitting portion L1.
- Semiconductor substrate 10 does not include a mask.
- the mask is removed before the electrodes are formed.
- the electrodes may be protected with a resist or the like and the mask may be removed by a method such as wet etching.
- the base semiconductor portion 8 includes a connection region 8C in contact with the base substrate UK and a non-connection region (non-contact region) 8D separated from the base substrate UK.
- the semiconductor substrate 10 includes a first hole H1 that penetrates the main substrate 1 in the thickness direction (Z direction) and overlaps the first light emitting portion L1 in plan view below the first light emitting portion L1.
- the first light emitting portion L1 overlaps the non-connection region 8D in plan view above the non-connection region 8D.
- the base semiconductor portion 8 includes a first portion HD and a second portion SD in which the density of dislocations extending in the thickness direction (Z direction) is lower than that of the first portion HD.
- the first light emitting portion L1 overlaps the second portion SD in plan view above the second portion SD.
- FIG. 42 is a flow chart showing another method for manufacturing a light-emitting device according to Example 5.
- 43 is a cross-sectional view showing another configuration of the light-emitting device according to Example 5.
- the compound semiconductor portion 9 is formed on the semiconductor substrate 10 including the mask, the first electrode E1 and the first pad P1 are formed, and the first hole H1 penetrating the main substrate 1 is formed. 10 is removed by etching or the like. After that, a first wavelength conversion layer J1 is formed in the first hole H1.
- a part of the transparent resin layer TL is arranged in the hollow portion TS generated by removing the mask, and the lower surface of the base semiconductor portion 8 is in contact with the transparent resin layer TL and the hollow portion TS.
- the base portion 4 of the UK is in contact with the hollow portion TS.
- the remainder of the transparent resin layer TL and the first wavelength conversion layer J1 are provided in the first hole H1.
- the first light-emitting portion L1 overlaps the non-connection region 8D above the non-connection region 8D in plan view, and the first light-emitting portion L1 overlaps the second portion SD above the second portion SD in plan view.
- FIG. 44 is a cross-sectional view showing another configuration of the light-emitting device according to Example 5.
- the base portion 4 is locally arranged in a slit shape, and for example, the bottom portion of the first hole H1 is positioned on the lower surface of the base semiconductor portion 8.
- the bottom of the base semiconductor portion 8 is exposed by removing the mask 6 by etching or the like after forming the first hole H1 reaching the lower surface of the base semiconductor portion 8 in the semiconductor substrate 10 .
- the first light-emitting portion L1 overlaps the non-connection region 8D above the non-connection region 8D in plan view, and the first light-emitting portion L1 overlaps the second portion SD above the second portion SD in plan view.
- the process for removing the base portion 4 is not necessary, so the process is shortened.
- the distance (in the Z direction) from the first light emitting portion L1 to the bottom of the first hole H1 is shortened, the light extraction efficiency from the first hole H1 is improved.
- the base semiconductor portion 8 can be a GaN layer, but is not limited to this.
- the base semiconductor portion 8 in Examples 1 to 5 can also be an InGaN layer, which is a GaN-based semiconductor layer.
- Lateral deposition of the InGaN layer is performed at low temperatures, eg, below 1000.degree. This is because, at high temperatures, the vapor pressure of indium increases and it is not effectively incorporated into the film. Lowering the film formation temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer.
- the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer.
- TAG triethylgallium
- Example 7 is a schematic plan view showing a display device of Example 7.
- a plurality of light-emitting devices 30 of Examples 1 to 6 can be mounted side by side on the drive substrate TK to form a display device 50.
- FIG. A plurality of light emitting devices 30 may be arranged in a matrix.
- the drive board TK may include first and second driver circuits D1 and D2 and a control circuit DC for controlling them (see FIG. 18). By doing so, a large display device can be manufactured with a high yield.
- FIG. 46 is a schematic diagram illustrating the configuration of an electronic device according to the eighth embodiment.
- An electronic device 90 in FIG. 46 includes a display device 50 including the light emitting device 30 of Examples 1 to 6, and a control section 80 including a processor.
- Examples of the electronic device 90 include a communication device, an information processing device, a medical device, an electric vehicle (EV), a monitor, and a television.
- EV electric vehicle
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Abstract
Description
図1は、本実施形態に係る発光デバイスの構成を示す断面図である。図1に示すように、本実施形態に係る発光デバイス30は、主基板1、主基板1よりも上方に位置し、マスク部5および開口部K1を含むマスク6、並びにマスク6よりも上方に位置するベース半導体部8を備える半導体基板10と、半導体基板10よりも上方に位置し、第1発光部L1を有する化合物半導体部9とを備える。半導体基板10は、主基板1(例えば、バルク結晶の自立基板)および半導体部(例えば、半導体層)を含んでいればよく、主基板1が半導体もあってもよいし、非半導体であってもよい。発光デバイス30では、主基板1(例えば、バルク結晶の自立基板)からベース半導体部8への向きを上方向とする(よって、鉛直方向上向き、あるいは図面での上向きとは異なる場合がある)。マスク6は、マスク部5および開口部K1を含むマスクパターンであってよい。開口部K1は、マスク部5が存在しない領域であり、開口部K1がマスク部5で囲まれていなくてもよい。
図2は、本実施形態にかかる発光デバイスの製造方法の一例を示すフローチャートである。図2の発光デバイスの製造方法では、テンプレート基板(ELO成長用基板)7を準備する工程の後に、ELO法を用いてベース半導体部8を形成する工程を行い、半導体基板10を得る。次いで、化合物半導体部9を形成する工程を行い、その後、主基板1に対してその裏面1Uからエッチングを行い、第1ホールH1を形成する工程を行う。
図4は、本実施形態に係る表示デバイスの構成を示す断面図である。図4に示すように、表示デバイス50は、発光デバイス30と、発光デバイス30における主基板1の反対側に配され、第1電極E1と電気的に接続する駆動基板TKとを備える。駆動基板TKに含まれる画素回路によって第1発光部L1の発光強度が制御される(後述)。駆動基板TKは、ガラス基板上あるいは樹脂基板上に複数のトランジスタを含む画素回路が形成されている構成でもよいし、シリコン基板上に複数のトランジスタを含む画素回路が形成されている構成でもよい。また、画素回路がCMOS(Complementary Metal Oxide Semiconductor)回路を含んでいてもよい。
(全体構成)
図5は、実施例1に係る発光デバイスの、X方向に沿った断面図である。図6は、実施例1に係る発光デバイスの、Y方向に沿った断面図である。図7は、実施例1に係る発光デバイスの平面図である。図5、図6および図7に示すように、実施例1に係る発光デバイス30は、半導体基板10と、半導体基板10上に位置する化合物半導体部9と、第1および第2電極E1・E2とを備える。半導体基板10は、主基板1と、主基板1上に位置する下地部4と、下地部4上に位置し、マスク部5および開口部K1・K2を含むマスク6と、マスク6上に位置するベース半導体部8とを有する。化合物半導体部9は第1発光部L1を有する。第1電極E1は化合物半導体部9の上方に位置し、第2電極E2はベース半導体部8の上方に位置する。ベース半導体部8および化合物半導体部9は、窒化物半導体(例えば、GaN系半導体)を含む。X方向はベース半導体部8の<11-20>方向(a軸方向)、Y方向はベース半導体部8の<1-100>方向(m軸方向)、Z方向はベース半導体部8の<0001>方向(c軸方向)である。換言すれば、X方向は窒化物半導体(例えば、GaN系半導体)の結晶構造における<11-20>方向、Y方向は窒化物半導体(例えば、GaN系半導体)の結晶構造における<1-100>方向、Z方向は窒化物半導体(例えば、GaN系半導体)の結晶構造における<0001>方向である。マスク6よりも下方の構成(例えば、主基板1および下地部4)を下地基板UKと称する場合がある。また、下地基板およびマスク6をまとめてテンプレート基板7と称することもある。下地部4は下地層であってもよい。マスク6はマスク層であってもよい。ベース半導体部8はベース半導体層であってもよい。化合物半導体部9は、化合物半導体層あるいはデバイス層であってもよい。
図10は、実施例1にかかる発光デバイスの製造方法の一例を示すフローチャートである。図11は、実施例1にかかる発光デバイスの製造方法の一例を示す断面図である。図10および図11に示す発光デバイスの製造方法では、テンプレート基板7を準備する工程の後に、ELO法を用いてベース半導体部8を形成する工程を行い、半導体基板10を得る。次いで、化合物半導体部9を形成する工程を行い、その後、第1および第2電極E1・E2を形成する工程を行い、その後、第1および第2パッドP1・P2を形成する工程を行う。その後、半導体基板10に対して、主基板1の裏面1Uからエッチングを行い、半導体基板10に、主基板1を貫通する第1ホールH1を形成する工程を行う。その後、第1ホールH1に第1波長変換層J1を形成する工程を行う。なお、主基板1に第1ホールH1などの貫通孔を形成する場合、例えば、ウェットエッチングまたはドライエッチングなどの手法によって形成することができる。より具体的には、例えば、Bosch法によって貫通孔を形成してもよい。また、第2ホールH2および第3ホールH3などの貫通孔も、上記の手法にて形成することができる。
主基板1には、GaN系半導体と異なる格子定数を有する異種基板を用いることができる。異種基板としては、単結晶のシリコン(Si)基板、サファイア(Al2O3)基板、シリコンカーバイド(SiC)基板等を挙げることができる。主基板1の面方位は、例えば、シリコン基板の(111)面、サファイア基板の(0001)面、SiC基板の6H-SiC(0001)面である。これらは例示であって、ELOベース半導体部8をELO法で成長させることができる主基板および面方位であればよい。
下地部4として、主基板1側から順に、バッファ部2およびシード部3を設けることができる。バッファ部2はバッファ層であってよい。シード部3がシード層であってもよい。バッファ部2は、例えば、主基板1とシード部3とがダイレクトに接触して互いに溶融することを低減する機能を有する。例えば、主基板1にシリコン基板を用い、シード部3にGaN系半導体を用いた場合、両者(主基板とシード部)が溶融し合うため、例えば、AlN層およびSiC(炭化シリコン)層の少なくとも一方を含むバッファ部2を設けることで、溶融が低減される。バッファ部2の一例であるAlN層は、例えばMOCVD装置を用いて、厚さ10nm程度~5μm程度に形成することができる。バッファ部2が、シード部3の結晶性を高める効果、ベース半導体部8の内部応力を緩和する(発光デバイス30の反りを緩和する)効果の少なくとも一方を有していてもよい。シード部3と溶融し合わない主基板1を用いた場合には、バッファ部2を設けない構成(すなわち、下地部4をシード部で構成する)ことも可能である。また、図5のように、下地部4が平面視でマスク部5の全体と重なる構成に限定されない。下地部4はマスク6の開口部K1・K2から露出すればよいため、下地部4を、平面視で開口部K1・K2と重なるように局所的に(例えば、Y方向に伸びるスリット状に)形成してもよい(後述)。
マスク6の開口部K1・K2は、シード部3を露出させ、ベース半導体部8の成長を開始させる成長開始用ホールの機能を有し、マスク6のマスク部5は、ベース半導体部8を横方向成長させる選択成長用マスクの機能を有する。開口部K1・K2はマスク部5がない部分であって、開口部K1・K2がマスク部5で囲まれていなくてもよい。
主基板1には、(111)面を有するシリコン基板を用い、下地部4のバッファ部2は、AlN層(30nm~300nm程度、例えば150nm)とした。下地部4のシード部3は、第1層であるAl0.6Ga0.4N層(例えば、300nm)と、第2層であるGaN層(例えば、1~2μm)とがこの順に形成されたグレーデット層とした。
実施例1では、ベース半導体部8をGaN層とし、MOCVD装置を用いて前述のテンプレート基板7上に窒化ガリウム(GaN)のELO成膜を行った。ELO成膜条件の一例として、基板温度:1120℃、成長圧力:50kPa、TMG(トリメチルガリウム):22sccm、NH3:15slm、V/III=6000(III族原料の供給量に対する、V族原料の供給量の比)を採用することができる。
図15は、ベース半導体部および化合物半導体部の構成を示す模式的断面図である。実施例1では、ベース半導体部8上に、LED(発光ダイオード)を構成する化合物半導体部9を成膜する。ベース半導体部8は、例えばシリコン等がドープされたn型である。化合物半導体部9は、下層側から順に、活性層34、電子ブロッキング層35、およびp型半導体層36を含む。活性層34は、MQW(Multi-Quantum Well)であり、InGaN層およびGaN層を含む。第1発光部L1は、活性層34に含まれる。電子ブロッキング層35は、例えばAlGaN層である。p型半導体層36は、例えばp型のGaN層である。アノードである第1電極E1は、p型半導体層36と接触するように配され、カソードである第2電極E2は、ベース半導体部8と接触するように配される。第1電極E1、ベース半導体部8、活性層34、電子ブロッキング層35、p型半導体層36および第2電極E2によって発光素子ED(いわゆるマイクロLED)が構成される。ベース半導体部8と活性層34との間にn型半導体層を設けてもよい。
第1~第3波長変換層J1~J3には、蛍光体および燐光体の少なくとも一方を含む材料を用いることができる。例えば、第1波長変換層J1として紫外光を青色光に変換する材料を用い、第2波長変換層J2として紫外光を緑色光に変換する材料を用い、第3波長変換層J3として紫外光を赤色光に変換する材料を用いることで、第1ホールH1の開口(発光面)KRから赤色光が出射し、第2ホールH2の開口(発光面)KGから緑色光が出射し、第3ホールH3の開口(発光面)KBから青色光が出射する。第1~第3波長変換層J1~J3は、フォトリソグラフィ法、インクジェット法等を用いて形成することができる。
図16および図17は、実施例1に係る表示デバイスの構成を示す断面図である。図18は、実施例1に係る表示デバイスの構成を示すブロック図である。図16~図18に示すように、表示デバイス50は、発光デバイス30と、発光デバイス30における主基板1の反対側に配され、第1および第2パッドP1・P2と電気的に接続する駆動基板TKとを備える。駆動基板TKは、高電位側電源PH、低電位側電源PL、複数の画素回路XC、第1および第2ドライバ回路D1・D2並びに制御回路DCを備える。画素回路XCは、例えば、導電パッドPK、書き込みトランジスタWT、駆動トランジスタDT、および容量(キャパシタ)CPを含み、駆動トランジスタDTによって第1発光部L1の発光強度(発光素子EDの電流値)が制御される。
図20は、実施例2に係る発光デバイスの、X方向に沿った断面図である。図21は、実施例2に係る発光デバイスの、Y方向に沿った断面図である。図22は、実施例2に係る発光デバイスの平面図である。実施例2の発光デバイス30では、第1ホールH1の底部の少なくとも一部が下地部4に含まれ、第1ホールH1内に、第1ホールH1の底部に接する透明樹脂層TLと、第1波長変換層J1とが設けられる。透明樹脂層TLおよび第1波長変換層J1が接触し、透明樹脂層TLおよび第1波長変換層J1の接触面が主基板1内に位置する。透明樹脂層TLには、下地部4よりも屈折率の小さな材料を用いることができる。第2および第3ホールH2・H3についても同様である。こうすれば、下地部4内に伝播した光(迷光)の第1~第3波長変換層J1~J3への入射を抑制することができる。
図31は、実施例3に係る発光デバイスの、X方向に沿った断面図である。図32は、実施例3に係る発光デバイスの、Y方向に沿った断面図である。図33は、実施例3に係る発光デバイスの平面図である。図31~図33に示すように、第1および第2発光部L1・L2がX方向に隣り合い、第1電極E1は、平面視において第1発光部L1に重なるアノード(p電極)であり、第2電極E2は第1電極E1とX方向に隣り合うカソード(n電極)であり、第3電極E3は、平面視において第2発光部L2に重なるアノードであり、第4電極E4は第3電極E3とX方向に隣り合うカソードである。実施例3では、第1電極E1、第2電極E2、第3電極E3および第4電極E4が、X方向、すなわち、GaN系半導体を含むベース半導体部8の<11-20>方向に、この順に並び、X方向については、アノード同士が隣り合わない。
図38および図39は、実施例4に係る発光デバイスの別構成を示す断面図である。図38では、下地部4を、平面視でマスク6の開口部K1と重なるように局所的に設ける。例えばY方向に伸びるスリット状のような、開口部K1と重なるパターニング形状とする。第1ホールH1の底部はベース半導体部8に含まれる。下地部4を局所的に設けることで、発光デバイス30の反りを低減することができ、駆動基板TKへの接合精度を高めることができる。主基板1がシリコン基板であり、局所的な下地部4が、バッファ部(例えば、AlNおよびSiCの少なくとも一方を含む)と、シード部(GaN系半導体)とを含んでいてもよいし、主基板1がシリコン基板であり、局所的な下地部4が、シード部(例えば、AlN,6H-SiC)を含んでいてもよい。なお、図39のように、ベース半導体部8の下面が第1ホールH1の底部となる構成でもよい。
図40は、実施例5に係る発光デバイスの製造方法を示すフローチャートである。図41は、実施例5に係る発光デバイスの構成を示す断面図である。実施例1~4では、発光デバイス30がマスク6を含むが、これに限定されない。図40に示すように、マスクを含む半導体基板10上に化合物半導体部9を形成した後にマスクを除去することもできる。マスクの除去は、例えば、フッ酸やバッファードフッ酸等のエッチャントを用いて、ウェットエッチング法などを用いることで除去することができる。図41の発光デバイス30は、主基板1を含む下地基板UK、および下地基板UKよりも上方に位置するベース半導体部8を有する半導体基板10と、半導体基板10よりも上方に位置し、第1発光部L1を有する化合物半導体部9とを備える。半導体基板10はマスクを含まない。なお、本実施形態では、マスクの除去を電極の形成前に行なっているが、電極を形成した後にレジスト等で電極を保護し、ウェットエッチング法などの方法でマスクを除去してもよい。
実施例1~5では、ベース半導体部8をGaN層とすることができるがこれに限定されない。実施例1~5のベース半導体部8を、GaN系半導体層であるInGaN層とすることもできる。InGaN層の横方向成膜は、例えば1000℃を下回るような低温で行う。高温ではインジウムの蒸気圧が高くなり、膜中に有効に取り込まれないためである。成膜温度が低温になることで、マスク部5とInGaN層の相互反応が低減される効果がある。また、InGaN層は、GaN層よりもマスク部5との反応性が低いという効果もある。InGaN層にインジウムがIn組成レベル1%以上で取り込まれるようになると、マスク部5との反応性がさらに低下するため、望ましい。ガリウム原料ガスとしては、トリエチルガリウム(TEG)を用いることが好ましい。
図45は、実施例7の表示デバイスを示す模式的平面図である。図45に示すように、駆動基板TKに、実施例1~6の発光デバイス30を複数並べて実装し、表示デバイス50とすることもできる。複数の発光デバイス30をマトリクス状に並べてもよい。駆動基板TKには、第1および第2ドライバ回路D1・D2およびこれらを制御する制御回路DCが含まれていてもよい(図18参照)。こうすれば、大型の表示デバイスを歩留まりよく製造することができる。
図46は、実施例8に係る電子機器の構成を示す模式図である。図46の電子機器90は、実施例1~6の発光デバイス30を含む表示デバイス50と、プロセッサを含む制御部80とを含む。電子機器90としては、通信装置、情報処理装置、医療機器、電気自動車(EV)、モニタ、テレビジョン等を挙げることができる。
以上、本開示に係る発明について、諸図面および実施例に基づいて説明してきた。しかし、本開示に係る発明は上述した各実施形態に限定されるものではない。すなわち、本開示に係る発明は本開示で示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本開示に係る発明の技術的範囲に含まれる。つまり、当業者であれば本開示に基づき種々の変形または修正を行うことが容易であることに注意されたい。また、これらの変形または修正は本開示の範囲に含まれることに留意されたい。
4 下地部
5 マスク部
6 マスク
8 ベース半導体部
9 化合物半導体部
10 半導体基板
30 発光デバイス
50 表示デバイス
L1 第1発光部
L2 第2発光部
K1・K2 開口部
E1 第1電極
E2 第2電極
J1 第1波長変換層
H1 第1ホール
H2 第2ホール
TK 駆動基板
UK 下地基板
Claims (62)
- 主基板、前記主基板よりも上方に位置し、マスク部および開口部を含むマスク、並びに前記マスクよりも上方に位置するベース半導体部を備える半導体基板と、
前記半導体基板よりも上方に位置し、第1発光部を有する化合物半導体部とを備え、
前記半導体基板は、前記主基板を厚み方向に貫通し、前記第1発光部の下方において前記第1発光部と重なる第1ホールを含む、発光デバイス。 - 平面視において、前記第1発光部が前記マスク部と重なる、請求項1に記載の発光デバイス。
- 平面視において、前記第1ホールが前記マスク部と重なる、請求項1に記載の発光デバイス。
- 前記第1ホールに配された、受光波長よりも長波長の光を発する第1波長変換層を備える、請求項1に記載の発光デバイス。
- 前記主基板上に位置する下地部を備え、
前記第1ホールの底部の少なくとも一部が前記下地部に含まれる、請求項1~4のいずれか1項に記載の発光デバイス。 - 前記第1ホールの底部の少なくとも一部が前記マスクに含まれる、請求項1~4のいずれか1項に記載の発光デバイス。
- 前記第1ホールは前記マスクを貫通し、前記第1ホールの底部の少なくとも一部が前記ベース半導体部に含まれる、請求項1~4のいずれか1項に記載の発光デバイス。
- 第1電極および第2電極を含み、
平面視において、前記第1電極が前記第1発光部に重なる、請求項1~7のいずれか1項に記載の発光デバイス。 - 前記第1電極は光反射性を有する、請求項8に記載の発光デバイス。
- 前記第1電極に接続する第1パッドと、前記第2電極に接続する第2パッドとを含む、請求項8または9に記載の発光デバイス。
- 前記第1パッドの少なくとも一部は、前記第1ホールと重ならない、請求項10に記載の発光デバイス。
- 前記第1パッドの少なくとも一部は、前記第1発光部と重ならない、請求項10または11に記載の発光デバイス。
- 平面視において、前記第2パッドの少なくとも一部は、前記第1ホールと重ならない、請求項10~12のいずれか1項に記載の発光デバイス。
- 前記第1パッドおよび前記第2パッドの上面の位置が一致している、請求項10~13のいずれか1項に記載の発光デバイス。
- 平面視において、前記第2電極が前記マスクの開口部と重なる、請求項8~14のいずれか1項に記載の発光デバイス。
- 前記第2電極が前記ベース半導体部に接する、請求項8~15のいずれか1項に記載の発光デバイス。
- 前記第2電極が凹部を有し、前記凹部に絶縁層が設けられている、請求項8~16のいずれか1項に記載の発光デバイス。
- 前記第1電極がアノードであり、前記第2電極がカソードである、請求項8~17のいずれか1項に記載の発光デバイス。
- 前記ベース半導体部がGaN系半導体を含み、
前記第1電極および前記第2電極が前記GaN系半導体の<1-100>方向に並ぶ、請求項8~18のいずれか1項に記載の発光デバイス。 - 前記ベース半導体部がGaN系半導体を含み、
前記第1電極および前記第2電極が前記GaN系半導体の<11-20>方向に並ぶ、請求項8~18のいずれか1項に記載の発光デバイス。 - 前記第1ホールの底部と前記第1波長変換層との間隙に透明樹脂層が配されている、請求項4に記載の発光デバイス。
- 前記透明樹脂層と前記第1波長変換層との接触面が前記主基板内に位置する、請求項21に記載の発光デバイス。
- 前記ベース半導体部は、前記開口部上に位置する第1部分と、前記マスク部上に位置し、貫通転位密度が5×106/cm2以下の第2部分とを含み、
前記第2部分は、平面視で前記第1発光部と重なる、請求項1~22のいずれか1項に記載の発光デバイス。 - 第3電極および第4電極を備え、
前記化合物半導体部は第2発光部を有し、
前記主基板は、厚み方向の貫通孔であり、平面視で前記第2発光部と重なる第2ホールを有し、
平面視で前記第3電極が前記第2発光部に重なる、請求項8に記載の発光デバイス。 - 前記ベース半導体部がGaN系半導体を含み、
前記第1電極、前記第2電極、前記第3電極および前記第4電極が、この順に前記GaN系半導体の<11-20>方向に並ぶ、請求項24に記載の発光デバイス。 - 前記ベース半導体部がGaN系半導体を含み、
前記第2電極、前記第1電極、前記第4電極および前記第3電極が、この順に前記GaN系半導体の<11-20>方向に並ぶ、請求項24に記載の発光デバイス。 - 前記化合物半導体部は、第2発光部および第3発光部を有し、
前記主基板は、厚み方向の貫通孔であり、平面視で前記第2発光部と重なる第2ホールと、厚み方向の貫通孔であり、平面視で前記第3発光部と重なる第3ホールとを含む、請求項1~26のいずれか1項に記載の発光デバイス。 - 前記第2ホールに、受光波長よりも長波長の光を発する第2波長変換層が設けられ、
前記第1~第3ホールから互いに異なる色の光が出射する、請求項27に記載の発光デバイス。 - 前記第1~第3発光部それぞれの発光ピーク波長が、430~640〔nm〕の波長域にある、請求項27または28に記載の発光デバイス。
- 前記第3ホールに、受光波長よりも長波長の光を発する第3波長変換層が設けられている、請求項27~29のいずれか1項に記載の発光デバイス。
- 前記第3ホールに波長変換層が設けられておらず、前記第3ホールから青色光が出射する、請求項27~29のいずれか1項に記載の発光デバイス。
- 平面視において前記第1発光部および前記第2発光部の間隙に位置する第1隔壁部を含む、請求項27~31のいずれか1項に記載の発光デバイス。
- 前記第1隔壁部は、平面視で前記マスクの前記開口部と重なる、請求項32に記載の発光デバイス。
- 前記第1隔壁部は、遮光性または前記ベース半導体部よりも低い屈折率を有する、請求項32または33に記載の発光デバイス。
- 平面視において前記第2発光部および前記第3発光部の間隙に位置する第2隔壁部を含む、請求項27~34のいずれか1項に記載の発光デバイス。
- 前記第2隔壁部は、平面視で前記マスク部中央と重なる、請求項35に記載の発光デバイス。
- 前記第2隔壁部は、遮光性または前記ベース半導体部よりも低い屈折率を有する、請求項35または36に記載の発光デバイス。
- 前記ベース半導体部は、互いに分離された複数の領域を含み、
各領域が長手形状である、請求項1~37のいずれか1項に記載の発光デバイス。 - 前記ベース半導体部および前記化合物半導体部それぞれがGaN系半導体を含む、請求項1~38のいずれか1項に記載の発光デバイス。
- 前記主基板が前記GaN系半導体と格子定数の異なる異種基板である、請求項39に記載の発光デバイス。
- 前記主基板が遮光性を有する、請求項40に記載の発光デバイス。
- 前記異種基板がシリコン基板である、請求項40または41に記載の発光デバイス。
- 前記第1ホールは、前記ベース半導体部側に向けて先細りとなるテーパ形状である、請求項1~42のいずれか1項に記載の発光デバイス。
- 前記第1波長変換層が、蛍光体および燐光体の少なくとも一方を含む、請求項4に記載の発光デバイス。
- 前記第1ホールに、前記第1波長変換層よりも光出射面側に位置する光学層が設けられている、請求項4に記載の発光デバイス。
- 前記光学層が光拡散機能および偏光機能の少なくとも一方を有する、請求項45に記載の発光デバイス。
- 前記第1ホールの孔壁の少なくとも一部に光反射膜が設けられている、請求項1~46のいずれか1項に記載の発光デバイス。
- 前記第1ホールに、受光波長よりも長波長の光を発する第1波長変換層が設けられ、
前記第2ホールに、受光波長よりも長波長の光を発する第2波長変換層が設けられ、
第1波長変換層の発光波長は、第2波長変換層の発光波長よりも長く、
前記第1電極および前記第1波長変換層間の距離は、前記第3電極および前記第2波長変換層間の距離よりも大きい、請求項24に記載の発光デバイス。 - 前記第1パッドと前記ベース半導体部との間に透明の絶縁膜が配されている、請求項11または12に記載の発光デバイス。
- 前記主基板上に位置する下地部を備え、
前記下地部が、平面視で前記マスクの開口部と重なるように局所的に設けられている、請求項1~4のいずれか1項に記載の発光デバイス。 - 主基板を含む下地基板、および前記下地基板よりも上方に位置するベース半導体部を有する半導体基板と、
前記半導体基板よりも上方に位置し、第1発光部を有する化合物半導体部とを備え、
前記ベース半導体部は、前記下地基板に接する接続領域と、前記下地基板から離れた非接続領域とを含み、
前記半導体基板は、前記主基板を厚み方向に貫通し、前記第1発光部の下方において前記第1発光部と重なる第1ホールを含む、発光デバイス。 - 前記第1発光部は、前記非接続領域の上方において前記非接続領域と重なる、請求項51に記載の発光デバイス。
- 主基板を含む下地基板、および前記下地基板よりも上方に位置するベース半導体部を有する半導体基板と、
前記半導体基板よりも上方に位置し、第1発光部を有する化合物半導体部とを備え、
前記ベース半導体部は、第1部分と、厚み方向に伸びる転位の密度が前記第1部分よりも小さい第2部分とを含み、
前記半導体基板は、前記主基板を厚み方向に貫通し、前記第1発光部の下方において前記第1発光部と重なる第1ホールを含む、発光デバイス。 - 前記第1発光部は、前記第2部分の上方において前記第2部分と重なる、請求項53に記載の発光デバイス。
- 前記ベース半導体部の下面に接する中空部を含む、請求項51または53に記載の発光デバイス。
- 前記中空部が前記下地基板に接する、請求項55に記載の発光デバイス。
- 請求項1~56のいずれか1項に記載の発光デバイスと、前記発光デバイスが実装される駆動基板とを含む表示デバイス。
- 請求項1~56のいずれか1項に記載の発光デバイスを含む電子機器。
- 請求項1、51、53のいずれか1項に記載の発光デバイスの製造方法であって、
選択成長用マスクを用いたELO法によって前記ベース半導体部を形成する工程と、
前記主基板の裏面からエッチングを行い、前記第1ホールを形成する工程とを含む、発光デバイスの製造方法。 - 前記第1ホールを形成する前に、前記半導体基板および前記化合物半導体部を駆動基板に保持させる工程を行う、請求項59に記載の発光デバイスの製造方法。
- 前記第1ホールを形成する前に、前記主基板の厚みを小さくする工程を行う、請求項59または60に記載の発光デバイスの製造方法。
- 請求項1、51、53のいずれか1項に記載の発光デバイスの製造装置であって、
選択成長用マスクを用いたELO法によって前記ベース半導体部を形成する工程と、
前記主基板の裏面からエッチングを行い、前記第1ホールを形成する工程とを行う、発光デバイスの製造装置。
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- 2022-07-15 WO PCT/JP2022/027815 patent/WO2023002929A1/ja active Application Filing
- 2022-07-15 KR KR1020247002082A patent/KR20240021984A/ko active Search and Examination
- 2022-07-18 TW TW111126871A patent/TW202310441A/zh unknown
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JPH10233559A (ja) * | 1997-02-20 | 1998-09-02 | Canon Inc | 半導体レーザ装置、その作製方法およびそれを用いた光通信方式 |
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TW202310441A (zh) | 2023-03-01 |
EP4376105A1 (en) | 2024-05-29 |
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