WO2022255252A1 - 半導体デバイス、半導体デバイスの製造方法および製造装置、並びに電子機器 - Google Patents
半導体デバイス、半導体デバイスの製造方法および製造装置、並びに電子機器 Download PDFInfo
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Images
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02367—Substrates
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01—ELECTRIC ELEMENTS
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02612—Formation types
- H01L21/02617—Deposition types
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
Definitions
- the present disclosure relates to semiconductor devices and the like.
- Patent Document 1 discloses a surface-emitting semiconductor laser device in which a DBR (Distributed Bragg Reflector) layer and a light-emitting layer are provided on a GaN substrate.
- DBR Distributed Bragg Reflector
- a structure using a DBR as a selective growth mask has a problem of heat dissipation.
- a semiconductor device includes a base substrate including a main substrate, a first light reflecting portion positioned above the base substrate, a first mask positioned above the first light reflecting portion, and the first light reflecting portion positioned above the first light reflecting portion. a base semiconductor portion positioned above the first mask; a compound semiconductor portion positioned above the base semiconductor portion; and a second light reflection portion positioned above the compound semiconductor portion and the first light reflection portion. , provided.
- FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment
- FIG. FIG. 4 is a cross-sectional view showing another configuration of the semiconductor device according to the embodiment
- It is a flow chart which shows an example of a manufacturing method of a semiconductor device concerning this embodiment.
- 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment
- FIG. 1 is a cross-sectional view along the X direction of the semiconductor device according to Example 1
- FIG. 1 is a cross-sectional view along the Y direction of the semiconductor device according to Example 1
- FIG. 1 is a plan view of a semiconductor device according to Example 1
- FIG. 2 is a partially enlarged view of the semiconductor device of Example 1.
- FIG. 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment
- FIG. 1 is a cross-sectional view along the X direction of the semiconductor device according to Example 1
- FIG. 1 is a cross-sectional view along the Y
- FIG. 2 is a partially enlarged view of the semiconductor device of Example 1.
- FIG. FIG. 3 is a cross-sectional view showing a configuration example of an underlying substrate;
- FIG. 5 is a cross-sectional view showing another configuration example around the first light reflecting portion;
- FIG. 5 is a cross-sectional view showing another configuration example around the first light reflecting portion;
- FIG. 5 is a cross-sectional view showing another configuration example around the first light reflecting portion;
- 4 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Example 1;
- 1A to 1D are process cross-sectional views showing an example of a method for manufacturing a semiconductor device according to Example 1;
- 4 is a cross-sectional view showing an example of lateral growth of the base semiconductor portion 8.
- FIG. 4 is a plan view showing another configuration of the semiconductor device of Example 1.
- FIG. 4 is a cross-sectional view showing another configuration of the semiconductor device of Example 1;
- FIG. 4 is a plan view showing another configuration of the semiconductor device of Example 1.
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 4 is a cross-sectional view showing another configuration of
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1;
- FIG. 4 is a plan view showing another configuration of the semiconductor device according to Example 1;
- FIG. 4 is a plan view showing another configuration of the semiconductor device according to Example 1;
- FIG. 4 is a schematic plan view showing another configuration of the semiconductor device according to Example 1.
- FIG. 4 is a schematic plan view showing another configuration of the semiconductor device according to Example 1.
- FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to Example 2;
- FIG. 8 is a cross-sectional view showing the configuration of a base substrate according to Example 2;
- FIG. 8 is a cross-sectional view showing the configuration of a base substrate according to Example 2;
- FIG. 8 is a cross-sectional view showing the configuration of a base substrate according to Example 2;
- FIG. 8 is a cross-sectional view showing the configuration of a base substrate according to Example 2;
- FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to Example 3;
- FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to Example 3;
- 10 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Example 4;
- FIG. 11 is a cross-sectional view showing the configuration of a semiconductor device according to Example 4;
- FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment.
- the semiconductor device 30 according to the present embodiment includes a base substrate UK, a first light reflection portion RF positioned above the base substrate UK, and a first light reflection portion RF positioned above the first light reflection portion RF.
- the semiconductor device 30 includes one or more surface emitting semiconductor laser elements 20 including a base semiconductor portion 8, a compound semiconductor portion 9, a first light reflecting portion RF and a second light reflecting portion RS.
- the normal direction of the base substrate UK and the direction from the base substrate UK to the first mask 6 is defined as the upward direction.
- the first mask 6 may be the mask layer 6
- the base semiconductor portion 8 may be the base semiconductor layer 8
- the compound semiconductor portion 9 may be the compound semiconductor layer 9
- the first light reflecting portion RF may be the first light reflecting layer
- the second light reflecting portion RS may be the second light reflecting layer.
- the first mask 6 may have the mask portion 5 and the opening K. That is, the first mask 6 may be a mask pattern including the mask portion 5 and the opening K.
- a first electrode E ⁇ b>1 can be provided on the compound semiconductor portion 9 .
- the first light reflecting portion RF, the base semiconductor portion 8, the compound semiconductor portion 9, the first electrode E1, and the second light reflecting portion RS may overlap each other in plan view.
- Two components overlap in plan view means that at least part of one component overlaps the other component when viewed in the normal direction of the base substrate UK (including perspective view).
- laser oscillation is enabled by reciprocating light generated in the compound semiconductor portion 9 between the first and second light reflecting portions RF and RS.
- the semiconductor device 30 since the first light reflecting portion RF is provided between the base substrate UK and the first mask 6, heat dissipation from the first light reflecting portion RF is improved, and the surface emitting semiconductor laser element is improved. 20 reliability is enhanced.
- Base semiconductor portion 8 and compound semiconductor portion 9 may contain a nitride semiconductor.
- a GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.
- the base semiconductor portion 8 may be doped (eg, n-type with donors).
- Each of the base semiconductor portion 8 and the compound semiconductor portion 9 may be a nitride semiconductor layer.
- the base semiconductor portion 8 containing a nitride semiconductor can be formed, for example, by an ELO (Epitaxial Lateral Overgrowth) method.
- ELO Epilateral Lateral Overgrowth
- threading dislocations (defects) of the base semiconductor portion 8 and the compound semiconductor portion 9 are reduced on the mask portion 5, so the luminous efficiency of the compound semiconductor portion 9 (for example, the charge from the first electrode E1 is reduced).
- the ratio of the amount of light to the amount of injection) is increased, and the amount of heat generated is reduced. This is because threading dislocations are dislocations (defects) that extend from the base semiconductor portion 8 to the compound semiconductor portion 9, inhibit charge transfer, and cause heat generation.
- a template substrate including the base substrate UK, the first light reflecting portion RF, and the mask pattern 6 on the first light reflecting portion RF may be used.
- the template substrate may have a growth suppression region (for example, a region that suppresses crystal growth in the Z direction) corresponding to the mask portion 5 and a seed region corresponding to the opening K.
- a growth suppression region and a seed region can be formed in the first light reflecting portion RF, and the base semiconductor portion 8 can be formed on the growth suppression region and the seed region using the ELO method.
- the first light reflector RF may be an epitaxial DBR (Distributed Bragg Reflector) containing a nitride semiconductor. By doing so, the light reflectance of the first light reflecting portion RF is increased.
- DBR Distributed Bragg Reflector
- FIG. 2 is a cross-sectional view showing another configuration of the semiconductor device according to this embodiment.
- the semiconductor device 30 is provided with a circuit board CB located on the opposite side of the base substrate UK (above the compound semiconductor portion 9) and electrically connected to the surface emitting semiconductor laser element 20. be able to.
- FIG. 3 is a flow chart showing an example of a method for manufacturing a semiconductor device according to this embodiment.
- a base substrate UK is prepared, a first light reflecting portion RF is formed, a first mask 6 is formed, and a base semiconductor portion 8 is formed by using the ELO method. , a step of forming the compound semiconductor portion 9, and a step of forming the second light reflecting portion RS.
- FIG. 4 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment.
- the semiconductor device manufacturing apparatus 70 of FIG. 4 includes a first film forming section 72 forming a first light reflecting section RF, a base semiconductor section 8, and a compound semiconductor section 9, a first mask 6, and a second light reflecting section RS.
- a second film forming section 73 to be formed and a control section 74 for controlling the first and second film forming sections 72 and 73 are provided.
- the first film forming unit 72 may include a MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and memory.
- the control unit 74 may be configured to control the first and second film forming units 72 and 73 by executing a program stored in an internal memory, a communicable communication device, or an accessible network, for example.
- the above program and a recording medium storing the above program are also included in this embodiment.
- FIG. 5 is a cross-sectional view along the X direction of the semiconductor device according to Example 1.
- FIG. 6 is a cross-sectional view along the Y direction of the semiconductor device according to Example 1.
- FIG. FIG. 7 is a plan view of a semiconductor device according to Example 1.
- the semiconductor device 30 according to the first embodiment includes a base substrate UK, a first light reflector RF positioned on the base substrate UK, and a light reflector RF on the first light reflector RF.
- the base semiconductor portion 8 and the compound semiconductor portion 9 may contain a nitride semiconductor (for example, a GaN-based semiconductor).
- the X direction is the ⁇ 11-20> direction of the base semiconductor portion 8
- the Y direction is the ⁇ 1-100> direction of the base semiconductor portion 8
- the Z direction is the ⁇ 0001> direction of the base semiconductor portion 8 .
- the base semiconductor portion 8 includes a first portion HD and a second portion SD (low defect portion) located on the mask portion 5 and having a threading dislocation density of 1 ⁇ 5 or less that of the first portion HD.
- the threading dislocation density of the second portion SD may be 5 ⁇ 10 6 /cm 2 or less.
- the second portion SD overlaps the compound semiconductor portion 9 in plan view.
- a portion of the compound semiconductor portion 9 that overlaps with the second portion SD in plan view becomes a low dislocation portion inheriting the low dislocation property (low defect property) of the base semiconductor portion 8 .
- the first light reflecting portion RF and the second light reflecting portion RS can be configured to overlap the second portion SD in plan view.
- the base semiconductor portion 8 can be composed of an n-type semiconductor (for example, silicon-doped gallium nitride).
- an n-type semiconductor for example, silicon-doped gallium nitride.
- the mask portion 5 contains silicon
- the base semiconductor portion 8 is deposited by unintentionally doping, part of the first mask 6 is diffused to make the base semiconductor portion 8 an n-type semiconductor.
- the first electrode E1 is a translucent anode
- the second electrode E2 is a cathode.
- the first electrode E1 is located above the compound semiconductor portion 9 and overlaps the second light reflecting portion RF in plan view.
- the second electrode E2 is located above the first mask 6 and does not overlap the second light reflecting portion RS in plan view.
- the second electrode E2 contacts the base semiconductor portion 8 .
- the compound semiconductor portion 9 is provided on the base semiconductor portion 8 , but the compound semiconductor portion 9 is not formed above a portion of the base semiconductor portion 8 , so that the compound semiconductor portion 9 is in contact with the portion of the base semiconductor portion 8 .
- a second electrode E2 is provided.
- the semiconductor device 30 is a surface emitting semiconductor laser including a first light reflecting portion RF, a base semiconductor portion 8, a compound semiconductor portion 9, an insulating film KF, first and second electrodes E1 and E2, and a second light reflecting portion RS.
- One or more elements 20 (VCSEL elements: a vertical cavity surface emitting laser element) are configured.
- the semiconductor laser element 20 the light generated in the compound semiconductor 9 by the current between the first and second electrodes E1 and E2 causes laser oscillation by stimulated emission and feedback action between the first and second light reflecting portions RF and RS. .
- the semiconductor device 30 since the first light reflecting portion RF is provided between the base substrate UK and the first mask 6, heat dissipation from the first light reflecting portion RF is improved, and the surface emitting semiconductor laser element is improved. 20 reliability is enhanced. In addition, the degree of freedom in designing (material, structure, etc.) of the base substrate UK and the first light reflecting portion RF is increased.
- FIG. 8 is a partially enlarged view of the semiconductor device of Example 1.
- the compound semiconductor portion 9 includes, from the bottom, an n-type semiconductor layer 9A as a first-type semiconductor layer, an active layer 9K, and a p-type semiconductor layer 9B as a second-type semiconductor layer.
- the active layer 9K has an MQW (Multi-Quantum Well) structure and includes, for example, at least one of InGaN and GaN.
- the n-type semiconductor layer 9A is, for example, an n-type AlGaN layer.
- the p-type semiconductor layer 9B is, for example, a p-type GaN layer.
- a first electrode E1, which is an anode, is provided so as to be in contact with the p-type semiconductor layer 9B.
- the semiconductor device 30 includes an insulating film KF located on the compound semiconductor portion 9, and the insulating film KF includes a first electrode E1, a first light reflecting portion RF, a second portion SD, and a second light reflecting portion RS in plan view. , including an aperture portion AP overlapping with .
- the first electrode E1 is a transparent electrode positioned between the compound semiconductor portion 9 and the second light reflecting portion RS, and is in contact with the upper surface of the insulating film KF. SiOx, SiNx, AlOx, or the like can be used for the insulating film KF.
- the first electrode E1 and the compound semiconductor portion 9 are in contact with each other. Specifically, the p-type semiconductor layer 9B exposed at the aperture portion AP and the central portion of the first electrode E1 are in contact with each other.
- the aperture part AP is a current constriction part formed by penetrating the insulating film KF, for example, in a circular shape. Increased.
- Example 1 the aperture portion AP overlaps the second light reflecting portion RS, the compound semiconductor portion 9, the second portion SD (low-defect portion) of the base semiconductor portion 8, and the first light reflecting portion RF in plan view. . Therefore, a current path from the first electrode E1 in the aperture portion AP to the base semiconductor portion 8 via the compound semiconductor portion 9 is formed in the base semiconductor portion 8 and the low-defect portion of the compound semiconductor portion 9 . Therefore, the luminous efficiency in the active layer 9K is enhanced, and heat generation in the base semiconductor portion 8 and the compound semiconductor portion 9 is suppressed.
- the semiconductor device 30 is provided with a first pad P1 in contact with the first electrode E1, and in plan view, the first pad P1, the aperture portion AP, and the second electrode E2 are arranged in the Y direction.
- the second electrode E2 can be formed on the second portion SD (low-defect portion) of the base semiconductor portion 8, and the luminous efficiency in the active layer 9K can be enhanced.
- the first pad P1 may be in contact with a part of the first electrode E1, but in order to inject the current more uniformly in the aperture part AP, the first pad P1 is in contact with the periphery of the first electrode E1 (
- the contact area with the first electrode E1 may have a shape such that it surrounds the aperture part AP in plan view.
- the first pad P1 may be circular.
- FIG. 9 is a partially enlarged view of the semiconductor device of Example 1.
- the first light reflector RF is located on the base substrate UK and can be an epitaxial DBR containing a nitride semiconductor.
- the first light reflecting portion RF has a plurality of pairs PF including a first refraction portion R1 and a second refraction portion R2 having a higher optical refractive index than the first refraction portion R1.
- the second refraction portion R2 may include a GaN-based semiconductor
- the first refraction portion R1 may include a refraction material (for example, a nitride semiconductor) having a lower optical refractive index than the GaN-based semiconductor of the second refraction portion R2.
- the seed portion 4 is provided between the first light reflecting portion RF and the first mask 6 .
- the upper surface of the first light reflecting portion RF is included in the first refraction portion R1
- the seed portion 4 containing, for example, a GaN-based semiconductor is formed on the first light reflecting portion RF.
- a first mask 6 is formed.
- the base semiconductor portion 8 located on the first mask 6 may have a higher optical refractive index than the mask portion 5 .
- the seed portion 4 may have a higher optical refractive index than the mask portion 5 and the first refractive portion R1.
- the light reflectance of the first light reflecting portion RF is increased, and the manufacturing process can be simplified. Moreover, the stress (tensile stress at room temperature) of the base semiconductor portion 8 is relaxed.
- the second light reflecting part RS is positioned on the first electrode E1 and can be a dielectric DBR containing a dielectric.
- the second light reflecting portion RS has a plurality of pairs PS each including a third refraction portion R3 and a fourth refraction portion R4 having a higher optical refractive index than the third refraction portion R3. and each of the third bend R3 and the fourth bend R4 comprises a dielectric material.
- the lower surface of the second light reflecting portion RS may be included in the third refraction portion R3, and the upper surface of the second light reflecting portion RS may be included in the fourth refraction portion R4.
- the third refraction portion R3 may have a lower optical refractive index than the p-type semiconductor layer 9B. By doing so, it is possible to increase the light reflectance of the second light reflecting portion RS. In addition, by providing the island-shaped second light reflecting portion RS on the first electrode E1, heat dissipation is enhanced.
- the semiconductor device 30 of Example 1 includes a gap TK in contact with the side surface of the base semiconductor portion 8, the side surface of the compound semiconductor portion 9, and the side surface of the second light reflection portion RS.
- the gap TK and the center 5C of the mask portion 5 overlap when viewed.
- Side surfaces of the base semiconductor portion 8 and the compound semiconductor portion 9 may each be an a-plane or an m-plane of a GaN-based semiconductor.
- FIG. 10 is a cross-sectional view showing a configuration example of the underlying substrate.
- the base substrate UK may be composed of a main substrate 1.
- the main substrate 1 may be, for example, a SiC substrate (6H—SiC bulk crystal), a GaN substrate (bulk crystal), An AlN substrate (bulk crystal) can be used.
- the base substrate UK may include a main substrate 1 and a base portion 3 positioned above the main substrate 1.
- the main substrate 1 is a SiC substrate and the base portion 3 is made of nitride.
- a semiconductor eg, GaN-based semiconductor
- an AlN substrate is used as the main substrate 1
- a nitride semiconductor eg, GaN-based semiconductor
- a Si substrate bulk crystal
- the base portion is used.
- Aluminum nitride (AlN) or silicon carbide (SiC) can be used for 3
- a GaN substrate can be used for main substrate 1
- GaN can be used for underlying portion 3
- the base substrate UK may include a main substrate 1, a buffer portion 2 positioned above the main substrate 1, and a base portion 3 positioned above the buffer portion 2.
- a SiC substrate or a Si substrate for the main substrate 1 using at least one of AlN (aluminum nitride) and SiC (silicon carbide) for the buffer portion 2, and using a nitride semiconductor (for example, a GaN-based semiconductor) for the underlying portion 3. can be used.
- AlN aluminum nitride
- SiC silicon carbide
- a nitride semiconductor for example, a GaN-based semiconductor
- FIG. 11 to 13 are cross-sectional views showing another configuration example around the first light reflecting portion.
- the upper surface of the first light reflecting portion RF is included in the second refraction portion R2, and the first mask 6 is formed on the first light reflecting portion RF.
- the uppermost second refraction portion R2 functions as a seed when the base semiconductor portion 8 grows laterally, and the base semiconductor portion 8 is formed in the opening portion K of the first mask 6 by the first light reflection portion R2. Contacts the top surface of the RF.
- the upper surface of the first light reflecting portion RF may be included in the first refraction portion R1, and the first mask 6 may be formed on the first light reflecting portion RF.
- the uppermost first bent portion R1 containing, for example, a nitride semiconductor functions as a seed when the base semiconductor portion 8 grows laterally, and the base semiconductor portion 8 is formed by the opening K of the first mask 6. in contact with the upper surface of the first light reflecting portion RF.
- the seed portion 4 is provided between the first light reflecting portion RF and the first mask 6 .
- the upper surface of the first light reflecting portion RF is included in the second refraction portion R2, and the seed portion 4 containing, for example, a nitride semiconductor is formed on the first light reflecting portion RF.
- a first mask 6 is formed. Further, by using the same material (for example, GaN-based semiconductor) for the uppermost layer or seed portion 4 of the first light reflecting portion RF and the base semiconductor portion 8, the manufacturing process can be simplified.
- FIG. 14 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to Example 1; 15A to 15D are process cross-sectional views showing an example of the method for manufacturing the semiconductor device according to the first embodiment.
- a step of preparing a base substrate UK a step of forming a first light reflection portion RF, a step of forming a seed portion 4, a step of forming a first mask 6, a step of forming a base semiconductor portion 8 by the ELO method, a step of forming a compound semiconductor portion 9, a step of forming an insulating film KF (current confinement layer), and first and second electrodes.
- a step of forming E1 and E2 and a step of forming the second light reflecting portion RS are included.
- a heterosubstrate having a lattice constant different from that of the base semiconductor section containing a GaN-based semiconductor can be used.
- hetero-substrates include single-crystal silicon (Si) substrates, sapphire (Al 2 O 3 ) substrates, silicon carbide (SiC) substrates, aluminum nitride (AlN) substrates, and the like.
- the plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H—SiC (0001) plane of a SiC substrate.
- the main substrate 1 may have higher thermal conductivity than the GaN bulk substrate.
- a SiC substrate may be adopted as the main substrate 1 from the viewpoint of being superior to the GaN substrate in thermal conductivity and translucency.
- a GaN substrate (bulk crystal) can also be used for the main substrate 1 (see FIG. 10).
- the underlying portion 3 or the buffer portion 2 including an AlN layer may be provided.
- the AlN layer can be formed with a thickness of about 10 nm to about 5 ⁇ m using, for example, an MOCVD apparatus.
- the buffer portion 2 may not be provided. is formed to a thickness of 1.0 ⁇ m using the MOCVD method.
- At least one of the buffer portion 2 (eg, aluminum nitride) and the underlying portion 3 (eg, GaN-based semiconductor) can also be formed using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).
- PLD pulse sputter deposition
- PLD pulse laser deposition
- the base semiconductor portion 8 When the base semiconductor portion 8 is grown laterally using the ELO method, even if an underlayer with poor crystallinity is used, the low crystallinity is inherited over the opening K (first portion HD), and the flat surface is formed.
- the second portion SD which visually overlaps the aperture portion AP and the light emitting region of the active layer 9K, does not take over (therefore, the second portion SD is a low-defect portion). Therefore, cost reduction can be achieved while maintaining light emission characteristics.
- the underlying portion 3 has the effect of preventing the melting of the main substrate 1 and the first light reflecting portion RF, the effect of increasing the crystallinity of the first light reflecting portion RF, and the effect of relieving the internal stress of the base semiconductor portion 8 (the effect of the semiconductor device 30). It may have at least one of the effect of alleviating warpage and the effect of increasing heat dissipation.
- the buffer portion 2 has the effect of preventing the melting of the main substrate 1 and the base portion 3, the effect of improving the crystallinity of the base portion 3, the effect of relieving the internal stress of the base semiconductor portion 8, and the effect of improving heat dissipation. You may have at least one.
- a GaN substrate can also be used for the main substrate 1.
- the first light reflecting portion RF epitaxial DBR
- the first light reflecting portion RF epitaxial DBR
- the first light reflecting portion RF epitaxial DBR
- the underlying portion 3 for example, a GaN layer
- a light reflecting portion RF epitaxial DBR
- the threading dislocations in the first light reflecting portion RF can be reduced, and the threading dislocations on the opening K in the base semiconductor portion 8 can be reduced.
- a base substrate in which a (11-22) plane GaN-based semiconductor layer is formed on a sapphire substrate or a base substrate in which a (20-21) plane GaN-based semiconductor layer is formed on a sapphire substrate may be used. good. Since the semiconductor layer epitaxially formed on the base substrate of these semipolar planes has high crystallinity, these base substrates can also be used in the first embodiment.
- Second light reflecting portion As shown in FIG. 9, by laminating 20 to 40 pairs containing AlN in the first refraction portion R1 and GaN in the second refraction portion R2, an epitaxial layer with high reflectance (96% or more) and high thermal conductivity can be obtained. A DBR can be formed. In this case, threading dislocations may occur due to lattice mismatch among the main substrate 1, the first bent portion R1, and the second bent portion R2. However, the first mask 6 prevents threading dislocations (defects extending in the Z direction) in the first light reflecting portion RF, and the second portion SD of the base semiconductor portion 8 and the compound semiconductor portion 9 thereabove (in particular, the aperture portion AP) ) are not inherited. As a result, the degree of freedom in designing the underlying substrate UK and the first light reflecting portion RF is increased, and it becomes possible to design in consideration of heat dissipation, crystal quality, power consumption, manufacturing cost, and the like.
- the thermal conductivity of the first light reflection part RF can be enhanced.
- the first mask 6 can alleviate stress propagation from the first light reflecting portion RF to the base semiconductor portion 8 and the compound semiconductor portion 9 .
- the first light reflecting portion RF can also be a lattice-matching epitaxial DBR such as AlInN (first refraction portion)/GaN (second refraction portion).
- the epitaxial DBR may be deposited using the MOCVD method, or may be deposited using the RPCVD (remote plasma chemical vapor deposition) method or the PSD (Pulse Sputter Deposition) method, which enables low-temperature deposition.
- RPCVD remote plasma chemical vapor deposition
- PSD Pulse Sputter Deposition
- the epitaxial DBR may be formed using a low temperature sputtering method or the like, and the seed portion 4 may be formed using the MOCVD method.
- Example 1 an undoped GaN layer of about 2 ⁇ m was formed as the underlayer 3 on a 6H—SiC (0001) substrate by a MOVPE (Metal Organic Vapor Phase Epitaxy) method. 30 pairs of 1 bent portion)/GaN (second bent portion) were laminated at a growth temperature of 1040° C. and a growth pressure of 50 Torr to form an epitaxial DBR.
- the design peak wavelength of the DBR is 400 nm, and the optical film thickness of AlN in one pair is ⁇ /4. This made it possible to obtain the first light reflecting portion RF with a high light reflectance of about 98%.
- the uppermost portion of the first light reflecting portion RF may be used as the first refraction portion (AlN), and a seed portion 4 containing a GaN-based semiconductor may be provided thereon.
- the uppermost portion of one light reflecting portion RF may be the second refraction portion (GaN).
- the refractive material of the first refractive portion R1 may be AlN, AlInN, or InN.
- the refractive material (eg, AlN) of the first refraction portion R1 may have a higher thermal conductivity than the GaN-based semiconductor (eg, GaN) of the second refraction portion R2.
- the refractive material of the first refraction portion R1 may have a lattice constant different from that of the GaN-based semiconductor of the second refraction portion R2.
- the refractive material (for example, AlN) of the first refraction portion R1 may have a smaller lattice constant than the GaN-based semiconductor (for example, GaN) of the second refraction portion R2.
- the main material of the main substrate 1 eg, SiC, Si
- the GaN-based semiconductor eg, GaN
- the refraction material of the first refraction portion R1 eg, AlN
- the opening K of the first mask 6 exposes the nitride semiconductor functioning as a seed and functions as a growth start hole for starting the growth of the base semiconductor portion 8 . It has the function of a selective growth mask for lateral growth.
- the mask portion 5 includes, for example, a silicon oxide film (SiO x ), a titanium nitride film (TiN, etc.), a silicon nitride film (SiN x ), a silicon oxynitride film (SiON), and a high melting point (for example, 1000° C. or higher).
- a single layer film containing any one of the metal films, or a laminated film containing at least two of these can be used.
- a silicon oxide film having a thickness of about 10 nm to about 500 nm is formed on the entire surface using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film.
- the resist is patterned by photolithography to form a resist having a plurality of striped openings.
- a portion of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings K, and the resist is removed by organic cleaning to remove the first mask 6. is formed.
- the opening K may be formed using a general lift-off method.
- the openings K have a longitudinal shape (slit shape) and are periodically arranged in the a-axis direction (X direction) of the base semiconductor portion 8 .
- the width of the opening K (opening width) can be about 0.1 ⁇ m to 20 ⁇ m (for example, about 5 ⁇ m). As the width of each opening decreases, the number of threading dislocations propagating from each opening to the base semiconductor portion 8 decreases. Also, the second portion (low-defect portion) SD can be increased.
- the thickness of the mask portion 5 is preferably thin from the viewpoint of heat radiation, but is set to 10 nm or more, 20 nm or more, or 40 nm or more in consideration of suppression of mutual reaction between the first mask 6 and the base semiconductor portion 8. be able to.
- the width of the mask portion 5 can be 10 ⁇ m to 200 ⁇ m.
- the area (effective area) of the second portion SD (low defect portion) of the base semiconductor portion 8 can be increased.
- the aperture diameter (aperture diameter of the aperture portion AP) can be increased, and a high-output semiconductor laser device can be realized.
- the silicon oxide film decomposes and evaporates in a very small amount during the film formation of the base semiconductor portion 8 and may be incorporated into the base semiconductor portion 8, the silicon nitride film and the silicon oxynitride film decompose and evaporate at high temperatures. It has the advantage of being difficult.
- the first mask 6 may be a single layer film of a silicon nitride film or a silicon oxynitride film, a laminated film formed by forming a silicon oxide film and a silicon nitride film in this order, or a silicon nitride film and a silicon oxide film.
- a laminate film in which films are formed in this order, or a laminate film in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are formed in this order may be used.
- Abnormal portions such as pinholes in the mask portion 5 can be eliminated by performing organic cleaning after film formation, introducing the film into the film forming apparatus again, and forming the same type of film.
- a general silicon oxide film (single layer) can also be used to form a high-quality first mask 6 using such a re-deposition method.
- the mask portion 5 may have a smaller optical refractive index than the second refraction portion R2 (for example, GaN-based semiconductor).
- the first mask 6 since the first mask 6 exists in the cavity, the first mask 6 can be designed so as not to disturb the resonance of light as much as possible. Since the mask portion 5 is a selectively grown film and also a light transmitting film, it may have high light transmission characteristics (low light absorption).
- the uppermost portion (second refraction portion R2) of the first light reflection portion RF or the seed portion 4 is a GaN layer, and a single layer of silicon oxide film or silicon nitride film having a lower refractive index than GaN is used as the mask material,
- the optical film thickness (physical film thickness/refractive index) of the silicon oxide film or silicon nitride film is set to an integral multiple of ⁇ (oscillation wavelength)/2
- the reflectance at the first light reflecting portion RF can be increased.
- a mask material composed of a plurality of film types, each of which has an optical film thickness that is an integral multiple of ⁇ /2 may be used.
- the uppermost portion (second refraction portion R2) of the first light reflecting portion RF or the seed portion 4 is a GaN layer
- a silicon oxide film and a silicon nitride film having a higher refractive index than this are formed on the GaN layer.
- the films may all be formed in this order with an optical film thickness of ⁇ /4.
- Example 1 a GaN layer was used as the base semiconductor portion 8 (ELO semiconductor layer), and an ELO film of gallium nitride (GaN) was formed on the aforementioned template substrate using an MOCVD apparatus.
- the base semiconductor portion 8 is selectively grown (vertically grown) on the seed portion 3 (eg, GaN layer) exposed in the opening K, and subsequently grown laterally on the mask portion 5 . Then, the lateral growth was stopped before the base semiconductor portion 8 growing laterally from both sides of the mask portion 5 joined together.
- a single silicon nitride film was used for the mask portion 5, and the optical film thickness of the mask portion 5 was set to ⁇ /4, assuming an emission wavelength of 450 nm.
- the width of the mask portion 5 is 50 ⁇ m
- the width of the opening K is 5 ⁇ m
- the width of the gap TK is 3 ⁇ m
- the width of the base semiconductor portion 8 is 52 ⁇ m
- the width of the low defect portion (size in the X direction) is 23.5 ⁇ m
- the layer thickness of the portion 8 was 5 ⁇ m.
- the width (effective width) of the low defect portion SD may be 10 ⁇ m or more or 20 ⁇ m or more.
- the lateral film formation rate is increased.
- a technique for increasing the lateral film formation rate is as follows. First, a vertical growth layer growing in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the opening K, and then a lateral growth layer growing in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertical growth layer to 10 ⁇ m or less, preferably 5 ⁇ m or less, and more preferably 3 ⁇ m or less, the thickness of the horizontal growth layer can be kept low and the horizontal film formation rate can be increased.
- FIG. 16 is a cross-sectional view showing an example of lateral growth of the base semiconductor portion 8.
- an initial growth layer SL is formed on the seed portion 3, and then the base semiconductor portion 8 can be laterally grown from the initial growth layer SL.
- the initial growth layer SL serves as a starting point for lateral growth of the base semiconductor portion 8 .
- the initial growth is performed immediately before the edge of the initial growth layer SL climbs over the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or immediately after it climbs over the upper surface of the mask portion 5.
- the film formation of the layer SL may be stopped (that is, at this timing, the ELO film formation conditions may be switched from the c-axis direction film formation conditions to the a-axis direction film formation conditions).
- consumption of material for growth in the thickness direction of the base semiconductor portion 8 can be reduced.
- the semiconductor portion 8 can be laterally grown at high speed.
- the initial growth layer SL may be formed with a thickness of, for example, 2.0 ⁇ m or more and 3.0 ⁇ m or less.
- the film forming temperature of the base semiconductor portion 8 may be a high temperature exceeding 1200°C, but may be 1150°C or less. It is possible to form the ELO semiconductor portion even at a low temperature of less than 1000° C., which is preferable from the viewpoint of reducing mutual reaction.
- TMG trimethylgallium
- the raw material is not sufficiently decomposed, and gallium atoms and carbon atoms are simultaneously incorporated into the ELO semiconductor portion in a larger amount than usual. .
- film formation in the a-axis direction is fast and film formation in the c-axis direction is slow.
- the carbon incorporated into the ELO semiconductor portion reduces the reaction with the mask portion 5 and reduces adhesion between the mask portion 5 and the ELO semiconductor portion (base semiconductor portion 8). Therefore, in the low-temperature film formation of the ELO semiconductor part, the supply amount of ammonia is reduced and the film is formed at a low V/III ( ⁇ 1000) level. Reaction with the part 5 can be reduced.
- the base semiconductor portion 8 is configured to contain carbon.
- FIG. 17 is a plan view showing another configuration of the semiconductor device of Example 1.
- the lateral growth of the base semiconductor portion 8 laterally growing from both sides of the mask portion 5 is stopped before the base semiconductor portions 8 meet, but the present invention is not limited to this.
- the lateral growth of base semiconductor portions 8 may be stopped after the base semiconductor portions 8 growing laterally from both sides of the mask portion 5 meet.
- the base semiconductor portion 8 includes a void VD that overlaps the center of the mask portion 5 in plan view, and dislocations (crystal defects) at the meeting portion increase. It is configured so that it does not overlap with the meeting part.
- the base semiconductor portion 8 and the compound semiconductor portion 9 may be continuously formed by the same device (for example, MOCVD device).
- the compound semiconductor portion 9 may be formed after the step. In this case, after forming an n-type GaN-based semiconductor layer (for example, about 0.1 ⁇ m to about 3 ⁇ m thick) to serve as a buffer during re-growth on the base semiconductor portion 8, the compound semiconductor portion 9 is formed.
- a sputtering apparatus, a remote plasma CVD apparatus (RPCVD), a PSD (Pulse Sputter Deposition) apparatus, or the like can be used. Since the remote plasma CVD apparatus and the PSD apparatus do not use hydrogen as a carrier gas, a p-type GaN-based semiconductor portion with low resistance can be formed.
- the MQW structure of the active layer 9K can be, for example, a structure of 5 to 6 periods of InGaN/GaN.
- the In composition differs depending on the target emission wavelength. For blue (around 450 nm), the In concentration can be about 15-20%, and for green (about 530 nm), the In concentration can be about 30%.
- An electron blocking layer eg, AlGaN layer
- the surface (about 10 nm) of the p-type semiconductor layer 9B may be made into a p-type highly doped layer.
- FIG. 18 is a cross-sectional view showing another configuration of the semiconductor device of Example 1.
- the insulating film KF is provided with the aperture portion AP in FIG. 8, the present invention is not limited to this.
- the p-type semiconductor layer 9B is provided with an annular high-resistance portion HR (a region with a low p-type doping concentration), and the inner side of the high-resistance portion HR is an aperture portion AP (current confinement portion) (high resistance portion HR).
- a configuration in which the resistor portion HR surrounds the aperture portion AP) may also be used.
- the aperture portion AP can also be formed by implanting Al (aluminum) or Fe (iron).
- the periphery of the aperture is dug to generate a refractive index difference between the aperture portion AP and its periphery (for example, the aperture portion AP is made to have a different refractive index than the aperture portion AP). to reduce the refractive index around it).
- the first electrode E1 is made of a transparent conductive material having optical transparency.
- transparent conductive materials include indium tin oxide (including crystalline ITO, amorphous ITO, and Sn-doped In 2 O 3 ), indium zinc oxide (IZO), IFO (F-doped In 2 O 3 ), tin oxide (including SnO 2 , Sb-doped SnO 2 and F-doped SnO 2 ), zinc oxide (including ZnO, AI-doped ZnO and B-doped ZnO).
- the first electrode E1 may include at least one of Ga (gallium) oxide, Ti (titanium) oxide, Nb (niobium) oxide, and Ni (nickel) oxide as a mother layer.
- the aperture diameter of the first electrode E1 (the diameter of the current injection region in contact with the p-type semiconductor portion) can be, for example, 2 ⁇ m or more and 100 ⁇ m or less.
- the first pad P1 in contact with the first electrode E1 is, for example, a single layer containing at least one of Au, Ag, Pd, Pt, Ni, Ti, V, W, Cr, Al, Cu, Zn, Sn and In. It may be a structure or a multi-layer structure. Regarding the multilayer structure, for example, with the left side as the lower layer side, Ti layer/Au layer, Ti layer/Al layer, Ti layer/Al layer/Au layer, Ti layer/Pt layer/Au layer, Ni layer/Au layer, Ni A configuration such as layer/Au layer/Pt layer, Ni layer/Pt layer, Pd layer/Pt layer, Ag layer/Pd layer, or the like can be employed.
- the second light reflecting portion RS is, for example, a DBR in which third refraction portions R3 and fourth refraction portions R4 are alternately stacked as shown in FIG.
- the third bending portion R3 contains, for example, SiO2 .
- the fourth refraction portion R4 is a layer containing a material having a higher refractive index than the third refraction portion R3, such as Ta2O5 , HfO2 , ZrO2 , TiO2 , Al2O3 , Nb2O . 5 , ZnO, AlN, SiN or MgO.
- Light incident on the interface between the third refraction portion R3 and the fourth refraction portion R4 at an angle equal to or greater than the critical angle is totally reflected at this interface. % or more) is realized.
- the second light reflecting portion RS when the main substrate 1 is translucent, the second light reflecting portion RS may have a reflectance of approximately 100%, for example, approximately 99% with respect to the emission wavelength of the active layer 9K.
- the first light reflecting portion RF may have a reflectance lower than that of the second light reflecting portion RS, for example, a reflectance of about 98%.
- the light traveling back and forth between the first light reflecting portion RF and the second light reflecting portion RS is emitted as laser light from the lower surface of the first light reflecting portion RF (the portion overlapping the aperture portion AP in plan view).
- the configuration is not limited to that the laser light is emitted from the first light reflecting portion RF side. If the main substrate 1 is not translucent, the laser light may be emitted from the second light reflecting portion RS side, or the laser light may be emitted from each of the first and second light reflecting portions RF and RS.
- (Singulation) 19 is a plan view showing another configuration of the semiconductor device of Example 1.
- FIG. 19 the semiconductor device 30 of FIG. 7 may be separated into a plurality of semiconductor devices 30 each including one semiconductor laser element 20 .
- FIG. 20 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1.
- the semiconductor device 30 includes a circuit board CB arranged on the opposite side of the main substrate 1 and electrically connected to the first and second electrodes E1 and E2.
- the first electrode E1 is connected to the circuit board via the first pad P1 and the conductive adhesive A1
- the second electrode E2 is connected to the circuit board CB via the conductive adhesive A2.
- a configuration in which the circuit board CB drives the semiconductor laser element 20 may also be used.
- FIG. 21 and 22 are cross-sectional views showing another configuration of the semiconductor device according to Example 1.
- FIG. A semiconductor device 30 shown in FIG. 21 includes a first pad P1 in contact with a first electrode E1 and a second pad P2 in contact with a second electrode E2. height positions) match each other, and the upper surfaces of the first and second pads P1 and P2 are positioned higher than the upper surface of the second light reflecting portion RS. This facilitates mounting on the circuit board CB (see FIG. 22).
- An insulating film DF can be provided between the peripheral portion of the second electrode E2 and the base semiconductor portion 8 .
- the second electrode E2 may have a shape in which the non-peripheral edge portion EH is recessed from the peripheral edge portion, and the recessed non-peripheral edge portion EH may be filled with the insulator DL.
- the insulator DL can planarize the top surface of the second pad P2. Further, heat dissipation can be enhanced by bringing the first pad P1 into contact with the upper surface of the second light reflecting portion RS.
- FIG. 23 and 24 are cross-sectional views showing another configuration of the semiconductor device according to Example 1.
- FIG. 23 and 24 are cross-sectional views showing another configuration of the semiconductor device according to Example 1.
- the seed portion 4 is formed entirely on the first light reflecting portion RF in FIG. 5 and the like, the present invention is not limited to this.
- the seed portion 4 may be locally provided so as to overlap with the opening K of the first mask 6 .
- the uppermost portion of the first light reflecting portion RF is referred to as the second refraction portion R2
- the uppermost portion of the first light reflecting portion RF is referred to as the first refraction portion R1.
- the seed portion 4 may be formed at a low temperature of 800° C. or lower.
- FIG. 25 and 26 are cross-sectional views showing another configuration of the semiconductor device according to Example 1.
- the second electrode E2 may be in contact with the seed portion 4 as shown in FIG.
- the seed portion 4 can be, for example, an n-type GaN-based semiconductor layer.
- the second electrode E2 may be in contact with the uppermost portion of the first light reflecting portion RF (for example, the second bending portion R2).
- the uppermost portion of the first light reflecting portion RF can be, for example, an n-type GaN-based semiconductor layer.
- FIG. 27 is a plan view showing another configuration of the semiconductor device according to Example 1.
- the first and second electrodes E1 and E2 may be arranged in the X direction, and the second electrode E2 may overlap the first portion HD in plan view. Note that the first electrode E1 and the aperture portion AP overlap the second portion SD in plan view.
- FIG. 28 is a plan view showing another configuration of the semiconductor device according to Example 1.
- FIG. A semiconductor device 30 of FIG. 28 has a first region L1 and a second region L2 having the same area and adjacent to each other in the X direction with an air gap TK interposed therebetween. is different.
- a plurality of two semiconductor laser elements 20 are arranged in the Y direction in the first area L1, and a plurality of six semiconductor laser elements 20 are arranged in the Y direction in the second area L2.
- the aperture diameter of the semiconductor laser device 20 in the first region L1 is larger than the aperture diameter of the semiconductor laser device 20 in the second region L2.
- the aperture portion AP and the first pad P1 are arranged in the Y direction, the Y direction being the longitudinal direction, and the second electrode E2 in contact with the base semiconductor portion 8 and the first electrode E2.
- Pads P1 are arranged in the X direction.
- the aperture portion AP and the first pad P1 are arranged in the X direction, the X direction is the longitudinal direction, and the second electrode E2 in contact with the base semiconductor portion 8 and the first electrode E2
- An aperture portion AP is positioned between the pad P1.
- FIG. 29 and 30 are schematic plan views showing another configuration of the semiconductor device according to Example 1.
- FIG. A semiconductor device 30 of FIG. 29 is obtained by mounting a plurality of semiconductor devices shown in FIG. 19 on a circuit board CB.
- the semiconductor device 30 of FIG. 30 is obtained by dividing the semiconductor device 30 of FIG. 28 into regions and mounting a plurality of semiconductor devices obtained from the second region L2 on the circuit board CB.
- FIG. 31 is a cross-sectional view showing the configuration of a semiconductor device according to Example 2.
- FIG. The semiconductor device 30 of Example 2 includes, for example, a base substrate UK shown in FIG. 10, the first light reflecting portion RF is located on the base substrate UK, and the base substrate UK has a concave portion UT that is open on the top surface.
- FIG. 32 to 35 are cross-sectional views showing the configuration of the base substrate according to Example 2.
- the main substrate 1 may be recessed at a portion corresponding to the recess UT.
- the base substrate UK may include a base portion 3 positioned above the main substrate 1, and the base portion 3 may be pierced at a portion corresponding to the recess UT.
- the base substrate UK includes a buffer portion 2 and a base portion 3 positioned above the main substrate 1, and the base portion 3 may be recessed at a portion corresponding to the recess UT. .
- FIG. 34 the base substrate UK includes a buffer portion 2 and a base portion 3 positioned above the main substrate 1, and the base portion 3 may be recessed at a portion corresponding to the recess UT.
- the base substrate UK includes a buffer portion 2 and a base portion 3 located above the main substrate 1, and the main substrate 1 is recessed in a portion corresponding to the recess UT, and the buffer portion 2 And the underlying portion 3 may be penetrated at a portion corresponding to the concave portion UT.
- the recess UT is formed in a stripe shape extending in the Y direction, and has a width (size in the X direction) of, for example, 3 ⁇ m and a depth (size in the Z direction) of, for example, 5 ⁇ m.
- the second light reflecting portion RS does not overlap the concave portion UT in plan view.
- the first and second refracting portions R1 and R2 of the first light reflecting portion RF have a U-shaped portion UC along the concave portion UT, and the U-shaped portion UC overlaps the center of the mask portion 5 in plan view.
- the semiconductor device 30 of Example 2 has the gap TK in contact with the side surfaces of the compound semiconductor portion 9 and the base semiconductor portion 8, and the gap TK and the recess UT overlap in plan view.
- the air gap TK is in contact with the side surface 5S of the mask part 5 and the side surface 4S of the seed part 4, and the U-shaped part UC (of the second refraction part R2) located at the top of the first light reflecting part RF is in contact with the air gap TK.
- the U-shaped portion UC (of the first refraction portion R1) positioned at the top of the first light reflection portion RF may be in contact with the air gap TK.
- Example 3 36 is a cross-sectional view showing the configuration of a semiconductor device according to Example 3.
- FIG. 37 is a cross-sectional view showing the configuration of a semiconductor device according to Example 3.
- the second electrode E2 is provided on the back surface of the underlying substrate UK.
- the base substrate UK for example, an n-type doped main substrate 1 (eg, SiC substrate, Si substrate) can be used.
- the base portion 3 is an n-type semiconductor layer (for example, a GaN-based semiconductor). (for example, a nitride semiconductor).
- Each epitaxial layer (eg, nitride semiconductor) of the first light reflecting portion RF and the seed portion 4 are also n-type semiconductor layers.
- FIG. 38 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the fourth embodiment.
- 39 to 40 are cross-sectional views showing the configuration of a semiconductor device according to Example 4.
- the base substrate UK has a main substrate 1 and a second mask MS located above the main substrate 1 .
- the step of preparing the main substrate 1 the step of forming the second mask MS and the step of forming the underlying portion 3 by the ELO method are performed. That is, the semiconductor device 30 shown in FIGS. 39 to 40 has the underlying portion 3 formed by the ELO method.
- a buffer section 2 may be provided between the main substrate 1 and the second mask MS.
- the main substrate 1 is a SiC substrate
- the buffer section 2 is a GaN-based semiconductor layer
- the second mask MS is a single-layer film or silicon nitride film containing at least one of a silicon oxide film and a silicon nitride film.
- a multi-layered film can be used, and the underlying portion 3 can be a GaN-based semiconductor layer formed by the ELO method.
- the second mask MS includes a mask portion M and an opening Q.
- the opening K of the first mask 6 and the opening Q of the second mask MS overlap in plan view.
- the gap TK of the base semiconductor portion 8 and the opening portion Q of the second mask MS may overlap in plan view.
- FIG. 41 is a flow chart showing another example of the semiconductor device manufacturing method according to the fourth embodiment.
- FIG. 42 is a cross-sectional view showing another configuration of the semiconductor device according to the fourth embodiment.
- the semiconductor device 30 of FIG. 42 has the first light reflecting portion RF formed at the bottom by the ELO method.
- Example 4 since the underlying portion 3 or the lowermost portion of the first light reflecting portion RF (epitaxial DBR) is formed by the ELO method, dislocations (defects) in the first light reflecting portion RF are reduced, and light reflectance is improved. can be enhanced.
- Example 5 an epitaxial DBR of InAlN (first bent portion R1)/GaN (second bent portion R2) is formed.
- the base substrate UK is placed in the reactor of the MOCVD apparatus, H 2 and NH 3 are supplied into the reactor, the substrate temperature is raised to 1070° C., and then TMG is supplied to the base substrate UK. Then, a 100 nm GaN layer as the buffer portion 2 is epitaxially grown.
- the supply gas is switched from H 2 to N 2 and TMI and TMA are supplied to form a non-doped InAlN layer (first bending portion R1). was grown to 50 nm.
- a Si-doped GaN layer was grown to 5 nm as the first layer of the second bending portion R2. Subsequently, the supply gas was switched from N 2 to H 2 , the substrate temperature was raised to 1070° C. (second temperature), and TMG was supplied to obtain non-doped GaN as the second layer of the second refraction portion R2. The layer was grown 40 nm. After that, the above steps were repeated to form an epitaxial DBR composed of 40 pairs of InAlN/GaN.
- the first light reflecting portion RF made of InAlN/GaN lattice-matched with the base semiconductor portion 8 for example, a GaN layer
- a GaN substrate bulk crystal
- the threading dislocation density on the openings K of the first mask 6 can be suppressed to about 5 ⁇ 10 6 cm ⁇ 2 or less, and the apertures AP can be formed on the openings K as well.
- Example 6 the first light reflecting portion RF (epitaxial DBR) is formed by the PSD method.
- the PSD method all or part of the elements for forming the compound epitaxial layer are intermittently supplied.
- group III-V nitrides generally all group III elements can be intermittently supplied.
- the group element may be fed continuously (preferably at a slow feed rate).
- the N element when nitrogen is supplied as a gas, it exists in the vicinity of the substrate growth surface in a gaseous state (molecules, radicals, ions), so it is not necessary to intentionally supply it intermittently.
- the N element can also be supplied intermittently by intermittently exciting (sputtering) a raw material containing N, such as a group III-V nitride.
- the group V element may be supplied by intermittently exciting a source material, or may be supplied by allowing the group V element source material to exist in the atmosphere, or simultaneously supplying another source material while allowing the group V element source material to exist in the atmosphere. may be intermittently excited and supplied.
- the timing of supplying the plurality of elements may or may not be the same.
- the supply duration time if it is too short, in order to obtain a practical film formation speed, a large amount of energy is instantaneously applied to increase the supply speed during the supply period, and as a result, as in the PLD method, droplets becomes more likely to occur.
- the supply continuation time if the supply continuation time is too long, it may not be possible to take a supply stop time that allows sufficient migration.
- the supply stop time if it is too short, the time for migration will be insufficient, making it difficult to obtain good crystals. continuation becomes difficult.
- Example 6 1.0 sccm of Ar gas and 4.0 sccm of nitrogen gas were introduced as atmosphere gases by a mass flow controller, and the growth pressure was set to 2 ⁇ 10 ⁇ 2 Torr.
- the SiC substrate is electrically grounded, the voltage applied between the SiC substrate and the Ga metal target is ⁇ 600 V, the voltage application time is 5 ⁇ sec, and the voltage application is paused for 95 ⁇ sec.
- the voltage applied was ⁇ 557 V, the voltage application time was 5 ⁇ sec, and the voltage application was paused for 50 ⁇ sec, and this was repeated.
- Sputtering discharge is started by temporarily increasing the amount of Ar gas introduced into the growth chamber, and after confirming that the amount of Ar gas and the growth pressure are stabilized at the above-described set values, each shutter is opened to perform the second step.
- a GaN layer which is the refraction portion R2, can be formed.
- the growth temperature was 350°C.
- An AlN layer, which is the first bent portion R1 can be formed by using an Al target in a similar manner.
- the base semiconductor portion 8 can be made of GaN, but the base semiconductor portion 8 may be made of InGaN, which is a GaN-based semiconductor. Lateral deposition of InGaN is performed at a low temperature, eg, below 1000°C. This is because, at high temperatures, the vapor pressure of indium increases and it is not effectively incorporated into the film. Lowering the film formation temperature has the effect of reducing the mutual reaction between the mask portion 5 and the base semiconductor portion 8 . InGaN also has the effect of being less reactive with the mask portion 5 (silicon oxide film, silicon nitride film, etc.) than GaN. When the base semiconductor portion 8 incorporates indium at an In composition level of 1% or more, the reactivity with the mask portion 5 is further reduced. Triethylgallium (TEG) can be used as the gallium source gas.
- TAG Triethylgallium
- Example 8 43 and 44 are cross-sectional views showing another configuration of the semiconductor device according to the eighth embodiment.
- the wavelength conversion part HS may be provided below (back side) the base substrate UK.
- white illumination can be achieved by disposing a general YAG phosphor that emits yellow light as the wavelength conversion unit HS.
- a red-emitting phosphor HR is arranged so as to overlap the aperture portion AP of the red sub-pixel semiconductor laser element 20 in plan view
- a phosphor HG emitting green light is arranged so as to overlap the aperture portion AP of the semiconductor laser element 20 for the green sub-pixel in plan view, and so as to overlap the aperture portion AP of the semiconductor laser element 20 for the blue sub-pixel in plan view.
- the semiconductor device 30 for a laser display device can be realized by arranging the phosphor HB that emits blue light.
- FIG. 45 is a cross-sectional view showing another configuration of the semiconductor device according to the ninth embodiment.
- a photonic crystal layer is used for the first light reflecting portion RF.
- the first light reflecting portion RF which is a photonic crystal layer, has, for example, a fifth refraction portion R5 and a sixth refraction portion R6 having a higher refractive index than the fifth refraction portion R5, which are two-dimensional (XY plane). It has an arranged structure.
- the fifth bending portion R5 may be a hole having a diameter of several tens to several hundreds of nanometers formed in the base layer in the form of lattice points.
- the base layer may be a nitride semiconductor layer.
- the lattice pitch can be about the emission wavelength of the compound semiconductor portion 9 (for example, 200 to 400 nm).
- a first light reflecting portion RF photonic crystal layer
- a base substrate UK for example, a GaN substrate
- a counter substrate SK is formed on the first light reflecting portion RF.
- the first mask 6 may be provided on the counter substrate SK with the seed portion 4 interposed therebetween. If the counter substrate SK is a GaN substrate, the first mask 6 may be provided on the counter substrate SK.
- the first mask 6 may be provided on the first light reflecting portion RF (photonic crystal layer) via the seed portion 4 without providing the counter substrate SK, or the first light reflecting portion RF (photonic crystal layer) may be provided.
- a first mask 6 may be provided on the crystal layer). It is known that when a photonic crystal is formed, the crystallinity of the upper layer is lowered. , a compound semiconductor portion 9 with high luminous efficiency can be obtained.
- FIG. 46 is a schematic diagram showing the configuration of an electronic device according to the tenth embodiment.
- the electronic equipment 40 of FIG. 46 includes the semiconductor device 30 of Examples 1 to 9, and a control section 80 including a processor that controls the semiconductor device 30 .
- Examples of the electronic device 40 include a communication device, an optical device, a display device, a lighting device, a sensor device, an information processing device, a medical device, an electric vehicle (EV), and the like.
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Abstract
Description
図1は、本実施形態に係る半導体デバイスの構成を示す断面図である。図1に示すように、本実施形態に係る半導体デバイス30は、下地基板UKと、下地基板UKの上方に位置する第1光反射部RFと、第1光反射部RFよりも上方に位置する第1マスク6と、第1マスク6よりも上方に位置するベース半導体部8と、ベース半導体部8よりも上方に位置する化合物半導体部9と、化合物半導体部9および第1光反射部RFの上方に位置する第2光反射部RSと、を備える。
図3は、本実施形態に係る半導体デバイスの製造方法の一例を示すフローチャートである。図3の半導体デバイスの製造方法では、下地基板UKを準備する工程と、第1光反射部RFを形成する工程と、第1マスク6を形成する工程と、ELO法を用いてベース半導体部8を形成する工程と、化合物半導体部9を形成する工程と、第2光反射部RSを形成する工程とを含む。
(全体構成)
図5は、実施例1に係る半導体デバイスの、X方向に沿った断面図である。図6は、実施例1に係る半導体デバイスの、Y方向に沿った断面図である。図7は、実施例1に係る半導体デバイスの平面図である。図5、図6および図7に示すように、実施例1に係る半導体デバイス30は、下地基板UKと、下地基板UK上に位置する第1光反射部RFと、第1光反射部RF上に位置するシード部4と、シード部4上に位置し、マスク部5および開口部Kを含む第1マスク6と、第1マスク6上に位置するベース半導体部8と、ベース半導体部8上に位置する化合物半導体部9と、化合物半導体部9上に位置する絶縁膜KFと、化合物半導体部9上に位置する第1電極E1と、ベース半導体部8上に位置する第2電極E2と、第1電極E1上に位置する第2光反射部RSとを備える。ベース半導体部8および化合物半導体部9は、窒化物半導体(例えば、GaN系半導体)を含んでいてもよい。X方向はベース半導体部8の<11-20>方向、Y方向はベース半導体部8の<1-100>方向、Z方向はベース半導体部8の<0001>方向である。
図14は、実施例1に係る半導体デバイスの製造方法の一例を示すフローチャートである。図15は、実施例1に係る半導体デバイスの製造方法の一例を示す工程断面図である。図14および図15に示すように、半導体デバイスの製造方法では、下地基板UKを準備する工程と、第1光反射部RFを形成する工程と、シード部4を形成する工程と、第1マスク6を形成する工程と、ELO法でベース半導体部8を形成する工程と、化合物半導体部9を形成する工程と、絶縁膜KF(電流狭窄層)を形成する工程と、第1および第2電極E1・E2を形成する工程と、第2光反射部RSを形成する工程とを含む。
下地基板UKの主基板1には、例えばGaN系半導体を含むベース半導体部と異なる格子定数を有する異種基板を用いることができる。異種基板としては、単結晶のシリコン(Si)基板、サファイア(Al2O3)基板、シリコンカーバイド(SiC)基板、窒化アルミニウム(AlN)基板等を挙げることができる。主基板1の面方位は、例えば、シリコン基板の(111)面、サファイア基板の(0001)面、SiC基板の6H-SiC(0001)面である。
図9に示すように、第1屈折部R1にAlN、第2屈折部R2にGaNを含むペアを、20~40ペア積層することで、高反射率(96%以上)かつ高熱伝導率のエピタキシャルDBRを形成することができる。この場合、主基板1、第1屈折部R1、および第2屈折部R2の格子不整合等に起因する貫通転位が生じる場合がある。しかし、第1マスク6によって第1光反射部RFの貫通転位(Z方向に伸びる欠陥)が止められ、ベース半導体部8の第2部分SDおよびその上部の化合物半導体部9(特に、アパーチャー部APと重なる部分)には引き継がれない。これにより、下地基板UKおよび第1光反射部RFの設計の自由度が上がり、放熱性、結晶品質、消費電力、製造コスト等を考慮した設計が可能となる。
第1マスク6の開口部Kは、シードとして機能する窒化物半導体を露出させ、ベース半導体部8の成長を開始させる成長開始用ホールの機能を有し、マスク部5は、ベース半導体部8を横方向成長させる選択成長用マスクの機能を有する。マスク部5として、例えば、シリコン酸化膜(SiOx)、窒化チタン膜(TiN等)、シリコン窒化膜(SiNx)、シリコン酸窒化膜(SiON)、および高融点(例えば1000℃以上)をもつ金属膜のいずれか1つを含む単層膜、またはこれらの少なくとも2つを含む積層膜を用いることができる。
実施例1では、ベース半導体部8(ELO半導体層)をGaN層とし、MOCVD装置を用いて前述のテンプレート基板上に窒化ガリウム(GaN)のELO成膜を行った。ELO成膜条件の一例として、基板温度:1120℃、成長圧力:50kPa、TMG(トリメチルガリウム):22sccm、NH3:15slm、V/III=6000(III族原料の供給量に対する、V族原料の供給量の比)を採用することができる。
ベース半導体部8および化合物半導体部9は、同一装置(例えば、MOCVD装置)で連続形成してもよいし、ベース半導体部8形成後に一旦基板を装置から取り出し、ベース半導体部8の表面研磨等を行った後に化合物半導体部9を形成してもよい。この場合、ベース半導体部8上に、再成長の際のバッファとなるn型のGaN系半導体層(例えば、厚さ0.1μm程度~3μm程度)を形成した後に、化合物半導体部9を形成してもよい。化合物半導体部9の形成には、MOCVD装置のほか、スパッタ装置、リモートプラズマCVD装置(RPCVD)、PSD(Pulse Sputter Deposition)装置等を用いることができる。リモートプラズマCVD装置、PSD装置では、水素をキャリアガスとして用いないため、低抵抗のp型GaN系半導体部を形成することができる。
第1電極E1は、光透過性を有する透明導電性材料によって形成されている。透明導電性材料としては、例えば、インジウム錫酸化物(結晶性ITO,アモルファスITO,SnドープのIn2O3を含む)、インジウム亜鉛酸化物(IZO:Indium Zinc Oxide)、IFO(FドープのIn2O3)、酸化錫(SnO2、SbドープのSnO2、FドープのSnO2を含む)、酸化亜鉛(ZnO,AIドープのZnO,BドープのZnOを含む)をあげることができる。
第2光反射部RSは、例えば、図8に示すように、第3屈折部R3と第4屈折部R4とが交互に積み重ねられたDBRである。第3屈折部R3は、例えば、SiO2等を含む。第4屈折部R4は、第3屈折部R3よりも高い屈折率を有する材料を含む層であり、例えば、Ta2O5、HfO2、ZrO2、TiO2、Al2O3、Nb2O5、ZnO、AlN、SiNまたはMgO等を含む。第3屈折部R3と第4屈折部R4との界面に臨界角以上の角度で入射した光は、この界面において全反射するため、第2光反射部RSにおいては高い光反射率(例えば、96%以上)が実現される。
図19は、実施例1の半導体デバイスの別構成を示す平面図である。図19に示すように、図7の半導体デバイス30を個片化し、それぞれが1つの半導体レーザ素子20を含む複数の半導体デバイス30としてもよい。
図20は、実施例1に係る半導体デバイスの別構成を示す断面図である。図20に示すように、半導体デバイス30は、主基板1の反対側に配され、第1および第2電極E1・E2と電気的に接続する回路基板CBを備える。具体的には、第1電極E1は、第1パッドP1および導電接着材A1を介して回路基板に接続され、第2電極E2は導電接着材A2を介して回路基板CBに接続される。回路基板CBが半導体レーザ素子20を駆動する構成でもよい。
図31は、実施例2に係る半導体デバイスの構成を示す断面図である。実施例2の半導体デバイス30は、例えば図10に示す下地基板UKを備え、第1光反射部RFが下地基板UK上に位置し、下地基板UKは、上面に開口した凹部UTを有する。
図36は、実施例3に係る半導体デバイスの構成を示す断面図である。図37は、実施例3に係る半導体デバイスの構成を示す断面図である。図36および図37の半導体デバイスでは、第2電極E2が下地基板UKの裏面に設けられている。下地基板UKには、例えばn型ドープがなされた主基板1(例えば、SiC基板、Si基板)を用いることができる。下地基板UKに下地部3を設ける場合は下地部3をn型半導体層(例えば、GaN系半導体)とし、下地基板UKにバッファ部2および下地部3を設ける場合は、これらをn型半導体層(例えば、窒化物半導体)とする。第1光反射部RFの各エピタキシャル層(例えば、窒化物半導体)およびシード部4(例えば、GaN系半導体)についても、n型半導体層とする。
図38は、実施例4に係る半導体デバイスの製造方法の一例を示すフローチャートである。図39~図40は、実施例4に係る半導体デバイスの構成を示す断面図である。実施例4では、下地基板UKが、主基板1と、主基板1の上方に位置する第2マスクMSとを有する。図38では、主基板1を準備する工程の後に、第2マスクMSを形成する工程と、ELO法で下地部3を形成する工程とを行う。すなわち、図39~図40の半導体デバイス30は、ELO法で形成される下地部3を有する。なお、主基板1と第2マスクMSとの間にバッファ部2を設けてもよい。
実施例5では、InAlN(第1屈折部R1)/GaN(第2屈折部R2)のエピタキシャルDBRを形成する。この場合、下地基板UKをMOCVD装置の反応炉内に設置し、反応炉内にH2およびNH3を供給して、基板温度を1070℃まで昇温させた後、下地基板UKにTMGを供給し、バッファ部2としてのGaN層を100nmエピタキシャル成長させる。次に、基板温度を930℃(第1の温度)に降温した後、供給ガスをH2からN2に切替え、TMIおよびTMAを供給することで、ノンドープのInAlN層(第1屈折部R1)を50nm成長させた。次に、基板温度を930℃に維持した状態でTEGおよびSiH4を供給することで、第2屈折部R2の第1層としてのSiドープGaN層を5nm成長させた。続いて、供給ガスをN2からH2に切替え、基板温度を1070℃(第2の温度)まで昇温し、TMGを供給することで、第2屈折部R2の第2層としてのノンドープGaN層を40nm成長させた。その後、上記工程を繰り返し、40ペアのInAlN/GaNからなるエピタキシャルDBRを形成した。ベース半導体部8(例えば、GaN層)と格子整合するInAlN/GaNからなる第1光反射部RFを形成する場合、下地基板UKはGaN基板(バルク結晶)を用いることができる。この場合、第1マスク6の開口部K上の貫通転位密度を5×106cm-2以下程度に抑えることができ、開口部K上にもアパーチャー部APを形成できるようになる。
実施例6では、第1光反射部RF(エピタキシャルDBR)をPSD法で形成する。PSD法では、化合物エピタキシャル層を形成するための元素の全て、または一部を、間欠的に供給する。化合物エピタキシャル層を形成するには、構成元素の全てを供給する必要があるが、間欠的に供給するのは一部の元素のみでよい場合がある。すなわち、構成する元素の原料の全てまたは一部を、間欠的に励起する。III-V族窒化物の場合、一般に、III族元素すべてを間欠的に供給することができるが、混晶を成膜するときには、一部のIII族元素を間欠的に供給し、他のIII族元素を連続的に(好ましくは遅い供給速度で)供給してもよい。
実施例1~6では、ベース半導体部8をGaNで構成することができるが、ベース半導体部8を、GaN系半導体であるInGaNで構成してもよい。InGaNの横方向成膜は、例えば1000℃を下回るような低温で行う。高温ではインジウムの蒸気圧が高くなり、膜中に有効に取り込まれないためである。成膜温度が低温になることで、マスク部5とベース半導体部8との相互反応が低減される効果がある。また、InGaNは、GaNよりもマスク部5(シリコン酸化膜、シリコン窒化膜等)との反応性が低いという効果もある。ベース半導体部8にインジウムがIn組成レベル1%以上で取り込まれるようになると、マスク部5との反応性がさらに低下する。ガリウム原料ガスとしては、トリエチルガリウム(TEG)を用いることができる。
図43および図44は、実施例8に係る半導体デバイスの別構成を示す断面図である。図43に示すように、下地基板UKの下方(裏面側)に波長変換部HSを設けてもよい。例えば、波長変換部HSとして、黄色で発光する一般的なYAG蛍光体などを配置することで、白色照明とすることができる。
図45は、実施例9に係る半導体デバイスの別構成を示す断面図である。図45では、第1光反射部RFにフォトニック結晶層を用いる。フォトニック結晶層である第1光反射部RFは、例えば、第5屈折部R5と、第5屈折部R5よりも高屈折率である第6屈折部R6とが2次元(X-Y平面)配置された構造を有する。第5屈折部R5は、ベース層に、格子点状に形成された、数十~数百ナノメートルの径を有する孔(ホール)であってもよい。ベース層は窒化物半導体層であってもよい。格子ピッチは、化合物半導体部9での発光波長程度(例えば、200~400nm)とすることができる。この場合、下地基板UK(例えば、GaN基板)上にGaN系半導体層をベース層とする第1光反射部RF(フォトニック結晶層)を形成し、第1光反射部RF上に対向基板SK(例えば、GaN基板)を配し、対向基板SK上にシード部4を介して第1マスク6を設けてもよい。対向基板SKがGaN基板であれば対向基板SK上に第1マスク6を設けてもよい。また、対向基板SKを設けずに、第1光反射部RF(フォトニック結晶層)上にシード部4を介して第1マスク6を設けてもよいし、第1光反射部RF(フォトニック結晶層)上に第1マスク6を設けてもよい。フォトニック結晶を形成すると、その上層の結晶性が低下することが知られているが、実施例9では、高光反射率を実現するフォトニック結晶を用いながら、上層の結晶性の低下が抑えられ、発光効率の高い化合物半導体部9を得ることができる。
図46は、実施例10に係る電子機器の構成を示す模式図である。図46の電子機器40は、実施例1~9の半導体デバイス30と、半導体デバイス30を制御するプロセッサを含む制御部80とを備える。電子機器40としては、通信装置、光学装置、表示装置、照明装置、センサ装置、情報処理装置、医療機器、電気自動車(EV)等を挙げることができる。
以上、本開示に係る発明について、諸図面および実施例に基づいて説明してきた。しかし、本開示に係る発明は上述した各実施形態に限定されるものではない。すなわち、本開示に係る発明は本開示で示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本開示に係る発明の技術的範囲に含まれる。つまり、当業者であれば本開示に基づき種々の変形または修正を行うことが容易であることに注意されたい。また、これらの変形または修正は本開示の範囲に含まれることに留意されたい。
2 バッファ部
3 下地部
5 マスク部
6 第1マスク
8 ベース半導体部
9 化合物半導体部
20 半導体レーザ素子
30 半導体デバイス
RF 第1光反射部
RS 第2光反射部
MS 第2マスク
R1~R4 第1~第4屈折部
UK 下地基板
K 開口部
Q 開口部
E1 第1電極
E2 第2電極
CB 回路基板
HD 第1部分
SD 第2部分
Claims (64)
- 主基板を含む下地基板と、
前記下地基板の上方に位置する第1光反射部と、
前記第1光反射部よりも上方に位置する第1マスクと、
前記第1マスクよりも上方に位置するベース半導体部と、
前記ベース半導体部よりも上方に位置する化合物半導体部と、
前記化合物半導体部および前記第1光反射部の上方に位置する第2光反射部と、を備える、半導体デバイス。 - 前記第1マスクは、マスク部および開口部を含み、
前記ベース半導体部は、第1部分と、前記マスク部上に位置し、貫通転位密度が前記第1部分の1/5以下である第2部分とを含む、請求項1に記載の半導体デバイス。 - 前記第2部分は、平面視で前記第1光反射部および前記第2光反射部と重なる、請求項2に記載の半導体デバイス。
- 前記第1マスクは、マスク部および開口部を含み、
前記第1光反射部は、第1屈折部と、前記第1屈折部よりも光屈折率が大きな第2屈折部とを含むペアを複数有する、請求項1~3のいずれか1項に記載の半導体デバイス。 - 前記第2屈折部は、GaN系半導体を含み、
前記第1屈折部は、前記第2屈折部のGaN系半導体よりも光屈折率の小さな屈折材料を含む、請求項4に記載の半導体デバイス。 - 前記屈折材料は、前記第2屈折部のGaN系半導体よりも熱伝導率が大きい、請求項5に記載の半導体デバイス。
- 前記屈折材料は、前記第2屈折部のGaN系半導体よりも格子定数が小さい、請求項5または6に記載の半導体デバイス。
- 熱膨張係数について、前記主基板の主材料<前記第2屈折部のGaN系半導体<前記屈折材料である、請求項5~7のいずれか1項に記載の半導体デバイス。
- 前記屈折材料が窒化物半導体である、請求項5~8のいずれか1項に記載の半導体デバイス。
- 前記屈折材料は、AlNあるいはAlInN、またはInNである、請求項5~9のいずれか1項に記載の半導体デバイス。
- 前記マスク部は、前記第2屈折部よりも光屈折率が小さい、請求項4~10のいずれか1項に記載の半導体デバイス。
- 前記ベース半導体部は、前記マスク部よりも光屈折率が大きい、請求項11に記載の半導体デバイス。
- 前記第1光反射部の上面は前記第2屈折部に含まれる、請求項4~12のいずれか1項に記載の半導体デバイス。
- 前記第1光反射部と前記第1マスクとの間にシード部を備える、請求項4~13のいずれか1項に記載の半導体デバイス。
- 前記シード部は、前記マスク部および前記第1屈折部よりも光屈折率が大きい、請求項14に記載の半導体デバイス。
- 前記ベース半導体部は、前記開口部において、前記第1光反射部の上面と接する、請求項2~15のいずれか1項に記載の半導体デバイス。
- 前記第1光反射部が前記下地基板上に位置し、
前記下地基板は、上面に開口した凹部を有する、請求項4に記載の半導体デバイス。 - 前記主基板は、前記凹部に対応する部分が凹んでいる、請求項17に記載の半導体デバイス。
- 前記下地基板は、前記主基板よりも上方に位置する下地部を含み、
前記下地部は、前記凹部に対応する部分が、凹んでいるかあるいは貫かれている、請求項17または18に記載の半導体デバイス。 - 平面視において前記第2光反射部は前記凹部と重ならない、請求項17~19のいずれか1項に記載の半導体デバイス。
- 前記第1屈折部および前記第2屈折部が、前記凹部に沿ったU字形状部を有する、請求項17~20のいずれか1項に記載の半導体デバイス。
- 前記化合物半導体部、前記ベース半導体部および前記マスク部の側面に接する空隙を備え、
平面視において前記空隙と前記凹部とが重なる、請求項21に記載の半導体デバイス。 - 前記第1光反射部の最上部に位置するU字形状部が前記空隙と接する、請求項22に記載の半導体デバイス。
- 前記主基板と前記第1光反射部との間に位置する下地部を備え、
前記下地部が窒化物半導体を含む、請求項1~23のいずれか1項に記載の半導体デバイス。 - 前記主基板上に位置するバッファ部と、
前記バッファ部および前記下地部の間に位置する第2マスクとを備える、請求項24に記載の半導体デバイス。 - 前記第2マスクはマスク部および開口部を含み、
平面視において、前記第1マスクの開口部と前記第2マスクの開口部とが重なる、請求項25に記載の半導体デバイス。 - 前記第2マスクはマスク部および開口部を含み、
平面視において、前記第1マスクのマスク部中央と前記第2マスクの開口部とが重なる、請求項25に記載の半導体デバイス。 - 前記化合物半導体部よりも上方に位置し、平面視で前記第2光反射部と重なる第1電極を備える、請求項2または3に記載の半導体デバイス。
- 前記第1マスクよりも上方、または前記主基板よりも下方に位置する第2電極を含む、請求項28に記載の半導体デバイス。
- 前記第2電極は、平面視で前記第2光反射部と重ならない、請求項29に記載の半導体デバイス。
- 前記第2電極は、前記ベース半導体部に接する、請求項29または30に記載の半導体デバイス。
- 前記第1光反射部と前記第1マスクとの間にシード部を備え、
前記第2電極は、前記シード部に接する、請求項29または30に記載の半導体デバイス。 - 前記第2電極は、前記第1光反射部の上面に接する、請求項29または30に記載の半導体デバイス。
- 前記化合物半導体部上に位置する絶縁膜を備え、
前記絶縁膜は、平面視において前記第1電極、前記第1光反射部、前記第2部分、および前記第2光反射部と重なるアパーチャー部を含む、請求項29に記載の半導体デバイス。 - 前記第1電極は、前記化合物半導体部と前記第2光反射部との間に位置する透明電極であり、
前記第1電極は前記絶縁膜の上面と接触し、
前記アパーチャー部では、前記第1電極および前記化合物半導体部が接触する、請求項34に記載の半導体デバイス。 - 前記第2光反射部は、前記第1電極上に島状に設けられている、請求項34または35に記載の半導体デバイス。
- 前記第2電極は、平面視において前記第2部分と重なる、請求項34~36のいずれか1項に記載の半導体デバイス。
- 前記化合物半導体部は、第1型半導体層、活性層、および第2型半導体層をこの順に含む、請求項2または3に記載の半導体デバイス。
- 前記第2型半導体層は、平面視において前記第1光反射部、前記第2部分、および前記第2光反射部と重なるアパーチャー部と、前記アパーチャー部を取り囲み、前記アパーチャー部よりも電流抵抗が大きな高抵抗部とを含む、請求項38に記載の半導体デバイス。
- 前記ベース半導体部および前記化合物半導体部それぞれが窒化物半導体を含む、請求項2または3に記載の半導体デバイス。
- 前記主基板は、前記ベース半導体部と格子定数が異なる異種基板である、請求項40に記載の半導体デバイス。
- 前記主基板は、GaNバルク基板よりも熱伝導率が高い、請求項1~41のいずれか1項に記載の半導体デバイス。
- 前記主基板が透光性であり、
前記第1光反射部は、前記第2光反射部よりも光反射率が小さい、請求項1~42のいずれか1項に記載の半導体デバイス。 - 前記主基板が炭化シリコン基板である、請求項40~43のいずれか1項に記載の半導体デバイス。
- 前記シード部は、前記開口部と重なるように局所的に設けられている、請求項14に記載の半導体デバイス。
- 前記ベース半導体部の側面、前記化合物半導体部の側面、および前記第2光反射部の側面に接する空隙を備える、請求項40に記載の半導体デバイス。
- 前記ベース半導体部および前記化合物半導体部それぞれの側面が、前記窒化物半導体のa面またはm面である、請求項46に記載の半導体デバイス。
- 平面視において前記空隙と前記マスク部の中央とが重なる、請求項46または47に記載の半導体デバイス。
- 前記アパーチャー部は、平面視において前記マスク部の中央とは重ならない、請求項34または39に記載の半導体デバイス。
- 前記ベース半導体部は、平面視において前記マスク部の中央と重なるボイドを内包する、請求項49に記載の半導体デバイス。
- 前記第2部分の貫通転位密度が5×106/cm2以下である、請求項2または3に記載の半導体デバイス。
- 前記主基板の下方に位置する波長変換部を備える、請求項1~51のいずれか1項に記載の半導体デバイス。
- 前記第2光反射部は、第3屈折部と、前記第3屈折部よりも光屈折率が大きな第4屈折部とを含むペアを複数有する、請求項38に記載の半導体デバイス。
- 前記第3屈折部および前記第4屈折部それぞれが誘電材料を含む、請求項53に記載の半導体デバイス。
- 前記第2光反射部の下面は前記第3屈折部に含まれ、
前記第2光反射部の上面は前記第4屈折部に含まれ、
前記第3屈折部は、前記第2型半導体層よりも光屈折率が小さい、請求項53または54に記載の半導体デバイス。 - 前記第1光反射部がフォトニック結晶層である、請求項1~3のいずれか1項に記載の半導体デバイス。
- 前記第1電極はアノードであり、前記第2電極はカソードである、請求項29に記載の半導体デバイス。
- 前記ベース半導体部および前記化合物半導体部並びに前記第1光反射部および前記第2光反射部を含む面発光半導体レーザ素子を1つ以上含む、請求項1~57のいずれか1項に記載の半導体デバイス。
- 1つ以上の前記面発光半導体レーザ素子に接続する回路基板を含む、請求項58に記載の半導体デバイス。
- 請求項59に記載の半導体デバイスを含む、電子機器。
- 請求項1~59のいずれか1項に記載の半導体デバイスの製造方法であって、
前記ベース半導体部をELO法で形成する、半導体デバイスの製造方法。 - 前記下地基板は下地部を含み、
前記下地部をELO法で形成する、請求項61に記載の半導体デバイスの製造方法。 - 前記第1光反射部の最下部をELO法で形成する、請求項61に記載の半導体デバイスの製造方法。
- 請求項1~59のいずれか1項に記載の半導体デバイスの製造装置であって、
前記ベース半導体部をELO法で形成する、半導体デバイスの製造装置。
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