WO2022198903A1 - 存储器的检测方法及检测装置 - Google Patents

存储器的检测方法及检测装置 Download PDF

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Publication number
WO2022198903A1
WO2022198903A1 PCT/CN2021/113439 CN2021113439W WO2022198903A1 WO 2022198903 A1 WO2022198903 A1 WO 2022198903A1 CN 2021113439 W CN2021113439 W CN 2021113439W WO 2022198903 A1 WO2022198903 A1 WO 2022198903A1
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WO
WIPO (PCT)
Prior art keywords
bit line
memory
line
storage
level
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PCT/CN2021/113439
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English (en)
French (fr)
Inventor
赵哲
孙龙杰
杨龙
陈永烜
许兰平
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长鑫存储技术有限公司
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Priority to US17/451,175 priority Critical patent/US11609705B2/en
Publication of WO2022198903A1 publication Critical patent/WO2022198903A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a detection method and a detection device for a memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • Embodiments of the present application provide a detection method and a detection device for a memory, which solve the problem that the accuracy of the bit line for detecting the leakage of the memory is not high.
  • An embodiment of the present application provides a method for detecting a memory, which is used to detect a leakage bit line, including: the memory includes a plurality of storage cells, a plurality of mutually separate bit lines and a plurality of mutually separate word lines, each The bit lines are connected to a number of the memory cells, each of the word lines is connected to a number of the memory cells, and each of the memory cells is connected to a corresponding bit line and a word line, the The memory also has a plurality of complementary bit lines, each of which is opposite to the level phase of a corresponding one of the bit lines; the memory also includes a plurality of sense amplifiers, each of the sense amplifiers is associated with a The bit line and one of the complementary bit lines are electrically coupled, and the sense amplifier includes a power supply line for providing a low potential voltage and a power supply line for providing a high potential voltage; writing first storage data to each of the memory cells ; After writing the first storage data, a read operation is performed, and the read operation includes: sequentially
  • Embodiments of the present application further provide a memory detection device for detecting leakage bit lines, including: a memory, wherein the memory includes a plurality of storage cells, a plurality of mutually separate bit lines, and a plurality of mutually separate word lines, Each of the bit lines is connected to a number of the memory cells, each of the word lines is connected to a number of the memory cells, and each of the memory cells is connected to a corresponding bit line and a word line , the memory also has a plurality of complementary bit lines, each of which is opposite to the level phase of a corresponding one of the bit lines; the memory also includes a plurality of sense amplifiers, each of which senses The amplifier is electrically coupled with one of the bit lines and the complementary bit lines, and the sense amplifier includes a power supply line for providing a low potential voltage and a power supply line for providing a high potential voltage; writing means for writing to the storage cell writing storage data; a reading device, the reading device is configured to select all the word lines for reading in turn, so as
  • the power supply line corresponding to the bit line that provides the low potential voltage is gated, so that the level of the bit line is lowered, and the power supply line that provides the low potential voltage is gated.
  • the power supply line corresponding to the bit line that provides the high potential voltage is gated, so that the level of the higher level of the bit line and the complementary bit line is raised;
  • a preset time is added between the power line that provides the low-potential voltage and the power line that provides the high-potential voltage.
  • the gated bit line is high level and leakage current, the level of the bit line can be lowered, then within a preset time period, the bit line of leakage current will drop from high level to low level, so that after being amplified by the sense amplifier
  • the first real data read out is different from the first stored data, so the exact position of the leakage current bit line can be determined; all word lines and bit lines are sequentially gated in this way, and write and first storage data are written in the memory cells respectively.
  • the second real data is read, and the exact position of the leakage current bit line can be obtained without omission according to the two comparison results, which improves the accuracy of the memory detection method and improves the product yield.
  • bit line and the corresponding complementary bit line are pre-charged, and the pre-charged bit line and the corresponding complementary bit line have the same level, which avoids other factors from selecting the bit line and the corresponding complementary bit line for the sense amplifier.
  • the influence of the one with the higher level between them ensures that the detected potential situation completely reflects the state of the memory itself, which is beneficial to improve the detection accuracy.
  • 1 is a schematic diagram of the level change of a bit line in a detection method of a memory
  • FIG. 2 is a schematic structural diagram of a memory in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a level change of a bit line in the first embodiment of the application.
  • FIG. 4 is a schematic diagram of the level change of another bit line in the first embodiment of the application.
  • FIG. 5 is an effect diagram of a detection method of a memory in an embodiment of the present application.
  • FIG. 6 is a schematic block diagram of a device for detecting a memory according to a second embodiment of the present application.
  • the detection method includes: the memory includes a plurality of storage units, and first storage data is written into each storage unit; after the first storage data is written, a read operation is performed, and the read operation includes: sequentially selecting all word lines to read to read the first real data in each memory cell through the bit line and the sense amplifier, and before reading, the power supply line NCS corresponding to the bit line that provides a low potential voltage is simultaneously selected, and the The power line PCS corresponding to the line provides a high potential voltage, so that the level of the higher level of the bit line and the complementary bit line is raised; based on the difference between the first real data and the first stored data, obtain the first Test result; write second storage data to each storage unit, and for the same storage unit, the second storage data is different from the first storage data; after writing the second storage data, perform the read operation again to read second real data in each memory cell; based on the difference between the second real data and the second stored data, obtain a second test result; based on the second test result and
  • bit line and the word line are short-circuited, the following four situations will occur during detection: In the first case, the bit line is at a low level. When the bit line is shorted with the gated word line, the bit line becomes a high level. The readout result is the high level of the bit line, which is inconsistent with the actual situation. Confirm the defect, so as to detect the specific position of the leakage potential line; in the second case, the bit line is high level.
  • the bit line When the bit line is shorted to the gated word line When the bit line is still high, the readout result is the high level of the bit line, which is consistent with the actual situation, no defects can be obtained, and the specific position of the leakage potential line cannot be detected; in the third case, the bit line is low, When the bit line is short-circuited with the unselected word line, the bit line is still low, and the read result is the low level of the bit line, which is consistent with the actual situation, no defects can be obtained, and the specific position of the leakage potential line cannot be detected; In the fourth case, the bit line is at a high level.
  • bit line When the bit line is short-circuited with an unselected word line, the bit line becomes a low level, and the read result is a low level of the bit line, which is inconsistent with the actual situation. Confirm defects, so as to detect the specific position of the leakage current bit line.
  • the second case and the third case cannot obtain defects, but by sequentially gating all word lines, the second case can be changed to the fourth case, and the third case can be changed to the first case In this way, the leakage current of the bit line caused by the short circuit of the bit line and the word line can be accurately detected, but the leakage current of the bit line caused by the incomplete short circuit of the bit line and the word line cannot be detected.
  • FIG. 1 is a schematic diagram of a level change of a bit line in a detection method of a memory.
  • the bit line is at a high level.
  • the activation operation ACT is performed at the T0 time node.
  • the power supply lines NCS and The power supply line PCS that provides the high potential voltage is precharged.
  • the level of the power supply line NCS that provides the low potential voltage is the same as the level of the power supply line PCS that provides the high potential voltage; the gated bit line and the corresponding The complementary bit line enters the charge sharing stage, and the bit line and the corresponding complementary bit line are pre-charged.
  • the pre-charged bit line and the corresponding complementary bit line have the same level; the word line is gated at the T1 time node; at T1 ⁇ T2 During the time period, the level of the complementary bit line does not change, but since the bit line is at a high level, the level of the bit line rises slowly; at the T2 time node, turn on the sense amplifier, and at the same time gate the corresponding bit line.
  • the bit line is high level, the bit line is not completely short-circuited with the unselected word line, the bit line is still high level, and the read result is the high level of the bit line. Consistent with the actual situation, no defects can be obtained, and the specific position of the leakage potential line cannot be detected. It can be obtained that this detection method of the memory cannot detect the leakage current of the bit line caused by incomplete short-circuiting of the bit line and the word line, resulting in incomplete detection of the leakage current of the bit line and affecting the product yield.
  • an embodiment of the present application provides a method for detecting a memory, adding a preset time between gating a power line that provides a low-potential voltage and a power line that provides a high-potential voltage.
  • the power supply line that provides the low potential voltage has been gated. If the gated bit line is at a high level and leaks current, the level of the bit line can be lowered, then within a preset time period, the bit line of the leakage current will be reduced.
  • the line will drop from a high level to a low level, so that the first real data read out after being amplified by the sense amplifier is different from the first stored data, and the exact position of the leakage current bit line can be determined; this method is used to sequentially select All word lines and bit lines, and write the second storage data different from the first storage data in the storage cells respectively, read the second real data, according to the two comparison results, the leakage current of the bit line can be obtained without omission.
  • the accurate location improves the accuracy of the memory detection method and improves the product yield.
  • FIG. 2 is a schematic structural diagram of a memory in an embodiment of the present application.
  • Embodiments of the present application provide a memory detection method for detecting leakage bit lines, including: referring to FIG. 2 , the memory 100 includes a plurality of memory cells 101 , a plurality of mutually separate bit lines 102 and a plurality of mutually separate word lines 103 , each bit line 102 is connected to a number of memory cells 101, each word line 103 is connected to a number of memory cells 101, and each memory cell 101 is connected to a corresponding bit line 102 and a word line 103, the memory 100 also has multiple Complementary bit lines (not marked), each complementary bit line and the corresponding bit line 102 have opposite levels; the memory 100 further includes a plurality of sense amplifiers 104, each sense amplifier 104 and the bit line 102 and A complementary bit line is electrically coupled, and the sense amplifier 104 includes a power supply line NCS providing a low potential voltage and a power supply line PCS providing a high potential voltage.
  • an initialization operation is performed on the storage unit 101 to activate the storage unit 101; after the initialization operation, a write operation is performed to write the first storage data into each storage unit 101, wherein in this embodiment, multiple storage units 101 are written to
  • the manner of writing the first storage data is that the first storage data written to all the storage units 101 are the same.
  • the manner of writing the first storage data to the memory cells includes: writing the same first storage data to several memory cells connected to the same word line, and simultaneously, writing the same first storage data to several memory cells connected to adjacent word lines The storage unit writes different first storage data.
  • the method of writing the first storage data to the memory cells further includes: every two adjacent word lines form a group, writing the same first storage data to several memory cells connected to the same group of word lines data, and at the same time, different first storage data are written to several memory cells connected to an adjacent group of word lines.
  • an automatic refresh operation can also be performed on all the memory cells 101; and then a read operation is performed, and the read operation includes: sequentially selecting all the word lines 103 to read to read the first real data in each memory cell 101 through the bit line 102 and the sense amplifier; based on the difference between the first real data and the first stored data, obtain the first test result; then to each memory cell 101 writes the second storage data, and for the same storage unit 101, the second storage data is different from the first storage data; after writing the second storage data, a read operation is performed again to read each storage unit 101. based on the difference between the second real data and the second stored data, obtain the second test result; and obtain the specific position of the leakage bit line 102 based on the second test result and the first test result.
  • the manner of writing the second storage data to the plurality of storage units 101 is that the second storage data written to all the storage units 101 is the same.
  • the manner of writing the second storage data to the memory cells includes: writing the same second storage data to several memory cells connected to the same word line, and simultaneously, writing the same second storage data to several memory cells connected to adjacent word lines
  • the storage unit writes different second storage data.
  • the method of writing the second storage data to the memory cells further includes: every two adjacent word lines are a group, and writing the same second storage data to several memory cells connected to the same group of word lines data, and at the same time, different second storage data is written to several memory cells connected to an adjacent group of word lines.
  • the power supply line NCS corresponding to the bit line 102 that provides the low-potential voltage is gated first, so that the level of the bit line 102 is lowered, and then the power supply line NCS that provides the low-potential voltage is gated. Then, after waiting for a preset time, the power supply line PCS corresponding to the bit line 102 that provides a high potential voltage is turned on, so that the level of the higher level of the bit line 102 and the complementary bit line is raised; then It is also possible to perform an automatic refresh operation on all memory cells 101 .
  • the level changes of the bit line 102 in various situations during the detection process will be described in detail below with reference to the accompanying drawings.
  • FIG. 3 is a schematic diagram of a level change of a bit line in the first embodiment of the present application.
  • the activation operation ACT is performed at the T0 time node. After the activation operation ACT, the power supply line NCS that provides the low potential voltage and the power supply line that provides the high potential voltage are connected. The PCS is precharged.
  • the level of the power supply line NCS that provides the low potential voltage is the same as the level of the power supply line PCS that provides the high potential voltage; the gated bit line 102 and the corresponding complementary bit line enter the charge sharing In the first stage, the bit line 102 and the corresponding complementary bit line are precharged, and the precharged bit line 102 and the corresponding complementary bit line have the same level; any word line 103 is gated at the T1 time node; at the time T1 to T2 In the segment, the level of the complementary bit line does not change, but since the bit line 102 is at a high level, the level of the bit line 102 rises slowly; at the T2 time node, the sense amplifier is turned on, and the gate corresponds to the bit line 102 At this time, the level of the bit line 102 and the complementary bit line are both lowered; after waiting for a preset time, the power supply line PCS corresponding to the bit line 102 that provides a high potential voltage is gated, so that the The level of
  • bit line 102 Since the bit line 102 is high and the complementary bit line is low, the bit line 102 and the complementary bit line fall at the same level. After the rate drops for a preset time, the level of the bit line 102 is still higher than that of the complementary bit line, so after the PCS power line is gated, the level of the bit line 102 increases.
  • the readout result is the high level of the bit line, which is consistent with the actual situation, and the detection method of the memory in this embodiment will not misjudge the bit line 102 that does not leak current.
  • bit line 102 and the word line 103 are completely short-circuited will be described in detail below, and the same parts as when the bit line 102 does not leak will not be repeated.
  • the bit line 102 is at a low level.
  • the bit line 102 short-circuits the gated word line 103, the bit line 102 becomes a high level.
  • the complementary bit line of the high level can be lowered.
  • the level of the bit line 102 cannot be lowered.
  • the level of the bit line 102 is higher than the level of the complementary bit line. The read result is that the bit line 102 is high, which is inconsistent with the actual situation.
  • the bit line 102 is at a high level, when the bit line 102 is shorted to the gated word line 103, the bit line 102 is still at a high level, and within a preset time, the complementary bit of the low level The line can be dropped, and the high-level bit line 102 cannot be dropped.
  • the level of the bit line 102 is higher than the level of the complementary bit line, and the read result is that the bit line 102 is high, which is different from the actual situation.
  • the bit line 102 is low level, when the bit line 102 is shorted with the unselected word line 103, the bit line 102 is still low level.
  • the complementary bit line with high level can be dropped, and the bit line 102 with low level can be dropped.
  • the level of the bit line 102 is lower than the level of the complementary bit line, and the result is read out.
  • bit line 102 It is the low level of the bit line 102, which is consistent with the actual situation, no defects can be obtained, and the specific position of the leakage potential line 102 cannot be detected; the bit line 102 is at a high level, when the bit line 102 is short-circuited with the unselected word line 103 When the bit line 102 changes to a low level, within a preset time, the complementary bit line of the low level can be lowered, and the bit line 102 of the low level can also be lowered. After the preset time, the bit line 102 is powered down If the level is lower than the level of the complementary bit line, the read result is the low level of the bit line 102, which is inconsistent with the actual situation. The defect is confirmed, and the specific position of the leakage current bit line 102 is detected.
  • the high-level bit line 102 is short-circuited with the gated word line 103 and the low-level bit line 102 is short-circuited with the non-gated word line 103. Defects cannot be obtained, but by sequentially gated all words If the high-level bit line 102 is short-circuited with the gated word line 103, the high-level bit line 102 and the unselected word line 103 can be short-circuited. The case where the gated word line 103 is short-circuited to a low-level bit line 102 is short-circuited with the gated word line 103, so that the leakage current of the bit line 102 caused by the complete short circuit between the bit line 102 and the word line 103 can be accurately detected.
  • bit line 102 and the word line 103 are not completely short-circuited resulting in leakage current of the bit line will be described in detail below with reference to the accompanying drawings.
  • FIG. 4 is a schematic diagram of the level change of another bit line in the first embodiment of the present application.
  • the bit line 102 is at a high level.
  • the activation operation ACT is performed at the T0 time node.
  • the power supply providing the low potential voltage is The line NCS and the power line PCS supplying the high potential voltage are precharged.
  • the level of the power supply line NCS supplying the low potential voltage is the same as the level of the power supply line PCS supplying the high potential voltage; the bit line of the gate 102 and the corresponding complementary bit line enter the charge sharing stage, pre-charge the bit line 102 and the corresponding complementary bit line, the pre-charged bit line 102 and the corresponding complementary bit line have the same level; at the T1 time node gate word Line 103; in the time period of T1 to T2, the level of the complementary bit line does not change, but since the bit line 102 is at a high level, the level of the bit line 102 rises slowly; at the T2 time node, turn on the sense amplifier , select the power supply line NCS corresponding to the bit line 102 that provides a low potential voltage, at this time the level of the bit line 102 and the complementary bit line both drop; after waiting for a preset time, select the power supply line NCS corresponding to the bit line 102 that provides a high potential voltage of the power supply line PCS
  • bit line 102 is high and the complementary bit line is low, due to the bit line 102 leaks electricity, and the incompletely shorted word line 103 cannot provide a level to the bit line 102, so the rate of decline of the level of the bit line 102 is higher than that of the complementary bit line level.
  • bit line The level of 102 is lower than the complementary bit line, so after the PCS power line is gated, the complementary bit line is the one whose level rises, and the readout result is the low level of the bit line 102, which does not match the actual situation. Defects can be obtained and detected. The specific position of the drain potential line 102 is revealed.
  • the low-level bit line 102 and the unselected word line 103 are not completely short-circuited, the high-level bit line 102 and the unselected word line 103 are not completely short-circuited, and the low-level bit line 102 is not completely short-circuited.
  • the open word line 103 by sequentially gating other word lines 103 and writing second storage data different from the first storage data to each storage cell 101 in the second detection, these three The situation is transformed into a situation where the high-level bit line 102 and the gated word line 103 are not completely short-circuited, resulting in leakage current, so that the specific position of the leakage potential line 102 can be detected more comprehensively and accurately, and the yield of the memory 100 can be improved.
  • the preset time is 90 nanoseconds to 120 nanoseconds, specifically 95 nanoseconds, 100 nanoseconds, or 110 nanoseconds. Within this time period, more leakage potential lines 102 can be guaranteed. been detected.
  • FIG. 5 is an effect diagram of a method for detecting a memory in an embodiment of the present application.
  • the first writing method is: write the same storage data to all storage cells;
  • the second writing method is: write the same storage data to several storage cells connected to the same word line, At the same time, different storage data is written to several memory cells connected to adjacent word lines;
  • the third writing method is: every two adjacent word lines are a group, and to several memory cells connected to the same group of word lines The same memory data is written to the memory cells, and at the same time, different memory data is written to a plurality of memory cells connected to an adjacent group of word lines.
  • the third writing method is used to write the stored data to the storage unit 101, and the detection effect is the best; the longer the preset time is, the better the detection effect is; for the third writing method, the preset time is greater than 90 nanometers. After seconds, the detection effect remains unchanged.
  • the power supply line NCS corresponding to the bit line 102 that provides a low potential voltage is firstly gated, so that the level of the bit line 102 is lowered, and a low potential is provided after the gate is turned on.
  • the power supply line NCS of the voltage after waiting for a preset time, the power supply line PCS corresponding to the bit line 102 that provides a high potential voltage is turned on, so that the power supply of the bit line 102 and the complementary bit line with a higher level is turned on.
  • Level up a preset time is added between gating the power supply line NCS supplying the low potential voltage and the power supply line PCS supplying the high potential voltage, within the preset time period, since the power supply line NCS supplying the low potential voltage has been selected If the gated bit line 102 is at a high level and leaks current, the level of the bit line 102 can be lowered, then within a preset time period, the bit line 102 with leakage current will drop from a high level to a low level, so that the real data read out after being amplified by the sense amplifier is different from the stored data, the exact position of the leakage current bit line 102 can be determined; this method is used to sequentially select all word lines 103 and bit lines 102, and Two different storage data are written in the storage unit 101 respectively, and the real data is read twice respectively. According to the two comparison results, the exact position of the bit line 102 of the leakage current can be obtained without omission, which improves the detection method of the memory 100. Accuracy, improve product yield.
  • the second embodiment of the present application provides a memory detection device corresponding to the memory detection method of the first embodiment, which is used to detect leakage bit lines.
  • the memory detection device of this embodiment will be described in detail below with reference to the accompanying drawings.
  • the memory 100 includes a plurality of memory cells 101, a plurality of mutually separate bit lines 102, and a plurality of mutually separate word lines 103, each bit line 102 is connected to a plurality of memory cells 101, and each word line 103 is connected to a plurality of memory cells 101, and each memory cell 101 is connected to a corresponding bit line 102 and a word line 103, the memory 100 also has a plurality of complementary bit lines (not shown), each complementary bit line is connected to a corresponding bit line The levels of 102 are opposite in phase; the memory 100 also includes a plurality of sense amplifiers 104, each sense amplifier 104 is electrically coupled to a bit line 102 and a complementary bit line, and the sense amplifier 104 includes a power supply line that provides a low potential voltage The NCS and the power supply line PCS supplying the high potential voltage.
  • FIG. 6 is a schematic block diagram of a device for detecting a memory according to a second embodiment of the present application.
  • the writing device 110 is used to write the storage data to the storage unit 101;
  • the instruction device 120 includes a power supply line control device 121, and the power supply line control device 121 is used to control the power supply line NCS that provides a low potential voltage corresponding to the bit line,
  • the power supply line control device 121 is used to control the power supply line NCS that provides a low potential voltage corresponding to the bit line,
  • the command device 120 further includes a time control device 122, and the time control device 122 is used to control the duration of the preset time.
  • the preset time is 90 nanoseconds to 120 nanoseconds, specifically 95 nanoseconds, 100 nanoseconds, or 110 nanoseconds. Within this time period, more leakage potential lines 102 can be guaranteed. been detected.
  • a precharging device is further included, and the precharging device is used to precharge the bit line 102 and the corresponding complementary bit line, so that after a word line 103 is gated, the level of the bit line 102 is the same as that of the corresponding complementary bit line.
  • the levels of the complementary bit lines are the same; and an automatic refresh device is also included, which is used to periodically perform an automatic refresh operation on the memory cell 101 .
  • an instruction decoder 130 is further included, configured to select the power supply line NCS providing a low potential voltage and the power supply line PCS providing a high voltage potential according to an instruction issued by the instruction device 120 .
  • the reading device 140 is used to sequentially select all the word lines 103 for reading, so as to read the real data in each memory cell 101 through the bit line 102 and the sense amplifier 104 ; the error reporting device 150 and the error reporting device 150 Based on the difference between the real data and the stored data, a test result is obtained, and based on the test result, the specific position of the leakage bit line is obtained.
  • the command device 120 controls the power supply line NCS corresponding to the bit line 102 that provides a low-potential voltage to be selected first, so that the level of the bit line 102 drops.
  • the time control device 122 controls the power supply line PCS that provides the high potential voltage corresponding to the bit line 102 after waiting for a preset time, so that the bit line 102 and the complementary bit line are powered on.
  • the level of the one with the higher level is raised; within a preset period of time, since the power supply line NCS providing the low potential voltage has been gated, if the gated bit line 102 is at a high level and leaks current, the The level of the bit line 102 can be lowered, so within a preset period of time, the bit line 102 of the leakage current will drop from a high level to a low level, so that the real data read out after being amplified by the sense amplifier 104 is the same as the one. If the stored data is different, the exact position of the leakage current bit line 102 can be determined, the accuracy of the detection method of the memory 100 is improved, and the product yield is improved.

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Abstract

本申请实施例提供一种存储器的检测方法及检测装置，用于检测漏电的位线，方法包括：存储器包括多个存储单元，存储器还包括多个感测放大器，感测放大器包括提供低电位电压的电源线以及提供高电位电压的电源线；向每一存储单元写入第一存储数据；在写入第一存储数据之后，进行读取操作，基于第一真实数据与第一存储数据的差异，获取第一测试结果；再次进行读取操作，以读取每一存储单元内的第二真实数据；基于第二真实数据与第二存储数据的差异，获取第二测试结果；基于第二测试结果以及第一测试结果，获取漏电的位线的具体位置。本申请实施例提供的存储器的检测方法，有利于提高检测存储器的漏电的位线的准确度。

Description

存储器的检测方法及检测装置
交叉引用
本申请基于申请号为202110310429.0、申请日为2021年03月23日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体领域，特别涉及一种存储器的检测方法及检测装置。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
随着DRAM的制程工艺越来越先进、存储密度越来越高，DRAM制程工艺中也出现了越来越多的问题，比如：副产物掉落引发的短路、位线漏电流、电容的倒塌、金属线的断裂，关键尺寸不合格造成的结构问题等，这些制程工艺中出现的问题需要在良率测试过程中筛选出来，但是现有的良率测试方法不能准确的检测出漏电流的位线，导致产品良率较低。
如何在良率测试过程中准确的检测出漏电流的位线，是本领域技 术人员亟须解决的问题。
发明内容
本申请实施例提供一种存储器的检测方法及检测装置，解决检测存储器的漏电的位线准确度不高的问题。
本申请实施例提供一种存储器的检测方法，用于检测漏电的位线，包括：所述存储器包括多个存储单元、多条相互分立的位线以及多条相互分立的字线，每条所述位线连接若干个所述存储单元，每条所述字线连接若干个所述存储单元，且每一所述存储单元与相应的一所述位线以及一所述字线连接，所述存储器还具有多条互补位线，每一所述互补位线与相应的一所述位线的电平相位相反；所述存储器还包括多个感测放大器，每一所述感测放大器与一所述位线以及一所述互补位线电耦合，且所述感测放大器包括提供低电位电压的电源线以及提供高电位电压的电源线；向每一所述存储单元写入第一存储数据；在写入所述第一存储数据之后，进行读取操作，所述读取操作包括：依次选通所有所述字线进行读取，以通过所述位线以及所述感测放大器读取每一所述存储单元内的第一真实数据，且在进行读取之前，先选通与所述位线对应的所述提供低电位电压的电源线，以使所述位线的电平下降，在选通所述提供低电位电压的电源线后，在等待预设时间后，选通与所述位线对应的所述提供高电位电压的电源线，以使所述位线和所述互补位线中电平更高的一者的电平升高；基于所述第一真实数据与所述第一存储数据的差异，获取第一测试结果；向每一所述存储单元写入第二存储数据，且针对同一所述存储单元，所 述第二存储数据与所述第一存储数据不同；在写入所述第二存储数据之后，再次进行所述读取操作，以读取每一所述存储单元内的第二真实数据；基于所述第二真实数据与所述第二存储数据的差异，获取第二测试结果；基于所述第二测试结果以及所述第一测试结果，获取漏电的所述位线的具体位置。
本申请实施例还提供一种存储器的检测装置，用以检测漏电的位线，包括：存储器，所述存储器包括多个存储单元、多条相互分立的位线以及多条相互分立的字线，每条所述位线连接若干个所述存储单元，每条所述字线连接若干个所述存储单元，且每一所述存储单元与相应的一所述位线以及一所述字线连接，所述存储器还具有多条互补位线，每一所述互补位线与相应的一所述位线的电平相位相反；所述存储器还包括多个感测放大器，每一所述感测放大器与一所述位线以及以所述互补位线电耦合，且所述感测放大器包括提供低电位电压的电源线以及提供高电位电压的电源线；写入装置，用于向所述存储单元写入存储数据；读取装置，所述读取装置用于依次选通所有所述字线进行读取，以通过所述位线以及所述感测放大器读取每一所述存储单元内的真实数据；指令装置，用于控制选通与所述位线对应的所述提供低电位电压的电源线，以使所述位线的电平下降，在选通所述提供低电位电压的电源线后等待预设时间之后，等待预设时间选通所述提供高电位电压的电源线，以使所述位线和所述互补位线中电平更高的一者的电平升高；报错装置，所述报错装置基于所述真实数据与所述存储数据的差异，获取测试结果，并基于所述测试结果，获取漏电 的所述位线的具体位置。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
本申请实施例提供的存储器的检测方法，在进行读取之前，先选通与位线对应的提供低电位电压的电源线，以使位线的电平下降，在选通提供低电位电压的电源线后，在等待预设时间后，选通与位线对应的提供高电位电压的电源线，以使位线和互补位线中电平更高的一者的电平升高；在选通提供低电位电压的电源线和提供高电位电压的电源线之间增加预设时间，在预设时间段内，由于提供低电位电压的电源线已经被选通，如果选通的位线为高电平且漏电流，则该位线的电平是可降的，那么在预设时间段内，漏电流的位线会从高电平降至低电平，这样经感测放大器放大后读出的第一真实数据与第一存储数据不同，则可确定漏电流位线的确切位置；采用如此方法依次选通所有字线和位线，且分别在存储单元中写入与第一存储数据不同的第二存储数据，读取第二真实数据，根据两次对比结果可以无遗漏的得到漏电流的位线的准确位置，提高了存储器检测方法的准确率，改善产品良率。
另外，对位线和对应的互补位线进行预充电，预充电后的位线和对应的互补位线电平相同，这样避免了其余因素对感测放大器挑选位线与对应的互补位线两者之间电平更大者的影响，保证了检测出的电位情况完全反应存储器本身的状况，有利于提高检测的准确性。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说 明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为一种存储器的检测方法中位线的电平变化示意图；
图2为本申请实施例中存储器的结构示意图；
图3为本申请第一实施例中一种位线的电平变化示意图；
图4为本申请第一实施例中另一种位线的电平变化示意图；
图5为本申请实施例中存储器的检测方法效果图；
图6为本申请第二实施例中存储器的检测装置的模块示意图。
具体实施方式
由背景技术可知，现有技术的存储器检测方法准确度不高。
现结合一种存储器的检测方法进行分析。检测方法包括：存储器包括若干个存储单元，向每一存储单元写入第一存储数据；在写入第一存储数据之后，进行读取操作，读取操作包括：依次选通所有字线进行读取，以通过位线以及感测放大器读取每一存储单元内的第一真实数据，且在进行读取之前，同时选通与位线对应的提供低电位电压的电源线NCS，和与位线对应的提供高电位电压的电源线PCS，以使位线和互补位线中电平更高的一者的电平升高；基于第一真实数据与第一存储数据的差异，获取第一测试结果；向每一存储单元写入第二存储数据，且针对同一存储单元，第二存储数据与第一存储数据不同；在写入第二存储数据之后，再次进行读取操作，以读取每一存储单元内的第二真实数据；基于第二真实数据与第二存储数据的差异，获取 第二测试结果；基于第二测试结果以及第一测试结果，获取漏电的位线的具体位置。
当位线与字线短路时，检测时会出现如下四种情况：第一种情况，位线为低电平，当位线短接选通的字线时，位线变为高电平，读出结果为位线高电平，与实际情况不符，确认缺陷，从而检测出漏电位线的具体位置；第二种情况，位线为高电平，当位线短接选通的字线时，位线还是高电平，读出结果为位线高电平，与实际情况相符，不能得到缺陷，不能检测出漏电位线的具体位置；第三种情况，位线为低电平，当位线与未选通的字线短接时，位线还是低电平，读出结果为位线低电平，与实际情况相符，不能得到缺陷，检测不出漏电位线的具体位置；第四种情况，位线为高电平，当位线与未选通的字线短接时，位线变为低电平，读出结果为位线低电平，与实际情况不符，确认缺陷，从而检测出漏电流位线的具体位置。
其中，第二种情况和第三种情况不能得出缺陷，但是通过依次选通所有字线的方式，就可以将第二种情况变为第四种情况，第三种情况变为第一种情况，这样对于位线与字线短路导致的位线漏电流情况，都可以准确检测出来，但是对于位线和字线不完全短接导致位线漏电流的情况，则无法检测出来。
图1为一种存储器的检测方法中位线的电平变化示意图。
参考图1，位线为高电平，当位线与选通的字线不完全短接时，在T0时间节点进行激活操作ACT，激活操作ACT之后，对提供低电位电压的电源线NCS和提供高电位电压的电源线PCS进行预充电处 理，预充电处理之后，提供低电位电压的电源线NCS的电平和提供高电位电压的电源线PCS的电平相同；选通的位线和对应的互补位线进入电荷分享阶段，对位线和对应的互补位线进行预充电，预充电后的位线和对应的互补位线电平相同；在T1时间节点选通字线；在T1～T2时间段内，互补位线的电平不发生变化，但由于位线为高电平，所以位线的电平缓慢升高；T2时间节点，打开感测放大器，同时选通与位线对应的提供低电位电压的电源线NCS和提供高电位电压的电源线PCS，位线还是高电平，读出结果为位线高电平，与实际情况相符，不能得到缺陷，检测不出漏电位线的具体位置；选通其他字线，则该位线为高电平，位线与未选通的字线不完全短接，位线还是高电平，读出结果为位线高电平，与实际情况相符，不能得到缺陷，检测不出漏电位线的具体位置。可以得到，这种存储器的检测方法不能检测出位线与字线不完全短接导致位线漏电流的情况，造成对位线漏电流检测不完全，影响产品良率。
为解决上述问题，本申请实施例提供一种存储器的检测方法，在选通提供低电位电压的电源线和提供高电位电压的电源线之间增加预设时间，在预设时间段内，由于提供低电位电压的电源线已经被选通，如果选通的位线为高电平且漏电流，则该位线的电平是可降的，那么在预设时间段内，漏电流的位线会从高电平降至低电平，这样经感测放大器放大后读出的第一真实数据与第一存储数据不同，则可确定漏电流位线的确切位置；采用如此方法依次选通所有字线和位线，且分别在存储单元中写入与第一存储数据不同的第二存储数据，读取 第二真实数据，根据两次对比结果可以无遗漏的得到漏电流的位线的准确位置，提高了存储器检测方法的准确率，改善产品良率。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图2为本申请实施例中存储器的结构示意图。
本申请实施例提供用于检测漏电的位线的存储器检测的方法，包括：参考图2，存储器100包括多个存储单元101、多条相互分立的位线102以及多条相互分立的字线103，每条位线102连接若干个存储单元101，每条字线103连接若干个存储单元101，且每一存储单元101与相应的一位线102以及一字线103连接，存储器100还具有多条互补位线(未标示)，每一互补位线与相应的一位线102的电平相位相反；存储器100还包括多个感测放大器104，每一感测放大器104与一位线102以及一互补位线电耦合，且感测放大器104包括提供低电位电压的电源线NCS以及提供高电位电压的电源线PCS。
首先对存储单元101进行初始化操作，以激活存储单元101；在初始化操作之后，进行写入操作，向每一存储单元101写入第一存储数据，其中，本实施例中向多个存储单元101写入第一存储数据的方式为，向所有的存储单元101写入的第一存储数据都相同。
在其他实施例中，向存储单元写入第一存储数据的方式包括：向与同一字线连接的若干存储单元写入相同的第一存储数据，同时，向与相邻的字线连接的若干存储单元写入不同的第一存储数据。
在其他实施例中，向存储单元写入第一存储数据的方式还包括：每相邻的两条字线为一组，向与同一组字线连接的若干存储单元写入相同的第一存储数据，同时，向与相邻的一组字线连接的若干存储单元写入不同的第一存储数据。
本实施例中，在向存储单元101写入第一存储数据之后，还可以对所有存储单元101进行自动刷新操作；然后进行读取操作，读取操作包括：依次选通所有字线103进行读取，以通过位线102以及感测放大器读取每一存储单元101内的第一真实数据；基于第一真实数据与第一存储数据的差异，获取第一测试结果；然后向每一存储单元101写入第二存储数据，且针对同一存储单元101，第二存储数据与第一存储数据不同；在写入第二存储数据之后，再次进行读取操作，以读取每一存储单元101内的第二真实数据；基于第二真实数据与第二存储数据的差异，获取第二测试结果；基于第二测试结果以及第一测试结果，获取漏电的位线102的具体位置。
本实施例中向多个存储单元101写入第二存储数据的方式为，向所有的存储单元101写入的第二存储数据都相同。
在其他实施例中，向存储单元写入第二存储数据的方式包括：向与同一字线连接的若干存储单元写入相同的第二存储数据，同时，向与相邻的字线连接的若干存储单元写入不同的第二存储数据。
在其他实施例中，向存储单元写入第二存储数据的方式还包括：每相邻的两条字线为一组，向与同一组字线连接的若干存储单元写入相同的第二存储数据，同时，向与相邻的一组字线连接的若干存储单元写入不同的第二存储数据。
本实施例中，在进行读取之前，先选通与位线102对应的提供低电位电压的电源线NCS，以使位线102的电平下降，在选通提供低电位电压的电源线NCS后，在等待预设时间后，选通与位线102对应的提供高电位电压的电源线PCS，以使位线102和互补位线中电平更高的一者的电平升高；然后还可以对所有存储单元101进行自动刷新操作。以下将结合附图对检测过程中各种不同情况的位线102的电平变化情况进行详细说明。
图3为本申请第一实施例中一种位线的电平变化示意图。
参考图3，当选通的位线102为高电平且不漏电时，在T0时间节点进行激活操作ACT，激活操作ACT之后，对提供低电位电压的电源线NCS和提供高电位电压的电源线PCS进行预充电处理，预充电处理之后，提供低电位电压的电源线NCS的电平和提供高电位电压的电源线PCS的电平相同；选通的位线102和对应的互补位线进入电荷分享阶段，对位线102和对应的互补位线进行预充电，预充电后的位线102和对应的互补位线电平相同；在T1时间节点选通任一字线103；在T1～T2时间段内，互补位线的电平不发生变化，但由于位线102为高电平，所以位线102的电平缓慢升高；T2时间节点，打开感测放大器，选通与位线102对应的提供低电位电压的电源线NCS，这时 位线102和互补位线的电平都下降；等待预设时间后，选通与位线102对应的提供高电位电压的电源线PCS，以使位线102和互补位线中电平更高的一者的电平升高，由于位线102为高电平，互补位线为低电平，在位线102和互补位线以相同的下降速率下降预设时间后，位线102的电平还是高于互补位线，所以在选通PCS电源线后，电平升高的是位线102。
这样，读出结果为位线高电平，与实际相符，本实施例的存储器的检测方法不会对不漏电的位线102误判。
以下将对位线102与字线103完全短路时的情况进行详细说明，与位线102不漏电时相同的部分，将不再赘述。
位线102为低电平，当位线102短接选通的字线103时，位线102变为高电平，在预设时间内，高电平的互补位线是可降的，高电平的位线102是不可降的，预设时间后，位线102电平高于互补位线电平，读出结果为位线102高电平，与实际情况不符，确认缺陷，检测出漏电位线102的具体位置；位线102为高电平，当位线102短接选通的字线103时，位线102还是高电平，在预设时间内，低电平的互补位线是可降的，高电平的位线102是不可降的，预设时间后，位线102电平高于互补位线电平，读出结果为位线102高电平，与实际情况相符，不能得到缺陷，不能检测出漏电位线102的具体位置；位线102为低电平，当位线102与未选通的字线103短接时，位线102还是低电平，在预设时间内，高电平的互补位线是可降的，低电平的位线102是可降的，预设时间后，位线102电平低于互补位线电平， 读出结果为位线102低电平，与实际情况相符，不能得到缺陷，检测不出漏电位线102的具体位置；位线102为高电平，当位线102与未选通的字线103短接时，位线102变为低电平，在预设时间内，低电平的互补位线是可降的，低电平的位线102也是可降的，预设时间后，位线102电平低于互补位线电平，读出结果为位线102低电平，与实际情况不符，确认缺陷，检测出漏电流位线102的具体位置。
其中，高电平位线102短接选通的字线103和低电平位线102与未选通的字线103短接的两种情况，不能得出缺陷，但是通过依次选通所有字线的方式，就可以将高电平位线102短接选通的字线103变为高电平位线102与未选通的字线103短接的情况，低电平位线102与未选通的字线103短接变为低电平位线102短接选通的字线103的情况，这样对于位线102与字线103完全短路导致的位线102漏电流情况，都可以准确检测出来。
以下将结合附图对位线102和字线103不完全短接导致位线漏电流的情况进行详细说明，与位线102不漏电时相同的部分，将不再赘述。
图4为本申请第一实施例中另一种位线的电平变化示意图。
参考图4，位线102为高电平，当位线102与选通的字线103不完全短接时，在T0时间节点进行激活操作ACT，激活操作ACT之后，对提供低电位电压的电源线NCS和提供高电位电压的电源线PCS进行预充电处理，预充电处理之后，提供低电位电压的电源线NCS的电平和提供高电位电压的电源线PCS的电平相同；选通的位线102和对应 的互补位线进入电荷分享阶段，对位线102和对应的互补位线进行预充电，预充电后的位线102和对应的互补位线电平相同；在T1时间节点选通字线103；在T1～T2时间段内，互补位线的电平不发生变化，但由于位线102为高电平，所以位线102的电平缓慢升高；T2时间节点，打开感测放大器，选通与位线102对应的提供低电位电压的电源线NCS，这时位线102和互补位线的电平都下降；等待预设时间后，选通与位线102对应的提供高电位电压的电源线PCS，以使位线102和互补位线中电平更高的一者的电平升高，虽然位线102为高电平，互补位线为低电平，但由于位线102漏电，且不完全短接的字线103不能给位线102提供电平，所以位线102的电平的下降速率高于互补位线电平的下降速率，在预设时间后，位线102的电平低于互补位线，所以在选通PCS电源线后，电平升高的是互补位线，读出结果为位线102低电平，与实际情况不符，能得到缺陷，检测出漏电位线102的具体位置。
对于低电平位线102与未选通的字线103不完全短接、高电平位线102与未选通的字线103不完全短接、低电平位线102不完全短接选通的字线103这三种情况，通过依次选通其他字线103和在第二次检测中向每一存储单元101写入与第一存储数据不同的第二存储数据，可以将这三种情况转化为高电平位线102与选通的字线103不完全短接导致漏电流的情况，从而可以更全面准确检测出漏电位线102的具体位置，提高存储器100的良率。
本实施例中，预设时间为90纳秒～120纳秒，具体可以为95纳 秒、100纳秒或110纳秒，预设时间在此时间段内，可以保证更多的漏电位线102被检测出来。
图5为本申请实施例中存储器的检测方法效果图。
参考图5，第一种写入方式为：向所有的存储单元写入的存储数据都相同；第二种写入方式为：向与同一字线连接的若干存储单元写入相同的存储数据，同时，向与相邻的字线连接的若干存储单元写入不同的存储数据；第三种写入方式为：每相邻的两条字线为一组，向与同一组字线连接的若干存储单元写入相同的存储数据，同时，向与相邻的一组字线连接的若干存储单元写入不同的存储数据。
可以得到，采用第三种写入方式向存储单元101写入存储数据，检测的效果最好；预设时间越长，检测效果越好；对于第三种写入方式，预设时间大于90纳秒之后，检测效果不变。
本实施例提供的存储器的检测方法，在进行读取之前，先选通与位线102对应的提供低电位电压的电源线NCS，以使位线102的电平下降，在选通提供低电位电压的电源线NCS后，在等待预设时间后，选通与位线102对应的提供高电位电压的电源线PCS，以使位线102和互补位线中电平更高的一者的电平升高；在选通提供低电位电压的电源线NCS和提供高电位电压的电源线PCS之间增加预设时间，在预设时间段内，由于提供低电位电压的电源线NCS已经被选通，如果选通的位线102为高电平且漏电流，则该位线102的电平是可降的，那么在预设时间段内，漏电流的位线102会从高电平降至低电平，这样经感测放大器放大后读出的真实数据与存储数据不同，则可确定漏电 流位线102的确切位置；采用如此方法依次选通所有字线103和位线102，且分别在存储单元101中写入两次不同的存储数据，分别读取两次真实数据，根据两次对比结果可以无遗漏的得到漏电流的位线102的准确位置，提高了存储器100检测方法的准确率，改善产品良率。
本申请第二实施例提供一种与第一实施例存储器的检测方法对应的存储器的检测装置，用以检测漏电的位线。以下将结合附图对本实施例的存储器的检测装置进行详细的说明。
参考图2，存储器100包括多个存储单元101、多条相互分立的位线102以及多条相互分立的字线103，每条位线102连接若干个存储单元101，每条字线103连接若干个存储单元101，且每一存储单元101与相应的一位线102以及一字线103连接，存储器100还具有多条互补位线(未标示)，每一互补位线与相应的一位线102的电平相位相反；存储器100还包括多个感测放大器104，每一感测放大器104与一位线102以及一互补位线电耦合，且感测放大器104包括提供低电位电压的电源线NCS以及提供高电位电压的电源线PCS。
图6为本申请第二实施例中存储器的检测装置的模块示意图。
写入装置110，用于向存储单元101写入存储数据；指令装置120包括电源线控制装置121，电源线控制装置121用于控制选通与位线对应的提供低电位电压的电源线NCS，以使位线102的电平下降，在选通提供低电位电压的电源线NCS后，等待预设时间选通提供高电位电压的电源线PCS，以使位线102和所补位线中电平更高的一者的电 平升高；指令装置120还包括时间控制装置122，时间控制装置122用于控制预设时间的时长。
本实施例中，预设时间为90纳秒～120纳秒，具体可以为95纳秒、100纳秒或110纳秒，预设时间在此时间段内，可以保证更多的漏电位线102被检测出来。
本实施例中，还包括：预充电装置，预充电装置用于对位线102和对应的互补位线进行预充电，使得在选通一字线103之后，位线102的电平与对应的互补位线的电平相同；还包括：自动刷新装置，用于定时对存储单元101进行自动刷新操作。
本实施例中，还包括：指令译码器130，用于根据指令装置120发出的指令选通提供低电位电压的电源线NCS和提供高电压电位的电源线PCS。
本实施例中读取装置140用于依次选通所有字线103进行读取，以通过位线102以及感测放大器104读取每一存储单元101内的真实数据；报错装置150，报错装置150基于真实数据与存储数据的差异，获取测试结果，并基于测试结果，获取漏电的位线的具体位置。
本实施例提供的存储器的检测装置，在进行读取之前，指令装置120控制先选通与位线102对应的提供低电位电压的电源线NCS，以使位线102的电平下降，在选通提供低电位电压的电源线NCS后，时间控制装置122控制等待预设时间后，选通与位线102对应的提供高电位电压的电源线PCS，以使位线102和互补位线中电平更高的一者的电平升高；在预设时间段内，由于提供低电位电压的电源线NCS已 经被选通，如果选通的位线102为高电平且漏电流，则该位线102的电平是可降的，那么在预设时间段内，漏电流的位线102会从高电平降至低电平，这样经感测放大器104放大后读出的真实数据与存储数据不同，则可确定漏电流位线102的确切位置，提高了存储器100检测方法的准确率，改善产品良率。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (16)

  1. 一种存储器的检测方法，用于检测漏电的位线，包括：
    所述存储器包括多个存储单元、多条相互分立的位线以及多条相互分立的字线，每条所述位线连接若干个所述存储单元，每条所述字线连接若干个所述存储单元，且每一所述存储单元与相应的一所述位线以及一所述字线连接，所述存储器还具有多条互补位线，每一所述互补位线与相应的一所述位线的电平相位相反；所述存储器还包括多个感测放大器，每一所述感测放大器与一所述位线以及一所述互补位线电耦合，且所述感测放大器包括提供低电位电压的电源线以及提供高电位电压的电源线；
    向每一所述存储单元写入第一存储数据；
    在写入所述第一存储数据之后，进行读取操作，所述读取操作包括：依次选通所有所述字线进行读取，以通过所述位线以及所述感测放大器读取每一所述存储单元内的第一真实数据，且在进行读取之前，先选通与所述位线对应的所述提供低电位电压的电源线，以使所述位线的电平下降，在选通所述提供低电位电压的电源线后，在等待预设时间后，选通与所述位线对应的所述提供高电位电压的电源线，以使所述位线和所述互补位线中电平更高的一者的电平升高；
    基于所述第一真实数据与所述第一存储数据的差异，获取第一测试结果；
    向每一所述存储单元写入第二存储数据，且针对同一所述存储单元，所述第二存储数据与所述第一存储数据不同；
    在写入所述第二存储数据之后，再次进行所述读取操作，以读取每一所述存储单元内的第二真实数据；
    基于所述第二真实数据与所述第二存储数据的差异，获取第二测试结果；
    基于所述第二测试结果以及所述第一测试结果，获取漏电的所述位线的具体位置。
  2. 根据权利要求1所述的存储器的检测方法，其中，所述预设时间为90纳秒～120纳秒。
  3. 根据权利要求1所述的存储器的检测方法，其中，向所述存储单元写入所述第一存储数据的方式包括：向所有所述存储单元写入相同的所述第一存储数据。
  4. 根据权利要求1或3所述的存储器的检测方法，其中，向所述存储单元写入所述第二存储数据的方式包括：向所有所述存储单元写入相同的所述第二存储数据。
  5. 根据权利要求1所述的存储器的检测方法，其中，向所述存储单元写入所述第一存储数据的方式包括：向与同一所述字线连接的若干所述存储单元写入相同的所述第一存储数据。
  6. 根据权利要求1或5所述的存储器的检测方法，其中，向所述存储单元写入所述第二存储数据的方式包括：向与同一所述字线连接的若干所述存储单元写入相同的所述第二存储数据。
  7. 根据权利要求6所述的存储器的检测方法，其中，向所述存储单元写入所述第一存储数据以及所述第二存储数据的方式还包括：向 与相邻的所述字线连接的若干所述存储单元写入不同的所述第一存储数据，且向与相邻的所述字线连接的若干所述存储单元写入不同的所述第二存储数据。
  8. 根据权利要求1所述的存储器的检测方法，其中，在选通所述提供低电位电压的电源线之前，还包括：对所述提供低电位电压的电源线和所述提供高电位电压的电源线进行预充电处理，所述预充电处理之后，所述提供低电位电压的电源线的电平和所述提供高电位电压的电源线的电平相同。
  9. 根据权利要求1所述的存储器的检测方法，其中，在选通一所述字线之后，还包括：对所述位线和对应的所述互补位线进行预充电，所述预充电后的所述位线和对应的所述互补位线电平相同。
  10. 根据权利要求1所述的存储器的检测方法，其中，在进行所述读取操作之前，还包括：对所有所述存储单元进行自动刷新操作。
  11. 根据权利要求1所述的存储器的检测方法，其中，在选通所述提供高电位电压的电源线之后，读取所述第一真实数据或所述第二真实数据之前，还包括：对所有所述存储单元进行自动刷新操作。
  12. 一种存储器的检测装置，用以检测漏电的位线，包括：
    存储器，所述存储器包括多个存储单元、多条相互分立的位线以及多条相互分立的字线，每条所述位线连接若干个所述存储单元，每条所述字线连接若干个所述存储单元，且每一所述存储单元与相应的一所述位线以及一所述字线连接，所述存储器还具有多条互补位线，每一所述互补位线与相应的一所述位线的电平相位相反；
    所述存储器还包括多个感测放大器，每一所述感测放大器与一所述位线以及以所述互补位线电耦合，且所述感测放大器包括提供低电位电压的电源线以及提供高电位电压的电源线；
    写入装置，用于向所述存储单元写入存储数据；
    读取装置，所述读取装置用于依次选通所有所述字线进行读取，以通过所述位线以及所述感测放大器读取每一所述存储单元内的真实数据；
    指令装置，用于控制选通与所述位线对应的所述提供低电位电压的电源线，以使所述位线的电平下降，在选通所述提供低电位电压的电源线后等待预设时间之后，等待预设时间选通所述提供高电位电压的电源线，以使所述位线和所述互补位线中电平更高的一者的电平升高；
    报错装置，所述报错装置基于所述真实数据与所述存储数据的差异，获取测试结果，并基于所述测试结果，获取漏电的所述位线的具体位置。
  13. 根据权利要求12所述的存储器的检测装置，其中，还包括：指令译码器，用于根据所述指令装置发出的指令选通所述提供低电位电压的电源线和所述提供高电压电位的电源线。
  14. 根据权利要求12所述的存储器的检测装置，其中，所述指令装置包括时间控制装置，所述时间控制装置用于控制所述预设时间的时长。
  15. 根据权利要求12所述的存储器的检测装置，其中，还包括： 预充电装置，所述预充电装置用于对所述位线和对应的所述互补位线进行预充电，使得在选通一所述字线之后，所述位线的电平与对应的所述互补位线的电平相同。
  16. 根据权利要求12所述的存储器的检测装置，其中，还包括：自动刷新装置，用于定时对所述存储单元进行自动刷新操作。
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