WO2022042014A1 - 字线驱动电路缺陷测试方法与装置 - Google Patents

字线驱动电路缺陷测试方法与装置 Download PDF

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Publication number
WO2022042014A1
WO2022042014A1 PCT/CN2021/103525 CN2021103525W WO2022042014A1 WO 2022042014 A1 WO2022042014 A1 WO 2022042014A1 CN 2021103525 W CN2021103525 W CN 2021103525W WO 2022042014 A1 WO2022042014 A1 WO 2022042014A1
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Prior art keywords
word line
word lines
potential
tested
word
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PCT/CN2021/103525
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English (en)
French (fr)
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陈武刚
杨龙
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长鑫存储技术有限公司
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Priority to US17/470,001 priority Critical patent/US11676678B2/en
Publication of WO2022042014A1 publication Critical patent/WO2022042014A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Definitions

  • the present disclosure relates to the technical field of semiconductor manufacturing, and exemplarily, to a method and apparatus for testing a word line driver circuit defect.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • gate defects Poly-Gate necking
  • the memory signal becomes weak or distorted, and after the burn-in process, the gate defects will be further amplified (further resistance or open circuit), resulting in a decrease in chip yield. Therefore, there is an urgent need for a method capable of detecting gate defects in word line driver circuits.
  • Embodiments of the present disclosure provide a word line driving circuit defect testing method and a word line driving circuit defect testing device, which overcome to a certain extent the problem that word line driving circuit defects cannot be tested due to limitations and defects of the related art.
  • a method for testing a word line driver circuit defect including: in a memory cell array and a corresponding word line driver circuit array, selecting m word lines as the word lines to be tested, One of the m word lines to be tested is set as the first word line, and the other m-1 are set as the second word line, wherein the m word lines to be tested are respectively connected to different m word lines Drive circuit, m is an integer greater than 1; the first write operation: write the first potential to the memory cells correspondingly connected to all the transistors controlled by the m word lines to be tested; the second write operation: write the first potential to the All transistors controlled by the first word line are correspondingly connected to write the second potential in the memory cells; read judgment operation: read the real-time potentials of the memory cells correspondingly connected to all the transistors controlled by each of the second word lines in turn, and then read When the difference between the obtained real-time potential of a target storage unit and the first potential is greater than the
  • a word line driver circuit defect testing apparatus comprising: a memory; and a processor coupled to the memory, the processor configured to be based on a data stored in the memory The instruction executes the method for testing a word line driver circuit defect as described in any one of the above.
  • the memory cell corresponding to the under-tested wordline corresponding to the defective wordline drive circuit can generate a real-time potential between the first potential and the second potential, and then by reading the remaining untested potentials
  • Defective word line driving cells are identified by measuring the real-time potential of the memory cells corresponding to the word lines.
  • FIG. 1A is a schematic diagram of a word line driver circuit.
  • FIG. 1B is a schematic circuit diagram of an inverter in a word line driving circuit.
  • FIG. 1C is a photograph of the gate defect at location A in FIGS. 1A and 1B .
  • FIG. 2 is a schematic diagram of a memory cell array and its corresponding word line driver circuit.
  • FIG. 3 is a schematic diagram of the relationship between a memory cell and a word line driver circuit.
  • FIG. 4 is a flowchart of a method for testing a word line driver circuit defect in an exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of selected locations of word lines to be tested in an exemplary embodiment of the present disclosure.
  • FIG. 6 is a sub-flow chart of step S2 in one embodiment.
  • FIG. 7 is a sub-flow chart of step S3 in one embodiment.
  • FIG. 8 is a schematic flowchart of another embodiment of the present disclosure.
  • FIG. 9 is a block diagram of a word line driver circuit defect testing apparatus provided in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • 1A to 1C are schematic diagrams of gate defects of a word line driver circuit.
  • the word line driving circuit 1 connects n word lines WL through n inverter circuits 11 , and the gates of the transistors in each inverter 11 are connected to the control node M of the word line driving circuit 1 .
  • the circuit of each inverter 11 is shown in FIG. 1B .
  • FIG. 2 is a schematic diagram of a memory cell array and its corresponding word line driver circuit.
  • the memory cell array 21 is located in the center, including N1 rows and N2 columns, that is, N1*N2 memory cells (not shown in the figure), and each memory cell is located in a word line connected by a word line driver circuit 1 and a sense The intersection of the bit lines to which the amplifier SA is connected.
  • the word line driver circuit arrays 22 are respectively located on both sides of the memory cell array 21.
  • Each word line driver circuit array 22 includes a plurality of word line driver circuits 1 respectively.
  • Each word line driver circuit 1 is connected to n word lines and is located in the memory cell.
  • a plurality of word lines in the array are arranged in parallel and staggered in a fork shape, and word line driving circuits 1 correspondingly connected to adjacent word lines are respectively located in the word line driving circuit array 22 on different sides.
  • a memory includes a plurality of memory cell arrays 21 and their corresponding word line driving circuit arrays 22 , and details are not described herein again.
  • one page of the memory includes 8 memory cell arrays 21 , and the corresponding word lines are 2048 in total.
  • FIG. 3 is a schematic diagram of the relationship between a memory cell and a word line driver circuit.
  • each word line WLi controls N1 transistors Mij.
  • the first end of the transistor Mij is connected to a memory cell Cij, and the second end of the transistor Mij is connected to a bit line BLj, where i is the word line number and j is the bit line number.
  • the present disclosure provides a method for testing the defects of the word line driving circuit.
  • FIG. 4 is a flowchart of a method for testing a word line driver circuit defect in an exemplary embodiment of the present disclosure.
  • the method 100 for testing word line driver circuit defects may include:
  • step S1 in the memory cell array and its corresponding word line driver circuit array, m word lines are selected as the word lines to be tested, one of the m word lines to be tested is set as the first word line, and the rest are set as the first word line.
  • m-1 is set as the second word line, wherein the m word lines to be tested are respectively connected to different m word line driving circuits, and m is an integer greater than 1;
  • Step S2 writing a first potential to the memory cells correspondingly connected to all the transistors controlled by the m word lines to be tested;
  • Step S3 writing a second potential to the memory cells correspondingly connected to all transistors controlled by the first word line;
  • Step S4 successively read the real-time potentials of the correspondingly connected storage cells of all transistors controlled by the second word lines, and the difference between the real-time potential of a target storage cell read and the first potential is greater than the first potential.
  • the preset value it is judged that the word line driver circuit connected to the second word line connected to the transistor corresponding to the target memory cell is defective; wherein, the difference between the first potential and the second potential is greater than or equal to 0.6 V.
  • the memory cell corresponding to the under-tested wordline corresponding to the defective wordline drive circuit can generate a real-time potential between the first potential and the second potential, and then by reading the remaining untested potentials
  • Defective word line driving cells are identified by measuring the real-time potential of the memory cells corresponding to the word lines.
  • step S1 in the memory cell array and its corresponding word line driving circuit array, m word lines are selected as the word lines to be tested, one of the m word lines to be tested is set as the first word line, and The remaining m-1 lines are set as second word lines, wherein the m word lines to be tested are respectively connected to different m word line driving circuits, where m is an integer greater than 1.
  • m word lines may be selected from a memory cell 21 to be tested and its corresponding word line driving circuit array 22 as the word lines to be tested.
  • m word lines to be tested correspond to different m word line driving circuits respectively.
  • FIG. 5 is a schematic diagram of selected locations of word lines to be tested in an exemplary embodiment of the present disclosure.
  • the m word line driving circuits may be arranged in the word line driving circuit array 22 on the same side. Since each word line driver circuit is connected to n word lines, the adjacent word lines in the memory cell array 21 correspond to the word line driver circuit arrays 22 located on different sides respectively. Therefore, at this time, it can be selected according to the spacing of 2n-1 word lines. m word lines to be tested (word lines in bold in FIG. 5 ).
  • step S2 a first potential is written into the memory cells correspondingly connected to all the transistors controlled by the m word lines to be tested.
  • FIG. 6 is a sub-flow chart of step S2 in one embodiment.
  • step S2 may include:
  • Step S21 adjusting all the bit lines correspondingly connected to all transistors controlled by the m word lines to be tested to the first potential
  • Step S22 turn on all the transistors controlled by the m word lines to be tested, so that the first potential is written in the memory cells corresponding to all the transistors controlled by the m word lines to be tested.
  • turning on all the transistors controlled by a word line to be tested means outputting the first storage control command to the word line to be measured through the word line driver circuit corresponding to the word line to be measured, and closing all the transistors controlled by a word line to be measured means passing the The word line driving circuit corresponding to the word line to be tested outputs a second storage control command to the word line to be tested.
  • step S2 is to control the memory cells corresponding to all word lines to be tested to be in the same initial potential, so as to provide a judgment basis for subsequent detection.
  • step S3 a second potential is written into the memory cells correspondingly connected to all transistors controlled by the first word line.
  • FIG. 7 is a sub-flow chart of step S3 in one embodiment.
  • step S3 may include:
  • Step S31 turning off all the transistors controlled by the m word lines to be tested
  • Step S32 adjusting all the bit lines correspondingly connected to all transistors controlled by the m word lines to be tested to the second potential
  • Step S33 turning on all the transistors controlled by the first word line, so that the memory cells correspondingly connected to all the transistors controlled by the first word line are written to the second potential;
  • step S34 all transistors controlled by the first word line are turned off.
  • a second word line corresponds to a word line drive circuit with a gate defect
  • the first storage control instruction and the second storage control instruction for controlling the second word line are both There will be weakening or delay, resulting in that the transistors controlled by the second word line cannot be turned off in time when step S32 is performed, and the memory cells connected to these transistors are affected by the second potential on the bit line, and the storage state is between the first potential and between the second potential.
  • step S4 the real-time potentials of the correspondingly connected memory cells of all the transistors controlled by the second word lines are sequentially read, and the difference between the real-time potential of a target memory cell read and the first potential is greater than the first potential.
  • a preset value it is determined that the word line driver circuit connected to the second word line connected to the transistor corresponding to the target memory cell is defective, wherein the difference between the first potential and the second potential is greater than or equal to 0.6V.
  • the difference between the first potential and the second potential is controlled to be greater than or equal to 0.6V.
  • the first potential can be set to -0.1-0.2V, and the second potential can be set to 0.8-1.1V; or, the first potential can be set to 0.8-1.1V, and the second potential can be set to - 0.1 ⁇ 0.2V.
  • the first preset value may be equal to 0.5V, for example.
  • Sequentially reading the real-time potentials of the correspondingly connected memory cells of all the transistors controlled by each second word line may be: selecting a second word line, reading the real-time potentials of the correspondingly connected memory cells of all the transistors controlled by it, and judging; continue The second word line is selected until the real-time potentials of the correspondingly connected memory cells of all transistors controlled by all the second word lines are read and judged.
  • step S3 the memory cell corresponding to the second word line corresponding to the word line driver circuit with gate defect is affected by the weakening or delay of the storage control command and the bit line being at the second potential, and the storage state will be between the first between the potential and the second potential.
  • it can be determined whether the storage state of the storage unit is abnormal by judging whether the difference between the real-time potential of each storage unit and the first potential is greater than the first preset value, so that the real-time potential of the target storage unit is not close to the first potential.
  • the potential is high, it is determined that the word line driver circuit corresponding to the second word line corresponding to the target memory cell has a gate defect.
  • the difference between the real-time potential of one memory cell and the second potential is smaller than the second preset value, that is, when the real-time potential of the target memory cell is closer to the second potential, it can be determined that the word line corresponding to the second word line corresponding to the target memory cell There is a gate defect in the driver circuit.
  • Both the above-mentioned first preset value and the second preset value can be set by those skilled in the art according to the difference between the first potential and the second potential, which is not specifically limited in the present disclosure.
  • step S4 the test of all word lines can be implemented by setting a loop test.
  • 2mn word lines arranged in a row may be selected as a test module, and the test module may be tested, including: in the test module, in the order of the word lines, sequentially selecting m to be Measure the word lines, set the first word lines in sequence according to the arrangement order of the word lines, and then perform the first write operation (step S2), the second write operation (step S3) and the read judgment operation (step S4) until 2mn Each word line has been set as the first word line. Then, in the memory cell array, each consecutive 2mn word lines are selected as a test module in the order of the word lines, and then the test module is tested until all word lines in the memory cell array have been selected as test modules. module.
  • step S1 the word lines WL11, WL31, WL51, and WL71 can be selected as the word lines to be tested, WL11 is set as the first word line, and WL31, WL51, and WL71 are set as the second word line.
  • the second potential is written to the memory cells connected to all transistors controlled by WL11, and all transistors controlled by WL31, WL51, and WL71 are sequentially read.
  • the real-time potentials of the connected memory cells are used to determine whether the word line driver circuits 1, 3, 5, and 7 have gate defects.
  • cyclic manners may also be set to implement testing of all word lines in the memory cell array.
  • FIG. 8 is a schematic flowchart of another embodiment of the present disclosure.
  • the method 100 may further include:
  • Step S81 selecting another word line to be measured among the m word lines to be measured as the third word line;
  • Step S82 writing a first potential to the memory cells correspondingly connected to all the transistors controlled by the m word lines to be tested;
  • Step S83 writing the second potential to the memory cells correspondingly connected to all transistors controlled by the third word line;
  • Step S84 Read the real-time potentials of the memory cells correspondingly connected to all transistors controlled by the first word line, and determine the first potential when the difference between the real-time potential and the first potential is greater than a first preset value.
  • a word line driver circuit connected by a word line has drawbacks.
  • the switching state of the transistor connected to the first word line is opposite to the switching state of the transistor connected to the third word line, the word line driving circuit connected to the first word line can be tested, and then the selected The m word line driver circuits corresponding to the m word lines to be tested are all tested.
  • each of the m word lines to be tested selected this time may be set as the first word line for testing in sequence, that is, the m word lines to be tested of this group are tested m times in total, In order to improve the probability of screening out the gate defects of the word line driving circuit corresponding to each word line to be tested.
  • m word lines to be tested can be continuously selected from the memory cell array and its corresponding word line driver circuit array for testing until all word lines in the memory cell to be tested are tested. All have been selected as word lines to be tested.
  • FIG. 9 is a block diagram of a word line driver circuit defect testing apparatus provided in an embodiment of the present disclosure.
  • a word line driver circuit defect testing apparatus 900 may include:
  • a processor 92 coupled to the memory 91 is configured to perform the word line driver circuit defect testing method as described in any of the above based on the instructions stored in the memory 91 .
  • modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • m word lines to be tested corresponding to m word line driving circuits respectively, firstly write the first potential to the memory cells corresponding to the m word lines to be tested, and then write the first potential to the memory cells corresponding to the m word lines to be tested.
  • the second potential is written into the memory cell of the 100000 , so that the memory cell corresponding to the word line to be tested corresponding to the defective word line driver circuit can generate a real-time potential between the first potential and the second potential, and then by reading the remaining to-be-tested potentials
  • Defective word line driving cells are identified by measuring the real-time potential of the memory cells corresponding to the word lines.

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Abstract

一种字线驱动电路缺陷测试方法与装置。方法包括：在存储单元阵列及其对应的字线驱动电路阵列中，选取m条字线作为待测字线，将m条待测字线中的一条设置为第一字线，将其余m-1条设置为第二字线，其中，m条待测字线分别对应连接不同的m个字线驱动电路；对m条待测字线控对应连接的存储单元写入第一电位；对第一字线对应连接的存储单元写入第二电位；依次读取各第二字线对应连接的存储单元的实时电位，在一个目标存储单元的实时电位与第一电位的差值大于第一预设值时，判断该目标存储单元对应的第二字线连接的字线驱动电路具有缺陷；其中，第一电位与第二电位的差值大于等于0.6V。本公开实施例可以测试字线驱动电路是否存在栅极缺陷。

Description

字线驱动电路缺陷测试方法与装置
交叉引用
本公开要求于2020年08月24日提交的申请号为202010858274.X、名称为“字线驱动电路缺陷测试方法与装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体制造技术领域，示例性而言，涉及一种字线驱动电路缺陷测试方法与装置。
背景技术
在DRAM(Dynamic Random Access Memory，动态随机存取存储器)中，由于栅极特征尺寸小，容易产生栅极缺陷(Poly-Gate necking)，在字线驱动电路中，这种栅极缺陷会导致电阻升高、存储信号变弱或失真，在老化工艺后，栅极缺陷会被进一步放大(电阻进一步升高或产生断路)，从而导致芯片良品率下降。因此，亟需一种能够检测字线驱动电路中栅极缺陷的方法。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开实施例提供一种字线驱动电路缺陷测试方法与字线驱动电路缺陷测试装置，在一定程度上克服由于相关技术的限制和缺陷而导致的字线驱动电路缺陷无法测试的问题。
根据本公开实施例的第一方面，提供一种字线驱动电路缺陷测试方法，包括：在存储单元阵列及其对应的字线驱动电路阵列中，选取m条字线作为待测字线，将m条所述待测字线中的一条设置为第一字线，将其余m-1条设置为第二字线，其中，m条所述待测字线分别对应连接不同的m个字线驱动电路，m为大于1的整数；第一写入操作：对所述m条所述待测字线控制的全部晶体管对应连接的存储单元写入第一电位；第二写入操作：对所述第一字线控制的全部晶体管对应连接的存储单元写入第二电位；读取判断操作：依次读取各所述第二字线控制的全部晶体管对应连接的存储单元的实时电位，在读取到的一个目标存储单元的实时电位与所述第一电位的差值大于第一预设值时，判断所述目标存储单元对应连接的晶体管对应连接的第二字线连接的字线驱动电路具有缺陷；其中，所述第一电位与所述第二电位的差值大于等于0.6V。
根据本公开实施例的第二方面，提供一种字线驱动电路缺陷测试装置，包括：存储器；以及耦合到所述存储器的处理器，所述处理器被配置为基于存储在所述存储器中的指令， 执行如上任一项所述的字线驱动电路缺陷测试方法。
本公开实施例通过选取分别对应m个字线驱动电路的m条待测字线，首先对m条待测字线对应的存储单元均写入第一电位，然后对其中一条待测字线对应的存储单元写入第二电位，可以使存在缺陷的字线驱动电路对应的待测字线对应的存储单元产生介于第一电位和第二电位之间的实时电位，进而通过读取其余待测字线对应的存储单元的实时电位识别出存在缺陷的字线驱动单元。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A是字线驱动电路的示意图。
图1B是字线驱动电路中反向器的电路示意图。
图1C是图1A和图1B中位置A的栅极缺陷照片。
图2是存储单元阵列及其对应的字线驱动电路的示意图。
图3是存储单元与字线驱动电路关系的示意图。
图4是本公开示例性实施例中字线驱动电路缺陷测试方法的流程图。
图5是本公开示例性实施例中待测字线选取位置的示意图。
图6是一个实施例中步骤S2的子流程图。
图7是一个实施例中步骤S3的子流程图。
图8是本公开另一个实施例的流程示意图。
图9是本公开一个实施例中提供的字线驱动电路缺陷测试装置的方框图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1A～图1C是字线驱动电路的栅极缺陷示意图。
参考图1A，字线驱动电路1通过n个反向器电路11连接n条字线WL，每个反向器11中晶体管的栅极均连接到字线驱动电路1的控制节点M。每一个反向器11的电路如图1B所示。
当任一反向器11x(x为反向器序号或字线序号)对应的晶体管的栅极(图中A位置)出现如图1C所示的栅极缺陷(栅极细小或断开)时，反向器11x的电阻升高，此时读写控制器通过控制节点M输出的字线控制指令无法准确到达字线WLx，会造成对字线WLx的控制产生异常。
图2是存储单元阵列及其对应的字线驱动电路的示意图。
参考图2，存储单元阵列21位于中央，包括N1行N2列即N1*N2个存储单元(图中未示出)，每个存储单元位于一个字线驱动电路1连接的字线和一个感测放大器SA连接的位线的交叉点。
字线驱动电路阵列22分别位于存储单元阵列21的两侧，每个字线驱动电路阵列22分别包括多个字线驱动电路1，每个字线驱动电路1连接n条字线，位于存储单元阵列中的多条字线呈叉状平行交错排列，相邻字线对应连接的字线驱动电路1分别位于不同侧的字线驱动电路阵列22中。在一个实施例中，一侧的字线驱动电路阵列22共包括16个字线驱动电路1，每个字线驱动电路1对应4条字线。即，存储单元阵列21中共有16*2*4＝128条字线，即N2＝128。此时，每次选取的待测字线数量可以为一侧字线驱动电路的数量16，即m＝16。
可以理解的是，一个存储器包括多个存储单元阵列21及其对应的字线驱动电路阵列22，于此不再赘述。在一实施例中，存储器的一页包括8个存储单元阵列21，对应的字线数量共为2048条。
图3是存储单元与字线驱动电路关系的示意图。
参考图3，在存储单元阵列21中，相邻两条字线分别对应位于不同侧的字线驱动电路1。每条字线WLi均控制N1个晶体管Mij，晶体管Mij的第一端均连接一个存储单元Cij，晶体管Mij的第二端连接一条位线BLj，其中i是字线序号，j是位线序号。
为了测试如图1A～图1C所示的字线驱动电路的栅极缺陷，本公开提供了一种字线驱动电路缺陷测试方法。
图4是本公开示例性实施例中字线驱动电路缺陷测试方法的流程图。
参考图4，字线驱动电路缺陷测试方法100可以包括：
步骤S1，在存储单元阵列及其对应的字线驱动电路阵列中，选取m条字线作为待测字线，将m条所述待测字线中的一条设置为第一字线，将其余m-1条设置为第二字线，其中，m条所述待测字线分别对应连接不同的m个字线驱动电路，m为大于1的整数；
步骤S2，对所述m条所述待测字线控制的全部晶体管对应连接的存储单元写入第一电位；
步骤S3，对所述第一字线控制的全部晶体管对应连接的存储单元写入第二电位；
步骤S4，依次读取各所述第二字线控制的全部晶体管对应连接的存储单元的实时电位，在读取到的一个目标存储单元的实时电位与所述第一电位的差值大于第一预设值时，判断所述目标存储单元对应连接的晶体管对应连接的第二字线连接的字线驱动电路具有缺陷；其中，所述第一电位与所述第二电位的差值大于等于0.6V。
本公开实施例通过选取分别对应m个字线驱动电路的m条待测字线，首先对m条待测字线对应的存储单元均写入第一电位，然后对其中一条待测字线对应的存储单元写入第二电位，可以使存在缺陷的字线驱动电路对应的待测字线对应的存储单元产生介于第一电位和第二电位之间的实时电位，进而通过读取其余待测字线对应的存储单元的实时电位识别出存在缺陷的字线驱动单元。
下面，对字线驱动电路缺陷测试方法100的各步骤进行详细说明。
在步骤S1，在存储单元阵列及其对应的字线驱动电路阵列中，选取m条字线作为待测字线，将m条所述待测字线中的一条设置为第一字线，将其余m-1条设置为第二字线，其中，m条所述待测字线分别对应连接不同的m个字线驱动电路，m为大于1的整数。
首先，可以在一个待测存储单元21及其对应的字线驱动电路阵列22中选取m条字线作为待测字线。为了测试字线驱动电路的栅极缺陷，m条待测字线分别对应不同的m个字线驱动电路。
图5是本公开示例性实施例中待测字线选取位置的示意图。
参考图5，在一个实施例中，可以设置该m个字线驱动电路位于同一侧的字线驱动电路阵列22中。由于每个字线驱动电路连接n条字线，存储单元阵列21中相邻字线分别对应位于不同侧的字线驱动电路阵列22，因此，此时可以按照2n-1条字线的间距选取m条待测字线(图5中加粗字线)。
在步骤S2，对所述m条所述待测字线控制的全部晶体管对应连接的存储单元写入第一电位。
图6是一个实施例中步骤S2的子流程图。
参考图6，步骤S2可以包括：
步骤S21，将所述m条待测字线控制的全部晶体管对应连接的位线全部调整到所述第一电位；
步骤S22，打开所述m条待测字线控制的全部晶体管，以使所述m条待测字线控制 的全部晶体管对应连接的所述存储单元写入所述第一电位。
其中，打开一条待测字线控制的全部晶体管即通过该待测字线对应的字线驱动电路对该待测字线输出第一存储控制指令，关闭一条待测字线控制的全部晶体管即通过该待测字线对应的字线驱动电路对该待测字线输出第二存储控制指令。
步骤S2的实施是为了控制全部待测字线对应的存储单元处于同一个初始电位中，为后续检测提供判断基础。
在步骤S3，对所述第一字线控制的全部晶体管对应连接的存储单元写入第二电位。
图7是一个实施例中步骤S3的子流程图。
参考图7，步骤S3可以包括：
步骤S31，关闭所述m条待测字线控制的全部晶体管；
步骤S32，将所述m条待测字线控制的全部晶体管对应连接的位线全部调整到所述第二电位；
步骤S33，打开所述第一字线控制的全部晶体管，以使所述第一字线控制的全部晶体管对应连接的所述存储单元写入所述第二电位；
步骤S34，关闭所述第一字线控制的全部晶体管。
如果一条第二字线对应一个存在栅极缺陷的字线驱动电路，由于该字线驱动电路中栅极缺陷的存在，控制该第二字线的第一存储控制指令和第二存储控制指令均会出现减弱或延迟，导致在进行步骤S32时，该第二字线控制的晶体管未能及时关闭，这些晶体管连接的存储单元受位线上的第二电位影响，存储状态介于第一电位和第二电位之间。
在步骤S4，依次读取各所述第二字线控制的全部晶体管对应连接的存储单元的实时电位，在读取到的一个目标存储单元的实时电位与所述第一电位的差值大于第一预设值时，判断所述目标存储单元对应连接的晶体管对应连接的第二字线连接的字线驱动电路具有缺陷，其中，所述第一电位与所述第二电位的差值大于等于0.6V。
为了增加检测成功的概率，提高存在栅极缺陷的字线驱动电路对应的存储单元产生存储状态异常的几率，控制第一电位与第二电位的差值大于等于0.6V。在一个实施例中，可以将第一电位设置为-0.1～0.2V，将第二电位设置为0.8～1.1V；或者，将第一电位设置为0.8～1.1V，将第二电位设置为-0.1～0.2V。在一个实施例中，第一预设值例如可以等于0.5V。
依次读取各第二字线控制的全部晶体管对应连接的存储单元的实时电位可以为：选取一条第二字线，读取其控制的全部晶体管对应连接的存储单元的实时电位并进行判断；继续选取第二字线，直至全部第二字线控制的全部晶体管对应连接的存储单元的实时电位均被读取并被判断。
如步骤S3所述，存在栅极缺陷的字线驱动电路对应的第二字线对应的存储单元，受存储控制指令减弱或延迟、位线为第二电位的影响，存储状态会介于第一电位和第二电位之间。此时可以通过判断该每个存储单元的实时电位是否与第一电位的差值大于第一预设 值来判断该存储单元的存储状态是否异常，从而在目标存储单元的实时电位不接近第一电位时，判断该目标存储单元对应的第二字线对应的字线驱动电路存在栅极缺陷。
在另一些实施例中，也可以通过判断每个存储单元的实时电位与第二电位的差值是否小于第二预设值来判断该存储单元的存储状态是否异常。当一个存储单元的实时电位与第二电位的差值小于第二预设值即目标存储单元的实时电位更接近第二电位时，可以判断该目标存储单元对应的第二字线对应的字线驱动电路存在栅极缺陷。
上述第一预设值和第二预设值均可以由本领域技术人员根据第一电位和第二电位的差值进行自行设置，本公开对此不做特殊限制。
在步骤S4之后，可以通过设置循环测试来实现对全部字线的测试。
在一个实施例中，可以在存储单元阵列中，选取连续排列的2mn条字线作为一个测试模块，对测试模块进行测试，包括：在测试模块中按字线的排列顺序依次选取出m条待测字线，按字线的排列顺序依次设置第一字线，再执行第一写入操作(步骤S2)、第二写入操作(步骤S3)和读取判断操作(步骤S4)，直至2mn条字线均已被设置为第一字线。然后，在存储单元阵列中，按字线排列顺序依次选取每连续排列的2mn条字线作为一个测试模块，再对测试模块进行测试，直至存储单元阵列中的全部字线均已被选取作为测试模块。
例如，如果一个字线驱动电路i对应的字线j的编号为WLij，存储单元阵列两侧的字线驱动电路的序号分别为1、3、5、7和2、4、6、8，每个字线驱动电路均对应4条字线。则，首先可以在步骤S1中选取字线WL11、WL31、WL51、WL71作为待测字线，将WL11设置为第一字线，将WL31、WL51、WL71设置为第二字线，对WL11、WL31、WL51、WL71控制的全部晶体管连接的存储单元均写入第一电位后，对WL11控制的全部晶体管连接的存储单元均写入第二电位，顺次读取WL31、WL51、WL71控制的全部晶体管连接的存储单元的实时电位以判断字线驱动电路1、3、5、7是否存在栅极缺陷。
然后，执行以下选取顺序以实现循环测试：
选取WL21、WL41、WL61、WL81作为待测字线，将WL21设置为第一字线，将WL41、WL61、WL81设置为第二字线进行测试；
选取WL12、WL32、WL52、WL72作为待测字线，将WL12设置为第一字线，将WL32、WL52、WL72设置为第二字线进行测试；
选取WL22、WL42、WL62、WL82作为待测字线，将WL22设置为第一字线，将WL42、WL62、WL82设置为第二字线进行测试；
选取WL13、WL33、WL53、WL73作为待测字线，将WL13设置为第一字线，将WL33、WL53、WL73设置为第二字线进行测试；
选取WL23、WL43、WL63、WL83作为待测字线，将WL23设置为第一字线，将WL43、WL63、WL83设置为第二字线进行测试；
选取WL14、WL34、WL54、WL74作为待测字线，将WL14设置为第一字线，将 WL34、WL54、WL74设置为第二字线进行测试；
选取WL24、WL44、WL64、WL84作为待测字线，将WL24设置为第一字线，将WL44、WL64、WL84设置为第二字线进行测试。
接下来，重复上次选取过程，顺次将WL31、WL41、WL32、WL42、WL33、WL43、WL34、WL44设置为第一字线进行测试。重复以上循环逻辑，直至每条待测位线均已被设置为第一字线参与测试。
在另一个实施例中，还可以设置其他循环方式来实现对存储单元阵列中全部字线的测试。
图8是本公开另一个实施例的流程示意图。
读完全部m-1条第二字线对应的存储单元后，即对本次选取的m条待测字线对应的m-1个字线驱动电路中的一个反向器进行了检测。此时，作为第一字线的待测字线对应的字线驱动电路还没有被检测。因此，参考图8，在一个实施例中，方法100还可以包括：
步骤S81，在m条所述待测字线中选取另一条待测字线作为第三字线；
步骤S82，对所述m条所述待测字线控制的全部晶体管对应连接的存储单元写入第一电位；
步骤S83，对所述第三字线控制的全部晶体管对应连接的存储单元写入所述第二电位；
步骤S84，读取所述第一字线控制的全部晶体管对应连接的存储单元的实时电位，在所述实时电位与所述第一电位的差值大于第一预设值时，判断所述第一字线连接的字线驱动电路具有缺陷。
通过选取第三字线，第一字线连接的晶体管的开关状态与第三字线连接的晶体管的开关状态相反，可以对第一字线连接的字线驱动电路进行测试，进而对本次选取的m条待测字线对应的m个字线驱动电路全部进行了测试。
在另一个实施例中，还可以顺次将本次选取的m条待测字线中的每一条均设置为第一字线进行测试，即对本组m条待测字线共测试m次，以提高筛选出各待测字线对应的字线驱动电路的栅极缺陷的概率。
测试完本次选取的m条待测字线之后，可以在存储单元阵列及其对应的字线驱动电路阵列中继续选取m条待测字线进行测试，直至待测存储单元中的全部字线均已被选取作为待测字线。
测试完当前的存储单元阵列及其对应的字线驱动电路阵列后，可以更换其他存储单元阵列及其对应的字线驱动电路阵列进行测试，直至完成对整个存储器中字线驱动电路的测试。
图9是本公开一个实施例中提供的字线驱动电路缺陷测试装置的方框图。
参考图9，字线驱动电路缺陷测试装置900可以包括：
存储器91；以及
耦合到存储器91的处理器92，处理器92被配置为基于存储在存储器91中的指令，执行如上任一项所述的字线驱动电路缺陷测试方法。
由于装置900执行的功能已在其对应的方法实施例中予以详细说明，本公开于此不再赘述。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，上述附图仅是根据本发明示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例通过选取分别对应m个字线驱动电路的m条待测字线，首先对m条待测字线对应的存储单元均写入第一电位，然后对其中一条待测字线对应的存储单元写入第二电位，可以使存在缺陷的字线驱动电路对应的待测字线对应的存储单元产生介于第一电位和第二电位之间的实时电位，进而通过读取其余待测字线对应的存储单元的实时电位识别出存在缺陷的字线驱动单元。

Claims (11)

  1. 一种字线驱动电路缺陷测试方法，其中，包括：
    在存储单元阵列及其对应的字线驱动电路阵列中，选取m条字线作为待测字线，将m条所述待测字线中的一条设置为第一字线，将其余m-1条设置为第二字线，其中，m条所述待测字线分别对应连接不同的m个字线驱动电路，m为大于1的整数；
    第一写入操作：对所述m条所述待测字线控制的全部晶体管对应连接的存储单元写入第一电位；
    第二写入操作：对所述第一字线控制的全部晶体管对应连接的存储单元写入第二电位；
    读取判断操作：依次读取各所述第二字线控制的全部晶体管对应连接的存储单元的实时电位，在读取到的一个目标存储单元的实时电位与所述第一电位的差值大于第一预设值时，判断所述目标存储单元对应连接的晶体管对应连接的第二字线连接的字线驱动电路具有缺陷；
    其中，所述第一电位与所述第二电位的差值大于等于0.6V。
  2. 如权利要求1所述的字线驱动电路缺陷测试方法，其中，所述字线驱动电路阵列位于所述存储单元阵列的两侧，位于所述存储单元阵列中的多条所述字线呈叉状平行交错排列，相邻的所述字线对应连接的所述字线驱动电路分别位于不同侧的所述字线驱动电路阵列中。
  3. 如权利要求2所述的字线驱动电路缺陷测试方法，其中，所述m条所述待测字线对应连接的m个字线驱动电路位于同一侧的所述字线驱动电路阵列中。
  4. 如权利要求3所述的字线驱动电路缺陷测试方法，其中，所述选取m条字线作为待测字线包括：
    在所述存储单元阵列中，依次间隔2n-1条所述字线选取出所述m条待测字线，其中n为一个所述字线驱动电路连接的所述字线的数量，n为正整数。
  5. 如权利要求1所述的字线驱动电路缺陷测试方法，其中，所述对所述m条所述待测字线控制的全部晶体管对应连接的存储单元写入第一电位包括：
    将所述m条待测字线控制的全部晶体管对应连接的位线全部调整到所述第一电位；
    打开所述m条待测字线控制的全部晶体管，以使所述m条待测字线控制的全部晶体管对应连接的所述存储单元写入所述第一电位。
  6. 如权利要求5所述的字线驱动电路缺陷测试方法，其中，所述对所述第一字线控制的全部晶体管对应连接的存储单元写入第二电位包括：
    关闭所述m条待测字线控制的全部晶体管；
    将所述m条待测字线控制的全部晶体管对应连接的位线全部调整到所述第二电位；
    打开所述第一字线控制的全部晶体管，以使所述第一字线控制的全部晶体管对应连接的所述存储单元写入所述第二电位；
    关闭所述第一字线控制的全部晶体管。
  7. 如权利要求1所述的字线驱动电路缺陷测试方法，其中，所述第一电位为-0.1～0.2V，所述第二电位为0.8～1.1V；或，所述第一电位为0.8～1.1V，所述第二电位为-0.1～0.2V，所述第一预设值等于0.5V。
  8. 如权利要求4所述的字线驱动电路缺陷测试方法，其中，还包括：
    在所述存储单元阵列中，选取连续排列的2mn条字线作为一个测试模块，对所述测试模块进行测试，包括：在所述测试模块中按所述字线的排列顺序依次选取出m条所述待测字线，按所述字线的排列顺序依次设置所述第一字线，再执行所述第一写入操作、所述第二写入操作和所述读取判断操作，直至所述2mn条所述字线均已被设置为所述第一字线。
  9. 如权利要求8所述的字线驱动电路缺陷测试方法，其中，还包括：
    在所述存储单元阵列中，按所述字线排列顺序依次选取每连续排列的2mn条字线作为一个所述测试模块，再对所述测试模块进行所述测试，直至所述存储单元阵列中的全部所述字线均已被选取作为所述测试模块。
  10. 如权利要求4所述的字线驱动电路缺陷测试方法，其中，被选取的所述待测字线的数量m为16，每个所述字线驱动电路对应连接的字线数量n为4。
  11. 一种字线驱动电路缺陷测试装置，其中，包括：
    存储器；以及
    耦合到所述存储器的处理器，所述处理器被配置为基于存储在所述存储器中的指令，执行如权利要求1-10任一项所述的字线驱动电路缺陷测试方法。
PCT/CN2021/103525 2020-08-24 2021-06-30 字线驱动电路缺陷测试方法与装置 WO2022042014A1 (zh)

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