WO2024016426A1 - 存储芯片的测试方法、装置、设备及存储介质 - Google Patents

存储芯片的测试方法、装置、设备及存储介质 Download PDF

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Publication number
WO2024016426A1
WO2024016426A1 PCT/CN2022/114876 CN2022114876W WO2024016426A1 WO 2024016426 A1 WO2024016426 A1 WO 2024016426A1 CN 2022114876 W CN2022114876 W CN 2022114876W WO 2024016426 A1 WO2024016426 A1 WO 2024016426A1
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word lines
memory
test
memory block
word line
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PCT/CN2022/114876
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English (en)
French (fr)
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许兰平
黄建钦
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

Definitions

  • the present disclosure relates to the field of semiconductor technology.
  • the present disclosure relates to, but is not limited to, a memory chip testing method, device, equipment and storage medium.
  • DRAM Dynamic Random Access Memory
  • RAM Dynamic Random Access Memory
  • RAM includes transistors, word lines (Row Address), bit lines (Column Address), capacitors, metal interconnections, and peripheral areas.
  • DRAM needs to go through a series of tests to evaluate its reliability. After the reliability meets the conditions, it can be shipped out of the factory. For example, the memory cells in the DRAM are tested to determine whether the storage and reading and writing data functions of the DRAM are normal. During the test process, there are The risk of memory chip damage and impact on test stability.
  • Embodiments of the present disclosure provide a memory chip testing method, device, equipment and storage medium.
  • embodiments of the present disclosure provide a method for testing a memory chip.
  • the method includes: enabling multiple word lines in a memory array of a memory chip to be tested in groups; wherein, enabling two adjacent groups of words
  • the time interval between lines is a preset time length; when the plurality of word lines are all in an enabled state, multiple memory cells corresponding to the plurality of word lines are tested at the same time.
  • the method further includes: turning on the delay test mode of the memory chip to be tested, obtaining the word line grouping information and the preset time length in the memory array; turning on the memory chip to be tested The multi-word line test mode of the chip; the grouping sequentially enables multiple word lines in the memory array of the memory chip to be tested, including: when the delay test mode and the multi-word line test mode are both turned on , based on the word line grouping information and the preset time length, sequentially enable each group of word lines in the memory chip.
  • the memory array includes at least one memory block, and each memory block includes a plurality of memory cells and a plurality of word lines; the grouping sequentially enables the memory chips in the memory array to be tested.
  • Multiple word lines include: grouping and sequentially enabling multiple word lines in each memory block; wherein word lines at the same position in each memory block are enabled at the same time; in the multiple When the word lines are all in the enabled state, multiple memory cells corresponding to the multiple word lines are tested at the same time, including: the multiple word lines in each of the memory blocks are in the enabled state. Next, multiple memory cells corresponding to the multiple word lines in each memory block are tested at the same time.
  • each of the memory blocks includes M word lines divided into R groups, where R is an integer greater than 1 and less than M; the groups sequentially enable multiple word lines in each of the memory blocks.
  • word lines including: enabling the i-th group of word lines of each memory block; and enabling each of the memory blocks at intervals of the preset time period after enabling the i-th group of word lines of each memory block.
  • the i+1th group of word lines of the block wherein, i is an integer greater than 0 and less than R.
  • the jth group of word lines includes the j+nRth word line, where j is an integer greater than 0 and less than R+1, and n is greater than an integer of 0, and j+nR does not exceed M.
  • the preset time length is less than or equal to tCK/(4R), where tCK is the duration of the enable signal within one clock cycle.
  • testing multiple memory cells corresponding to the plurality of word lines at the same time includes: when the plurality of word lines are in an enabled state, In the enabled state, test data is written to multiple storage units corresponding to the multiple word lines at the same time; target data is read from the multiple storage units at the same time; based on the test data, the The target data is verified to obtain the test results of the storage array.
  • verifying each of the target data to obtain the test results of the storage array includes: performing compression processing on the test data to obtain the first compressed data; performing the above steps on the target data. Perform the compression process to obtain second compressed data; and determine the test result of the storage array based on the consistency of the first compressed data and the second compressed data.
  • a memory chip testing device which device includes: an enabling component configured to group and sequentially enable multiple word lines in a memory array of a memory chip to be tested; wherein, The time interval between two adjacent groups of word lines is a preset time length; the test component is used to simultaneously test multiple words corresponding to the plurality of word lines when the plurality of word lines are in an enabled state. storage unit for testing.
  • the device further includes: a mode enable component, configured to: enable the delay test mode of the memory chip to be tested, and obtain the word line grouping information and the preset time length in the memory array; Turn on the multi-word line test mode of the memory chip to be tested; the enabling component includes: a first enabling unit configured to when both the delay test mode and the multi-word line test mode are turned on, Based on the word line grouping information and the preset time length, each group of word lines in the memory chip is sequentially enabled.
  • the memory array includes at least one memory block, each memory block including a plurality of memory cells and a plurality of word lines;
  • the enabling component includes: a second enabling unit configured to group Multiple word lines in each memory block are enabled in sequence; wherein the word lines at the same position in each memory block are enabled at the same time;
  • the test component includes: a test unit configured to When multiple word lines in the memory block are all in an enabled state, multiple memory cells corresponding to the multiple word lines in each memory block are tested at the same time.
  • each memory block includes M word lines divided into R groups, where R is an integer greater than 1 and less than M; the second enabling unit is further configured to: enable each The i-th group of word lines of the memory block; after enabling the i-th group of word lines of each of the memory blocks, enable the i+1 group of word lines of each of the memory blocks at intervals of the preset time period; Wherein, the i is an integer greater than 0 and less than R.
  • the test component includes a writing unit, a reading unit and a verification unit, wherein the writing unit is configured to: when the plurality of word lines are all in an enabled state, simultaneously Write test data into multiple memory cells corresponding to the multiple word lines; the readout unit is configured to read target data from the multiple memory cells simultaneously; the verification unit is configured to: based on The test data is used to verify the target data to obtain the test results of the storage array.
  • the verification unit includes a first compression subunit, a second compression subunit and a determination subunit; wherein the first compression subunit is configured to compress the test data, obtaining first compressed data; the second compression subunit is configured to perform the compression processing on the target data to obtain second compressed data; the determining subunit is configured to perform the compression process based on the first compressed data and the The consistency of the second compressed data determines the test results of the storage array.
  • an embodiment of the present disclosure provides a memory chip testing device, which device includes: a processor, configured to execute the method described in any of the above embodiments; and configured to store instructions executable by the processor. memory.
  • embodiments of the present disclosure provide a computer-readable storage medium, which when instructions in the storage medium are executed by a processor, enables the processor to perform the method described in any of the above embodiments.
  • multiple word lines in the memory array of the memory chip to be tested are sequentially enabled in groups; wherein, the time interval between enabling two adjacent groups of word lines is a preset time length, so that The order of word line switching can be delayed according to a certain delay, which can reduce the number of internal circuit operations of the memory chip at the same time, thereby reducing the peak current, thereby reducing damage to the memory chip and improving test stability; on the other hand, when multiple word lines are in the enabled state, multiple memory cells corresponding to multiple word lines are tested at the same time. There is no need to test the memory cells corresponding to one word line first, and then test the memory cells corresponding to another word line. The storage unit is tested, so that a lot of time can be saved, thereby saving testing costs.
  • Figure 1 is a schematic diagram of the opening sequence of memory blocks in a multi-storage block delay mode provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the peak current of the pin of a memory chip in the related art in a high compression ratio test mode
  • Figure 3 is a schematic flow chart of the implementation of a memory chip testing method provided by an embodiment of the present disclosure
  • Figure 4 is a schematic diagram of the peak current of the pin when using a memory chip testing method provided by an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram of a storage array provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of multiple word lines in a memory array that groups and sequentially enables memory chips to be tested according to an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of another grouping provided by an embodiment of the present disclosure to sequentially enable multiple word lines in a memory array of a memory chip to be tested;
  • Figure 8 is a schematic flow chart of the implementation of another memory chip testing method provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of a memory chip testing device provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a memory chip testing device provided by an embodiment of the present disclosure.
  • word lines i.e. word lines
  • test time increases accordingly.
  • a high compression ratio test mode is generated; in order to better improve product reliability evaluation, multiple lines are switched on and off at one time.
  • Word line testing methods are also proposed. Under the test method of switching multiple word lines at once, how to reduce damage to the memory chip and improve test stability is a difficult problem.
  • the high compression ratio test mode of DRAM can include the following three types:
  • Multi-Bank compression mode Write data to the storage units (cells) at the same location of multiple banks (banks) at the same time, compress the data of multiple banks and press "0" or "1" output.
  • Multi-DQ compression mode The data (DQ) here is also considered as another dimension of the storage space.
  • the data compression output will operate the multi-DQ according to the logical circuit relationship, and finally output "0" or "1".
  • Multi-WL compression mode Multiple word lines (Word Line, WL) can be enabled at the same time.
  • one activation command can enable multiple banks to open multiple banks at the same time; in Multi-Bank Delay mode, when multiple banks are enabled, They are opened successively.
  • the first memory block 11 is opened first
  • the second memory block 12 is opened after an interval of 2 nanoseconds (ns)
  • the third memory block 13 is opened after an interval of 3 ns.
  • the current of the pin is basically in a stable state; it should be noted that because the devices under test DUT1 to DUT10 have pins under the same command The current difference is small, so the 10 polylines shown in Figure 2 partially overlap.
  • the peak current will cause damage to the DRAM, and the measurement work of the machine will also be limited; on the other hand, the DRAM is unstable in the high compression ratio test mode, resulting in the test only reducing the test compression ratio, thus DRAM Reliability assessment cannot be carried out in a theoretical manner and the test time increases.
  • Embodiments of the present disclosure provide a method for testing a memory chip, which method can be executed by a memory chip testing equipment, such as a memory chip testing machine.
  • a memory chip testing equipment such as a memory chip testing machine.
  • the method includes step S101 and step S102, wherein:
  • Step S101 Group and sequentially enable multiple word lines in the memory array of the memory chip to be tested; wherein, the time interval between enabling two adjacent groups of word lines is a preset time length;
  • the memory chip to be tested may be a memory chip that needs to test whether the storage unit can store data normally, or it may be a memory chip that needs to test whether other functions are normal, or other memory chips that need to test reliability.
  • the memory chips to be tested may include but are not limited to DRAM.
  • the number of memory chips to be tested may be one, two or even multiple, which is not limited in the embodiments of the present disclosure.
  • the memory chip to be tested can include multiple banks, such as 8, 16, etc., and the reading and writing inside each bank can be performed in parallel.
  • Each bank includes row address decoders, column address decoders, sense amplifiers, and memory arrays.
  • the storage array is composed of rows and columns, and each unit where the rows and rows intersect is a storage unit.
  • the memory unit is usually the smallest memory unit in the memory chip.
  • Each memory unit is a unit with the functions of storing data and reading and writing data.
  • Each memory cell is composed of a transistor and a capacitor. The amount of charge stored in the capacitor can represent whether a binary bit is 0 or 1.
  • the word line connected to the transistor in the memory unit can control the on and off of the transistor, and then control the charging and discharging of the capacitor to achieve writing or reading of stored data. Therefore, in order to test the memory chip, it is necessary to enable the word lines in the memory array through activation commands to open the corresponding memory cells.
  • Grouping and sequentially enabling multiple word lines in the memory array of the memory chip to be tested means sequentially enabling multiple word lines according to the order of delaying the word line switching with a certain time delay. This is a word line delay test mode.
  • the word lines in the memory array of the memory chip to be tested can be divided into multiple groups, each group of word lines is enabled in sequence, and the time interval between two adjacent groups of word lines is enabled to be a preset time length. The preset duration can be determined based on the duration of the high level in the activation command and the number of word line groupings.
  • multiple word lines in the memory array of the memory chip to be tested may be multiple word lines in one bank, or may be multiple word lines in multiple banks.
  • Step S102 When multiple word lines are all in the enabled state, multiple memory cells corresponding to the multiple word lines are tested simultaneously.
  • testing multiple memory cells corresponding to the multiple word lines at the same time may include: writing test data to multiple memory cells corresponding to the multiple word lines simultaneously, For example, the data is "0" or "1", and then read the test data to determine whether the read data is consistent with the written data. If they are consistent, the reading and storing data functions of the storage cells in the storage array are normal. If If they are inconsistent, the reading and storing data functions of the storage units in the storage array will be abnormal.
  • multiple word lines in the memory array of the memory chip to be tested are sequentially enabled in groups; wherein, the time interval between enabling two adjacent groups of word lines is a preset time length, so that Multiple word lines can be enabled in sequence according to the sequence of delayed word line switching with a certain delay, which can reduce the number of internal circuit operations of the memory chip at the same time, thus reducing the peak current and thus reducing damage to the memory chip.
  • Improve test stability on the other hand, when multiple word lines are in the enabled state, multiple memory cells corresponding to multiple word lines are tested at the same time, without first testing the memory cells corresponding to one word line. , and then test the memory unit corresponding to another word line, so that a lot of time can be saved, thereby saving testing costs.
  • a memory array includes at least one memory block, each memory block including a plurality of memory cells and a plurality of word lines.
  • the storage array may include one storage block, or may include two or even more storage blocks. The more storage blocks and/or the more storage units in the storage block, the greater the storage density of the corresponding memory chip. , the more data the memory chip can store.
  • step S101 may include:
  • S1011 groups enable multiple word lines in each memory block in sequence; wherein, word lines at the same position in each memory block are enabled at the same time;
  • step S102 may include:
  • Step S102a When multiple word lines in each memory block are in the enabled state, multiple memory cells corresponding to the multiple word lines in each memory block are tested simultaneously.
  • the storage array 20 includes eight storage blocks, namely 21, 22, 23, 24, 25, 26, 27 and 28.
  • Memory block 21 exemplarily shows 8 word lines, respectively WL0, WL1, WL2, WL3, WL4, WL5, WL6, WL7, and the words in memory blocks 22, 23, 24, 25, 26, 27 and 28 Lines may reference memory block 21.
  • WL0, WL2, WL4, and WL6 in memory blocks 21 to 28 can be enabled first, and WL1, WL3, WL5, and WL7 in memory blocks 21 to 28 can be enabled after a preset period of time; storage can also be enabled first.
  • WL0, WL1, WL2 and WL3 in blocks 21 to 28 enable WL4, WL5, WL6 and WL7 in storage blocks 21 to 28 after a preset time period. After that, multiple word lines in each memory block are in the enabled state, and multiple memory cells corresponding to the multiple word lines in each memory block are tested at the same time, so that all memory cells in the memory array can be tested at the same time. Testing the storage units in the block can further save testing time and thereby further save testing costs.
  • each memory block includes M word lines divided into R groups, where R is an integer greater than 1 and less than M.
  • R can be 2, 4, or 6, etc.
  • M can be 8, 16, 32, or 64, etc.
  • step S1011 may include step S111 and step S112, wherein:
  • Step S111 enable the i-th group of word lines of each memory block
  • Step S112 After enabling the i-th group of word lines of each memory block, enable the i+1-th group of word lines of each memory block at a preset time interval; where i is an integer greater than 0 and less than R.
  • the total time for enabling word lines from the first group to the R-th group should not exceed the duration of the high level in one cycle of the clock signal CLK_t.
  • the high level time can be 1/ 2tCK
  • tCK is the duration of the enable signal (ie high level) in one clock cycle. Since the total time for enabling the R group of word lines is (R-1) multiplied by the preset time length, the preset time length may be less than or equal to tCK/(2(R-1)).
  • the preset time length can be less than or equal to tCK/(4R), tCK/(4(R-1)), tCK/ (10(R-1)) or tCK/(10R) and so on. In this way, all word lines can be enabled within the duration of the enable signal in one clock cycle, thus not affecting subsequent timing.
  • the first group of word lines 1/2WL ⁇ 0> includes the 2nd word line, the 4th word line, the 6th word line, the 8th word line, the 10th word line and the 12th word line;
  • the second group Group word line 1/2WL ⁇ 1> includes the 1st word line, the 3rd word line, the 5th word line, the 7th word line, the 9th word line and the 11th word line.
  • the first group of word lines may include a 1st word line, a 2nd word line, a 3rd word line, a 4th word line, a 5th word line and a 6th word line
  • the second group of word lines may include a 7th word line, an 8th word line, a 9th word line, a 10th word line, an 11th word line and a 12th word line.
  • each word line is The word lines included in a group of word lines are not limited. After that, the first group of word lines 1/2WL ⁇ 0> can be enabled.
  • the second group of word lines of each memory block can be enabled at a preset time interval of m1ns.
  • the preset time length m1ns can be less than or equal to tCK/8, or less than or equal to tCK/4.
  • steps S111 and S112 will be described. Refer to Figure 7.
  • the time interval between two adjacent groups of word lines is a preset time length of m2ns.
  • the first group of word lines 1/4WL ⁇ 0> includes the 1st word line, the 5th word line and the 9th word line;
  • the second group of word lines 1/4WL ⁇ 1> includes the 2nd word line, the 6th word line word line and the 10th word line;
  • the third group of word lines 1/4WL ⁇ 2> includes the 3rd word line, the 7th word line and the 11th word line;
  • the word lines included in each group of word lines may also be adjacent. After that, the first group of word lines 1/4WL ⁇ 0> can be enabled.
  • the second group of word lines of each memory block can be enabled at a preset time interval of m2ns.
  • the preset time length m2ns can be less than or equal to tCK/8, or less than or equal to tCK/16.
  • the jth group of word lines includes the j+nRth word line, where j is an integer greater than 0 and less than R+1, n is an integer greater than 0, and j +nR does not exceed M.
  • the word lines included in each group of word lines are not adjacent, which can reduce the influence between adjacent word lines and is more conducive to reducing the peak current.
  • step S102 may further include steps S1021 to S1023, wherein:
  • Step S1021 When multiple word lines are all in the enabled state, test data is written into multiple memory cells corresponding to the multiple word lines at the same time;
  • the test data refers to the data written into the memory unit for testing the read and write functions of the memory unit of the memory chip to be tested.
  • the test data can also be a binary sequence with a certain data bit length, that is, the test data can be any sequence composed of 0s and 1s, or it can also be a sequence of all 0s or a sequence of all 1s.
  • the sequence length of the test data can be set to a fixed length according to the number of memory cells of the memory chip to be tested, such as the number of columns or rows, or it can be simply set to any length.
  • Step S1022 read target data from multiple storage units at the same time
  • the target data here refers to the target data stored in the storage unit when the read operation is in progress.
  • Step S1023 Verify the target data based on the test data to obtain the test results of the storage array.
  • the read target data can be verified according to the written test data, and the test results of the storage array can be obtained, where the test results of the storage array can include normal and abnormal.
  • test data is written to multiple storage units corresponding to multiple word lines at the same time, and target data is read from multiple storage units at the same time. Based on the test data, the target data is verified to obtain the storage Array test results. In this way, data can be written or read to multiple memory cells through one command, without having to write data or read data multiple times in rows and columns to the memory cells in the storage array, thereby improving the testing efficiency of the memory chip.
  • step S1023 may include step S1231, step S1232 and step S1233, wherein:
  • Step S1231 perform compression processing on the test data to obtain first compressed data
  • Compression of test data refers to a technology that reduces the amount of test data to reduce storage space and improve its transmission, storage and processing efficiency without losing information.
  • the test data including 8-bit data as an example.
  • the compression process can be to perform logical operations on the 8-bit data of 11111111 to obtain 4-bit, 2-bit or 1-bit data. For example, convert 11111111 to Perform XOR operation on 8-bit data, thus obtaining 1-bit first compressed data 0.
  • compressing the test data may include multiple storage units as a compression group, and then compressing the data in the compression group to obtain the first compressed data.
  • the compression processing method of the test data is not limited, and it is only necessary to reduce the number of bits of the test data.
  • Step S1232 perform compression processing on the target data to obtain second compressed data
  • the compression processing of the target data and the compression processing of the test data need to be the same, so that the first compressed data and the second compressed data can be compared in the subsequent process to determine the test results of the storage array. For example, if the target data is 10111111, perform an XOR operation on the 8-bit data of 10111111, and the second compressed data obtained is 1.
  • Step S1233 Determine the test result of the storage array based on the consistency of the first compressed data and the second compressed data.
  • the read and write functions of the storage units in the storage array are not abnormal, and the test results of the storage array can be normal; when the first compressed data and the second compressed data are inconsistent In the case of, for example, the first compressed data is 0, the second compressed data is 1, the read and write functions of the storage units in the storage array are abnormal, and the test results of the storage array may be abnormal.
  • the first compressed data and the second compressed data are obtained by respectively compressing the test data and the target data; and based on the consistency of the first compressed data and the second compressed data, the test result of the storage array is determined, This can improve the testing efficiency of memory chips and shorten the testing time.
  • An embodiment of the present disclosure provides a memory chip testing method. Referring to Figure 8, the method includes steps S301 to S304, wherein:
  • Step S301 turn on the delay test mode of the memory chip to be tested, and obtain the word line grouping information and preset time length in the memory array;
  • the delay test mode is to enable multiple word lines in the memory array of the memory chip to be tested to be grouped and enabled sequentially.
  • the delay test pattern can include word line grouping information in the memory array.
  • the even word lines (Even WL) are divided into one group and the odd word lines (Odd WL) are divided into one group.
  • the memory array includes 16 Word lines, divide the 16 word lines into 4 groups, the 1st word line, the 5th word line, the 9th word line, and the 13th word line are one group, the 2nd word line, the 6th word line, The 10th word line and the 14th word line are a group.
  • the 3rd word line, the 7th word line, the 11th word line and the 15th word line are a group.
  • the 4th word line and the 8th word line are a group.
  • the first word line, the 12th word line, and the 16th word line are one group; the delay test mode can also include enabling the time interval between two adjacent groups of word lines, that is, the preset time length, for example, the preset time length is 2ns.
  • Step S302 turn on the multi-word line test mode of the memory chip to be tested
  • the multi-word line test mode is the multi-word line compression mode, that is, multiple word lines can be enabled at the same time.
  • Step S303 when both the delay test mode and the multi-word line test mode are turned on, each group of word lines in the memory chip is sequentially enabled based on the word line grouping information and the preset time length;
  • the following will take the memory array including 16 word lines divided into 4 groups as an example.
  • first enable the first group of word lines that is, the 1st group of word lines.
  • Word line 5th word line, 9th word line, 13th word line; after an interval of 2ns, enable the second group of word lines, that is, 2nd word line, 6th word line, 10th word line line, the 14th word line; after an interval of 2ns, enable the third group of word lines, that is, the 3rd word line, the 7th word line, the 11th word line, and the 15th word line; after an interval of 2ns, enable
  • the fourth group of word lines can be used, that is, the 4th word line, the 8th word line, the 12th word line, and the 16th word line.
  • Step S304 When multiple word lines are all in the enabled state, multiple memory cells corresponding to the multiple word lines are tested simultaneously.
  • step S304 may refer to step S102.
  • step S301 and step S302 are not limited. Step S301 can be executed first, and then step S302 can be executed; step S302 can also be executed first, and then step S301 can be executed; of course, step S301 and step S301 can also be executed at the same time. S302.
  • the delay test mode and the multi-word line test mode of the memory chip to be tested are turned on, the word line grouping information in the memory array is automatically obtained, and the time interval between two adjacent groups of word lines is enabled, which is the predetermined time interval. Set the time length, and enable multiple word lines at the same time. In the subsequent process, there is no need to configure the word line grouping information and the preset time length.
  • the memory chip can be automatically obtained and sequentially enabled based on the word line grouping information and the preset time length. Each group of word lines, and when multiple word lines are in the enabled state, multiple memory cells corresponding to the multiple word lines are tested at the same time. In this way, the testing method of the memory chip can be simplified.
  • An embodiment of the present disclosure provides a memory chip testing device.
  • the device includes:
  • the enabling component 910 is used to group and sequentially enable multiple word lines in the memory array of the memory chip to be tested; wherein the time interval between enabling two adjacent groups of word lines is a preset time length;
  • the test component 920 is used to test multiple memory cells corresponding to the multiple word lines at the same time when the multiple word lines are in an enabled state.
  • multiple word lines in the memory array of the memory chip to be tested are sequentially enabled in groups; wherein, the time interval between enabling two adjacent groups of word lines is a preset time length, so that The order of word line switching can be delayed according to a certain delay, which can reduce the number of internal circuit operations of the memory chip at the same time, thereby reducing the peak current, thereby reducing damage to the memory chip and improving test stability; on the other hand, when multiple word lines are in an enabled state, multiple memory cells corresponding to multiple word lines are tested at the same time. In this way, a lot of time can be saved, thereby saving testing costs.
  • the memory chip testing device further includes: a mode opening component, configured to: turn on the delay test mode of the memory chip to be tested, and obtain the word line grouping information and the preset time length in the memory array; turn on the delay test mode of the memory chip to be tested;
  • the enabling component includes: a first enabling unit configured to, when both the delay test mode and the multi-word line test mode are turned on, based on the word line grouping information and the preset time length, Each group of word lines in the memory chip is enabled in turn.
  • the delay test mode and the multi-word line test mode of the memory chip to be tested are turned on, the word line grouping information in the memory array is automatically obtained, and the time interval between two adjacent groups of word lines is enabled, which is the predetermined time interval. Set the duration, and enable multiple word lines at the same time. In the subsequent process, there is no need to set additional components to configure the word line grouping information and preset duration. It can be automatically obtained and enabled sequentially based on the word line grouping information and preset duration. Each group of word lines in the memory chip tests multiple memory cells corresponding to the multiple word lines at the same time when multiple word lines are in an enabled state. In this way, the test device of the memory chip can be simplified.
  • the memory array includes at least one memory block, each memory block includes a plurality of memory cells and a plurality of word lines; the enabling component includes: a second enabling unit configured to enable each memory block in sequence. Multiple word lines in the block; wherein, the word lines at the same position in each memory block are enabled at the same time; the test component includes: a test unit configured such that multiple word lines in each memory block are in an enabled state In this case, multiple memory cells corresponding to multiple word lines in each memory block are tested at the same time. In this way, the storage cells in all storage blocks in the storage array can be tested at the same time, which can further save testing time and thereby further save testing costs.
  • each memory block includes M word lines divided into R groups, where R is an integer greater than 1 and less than M; the second enabling unit is further configured to: enable the i-th group of each memory block Word lines; after enabling the i-th group of word lines of each memory block, enable the i+1th group of word lines of each memory block at a preset time interval; where i is an integer greater than 0 and less than R.
  • the jth group of word lines includes the j+nRth word line, where j is an integer greater than 0 and less than R+1, n is an integer greater than 0, and j +nR does not exceed M.
  • the word lines included in each group of word lines are not adjacent, which can reduce the influence between adjacent word lines and is more conducive to reducing the peak current.
  • the preset time length is less than or equal to tCK/(4R), and tCK is the duration of the enable signal within one clock cycle. In this way, all word lines can be enabled within the duration of the enable signal in one clock cycle, thus not affecting subsequent timing.
  • the test component includes a writing unit, a reading unit and a verification unit, wherein the writing unit is configured to: when multiple word lines are in an enabled state, simultaneously respond to multiple word lines.
  • the writing unit is configured to: when multiple word lines are in an enabled state, simultaneously respond to multiple word lines.
  • Write test data into multiple storage units; the read unit is configured to read target data from multiple storage units at the same time; the verification unit is configured to: based on the test data, verify the target data to obtain the storage array Test Results.
  • test data is written to multiple storage units corresponding to multiple word lines at the same time, and target data is read from multiple storage units at the same time. Based on the test data, the target data is verified to obtain the storage Array test results. In this way, data can be written or read to multiple memory cells through one command, without having to write data or read data multiple times in rows and columns to the memory cells in the storage array, thereby improving the testing efficiency of the memory chip.
  • the verification unit includes a first compression subunit, a second compression subunit and a determination subunit; wherein the first compression subunit is configured to compress the test data to obtain first compressed data; The second compression subunit is configured to compress the target data to obtain second compressed data; the determination subunit is configured to determine the test result of the storage array based on the consistency of the first compressed data and the second compressed data.
  • the first compressed data and the second compressed data are obtained by respectively compressing the test data and the target data; and based on the consistency of the first compressed data and the second compressed data, the test result of the storage array is determined, This can improve the testing efficiency of memory chips and shorten the testing time.
  • the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments.
  • the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments.
  • the features similar to those in the method embodiments are beneficial effects.
  • An embodiment of the present disclosure also provides a memory chip testing equipment.
  • the equipment includes:
  • Processor 100 configured to execute the steps in the above embodiment of the memory chip testing method
  • Memory 1002 for storing instructions executable by processor 1001.
  • the processor can also be called a central processing unit (Central Processing Unit, CPU).
  • the processor may be an integrated circuit chip that has signal processing capabilities.
  • the processor can also be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field-Programmable Gate Array, FPGA) or other available Programmed logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the processor can be implemented by integrated circuit chips.
  • Embodiments of the present disclosure provide a computer-readable storage medium, which when instructions in the storage medium are executed by a processor, enables the processor to perform the steps in the above embodiment of the method for testing a memory chip.
  • the storage medium can include: U disk, mobile hard disk, read-only memory (Read Only Memory, ROM), magnetic disk or optical disk and other various media that can store program code.
  • U disk mobile hard disk
  • read-only memory Read Only Memory
  • ROM Read Only Memory
  • magnetic disk or optical disk and other various media that can store program code.
  • the embodiments of the present disclosure are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the components shown or discussed are coupled to each other, or directly coupled.
  • the units described above as separate components may or may not be physically separated.
  • the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • multiple word lines in the memory array of the memory chip to be tested are sequentially enabled in groups; wherein, the time interval between enabling two adjacent groups of word lines is a preset time length, so that The order of word line switching can be delayed according to a certain delay, which can reduce the number of internal circuit operations of the memory chip at the same time, thereby reducing the peak current, thereby reducing damage to the memory chip and improving test stability; on the other hand, when multiple word lines are in the enabled state, multiple memory cells corresponding to multiple word lines are tested at the same time. There is no need to test the memory cells corresponding to one word line first, and then test the memory cells corresponding to another word line. The storage unit is tested, so that a lot of time can be saved, thereby saving testing costs.

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Abstract

一种存储芯片的测试方法、装置、设备及存储介质。其中，所述方法包括：分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长（S101）；在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试（S102）。

Description

存储芯片的测试方法、装置、设备及存储介质
相关申请的交叉引用
本公开基于申请号为202210869272.X、申请日为2022年07月22日、发明名称为“存储芯片的测试方法、装置、设备及存储介质”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，本公开涉及但不限于一种存储芯片的测试方法、装置、设备及存储介质。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种广泛应用多计算机系统的半导体存储器。DRAM包括晶体管、字元线(Row Address)、位元线(Column Address)、电容、金属互连和外缘区域等。
DRAM需要经过一系列测试对其可靠性进行评估，可靠性满足条件后才能出厂应用，例如，对DRAM中的存储单元进行测试，确定DRAM的存储和读写数据功能是否正常，在测试过程中存在存储芯片受损的风险且影响测试稳定性。
发明内容
本公开实施例提供一种存储芯片的测试方法、装置、设备及存储介质。
一方面，本公开实施例提供一种存储芯片的测试方法，所述方法包括：分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长；在所述多条字线均处于使能状态的情况下，同时对所述多条字线对应的多个存储单元进行测试。
在一些实施例中，所述方法还包括：开启所述待测试的存储芯片的延迟测试模式，得到所述存储阵列中的字线分组信息和所述预设时长；开启所述待测试的存储芯片的多字线测试模式；所述分组依次使能待测试的存储芯片的存储阵列中的多条字线，包括：在所述延迟测试模式和所述多字线测试模式均开启的情况下，基于所述字线分组信息和所述预设时长，依次使能所述存储芯片中每一组字线。
在一些实施例中，所述存储阵列包括至少一个存储块，每一所述存储块中包括多个存储单元和多条字线；所述分组依次使能待测试的存储芯片的存储阵列中的多条字线，包括：分组依次使能每一所述存储块中的多条字线；其中，所述每一所述存储块中相同位置的字线同时被使能；在所述多条字线均处于使能状态的情况下，同时对所述多条字线对应的多个存储单元进行测试，包括：在每一所述存储块中的多条字线均处于使能状态的情况下，同时对每一所述存储块中所述多条字线对应的多个存储单元进行测试。
在一些实施例中，每一所述存储块包括分为R组的M条字线，所述R为大于1且小于M的整数；所述分组依次使能每一所述存储块中的多条字线，包括：使能每一所述存储块的第i组字线；在使能每一所述存储块的第i组字线之后间隔所述预设时长使能每一所述存储块的第i+1组字线；其中，所述i为大于0且小于R的整数。
在一些实施例中，在每一所述存储块中，第j组字线包括第j+nR条字线，其中，所述j为大于0且小于R+1的整数，所述n为大于0的整数，且所述j+nR不超过M。
在一些实施例中，所述预设时长小于等于tCK/(4R)，所述tCK为一个时钟周期内使能信号持续的时间。
在一些实施例中，在所述多条字线均处于使能状态的情况下，同时对所述多条字线对应的多个存储单元进行测试，包括：在所述多条字线均处于使能状态的情况下，同时向所述多条字线对应的多个存储单元中写入测试数据；同时从所述多个存储单元中读出目标数据；基于所述测试数据，对所述目标数据进行校验，得到所述存储阵列的测试结果。
在一些实施例中，对每一所述目标数据进行校验，得到所述存储阵列的测试结果，包括：对所述测试数据进行压缩处理，得到第一压缩数据；对所述目标数据进行所述压缩处理，得到第二压缩数据；基于所述第一压缩数据和所述第二压缩数据的一致性，确定所述存储阵列的测试结果。
另一方面，本公开实施例提供一种存储芯片的测试装置，所述装置包括：使能组件，用于分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长；测试组件，用于在所述多条字线均处于使能状态的情况下，同时对所述多条字线对应的多个存储单元进行测试。
在一些实施例中，所述装置还包括：模式开启组件，用于：开启所述待测试的存储芯片的延迟测试模式，得到所述存储阵列中的字线分组信息和所述预设时长；开启所述待测试的存储芯片的多字线测试模式；所述使能组件包括：第一使能单元，配置为在所述延迟测试模式和所述多字线测试模式均开启的情况下，基于所述字线分组信息和所述预设时长，依次使能所述存储芯片中每一组字线。
在一些实施例中，所述存储阵列包括至少一个存储块，每一所述存储块中包括多个存储单元和多条字线；所述使能组件包括：第二使能单元，配置为分组依次使能每一所述存储块中的多条字线；其中，所述每一所述存储块中相同位置的字线同时被使能；所述测试组件包括：测试单元，配置为在每一所述存储块中的多条字线均处于使能状态的情况下，同时对每一所述存储块中所述多条字线对应的多个存储单元进行测试。
在一些实施例中，每一所述存储块包括分为R组的M条字线，所述R为大于1且小于M的整数；所述第二使能单元还配置为：使能每一所述存储块的第i组字线；在使能每一所述存储块的第i组字线之后间隔所述预设时长使能每一所述存储块的第i+1组字线；其中，所述i为大于0且小于R的整数。
在一些实施例中，所述测试组件包括写入单元、读出单元和校验单元，其中，所述写入单元配置为：在所述多条字线均处于使能状态的情况下，同时向所述多条字线对应的多个存储单元中写入测试数据；所述读出单元配置为：同时从所述多个存储单元中读出目标数据；所述校验单元配置为：基于所述测试数据，对所述目标数据进行校验，得到所述存储阵列的测试结果。
在一些实施例中，所述校验单元包括第一压缩子单元、第二压缩子单元和确定子单元；其中，所述第一压缩子单元，配置为对所述测试数据进行压缩处理，得到第一压缩数据；所述第二压缩子单元，配置为对所述目标数据进行所述压缩处理，得到第二压缩数据；所述确定子单元，配置为基于所述第一压缩数据和所述第二压缩数据的一致性，确定所述存储阵列的测试结果。
再一方面，本公开实施例提供一种存储芯片的测试设备，所述设备包括：处理器，用于执行上述任一实施例中所述的方法；用于存储所述处理器可执行指令的存储器。
又一方面，本公开实施例提供一种计算机可读存储介质，当所述存储介质中的指令由处理器执行时，使得处理器能够执行上述任一实施例中所述的方法。
本公开实施例中，一方面，分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长，这样可以按照一定的时延延迟字线开关的顺序，可以减少同一时间存储芯片内部电路工作的数量，从而可以减小峰值电流，进而可以减少存储芯片受损的情况并且提高测试稳定性；另一方面，在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试，无需先对一条字线对应的存储单元进行测试，再对另一条字线对应的存储单元进行测试，这样，可以节省大量的时间，从而节省测试成本。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本公开实施例提供的一种多存储块延迟模式下存储块的打开顺序示意图；
图2为相关技术中的存储芯片在高压缩比测试模式下引脚的峰值电流示意图；
图3为本公开实施例提供的一种存储芯片的测试方法的实现流程示意图；
图4为采用本公开实施例提供存储芯片的测试方法时引脚的峰值电流示意图；
图5为本公开实施例提供的一种存储阵列的组成结构示意图；
图6为本公开实施例提供的一种分组依次使能待测试的存储芯片的存储阵列中的多条字线示意图；
图7为本公开实施例提供的另一种分组依次使能待测试的存储芯片的存储阵列中的多条字线示意图；
图8为本公开实施例提供的另一种存储芯片的测试方法的实现流程示意图；
图9为本公开实施例提供的一种存储芯片的测试装置的组成结构示意图；
图10为本公开实施例提供的一种存储芯片的测试设备的组成结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸 大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
随着DRAM存储容量的增加，字线(即字元线)数目逐渐增多，测试时间也相应增加，随之高压缩比测试模式产生；为了更好地提高产品可靠性评估，一次性开关多条字线的测试方法也被提出。在一次性开关多条字线的测试方法下，如何减少存储芯片受损的情况并且提高测试稳定性是一难题。
在介绍本公开实施例的技术方案之前，先介绍一下相关技术中的存储芯片例如DRAM的高压缩比测试模式，DRAM的高压缩比测试模式可以包括以下三种：
1、多存储块(Multi-Bank)压缩模式：向多个存储块(bank)相同位置的存储单元(cell)同时写入数据，将多个bank的数据压缩后按“0”或“1”输出。
2、多数据(Multi-DQ)压缩模式：这里的数据(DQ)也被认作是存储空间的另外一个维度，数据压缩输出会将多DQ按照逻辑电路关系进行运算，最后输出“0”或“1”。
3、多字线(Multi-WL)压缩模式：多条字线(Word Line，WL)在同一时间内可以被使能。
在Multi-Bank压缩模式下，一个激活命令(ACT)可以使能多个bank，从而同时打开多个bank；在多存储块延迟(Multi-Bank Delay)模式下，在多个bank使能时可以先后打开，例如参考图1，第一个存储块11先打开， 间隔2纳秒(ns)后第二个存储块12打开，间隔3ns后第三个存储块13打开。
在利用上述三种测试模式对DRAM进行测试的过程中，由于一个激活命令可以使能多个数据、多个存储块以及一个存储块中的多条字线，这样，同一时间内DRAM多个内部电路会同时工作，就会产生如图2所示的峰值电流，从图2中可以看出被测装置DUT1至DUT10在激活命令(ACT)下引脚的电流都会有一个峰值，峰值达到200毫安(mA)，在无操作命令(NOP)和预充电命令(PRE)下，引脚的电流基本上都处于稳定状态；需要说明的是，由于被测装置DUT1至DUT10在同一命令下引脚的电流相差较小，所以图2示出的10条折线有部分重叠。一方面，峰值电流会造成DRAM受损，同时机台的测量工作也会受限；另一方面，DRAM在高压缩比测试模式下工作状态不稳定，导致测试只能降低测试压缩比，从而DRAM可靠性评估不能按照理论方式进行，测试时间增长。
本公开实施例提供一种存储芯片的测试方法，该方法可以由存储芯片的测试设备例如存储芯片的测试机台来执行。参考图3，该方法包括步骤S101和步骤S102，其中：
步骤S101，分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长；
这里，待测试的存储芯片可以是需要测试存储单元是否可以正常存储数据的存储芯片，也可以是需要测试其他功能是否正常的存储芯片以及其他需要测试可靠性的存储芯片。在实施时，待测试的存储芯片可以包括但不限于DRAM。待测试的存储芯片的个数可以为一个、两个甚至多个，本公开实施例对此并不限定。
待测试的存储芯片可以包括多个bank，例如8个、16个等，每个bank内部的读写可以并行进行。每个bank内部包括行地址解码器、列地址解码器、感应放大器以及存储阵列等。存储阵列由行列组成，每个行列交叉的单元即为一个存储单元。存储单元通常为存储芯片中最小的存储单元，每个存储单元是具有存储数据和读写数据功能的单元。每个存储单元由一个晶体管和电容组成，利用电容内存储电荷的多少可以代表一个二进制比特是0还是1。与存储单元中的晶体管连接的字线可以控制晶体管的导通与关断，进而控制电容的充放电，以实现存储资料的写入或读出。因此，为了测试存储芯片，需要通过激活命令使能存储阵列中的字线，以打开对应的存储单元。
分组依次使能待测试的存储芯片的存储阵列中的多条字线就是按照一定的时延延迟字线开关的顺序，依次使能多条字线，这是一种字线延迟测试模式，实施时，可以将待测试的存储芯片的存储阵列中的字线分成多组，按顺序依次使能每一组字线，使能相邻的两组字线之间的时间间隔为预设时长。预设时长可以根据激活命令中高电平持续的时间以及字线分组的组 数来确定。
需要说明的是，待测试的存储芯片的存储阵列中的多条字线可以是一个bank中的多条字线，也可以是多个bank中的多条字线。
步骤S102，在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试。
这里，在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试可以包括：向多条字线对应的多个存储单元同时写入测试数据，例如数据“0”或“1”，再将测试数据读出，判断读出的数据与写入的数据是否一致，若一致，则存储阵列中的存储单元的读取与存储数据功能正常，若不一致，则存储阵列中的存储单元的读取与存储数据功能异常。
由于多条字线是分组依次使能的，并且使能相邻的两组字线之间的时间间隔为预设时长，同一时间就不会有多条字线同时使能，这样可以减小峰值电流。从图4中可以看出，在采用本公开实施例中的存储阵列的测试方法的情况下，各个被测装置(包括DUT1至DUT10)在激活命令下的引脚的电流均小于110mA。相较于图2，峰值电流减小，从而可以减少存储芯片受损的情况，而且由于峰值电流减小，存储芯片在高压缩比下工作状态稳定性提高，可以使DRAM可靠性评估可以按照理论方式进行，可以节省测试时间。
本公开实施例中，一方面，分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长，这样可以按照一定的时延延迟字线开关的顺序，依次使能多条字线，可以减少同一时间存储芯片内部电路工作的数量，从而可以减小峰值电流，进而可以减少存储芯片受损的情况并且提高测试稳定性；另一方面，在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试，无需先对一条字线对应的存储单元进行测试，再对另一条字线对应的存储单元进行测试，这样，可以节省大量的时间，从而节省测试成本。
在一些实施例中，存储阵列包括至少一个存储块，每一存储块中包括多个存储单元和多条字线。在实施时，存储阵列可以包括一个存储块，也可以包括两个甚至多个存储块，存储块越多、和/或存储块中的存储单元越多，对应的存储芯片的存储密度就越大，存储芯片存储的数据就越多。
在一些实施例中，步骤S101的实施可以包括：
S1011，分组依次使能每一存储块中的多条字线；其中，每一存储块中相同位置的字线同时被使能；
步骤S102的实施可以包括：
步骤S102a，在每一存储块中的多条字线均处于使能状态的情况下，同时对每一存储块中多条字线对应的多个存储单元进行测试。
例如，参考图5，存储阵列20中包括8个存储块，分别为21、22、23、 24、25、26、27和28。存储块21示例性地示出了8条字线，分别为WL0、WL1、WL2、WL3、WL4、WL5、WL6、WL7，存储块22、23、24、25、26、27和28中的字线可以参考存储块21。在实施时，可以先使能存储块21至28中的WL0、WL2、WL4和WL6，预设时长后使能存储块21至28中的WL1、WL3、WL5和WL7；也可以先使能存储块21至28中的WL0、WL1、WL2和WL3，预设时长后使能存储块21至28中的WL4、WL5、WL6和WL7。之后在每一存储块中的多条字线均处于使能状态下，同时对每一存储块中的多条字线对应的多个存储单元进行测试，这样可以同时对存储阵列中的所有存储块中的存储单元进行测试，可以进一步节省测试时间，从而进一步节省测试成本。
在一些实施例中，每一存储块包括分为R组的M条字线，R为大于1且小于M的整数。这里，R可以为2、4或6等等，M可以为8、16、32或64等等。
在一些实施例中，步骤S1011的实施可以包括步骤S111和步骤S112，其中：
步骤S111，使能每一存储块的第i组字线；
步骤S112，在使能每一存储块的第i组字线之后间隔预设时长使能每一存储块的第i+1组字线；其中，i为大于0且小于R的整数。
这里，为了减少对后续时序的影响，第一组到第R组字线使能的总时间应该不超过时钟信号CLK_t中一个周期内高电平持续的时间，高电平的时间可以是1/2tCK，tCK为一个时钟周期内使能信号(即高电平)持续的时间。由于R组字线使能的总时间是(R-1)乘以预设时长，因此，预设时长可以小于等于tCK/(2(R-1))。在一些实施例中，由于存储芯片内部电路使能也需要时间，为了不卡住内部的时序，预设时长可以小于等于tCK/(4R)、tCK/(4(R-1))、tCK/(10(R-1))或tCK/(10R)等等。这样可以在一个时钟周期内使能信号持续的时间段内使能所有的字线，从而不影响后续的时序。
下面以R等于2、M等于12为例，对步骤S111和步骤S112进行说明，参考图6，在时钟信号CLK_t的上升沿，响应于激活命令ACT开始使能所有的字线，使能相邻的两组字线之间的时间间隔为预设时长m1ns。第一组字线1/2WL<0>包括第2条字线、第4条字线、第6条字线、第8条字线、第10条字线和第12条字线；第二组字线1/2WL<1>包括第1条字线、第3条字线、第5条字线、第7条字线、第9条字线和第11条字线。在另一些实施方式中，第一组字线可以包括第1条字线、第2条字线、第3条字线、第4条字线、第5条字线和第6条字线，第二组字线可以包括第7条字线、第8条字线、第9条字线、第10条字线、第11条字线和第12条字线，本公开实施例中对每一组字线中所包括的字线并不限定。之后可以使能第一组字线1/2WL<0>，在使能每一存储块的第一组字线1/2WL<0>之后间隔预 设时长m1ns使能每一存储块的第二组字线1/2WL<1>。这里，预设时长m1ns可以小于等于tCK/8，也可以小于等于tCK/4。
下面再以R等于4、M等于12为例，对步骤S111和步骤S112进行说明，参考图7，在时钟信号CLK_t的上升沿，响应于激活命令ACT开始使能所有的字线，使能相邻的两组字线之间的时间间隔为预设时长m2ns。第一组字线1/4WL<0>包括第1条字线、第5条字线和第9条字线；第二组字线1/4WL<1>包括第2条字线、第6条字线和第10条字线；第三组字线1/4WL<2>包括第3条字线、第7条字线和第11条字线；第四组字线1/4WL<3>包括第4条字线、第8条字线和第12条字线。在另一些实施方式中，每一组字线中包括的字线也可以相邻。之后可以使能第一组字线1/4WL<0>，在使能每一存储块的第一组字线1/4WL<0>之后间隔预设时长m2ns使能每一存储块的第二组字线1/4WL<1>，在使能每一存储块的第二组字线1/4WL<1>之后间隔预设时长m2ns使能每一存储块的第三组字线1/4WL<2>，在使能每一存储块的第三组字线1/4WL<2>之后间隔预设时长m2ns使能每一存储块的第四组字线1/4WL<3>。这里，预设时长m2ns可以小于等于tCK/8，也可以小于等于tCK/16。
在一些实施例中，在每一存储块中，第j组字线包括第j+nR条字线，其中，j为大于0且小于R+1的整数，n为大于0的整数，且j+nR不超过M。这样，每一组字线中包括的字线均不相邻，这样可以减小相邻字线之间的影响，更有利于减小峰值电流。
在一些实施例中，步骤S102的实施可以还包括步骤S1021至步骤S1023，其中：
步骤S1021，在多条字线均处于使能状态的情况下，同时向多条字线对应的多个存储单元中写入测试数据；
这里，测试数据指用于测试待测试的存储芯片的存储单元的读写功能而被写入存储单元的数据，同时，由于待测试的存储芯片中是以二进制形式来存储数据的，所以测试数据也可以是具有一定数据位长度的二进制序列，即测试数据可以是由0和1构成的任意序列，或者也可以是全0序列或全1序列。测试数据的序列长度可以按照待测试的存储芯片的存储单元的数量，如列数或行数等设置为固定长度，或者也可以简单设置为任意长度。
在多条字线均处于使能状态的情况下，也就是多条字线的电压达到字线开启电压时，多条字线对应的多个存储单元中的晶体管就会打开，从而可以通过位线读取存储在电容中的数据或者通过位线将数据写入到电容中进行存储。
步骤S1022，同时从多个存储单元中读出目标数据；
在存储单元中写入测试数据之后，通过读取操作读取存储单元中存储的与写入的测试数据对应的目标数据，这里的目标数据指的是读取操作进 行时，存储单元中存储的与测试数据对应的实时数据。
步骤S1023，基于测试数据，对目标数据进行校验，得到存储阵列的测试结果。
根据写入的测试数据可以对读出的目标数据进行校验，就可以得到存储阵列的测试结果，其中，存储阵列的测试结果可以包括正常和异常。
本公开实施例中，同时向多条字线对应的多个存储单元中写入测试数据，并同时从多个存储单元中读出目标数据，基于测试数据，对目标数据进行校验，得到存储阵列的测试结果。这样可以通过一个命令对多个存储单元进行写入数据或者读取数据，不必对存储阵列中的存储单元进行多次一行一列的写入数据或者读取数据，从而可以提高存储芯片的测试效率。
在一些实施例中，步骤S1023的实施可以包括步骤S1231、步骤S1232和步骤S1233，其中：
步骤S1231，对测试数据进行压缩处理，得到第一压缩数据；
对测试数据进行压缩处理是指在不丢失信息的前提下，缩减测试数据的数量以减少存储空间，提高其传输、存储和处理效率的一种技术。以测试数据包括8比特(bit)的数据为例，在测试数据为11111111的情况下，压缩处理可以是对11111111这8bit数据进行逻辑运算，得到4bit、2bit或者1bit的数据，例如，将11111111这8bit数据进行异或运算，这样得到1bit的第一压缩数据0。
在一些实施例中，对测试数据进行压缩处理可以是将多个存储单元作为一个压缩组，之后对压缩组中的数据进行压缩处理，从而得到第一压缩数据。本公开实施例中对测试数据的压缩处理方式并不限定，只需将测试数据的比特数减小即可。
步骤S1232，对目标数据进行压缩处理，得到第二压缩数据；
这里，对目标数据进行的压缩处理与对测试数据的压缩处理方式需要相同，这样才可以在后续过程中对比第一压缩数据和第二压缩数据，从而确定存储阵列的测试结果。例如，目标数据是10111111，对10111111这8bit数据进行异或运算，这样得到的第二压缩数据就是1。
步骤S1233，基于第一压缩数据和第二压缩数据的一致性，确定存储阵列的测试结果。
这里，在第一压缩数据与第二压缩数据一致的情况下，存储阵列中的存储单元的读写功能没有异常，存储阵列的测试结果可以为正常；在第一压缩数据与第二压缩数据不一致的情况下，例如，第一压缩数据为0，第二压缩数据为1，存储阵列中的存储单元的读写功能有异常，存储阵列的测试结果可以为异常。
本公开实施例中，通过对测试数据和目标数据分别进行压缩，得到第一压缩数据和第二压缩数据；并基于第一压缩数据和第二压缩数据的一致性，确定存储阵列的测试结果，这样可以提高存储芯片的测试效率，缩短 测试时间。
本公开实施例提供一种存储芯片的测试方法，参考图8，该方法包括步骤S301至步骤S304，其中：
步骤S301，开启待测试的存储芯片的延迟测试模式，得到存储阵列中的字线分组信息和预设时长；
这里，延迟测试模式就是使待测试的存储芯片的存储阵列中的多条字线可以分组依次使能。延迟测试模式中可以包括存储阵列中的字线分组信息，例如，将偶数字线(Even WL)分成一组，将奇数字线(Odd WL)分成一组，又例如，存储阵列中包括16条字线，将16字线分成4组，第1条字线、第5条字线、第9条字线、第13条字线为一组，第2条字线、第6条字线、第10条字线、第14条字线为一组，第3条字线、第7条字线、第11条字线、第15条字线为一组，第4条字线、第8条字线、第12条字线、第16条字线为一组；延迟测试模式中还可以包括使能相邻的两组字线之间的时间间隔即预设时长，例如，预设时长为2ns。
步骤S302，开启待测试的存储芯片的多字线测试模式；
这里，多字线测试模式就是多字线压缩模式，即多条字线在同一时间内可以被使能。
步骤S303，在延迟测试模式和多字线测试模式均开启的情况下，基于字线分组信息和预设时长，依次使能存储芯片中每一组字线；
下面将以存储阵列中包括被分成4组的16条字线为例进行说明，在延迟测试模式和多字线测试模式均开启的情况下，首先使能第一组字线，即第1条字线、第5条字线、第9条字线、第13条字线；间隔2ns之后，使能第二组字线，即第2条字线、第6条字线、第10条字线、第14条字线；间隔2ns之后，使能第三组字线，即第3条字线、第7条字线、第11条字线、第15条字线；间隔2ns之后，使能第四组字线，即第4条字线、第8条字线、第12条字线、第16条字线。
步骤S304，在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试。
这里，步骤S304可以参考步骤S102。
本公开实施例中，对步骤S301和步骤S302先后顺序并不限定，可以先执行步骤S301，再执行步骤S302；也可以先执行步骤S302，再执行步骤S301；当然也可以同时执行步骤S301和步骤S302。
本公开实施例中，开启待测试的存储芯片的延迟测试模式和多字线测试模式，自动得到存储阵列中的字线分组信息和使能相邻的两组字线之间的时间间隔即预设时长，并且使多条字线可以同时使能，在后续过程中无需额外配置字线分组信息和预设时长，就可以自动得到并基于字线分组信息和预设时长依次使能存储芯片中的每一组字线，并在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试，如此， 可以简化存储芯片的测试方法。
本公开实施例提供一种存储芯片的测试装置，参考图9，该装置包括：
使能组件910，用于分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长；
测试组件920，用于在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试。
本公开实施例中，一方面，分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长，这样可以按照一定的时延延迟字线开关的顺序，可以减少同一时间存储芯片内部电路工作的数量，从而可以减小峰值电流，进而可以减少存储芯片受损的情况并且提高测试稳定性；另一方面，在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试，这样，可以节省大量的时间，从而节省测试成本。
在一些实施例中，存储芯片的测试装置还包括：模式开启组件，用于：开启待测试的存储芯片的延迟测试模式，得到存储阵列中的字线分组信息和所述预设时长；开启待测试的存储芯片的多字线测试模式；使能组件包括：第一使能单元，配置为在延迟测试模式和多字线测试模式均开启的情况下，基于字线分组信息和预设时长，依次使能存储芯片中每一组字线。
本公开实施例中，开启待测试的存储芯片的延迟测试模式和多字线测试模式，自动得到存储阵列中的字线分组信息和使能相邻的两组字线之间的时间间隔即预设时长，并且使多条字线可以同时使能，在后续过程中无需额外设置组件来配置字线分组信息和预设时长，就可以自动得到并基于字线分组信息和预设时长依次使能存储芯片中的每一组字线，并在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试，如此，可以简化存储芯片的测试装置。
在一些实施例中，存储阵列包括至少一个存储块，每一存储块中包括多个存储单元和多条字线；使能组件包括：第二使能单元，配置为分组依次使能每一存储块中的多条字线；其中，每一存储块中相同位置的字线同时被使能；测试组件包括：测试单元，配置为在每一存储块中的多条字线均处于使能状态的情况下，同时对每一存储块中多条字线对应的多个存储单元进行测试。这样可以同时对存储阵列中的所有存储块中的存储单元进行测试，可以进一步节省测试时间，从而进一步节省测试成本。
在一些实施例中，每一存储块包括分为R组的M条字线，R为大于1且小于M的整数；第二使能单元还配置为：使能每一存储块的第i组字线；在使能每一存储块的第i组字线之后间隔预设时长使能每一存储块的第i+1组字线；其中，i为大于0且小于R的整数。
在一些实施例中，在每一存储块中，第j组字线包括第j+nR条字线，其中，j为大于0且小于R+1的整数，n为大于0的整数，且j+nR不超过 M。这样，每一组字线中包括的字线均不相邻，这样可以减小相邻字线之间的影响，更有利于减小峰值电流。
在一些实施例中，预设时长小于等于tCK/(4R)，tCK为一个时钟周期内使能信号持续的时间。这样可以在一个时钟周期内使能信号持续的时间段内使能所有的字线，从而不影响后续的时序。
在一些实施例中，测试组件包括写入单元、读出单元和校验单元，其中，写入单元配置为：在多条字线均处于使能状态的情况下，同时向多条字线对应的多个存储单元中写入测试数据；读出单元配置为：同时从多个存储单元中读出目标数据；校验单元配置为：基于测试数据，对目标数据进行校验，得到存储阵列的测试结果。
本公开实施例中，同时向多条字线对应的多个存储单元中写入测试数据，并同时从多个存储单元中读出目标数据，基于测试数据，对目标数据进行校验，得到存储阵列的测试结果。这样可以通过一个命令对多个存储单元进行写入数据或者读取数据，不必对存储阵列中的存储单元进行多次一行一列的写入数据或者读取数据，从而可以提高存储芯片的测试效率。
在一些实施例中，校验单元包括第一压缩子单元、第二压缩子单元和确定子单元；其中，第一压缩子单元，配置为对测试数据进行压缩处理，得到第一压缩数据；第二压缩子单元，配置为对目标数据进行压缩处理，得到第二压缩数据；确定子单元，配置为基于第一压缩数据和第二压缩数据的一致性，确定存储阵列的测试结果。
本公开实施例中，通过对测试数据和目标数据分别进行压缩，得到第一压缩数据和第二压缩数据；并基于第一压缩数据和第二压缩数据的一致性，确定存储阵列的测试结果，这样可以提高存储芯片的测试效率，缩短测试时间。
在一些实施例中，本公开实施例提供的装置具有的功能或包含的模块可以用于执行上述方法实施例描述的方法，其具体实现可以参照上述方法实施例的描述，具有同方法实施例相似的有益效果。
本公开实施例还提供一种存储芯片的测试设备，参考图10，该设备包括：
处理器1001，用于执行上述存储芯片的测试方法实施例中的步骤；
用于存储处理器1001可执行指令的存储器1002。
处理器还可以称为中央处理单元(Central Processing Unit，CPU)。处理器可能是一种集成电路芯片，具有信号的处理能力。处理器还可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。另外，处理器可以由集成电路芯 片共同实现。
本公开实施例提供一种计算机可读存储介质，当所述存储介质中的指令由处理器执行时，使得处理器能够执行上述存储芯片的测试方法实施例中的步骤。
这里，存储介质可以包括：U盘、移动硬盘、只读存储器(Read Only Memory，ROM)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本公开实施例不限制于任何特定的硬件、软件或固件，或者硬件、软件、固件三者之间的任意结合。
上文对各个实施例的描述倾向于强调各个实施例之间的不同之处，其相同或相似之处可以互相参考。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开实施例的一些实施方式，但本公开实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开实施例的保护范围之内。
工业实用性
本公开实施例中，一方面，分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长，这样可以按照一定的时延延迟字线开关的顺序，可以减少同一时间存储芯片内部电路工作的数量，从而可以减小峰值电流，进而可以减少存储芯片受损的情况并且提高测试稳定性；另一方面，在多条字线均处于使能状态的情况下，同时对多条字线对应的多个存储单元进行测试，无需先对一条字线对应的存储单元进行测试，再对另一条字线对应的存储单元进行测试，这样，可以节省大量的时间，从而节省测试成本。

Claims (16)

  1. 一种存储芯片的测试方法，所述方法包括：
    分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长；
    在所述多条字线均处于使能状态的情况下，同时对所述多条字线对应的多个存储单元进行测试。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    开启所述待测试的存储芯片的延迟测试模式，得到所述存储阵列中的字线分组信息和所述预设时长；
    开启所述待测试的存储芯片的多字线测试模式；
    所述分组依次使能待测试的存储芯片的存储阵列中的多条字线，包括：
    在所述延迟测试模式和所述多字线测试模式均开启的情况下，基于所述字线分组信息和所述预设时长，依次使能所述存储芯片中每一组字线。
  3. 根据权利要求1所述的方法，其中，所述存储阵列包括至少一个存储块，每一所述存储块中包括多个存储单元和多条字线；
    所述分组依次使能待测试的存储芯片的存储阵列中的多条字线，包括：
    分组依次使能每一所述存储块中的多条字线；其中，所述每一所述存储块中相同位置的字线同时被使能；
    在所述多条字线均处于使能状态的情况下，同时对所述多条字线对应的多个存储单元进行测试，包括：
    在每一所述存储块中的多条字线均处于使能状态的情况下，同时对每一所述存储块中所述多条字线对应的多个存储单元进行测试。
  4. 根据权利要求3所述的方法，其中，每一所述存储块包括分为R组的M条字线，所述R为大于1且小于M的整数；
    所述分组依次使能每一所述存储块中的多条字线，包括：
    使能每一所述存储块的第i组字线；
    在使能每一所述存储块的第i组字线之后间隔所述预设时长使能每一所述存储块的第i+1组字线；其中，所述i为大于0且小于R的整数。
  5. 根据权利要求4所述的方法，其中，在每一所述存储块中，第j组字线包括第j+nR条字线，其中，所述j为大于0且小于R+1的整数，所述n为大于0的整数，且所述j+nR不超过M。
  6. 根据权利要求4或5所述的方法，其中，所述预设时长小于等于tCK/(4R)，所述tCK为一个时钟周期内使能信号持续的时间。
  7. 根据权利要求1至5任一项所述的方法，其中，在所述多条字线均处于使能状态的情况下，同时对所述多条字线对应的多个存储单元进行测试，包括：
    在所述多条字线均处于使能状态的情况下，同时向所述多条字线对应 的多个存储单元中写入测试数据；
    同时从所述多个存储单元中读出目标数据；
    基于所述测试数据，对所述目标数据进行校验，得到所述存储阵列的测试结果。
  8. 根据权利要求7所述的方法，其中，对每一所述目标数据进行校验，得到所述存储阵列的测试结果，包括：
    对所述测试数据进行压缩处理，得到第一压缩数据；
    对所述目标数据进行所述压缩处理，得到第二压缩数据；
    基于所述第一压缩数据和所述第二压缩数据的一致性，确定所述存储阵列的测试结果。
  9. 一种存储芯片的测试装置，所述装置包括：
    使能组件，用于分组依次使能待测试的存储芯片的存储阵列中的多条字线；其中，使能相邻的两组字线之间的时间间隔为预设时长；
    测试组件，用于在所述多条字线均处于使能状态的情况下，同时对所述多条字线对应的多个存储单元进行测试。
  10. 根据权利要求9所述的装置，其中，所述装置还包括：模式开启组件，用于：开启所述待测试的存储芯片的延迟测试模式，得到所述存储阵列中的字线分组信息和所述预设时长；开启所述待测试的存储芯片的多字线测试模式；
    所述使能组件包括：第一使能单元，配置为在所述延迟测试模式和所述多字线测试模式均开启的情况下，基于所述字线分组信息和所述预设时长，依次使能所述存储芯片中每一组字线。
  11. 根据权利要求9所述的装置，其中，所述存储阵列包括至少一个存储块，每一所述存储块中包括多个存储单元和多条字线；
    所述使能组件包括：第二使能单元，配置为分组依次使能每一所述存储块中的多条字线；其中，所述每一所述存储块中相同位置的字线同时被使能；
    所述测试组件包括：测试单元，配置为在每一所述存储块中的多条字线均处于使能状态的情况下，同时对每一所述存储块中所述多条字线对应的多个存储单元进行测试。
  12. 根据权利要求11所述的装置，其中，每一所述存储块包括分为R组的M条字线，所述R为大于1且小于M的整数；所述第二使能单元还配置为：使能每一所述存储块的第i组字线；在使能每一所述存储块的第i组字线之后间隔所述预设时长使能每一所述存储块的第i+1组字线；其中，所述i为大于0且小于R的整数。
  13. 根据权利要求9所述的装置，其中，所述测试组件包括写入单元、读出单元和校验单元，其中，所述写入单元配置为：在所述多条字线均处于使能状态的情况下，同时向所述多条字线对应的多个存储单元中写入测 试数据；所述读出单元配置为：同时从所述多个存储单元中读出目标数据；所述校验单元配置为：基于所述测试数据，对所述目标数据进行校验，得到所述存储阵列的测试结果。
  14. 根据权利要求13所述的装置，其中，所述校验单元包括第一压缩子单元、第二压缩子单元和确定子单元；其中，所述第一压缩子单元，配置为对所述测试数据进行压缩处理，得到第一压缩数据；所述第二压缩子单元，配置为对所述目标数据进行所述压缩处理，得到第二压缩数据；所述确定子单元，配置为基于所述第一压缩数据和所述第二压缩数据的一致性，确定所述存储阵列的测试结果。
  15. 一种存储芯片的测试设备，所述设备包括：
    处理器，用于执行如权利要求1至8任一项所述的方法；
    用于存储所述处理器可执行指令的存储器。
  16. 一种计算机可读存储介质，当所述存储介质中的指令由处理器执行时，使得处理器能够执行如权利要求1至8任一项所述的方法。
PCT/CN2022/114876 2022-07-22 2022-08-25 存储芯片的测试方法、装置、设备及存储介质 WO2024016426A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020006067A1 (en) * 2000-07-11 2002-01-17 Sung-Hoon Kim Integrated circuit memory devices having efficient multi-row address test capability and methods of operating same
CN103003886A (zh) * 2010-07-09 2013-03-27 桑迪士克科技股份有限公司 存储器阵列中的断裂字线的检测
CN105405468A (zh) * 2014-08-07 2016-03-16 旺宏电子股份有限公司 存储器测试方法
CN108062965A (zh) * 2016-11-08 2018-05-22 爱思开海力士有限公司 半导体存储装置、控制器及其操作方法
CN114171098A (zh) * 2021-11-22 2022-03-11 长江存储科技有限责任公司 一种异常字线的测试方法、装置、存储器及存储器系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020006067A1 (en) * 2000-07-11 2002-01-17 Sung-Hoon Kim Integrated circuit memory devices having efficient multi-row address test capability and methods of operating same
CN103003886A (zh) * 2010-07-09 2013-03-27 桑迪士克科技股份有限公司 存储器阵列中的断裂字线的检测
CN105405468A (zh) * 2014-08-07 2016-03-16 旺宏电子股份有限公司 存储器测试方法
CN108062965A (zh) * 2016-11-08 2018-05-22 爱思开海力士有限公司 半导体存储装置、控制器及其操作方法
CN114171098A (zh) * 2021-11-22 2022-03-11 长江存储科技有限责任公司 一种异常字线的测试方法、装置、存储器及存储器系统

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