WO2022188349A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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WO2022188349A1
WO2022188349A1 PCT/CN2021/110749 CN2021110749W WO2022188349A1 WO 2022188349 A1 WO2022188349 A1 WO 2022188349A1 CN 2021110749 W CN2021110749 W CN 2021110749W WO 2022188349 A1 WO2022188349 A1 WO 2022188349A1
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work function
gate
layer
conductive layer
groove
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PCT/CN2021/110749
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English (en)
French (fr)
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元大中
朴淳秉
平尔萱
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长鑫存储技术有限公司
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Priority to US17/452,788 priority Critical patent/US20220293722A1/en
Publication of WO2022188349A1 publication Critical patent/WO2022188349A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, a semiconductor structure and a method for forming the same.
  • GIDL gate-induce drain leakage
  • the magnitude of the GIDL current is related to the thickness of the gate dielectric layer near the drain. The greater the thickness, the smaller the GIDL current. Therefore, in order to solve the problem of GIDL current, the existing methods usually use a thicker gate dielectric layer in MOS transistors. However, the thicker gate dielectric layer will make the gate's ability to control the channel worse, and the threshold voltage will increase. In turn, the MOS transistor requires a higher driving voltage.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which can reduce the GIDL current of the semiconductor structure without changing the driving voltage.
  • a semiconductor structure including: a substrate having a source region, a drain region, and a gate dielectric layer in the substrate, and the gate dielectric layer is located between the source region and the drain region During the period, the gate dielectric layer surrounds a groove, the source region and the drain region are located on opposite sides of the top of the groove, and the groove has an extension direction parallel to the surface of the substrate; the first gate The electrode includes a first work function layer and a first conductive layer, the first gate is filled in the groove, the first work function layer covers the bottom surface and part of the sidewall of the groove, and the first gate electrode is filled in the groove.
  • the conductive layer covers the surface of the first work function layer, and the top surface of the first conductive layer is flush with or lower than the top surface of the first work function layer;
  • the second gate includes a second work function layer and a second a conductive layer, the second gate is stacked on the first gate and the top surface is lower than the surface of the substrate, the second work function layer covers the sidewall of the groove part, the second conductive layer Covering the surface of the second work function layer, the top surface of the second conductive layer is flush with or lower than the top surface of the second work function layer, and in the direction perpendicular to the surface of the substrate, the unit thickness of the The resistance of the second conductive layer is smaller than the resistance of the first conductive layer per unit thickness; the isolation layer is stacked on the second gate and fills the groove.
  • a method for forming a semiconductor structure including: providing a substrate, wherein the substrate has a source region, a drain region and a gate dielectric layer, and the gate dielectric layer is located between the source region and the gate dielectric layer.
  • the gate dielectric layer surrounds a groove, the source region and the drain region are located on opposite sides of the top of the groove, and the groove has an extension direction parallel to the surface of the substrate forming a first gate, including a first work function layer and a first conductive layer, the first gate is filled in the groove, and the first work function layer covers the bottom surface and part of the sidewall of the groove , the first conductive layer covers the surface of the first work function layer, the top surface of the first conductive layer is flush with or lower than the top surface of the first work function layer; a second gate is formed, including a second gate a work function layer and a second conductive layer, the second gate is stacked on the first gate, the top surface of the second gate is lower than the surface of the substrate, and the second work function layer covers the The sidewall of the groove part, the second conductive layer covers the surface of the second work function layer, and the top surface of the second conductive layer is flush with or lower than the top surface of the second work function layer, and is perpendic
  • the resistance per unit thickness of the second conductive layer is set to be relatively small, so that the thickness of the first conductive layer and the second conductive layer can not be changed, and the driving voltage of the semiconductor structure can be reduced.
  • the partial voltage of the second conductive layer further reduces the electric field between the second gate and the drain, thereby reducing the GIDL current caused by the strong electric field and improving the refresh performance of the semiconductor structure.
  • the thickness of the first part of the gate dielectric layer is relatively thick, the sensitivity to the electric field is low, and gate leakage current is not easily formed between the first gate and the channel. Therefore, the thickness of the second part can be set to be thin, so that the The electrons in the silicon at the gate-drain overlap region are more easily driven to move towards the channel, thereby reducing the electric field between the second gate and the drain, thereby reducing the GIDL current; at the same time, since the electrons are more easily driven, move toward the channel, so the movement of electrons can be effectively controlled without applying a large driving voltage.
  • 1 is a schematic structural diagram of a semiconductor structure
  • 2 to 5 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure
  • FIG. 6 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7 to 13 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 10, the substrate 10 has a source region (not shown), a drain region (not shown) and a gate dielectric layer 11, the gate dielectric layer 11 is located between the source region and the drain region, and the gate dielectric layer 11 is located between the source region and the drain region.
  • the dielectric layer 11 surrounds a groove, the source region and the drain region are located on opposite sides of the top of the groove, and the groove has an extending direction parallel to the surface of the substrate 10;
  • the gate (not marked) includes a work function layer 12 and a conductive layer 13 , the gate is filled in the groove, the work function layer 12 covers the bottom surface and part of the sidewall of the groove, the conductive layer 13 covers the surface of the work function layer 12, and the top surface of the conductive layer 13 is flush with or lower than the top surface of the work function layer 12;
  • the isolation layer 14 is stacked on the gate and fills the groove.
  • the process steps of forming the semiconductor structure shown in FIG. 1 include: referring to FIG. 2 , providing a substrate 10 with an initial groove in the substrate; referring to FIG. 3 , forming a gate dielectric layer 11 , a work function film 12 a and a conductive film 13 a , and the gate dielectric layer 11 Covers the bottom surface and sidewalls of the initial groove and surrounds the groove, the work function film 12a covers the bottom surface and sidewalls of the groove, and covers the top surface of the substrate 10, the conductive film 13a fills the groove, and covers the top surface of the work function film 12a 3 and 4, the work function film 12a and the conductive film 13a are etched back to form the work function layer 12 and the conductive layer 13, and the work function layer 12 and the conductive layer 13 constitute the gate; with reference to Figure 5, the isolation film 14a is deposited, The isolation film 14 a fills the groove and covers the surface of the substrate 10 ; referring to FIG. 1 , a planarization process is performed to remove the isolation
  • the thickness of the gate dielectric layer 11 at different positions is equal, which is the electric field of the gate-drain overlap region, so as to reduce the GIDL current caused by the strong electric field.
  • a thicker gate dielectric layer 11 is provided; however, when a thicker gate dielectric layer 11 is provided, it is easy to cause excess electrons that cannot be driven to gather in the gate-drain overlap region, thereby making the electric field of the gate-drain overlap region larger. , which may eventually lead to the breakdown of the gate dielectric layer 11 .
  • the present disclosure provides a semiconductor structure and a method for forming the same.
  • the resistance per unit thickness of the second conductive layer By setting the resistance per unit thickness of the second conductive layer to be small, the thicknesses of the first conductive layer and the second conductive layer are not changed, and the driving force of the semiconductor structure is not reduced.
  • the partial voltage of the second conductive layer is reduced, and the electric field between the second gate and the drain is reduced, thereby reducing the GIDL current caused by the strong electric field, and improving the refresh performance of the semiconductor structure.
  • the semiconductor structure includes: a substrate 20 having a source region (not shown), a drain region (not shown) and a gate dielectric layer 21 in the substrate 20 ,
  • the gate dielectric layer 21 encloses a groove 21a, the source region and the drain region are located on opposite sides of the top of the groove 21a, and the groove 21a has an extending direction parallel to the surface of the substrate 20;
  • the first gate 22 includes a first work function layer 221 and the first conductive layer 222, the first gate 22 is filled in the groove 21a, the first work function layer 221 covers the bottom surface and part of the sidewall of the groove 21a, the first conductive layer 222 covers the surface of the first work function layer 221,
  • the top surface of the first conductive layer 222 is flush with or lower than the top surface of the first work function layer 221;
  • the second gate 23 includes a second work function layer 231 and a second conductive layer 232, and the second gate 23 is stacked on the
  • the gate dielectric layer 21, the first gate 22, the second gate 23 and the isolation layer 24 together form a buried word line, and the extension direction of the buried word line is the same as the extension direction of the groove 21a.
  • the flow direction of the current is the same as the extending direction of the groove 21a; the vertical distance between the top surface of the second gate 23 and the top surface of the substrate 20 should be greater than the preset distance to avoid the second gate 23 and the source and drain regions formed subsequently. Overlap occurs horizontally.
  • the cross section of the second conductive layer 232 in the cross section perpendicular to the extending direction, is an inverted trapezoid, and in the horizontal direction parallel to the bottom edge of the inverted trapezoid, the minimum width of the second conductive layer 232 is greater than or equal to the first
  • the maximum width of the conductive layer 222 is that the cross-sectional area of the second conductive layer 232 per unit thickness is greater than the cross-sectional area of the first conductive layer 222 per unit thickness. It is beneficial to reduce the resistance of the second conductive layer 232 per unit thickness, thereby reducing the partial voltage of the second conductive layer 232 under the condition that the word line driving voltage remains unchanged. The weaker the electric field in the overlapping region between them is beneficial to suppress the generation of GIDL current.
  • the side of the above-mentioned inverted trapezoid is not necessarily a straight line, but can actually be a curve.
  • An inverted trapezoid with curved sides meets the basic shape requirements: the width of the inverted trapezoid in the horizontal direction increases in the direction of the short side toward the long side.
  • the resistivity of the material of the second conductive layer 232 is greater than, equal to or limitedly smaller than the resistivity of the material of the first conductive layer 222, so that the second conductive layer of unit thickness can be realized.
  • the resistance of 232 is smaller than the resistance of the first conductive layer 222 per unit thickness, so as to reduce the partial pressure of the second conductive layer 232 .
  • the material of the second conductive layer 232 is the same as the material of the first conductive layer 222, which is beneficial to reduce the contact resistance between the first conductive layer 222 and the second conductive layer 232, thereby reducing the first gate electrode 22 and the second gate 23 as a whole resistance, thereby reducing the loss and heat generation in the process of current flow, and improving the performance of the buried word line.
  • a second conductive layer can be provided under the condition that the cross-sectional shape of the second conductive layer is not changed, that is, the cross-section of the second conductive layer is still in the above-mentioned inverted trapezoid shape.
  • the resistivity of the material is lower than the resistivity of the material of the first conductive layer; or, the sides of the first conductive layer and the second conductive layer are both vertical sides, and the width of the first conductive layer is the same as the width of the second conductive layer.
  • the resistivity of the material of the second conductive layer can be set lower than that of the material of the first conductive layer.
  • the work function of the material of the first work function layer 221 is greater than the work function of the material of the second work function layer 231 . Since the work function of the material of the first work function layer 221 is large, the first conductive layer 222 is less sensitive to electrons in the channel, and it is difficult to induce leakage current in the channel, so the channel can accommodate more electrons;
  • the work function of the material of the second work function layer 231 is smaller, so that the second conductive layer 232 can more easily drive the electrons in the gate-drain overlap region to move to the channel, thereby reducing the electrons in the gate-drain overlap region and reducing the
  • the electric field in the gate-drain overlap region suppresses the GIDL current in the gate-drain overlap region. At the same time, since the electrons are more easily driven to move toward the channel, the electrons can be effectively controlled without applying a large driving voltage. move.
  • the horizontal width of the second work function layer 232 is greater than the horizontal width of the first work function layer 221, and the horizontal width refers to the horizontal width parallel to the bottom edge of the inverted trapezoid. width. It is beneficial to further enhance the driving capability of the second gate 23, weaken the electric field in the gate-drain overlap region, and thereby suppress the GIDL current.
  • the first work function layer 221 is made of one material
  • the second work function layer 231 is made of another material.
  • the first work function layer 221 and the second work function layer 231 are two independent bodies.
  • the material of the first work function layer 221 includes titanium nitride
  • the material of the second work function layer 231 includes lanthanum.
  • the gate dielectric layer 21 includes a first portion 211 covered by the first gate 22 and a second portion 212 covered by the second gate 23.
  • the width of the second portion 212 is smaller than the width of the first portion 211 . It is beneficial to enhance the driving capability of the second gate 23, further reduce electrons in the gate-drain overlap region, and reduce the electric field in the gate-drain overlap region, thereby suppressing the GIDL current in the gate-drain overlap region.
  • the side of the first part 211 away from the first gate 22 and the side of the second part 212 away from the second gate 23 are in the same smooth interface, reducing the width of the second part 212 is conducive to reserving more space for the first part 212
  • the sum of the width of the first work function layer 221 and the width of the first portion 211 is the first width
  • the sum of the width of the second work function layer 231 and the width of the second portion 212 is denoted as the first width.
  • the second width is less than or equal to the first width
  • the widths of different regions of the first part 211 in the horizontal direction are equal, the widths of different regions of the second part 212 in the horizontal direction are the same, and the first work function layers 221 are different.
  • the widths of the regions in the horizontal direction are equal, and the widths of the different regions of the second work function layer 231 in the horizontal direction decrease.
  • the second width decreases, the first width remains unchanged, and the largest second width is equal to the first width.
  • the resistance per unit thickness of the second conductive layer is set to be small, so that the thickness of the first conductive layer and the second conductive layer is not changed, and the driving voltage of the semiconductor structure is not reduced.
  • the partial voltage of the conductive layer further reduces the electric field between the second gate and the drain, thereby reducing the GIDL current caused by the strong electric field, and improving the refresh performance of the semiconductor structure.
  • An exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, which can be used to form the semiconductor structure in the above-mentioned embodiments. 6 to 13, the method of forming a semiconductor structure includes the following steps:
  • a substrate 20 an initial gate dielectric layer 21b and a first gate electrode 22 are provided.
  • the substrate 20 has a source region (not shown), a drain region (not shown), and an initial gate dielectric layer 21b.
  • the initial gate dielectric layer 21b is located between the source region and the drain region and surrounds an initial groove.
  • the drain regions are located on opposite sides of the top of the initial groove, and the initial groove has an extending direction parallel to the surface of the substrate 20 .
  • the first gate 22 includes a first work function layer 221 and a first conductive layer 222.
  • the first gate 22 is filled in the initial groove.
  • the first work function layer 221 covers the bottom surface and part of the sidewall of the initial groove.
  • the layer 222 covers the surface of the first work function layer 221 , and the top surface of the first conductive layer 222 is flush with or lower than the top surface of the first work function layer 221 .
  • the first work function layer 221 is generally a blocking layer, which is configured to block the migration of metal ions in the first conductive layer 222 to the initial gate dielectric layer 21b and the substrate 20.
  • the material of the first work function layer 221 includes titanium nitride,
  • the material of a conductive layer 222 includes tungsten.
  • the second gate is also to be stacked on the first gate 22, in the direction perpendicular to the surface of the substrate 20, the vertical distance between the top surface of the first gate 22 and the top surface of the substrate 20 should be greater than the distance between the source region and the drain region.
  • the maximum doping depth is to ensure that the positional relationship between the subsequently formed second gate and the source and drain regions meets the performance requirements of the buried word line.
  • the exposed initial gate dielectric layer 21 b is etched to form a gate dielectric layer 21 .
  • the uncovered initial gate dielectric layer 21b is etched to reduce the width of a part of the initial gate dielectric layer 21b, which is the first gate dielectric layer 21b to be formed subsequently and stacked on the first gate 22.
  • the second gate reserves more space.
  • width refers to the width in the section perpendicular to the extension direction of the initial groove and in the direction parallel to the surface of the substrate 20. Unless otherwise specified, the "width" in the subsequent expressions is The width in this direction is not repeated here.
  • the remaining initial gate dielectric layer 21b is used as the gate dielectric layer 21 , and the gate dielectric layer 21 can be divided into a first part 211 covered by the first gate 22 and a second part exposed by the first gate 22 212, the second gate formed subsequently covers part of the surface of the second part 212; the gate dielectric layer 21 surrounds a groove 21a, and the top space of the groove 21a is larger than the initial groove, which can accommodate a wider second gate pole, the extending direction of the groove 21a is the same as the extending direction of the initial groove.
  • the etching process is a wet etching process, which is beneficial to uniformly etch the exposed initial gate dielectric layer 21b, so that in the direction perpendicular to the surface of the substrate 20, the widths of the second portions 212 at different positions are equal Or tend to be equal, to ensure that the second part 212 of the gate dielectric layer 21 has stable performance and better isolation effect; it is beneficial to avoid the top surface of the first gate 22 from being damaged by ion bombardment, and to ensure that the first gate 22 and the subsequent formation
  • the second gate has smaller contact resistance.
  • a second work function film 231a is formed.
  • a second work function film 231 a covering the surface of the substrate 20 , the surface of the second portion 212 , the top surface of the first portion 211 and the top surface of the first gate electrode 22 is deposited.
  • the width of the second work function film 231a is greater than that of the first work function layer 221, and the width of the second work function film 231a is larger than that of the first work function layer 221.
  • the sum of the width and the width of the second portion 212 is less than or equal to the sum of the width of the first work function layer 221 and the width of the first portion 211 .
  • the work function of the material of the second work function film 231 a is smaller than that of the material of the first work function layer 221 , and the material of the second work function film 231 a includes lanthanum.
  • the second work function film 231a is etched back.
  • the second work function film 231a is etched back to expose the first conductive layer 222 to ensure that the second conductive layer formed subsequently is in effective contact with the first conductive layer.
  • the etch-back process removes the second work function film 231a covering the surface of the substrate 20 and the surface of the first conductive layer 222, and remains covering the surface of the second portion 212, the top surface of the first portion 211 and the first work function layer 221 the second work function film 231a on the top surface.
  • the interface of the region surrounded by the remaining second work function film 231 a is an inverted trapezoid.
  • the minimum width of the inverted trapezoid is greater than or equal to the maximum width of the first conductive layer 222 .
  • the etching back process is a wet etching process, which is beneficial to avoid ion bombardment damage to the surface of the first conductive layer 222 caused by the etching process, and to ensure that the first conductive layer 222 and the second conductive layer formed subsequently have a smaller size. Since the etching molecules that play the role of etching always tend to converge toward the middle during the wet etching process, in the direction in which the first part 211 extends toward the second part 212, the remaining second work function film 231a The width decreases at different positions.
  • the second conductive layer 232 and the second gate electrode 23 are formed.
  • a second conductive film 232a that fills the groove 21a is formed; the second conductive film 232a and the remaining second work function film 231a are etched back to form the second work function layer 231 and
  • the second conductive layer 232 , the second work function layer 231 and the second conductive layer 232 constitute the second gate electrode 23 .
  • the material of the second conductive layer 232 is the same as the material of the first conductive layer 222, and the material of the first conductive layer 222 includes tungsten; in other embodiments, the material of the second conductive layer 232 is the same as that of the first conductive layer 222.
  • the material of 222 may also be different, and the resistivity of the material of the second conductive layer is smaller than that of the material of the first conductive layer.
  • isolation layers 24 are formed.
  • an isolation film 24a that fills the groove 21a and covers the surface of the substrate 20 is formed;
  • the resistance per unit thickness of the second conductive layer 232 is set to be small, which can reduce the thickness of the first conductive layer 222 and the second conductive layer 232 without changing the thickness of the first conductive layer 222 and the thickness of the second conductive layer 232, and without reducing the driving voltage of the semiconductor structure.
  • the partial voltage of the second conductive layer 232 is reduced, thereby reducing the electric field between the second gate 23 and the drain, thereby reducing the GIDL current caused by the strong electric field, and improving the refresh performance of the semiconductor structure.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are beneficial to reduce the leakage current of the semiconductor structure and improve the refresh performance of the semiconductor structure.

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Abstract

本公开实施例公布一种半导体结构及其制作方法，半导体结构包括：基底，基底内具有围成凹槽的栅介质层，源区和漏区位于凹槽顶部的相对两侧，凹槽具有平行于基底表面的延伸方向；第一栅极，包括第一功函数层和第一导电层，第一功函数层覆盖凹槽底面和部分侧壁，第一导电层覆盖第一功函数层表面；第二栅极，包括第二功函数层和第二导电层，第二栅极层叠于第一栅极上且顶面低于基底表面，第二功函数层覆盖凹槽部分侧壁，第二导电层填充于第二功函数层围成的区域内，在垂直于基底表面的方向上，单位厚度的第二导电层的电阻小于单位厚度的第一导电层的电阻。

Description

半导体结构及其形成方法
本公开基于申请号为202110267911.0，申请日为2021年03月11日，申请名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及但不限于一种半导体结构及其形成方法。
背景技术
当栅漏交叠区电场很强时，交叠区界面附近的电子在价带和导带之间发生带带隧穿而形成电流，一般将这种电流称之为GIDL(gate-induce drain leakage，栅诱导漏极泄露电流)。
GIDL电流的大小与漏极附近栅介质层的厚度有关，厚度越大，GIDL电流越小。因此，为了解决GIDL电流问题，现有方法通常在MOS晶体管中使用较厚的栅介质层，然而，较厚的栅介质层会使得栅极对沟道的控制能力变差，阈值电压升高，进而使得MOS晶体管需要更高的驱动电压。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构及其形成方法，在不改变驱动电压的情况下，减小半导体结构的GIDL电流。
本公开实施例的第一方面，提供一种半导体结构，包括：基底，所述基底内具有源区、漏区以及栅介质层，所述栅介质层位于所述源区和所述漏区之间，所述栅介质层围成凹槽，所述源区和所述漏区位于所述凹槽顶部的相对两侧，所述凹槽具有平行于所述基底表面的延伸方向；第一栅极，包括第一功函数层和第一导电层，所述第一栅极填充于所述凹槽内，所述第一功函数层覆盖所述凹槽底面和部分侧壁，所述第一导电层覆盖所述第一功函数层 表面，所述第一导电层顶面平齐于或低于所述第一功函数层顶面；第二栅极，包括第二功函数层和第二导电层，所述第二栅极层叠于所述第一栅极上且顶面低于所述基底表面，所述第二功函数层覆盖所述凹槽部分侧壁，所述第二导电层覆盖所述第二功函数层表面，所述第二导电层顶面平齐于或低于所述第二功函数层顶面，在垂直于所述基底表面的方向上，单位厚度的所述第二导电层的电阻小于单位厚度的所述第一导电层的电阻；隔离层，层叠于所述第二栅极上且填充满所述凹槽。
本公开实施例的第二方面，提供一种半导体结构的形成方法，包括：提供基底，所述基底内具有源区、漏区以及栅介质层，所述栅介质层位于所述源区和所述漏区之间，所述栅介质层围成凹槽，所述源区和所述漏区位于所述凹槽顶部的相对两侧，所述凹槽具有平行于所述基底表面的延伸方向；形成第一栅极，包括第一功函数层和第一导电层，所述第一栅极填充于所述凹槽内，所述第一功函数层覆盖所述凹槽底面和部分侧壁，所述第一导电层覆盖所述第一功函数层表面，所述第一导电层顶面平齐于或低于所述第一功函数层顶面；形成第二栅极，包括第二功函数层和第二导电层，所述第二栅极层叠于所述第一栅极上，且所述第二栅极顶面低于所述基底表面，所述第二功函数层覆盖所述凹槽部分侧壁，所述第二导电层覆盖所述第二功函数层表面，所述第二导电层顶面平齐于或低于所述第二功函数层顶面，在垂直于所述基底表面的方向上，单位厚度的所述第二导电层的电阻小于单位厚度的所述第一导电层的电阻；形成隔离层，层叠于所述第二栅极上且填充满所述凹槽。
与现有技术相比，本发明实施例提供的技术方案具有以下优点：
上述技术方案中，设置第二导电层的单位厚度电阻较小，如此，可在不改变第一导电层和第二导电层的厚度，以及不减小半导体结构的驱动电压的情况上，减小第二导电层的分压，进而减小第二栅极与漏极之间的电场，从而减小强电场导致的GIDL电流，提高半导体结构的刷新性能。
另外，由于栅介质层第一部分的厚度较厚，对电场的敏感性较低，第一栅极与沟道之间不容易形成栅泄露电流，因此，可设置第二部分的厚度较薄，使得栅漏交叠区处的硅中电子更容易被驱动而朝沟道移动，从而减小第二栅极与漏极之间的电场，进而减小GIDL电流；同时，由于电子更容易受驱动 而朝沟道移动，因此，无需施加较大的驱动电压，就可以有效控制电子的移动。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为半导体结构的结构示意图；
图2至图5为半导体结构的形成方法各步骤对应的结构示意图；
图6为本公开实施例提供的半导体结构的结构示意图；
图7至图13为本公开实施例提供的半导体结构的形成方法各步骤对应的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
参考图1，半导体结构包括：基底10，基底10内具有源区(未图示)、漏区(未图示)以及栅介质层11，栅介质层11位于源区和漏区之间，栅介质层11围成凹槽，源区和漏区位于凹槽顶部的相对两侧，凹槽具有平行于基底10表面的延伸方向；栅极(未标示)，包括功函数层12和导电层13，栅极填充于凹槽内，功函数层12覆盖凹槽底面和部分侧壁，导电层13覆盖功函数层12表面，导电层13顶面平齐于或低于功函数层12顶面；隔离层14，层叠与栅极上且填充满凹槽。
形成图1所示半导体结构的工艺步骤包括：参考图2，提供基底10，基底内具有初始凹槽；参考图3，形成栅介质层11、功函数膜12a以及导电膜13a，栅介质层11覆盖初始凹槽底面和侧壁，并围成凹槽，功函数膜12a覆盖凹槽底面和侧壁，以及覆盖基底10顶面，导电膜13a填充满凹槽，并覆盖功函数膜12a顶面；结合图3和图4，回刻功函数膜12a和导电膜13a，形成功函数层12和导电层13，功函数层12和导电层13构成栅极；参考图5，沉积隔离膜14a，隔离膜14a填充满凹槽且覆盖基底10表面；参考图1，进行平坦化工艺，去除覆盖基底10表面的隔离膜，剩余隔离膜作为隔离层14。
上述半导体结构中，在垂直于延伸方向并平行于基底表面的水平方向上，不同位置的栅介质层11的厚度相等，为栅漏交叠区的电场，以减小强电场导致的GIDL电流，一般设置厚度较厚的栅介质层11；然而，设置较厚的栅介质层11，容易使得过量的无法被驱动的电子聚集在栅漏交叠区，进而使得栅漏交叠区的电场较大，最终可能导致栅介质层11发生击穿。
本公开实施提供一种半导体结构及其形成方法，通过设置第二导电层的单位厚度电阻较小，使得在不改变第一导电层和第二导电层的厚度，以及不减小半导体结构的驱动电压的情况下，减小第二导电层的分压，减小第二栅极与漏极之间的电场，从而减小强电场导致的GIDL电流，提高半导体结构的刷新性能。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。其中，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本公开一示例性的实施例提供一种半导体结构，参考图6，半导体结构包括：基底20，基底20内具有源区(未图示)、漏区(未图示)以及栅介质层21，栅介质层21围成凹槽21a，源区和漏区位于凹槽21a顶部的相对两侧，凹槽21a具有平行于基底20表面的延伸方向；第一栅极22，包括第一功函数层221和第一导电层222，第一栅极22填充于凹槽21a内，第一功函数层221覆盖凹槽21a底面和部分侧壁，第一导电层222覆盖第一功函数层221表面，第一导电层222顶面平齐于或低于第一功函数层221顶面；第二栅极 23，包括第二功函数层231和第二导电层232，第二栅极23层叠于第一栅极22上且顶面低于基底20表面，第二功函数层231覆盖凹槽21a部分侧壁，第二导电层232覆盖第二功函数层231表面，第二导电层232顶面平齐于或低于第二功函数层231顶面，在垂直于基底20表面的方向上，单位厚度的第二导电层232的电阻小于单位厚度的第一导电层222的电阻；隔离层24，层叠于第二栅极23上且填充满凹槽21a。
其中，栅介质层21、第一栅极22、第二栅极23以及隔离层24共同构成埋入式字线，埋入式字线的延伸方向与凹槽21a的延伸方向相同，字线中电流的流动方向与凹槽21a的延伸方向相同；第二栅极23顶面与基底20顶面的垂直距离应大于预设距离，以避免第二栅极23与后续形成的源区和漏区在水平方向上发生交叠。
本实施例中，在垂直于延伸方向的横截面内，第二导电层232的截面呈倒梯形，在平行于倒梯形底边的水平方向上，第二导电层232的最小宽度大于等于第一导电层222的最大宽度，单位厚度的第二导电层232的横截面积大于单位厚度的第一导电层222的横截面积。有利于减小单位厚度的第二导电层232的电阻，进而在字线驱动电压不变的情况下减小第二导电层232的分压，分压越小，第二栅极23与漏区之间的交叠区域的电场越弱，有利于抑制GIDL电流的生成。
上述倒梯形的侧边并非一定是直线，实际上还可以是曲线，具有曲线侧边的倒梯形满足基本形状要求：在短边朝向长边的方向上，倒梯形在水平方向上的宽度递增。
在上述第二导电层232的结构基础上，第二导电层232的材料的电阻率大于、等于或者有限地小于第一导电层222的材料的电阻率，都可以实现单位厚度的第二导电层232的电阻小于单位厚度的第一导电层222的电阻，以减小第二导电层232的分压。
本实施例中，第二导电层232的材料与第一导电层222的材料相同，有利于减小第一导电层222与第二导电层232之间的接触电阻，从而减小第一栅极22和第二栅极23作为一个整体的电阻，进而减小电流流通过程中的损耗和发热，改善埋入式字线的性能。
在其他实施例中，在不改变第二导电层的截面形状，即第二导电层的截 面依旧呈上述倒梯形的情况下，为进一步降低第二导电层的分压，可设置第二导电层的材料的电阻率低于第一导电层的材料的电阻率；或者，第一导电层和第二导电层的侧边均为竖直侧边，第一导电层的宽度与第二导电层的宽度相等，为降低第二导电层的分压，可设置第二导电层的材料的电阻率低于第一导电层的材料的电阻率。
本实施例中，第一功函数层221的材料的功函数大于第二功函数层231的材料的功函数。由于第一功函数层221的材料的功函数较大，第一导电层222对沟道内电子的敏感性较低，较难诱导沟道发生泄漏电流，因此，沟道可容纳更多电子；可设置第二功函数层231的材料的功函数较小，使得第二导电层232更容易驱动栅漏交叠区中的电子向沟道移动，从而减少栅漏交叠区中的电子以及减小栅漏交叠区中的电场，进而抑制栅漏交叠区的GIDL电流，同时，由于电子更容易受驱动而朝沟道移动，因此，无需施加较大的驱动电压，就可以有效控制电子的移动。
本实施例中，在垂直于延伸方向的横截面内，第二功函数层232的水平宽度大于第一功函数层221的水平宽度，水平宽度指的平行于倒梯形底边的水平方向上的宽度。有利于进一步增强第二栅极23的驱动能力，减弱栅漏交叠区的电场，进而抑制GIDL电流。
本实施例中，第一功函数层221由一种材料构成，第二功函数层231由另一种材料构成。第一功函数层221和第二功函数层231是相互独立的两个个体，第一功函数层221的材料包括氮化钛，第二功函数层231的材料包括镧。
本实施例中，栅介质层21包括第一栅极22覆盖的第一部分211和第二栅极23覆盖的第二部分212，在垂直于延伸方向且平行于基底20表面的水平方向上，第二部分212的宽度小于第一部分211的宽度。有利于增强第二栅极23的驱动能力，进一步减少栅漏交叠区中的电子以及减小栅漏交叠区中的电场，进而抑制栅漏交叠区的GIDL电流。
其中，第一部分211远离第一栅极22的侧面与第二部分212远离第二栅极23的侧面处于同一平滑界面内，减小第二部分212的宽度，有利于预留更多空间给第二栅极23，避免较厚的第二功函数层231挤占了第二导电层232的空间，保证第二导电层232以及以第二导电层232为导电主体的第二栅极 23具有良好的导电性能。
本实施例中，在水平方向上，记第一功函数层221的宽度与第一部分211的宽度之和为第一宽度，记第二功函数层231的宽度与第二部分212的宽度之和为第二宽度，第二宽度小于等于第一宽度。
在第一栅极22朝向第二栅极23的方向上，第一部分211不同区域在水平方向上的宽度相等、第二部分212不同区域在水平方向上的宽度相等、第一功函数层221不同区域在水平方向上的宽度相等，第二功函数层231不同区域在水平方向上的宽度递减。在第一栅极22朝向第二栅极23的方向上，第二宽度递减，第一宽度不变，最大的第二宽度等于第一宽度。
本实施例中，设置第二导电层的单位厚度电阻较小，可在不改变第一导电层和第二导电层的厚度，以及不减小半导体结构的驱动电压的情况下，减小第二导电层的分压，进而减小第二栅极与漏极之间的电场，从而减小强电场导致的GIDL电流，提高半导体结构的刷新性能。
本公开一示例性的实施例提供一种半导体结构的形成方法，可用于形成上述实施例中的半导体结构。参考图6至图13，半导体结构的形成方法包括以下步骤：
参考图7，提供基底20、初始栅介质层21b和第一栅极22。
基底20内具有源区(未图示)、漏区(未图示)和初始栅介质层21b，初始栅介质层21b位于源区和漏区之间，且围成初始凹槽，源区和漏区位于初始凹槽顶部的相对两侧，初始凹槽具有平行于基底20表面的延伸方向。
第一栅极22包括第一功函数层221和第一导电层222，第一栅极22填充于初始凹槽内，第一功函数层221覆盖初始凹槽底面和部分侧壁，第一导电层222覆盖第一功函数层221表面，第一导电层222顶面平齐于或低于第一功函数层221顶面。第一功函数层221通常实质为阻拦层，设置为阻拦第一导电层222内的金属离子迁移至初始栅介质层21b以及基底20内，第一功函数层221的材料包括氮化钛，第一导电层222的材料包括钨。
由于还要在第一栅极22上叠放第二栅极，在垂直于基底20表面的方向上，第一栅极22顶面与基底20顶面的垂直距离应当大于源区和漏区的最大掺杂深度，以保证后续形成的第二栅极与源区和漏区的位置关系满足埋入式字线的性能要求。
参考图7和图8，刻蚀被暴露的初始栅介质层21b，形成栅介质层21。
以第一栅极22为掩膜，对未被覆盖的初始栅介质层21b进行刻蚀，可减薄部分初始栅介质层21b的宽度，为后续形成的层叠于第一栅极22上的第二栅极预留更大的空间。上述“宽度”指的是，在垂直于初始凹槽延伸方向的截面内，在平行于基底20表面的方向上的宽度，在不进行额外说明的情况下，后续表述中的“宽度”都为该方向上的宽度，不再进行赘述。
在进行刻蚀工艺之后，剩余的初始栅介质层21b作为栅介质层21，栅介质层21可划分为被第一栅极22覆盖的第一部分211以及被第一栅极22暴露的第二部分212，后续形成的第二栅极覆盖第二部分212部分表面；栅介质层21围成凹槽21a，相对于初始凹槽，凹槽21a的顶部空间更大，可容纳更宽的第二栅极，凹槽21a的延伸方向与初始凹槽的延伸方向相同。
本实施例中，刻蚀工艺为湿法刻蚀工艺，有利于均匀刻蚀被暴露的初始栅介质层21b，使得在垂直于基底20表面的方向上，不同位置的第二部分212的宽度相等或趋于相等，保证栅介质层21的第二部分212具有稳定的性能以及较优的隔离效果；有利于避免第一栅极22顶面受到离子轰击损伤，保证第一栅极22与后续形成的第二栅极具有较小的接触电阻。
参考图9，形成第二功函数膜231a。
在形成栅介质层21之后，沉积形成覆盖基底20表面、第二部分212表面、第一部分211顶面以及第一栅极22顶面的第二功函数膜231a。在垂直于延伸方向且平行于基底20表面的水平方向(以下简称为“水平方向”)上，第二功函数膜231a的宽度大于第一功函数层221的宽度，第二功函数膜231a的宽度与第二部分212的宽度之和小于等于第一功函数层221的宽度与第一部分211的宽度之和。
本实施例中，第二功函数膜231a的材料的功函数小于第一功函数层221的材料的功函数，第二功函数膜231a的材料包括镧。
参考图9和图10，回刻第二功函数膜231a。
对第二功函数膜231a进行回刻，以暴露第一导电层222，保证后续形成的第二导电层与第一导电层有效接触。
本实施例中，回刻工艺刻蚀去除覆盖基底20表面和覆盖第一导电层222表面的第二功函数膜231a，保留覆盖第二部分212表面、第一部分211顶面 以及第一功函数层221顶面的第二功函数膜231a。在垂直于延伸方向的横截面内，剩余第二功函数膜231a包围的区域的界面呈倒梯形，在水平方向上，倒梯形的最小宽度大于等于第一导电层222的最大宽度。
本实施例中，回刻工艺为湿法刻蚀工艺，有利于避免刻蚀工艺对第一导电层222表面造成离子轰击损伤，保证第一导电层222与后续形成的第二导电层具有较小的接触电阻；由于湿法刻蚀过程中，起到刻蚀作用的刻蚀分子总是倾向于向中间汇聚，在第一部分211朝第二部分212延伸的方向上，剩余第二功函数膜231a不同位置的宽度递减。
参考图11和图12，形成第二导电层232和第二栅极23。
在回刻第二功函数膜231a之后，形成填充满凹槽21a的第二导电膜232a；对第二导电膜232a和剩余第二功函数膜231a进行回刻，形成第二功函数层231和第二导电层232，第二功函数层231和第二导电层232构成第二栅极23。
本实施例中，第二导电层232的材料与第一导电层222的材料相同，第一导电层222的材料包括钨；在其他实施例中，第二导电层232的材料与第一导电层222的材料也可以不相同，且第二导电层的材料的电阻率小于第一导电层的材料的电阻率。
参考图13和图1，形成隔离层24。
在形成第二栅极23之后，形成填充满凹槽21a和覆盖基底20表面的隔离膜24a；对隔离膜24a进行平坦化工艺，保留填充满凹槽21a的隔离膜24a，作为隔离层24。
本实施例中，设置第二导电层232的单位厚度电阻较小，可在不改变第一导电层222和第二导电层232的厚度，以及不减小半导体结构的驱动电压的情况下，减小第二导电层232的分压，进而减小第二栅极23与漏极之间的电场，从而减小强电场导致的GIDL电流，提高半导体结构的刷新性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例 描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例提供一种半导体结构及其制作方法，有利于减小半导体结构的漏电流，提高半导体结构的刷新性能。

Claims (15)

  1. 一种半导体结构，包括：
    基底，所述基底内具有源区、漏区以及栅介质层，所述栅介质层位于所述源区和所述漏区之间，所述栅介质层围成凹槽，所述源区和所述漏区位于所述凹槽顶部的相对两侧，所述凹槽具有平行于所述基底表面的延伸方向；
    第一栅极，包括第一功函数层和第一导电层，所述第一栅极填充于所述凹槽内，所述第一功函数层覆盖所述凹槽底面和部分侧壁，所述第一导电层覆盖所述第一功函数层表面，所述第一导电层顶面平齐于或低于所述第一功函数层顶面；
    第二栅极，包括第二功函数层和第二导电层，所述第二栅极层叠于所述第一栅极上且顶面低于所述基底表面，所述第二功函数层覆盖所述凹槽部分侧壁，所述第二导电层覆盖所述第二功函数层表面，所述第二导电层顶面平齐于或低于所述第二功函数层顶面，在垂直于所述基底表面的方向上，单位厚度的所述第二导电层的电阻小于单位厚度的所述第一导电层的电阻；
    隔离层，层叠于所述第二栅极上且填充满所述凹槽。
  2. 根据权利要求1所述的半导体结构，其中，在垂直于所述延伸方向的横截面内，所述第二导电层的截面呈倒梯形，在平行于所述倒梯形底边的水平方向上，所述第二导电层的最小宽度大于等于所述第一导电层的最大宽度。
  3. 根据权利要求2所述的半导体结构，其中，所述第二导电层的材料与所述第一导电层的材料相同。
  4. 根据权利要求1所述的半导体结构，其中，所述第二导电层的材料的电阻率小于所述第一导电层的材料的电阻率。
  5. 根据权利要求1所述的半导体结构，其中，所述第一功函数层的材料的功函数大于所述第二功函数层的材料的功函数。
  6. 根据权利要求5所述的半导体结构，其中，在垂直于所述延伸方向的横截面内，所述第二功函数层的水平宽度大于所述第一功函数层的水平宽度。
  7. 根据权利要求5或6所述的半导体结构，其中，所述第一功函数层由一种材料构成，所述第二功函数层由另一种材料构成。
  8. 根据权利要求1或6所述的半导体结构，其中，所述栅介质层包括所 述第一栅极覆盖的第一部分和所述第二栅极覆盖的第二部分，在垂直于所述延伸方向且平行于所述基底表面的水平方向上，所述第二部分的宽度小于所述第一部分的宽度。
  9. 根据权利要求8所述的半导体结构，其中，在所述水平方向上，记所述第一功函数层的宽度与所述第一部分的宽度之和为第一宽度，记所述第二功函数层的宽度与所述第二部分的宽度之和为第二宽度，所述第二宽度小于等于所述第一宽度。
  10. 一种半导体结构的形成方法，包括：
    提供基底，所述基底内具有源区、漏区以及栅介质层，所述栅介质层位于所述源区和所述漏区之间，所述栅介质层围成凹槽，所述源区和所述漏区位于所述凹槽顶部的相对两侧，所述凹槽具有平行于所述基底表面的延伸方向；
    形成第一栅极，包括第一功函数层和第一导电层，所述第一栅极填充于所述凹槽内，所述第一功函数层覆盖所述凹槽底面和部分侧壁，所述第一导电层覆盖所述第一功函数层表面，所述第一导电层顶面平齐于或低于所述第一功函数层顶面；
    形成第二栅极，包括第二功函数层和第二导电层，所述第二栅极层叠于所述第一栅极上，且所述第二栅极顶面低于所述基底表面，所述第二功函数层覆盖所述凹槽部分侧壁，所述第二导电层覆盖所述第二功函数层表面，所述第二导电层顶面平齐于或低于所述第二功函数层顶面，在垂直于所述基底表面的方向上，单位厚度的所述第二导电层的电阻小于单位厚度的所述第一导电层的电阻；
    形成隔离层，层叠于所述第二栅极上且填充满所述凹槽。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，提供所述栅介质层和形成所述第一栅极的步骤包括：
    提供初始栅介质层，所述初始栅介质层围成初始凹槽；
    形成所述第一栅极，所述第一栅极覆盖所述初始凹槽底面和部分侧壁；
    以所述第一栅极为掩膜，刻蚀未被覆盖的部分所述初始栅介质层，以在垂直于所述延伸方向且平行于所述基底表面的水平方向上，减薄未被覆盖的部分所述初始栅介质层的厚度，剩余所述初始栅介质层作为所述栅介质层。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，形成所述第二功函数层的工艺步骤包括：
    在形成所述第一栅极之后，形成覆盖所述凹槽侧壁和所述第一栅极顶面的第二功函数膜；
    对所述第二功函数膜进行回刻，以暴露所述第一导电层；在垂直于所述延伸方向的横截面内，剩余所述第二功函数膜所包围的区域的截面呈倒梯形，在所述水平方向上，所述倒梯形的最小宽度大于等于所述第一导电层的最大宽度。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，采用湿法刻蚀工艺对所述第二功函数膜进行回刻。
  14. 根据权利要求12所述的半导体结构的形成方法，其中，形成所述第二栅极的工艺步骤包括：
    在回刻所述第二功函数膜之后，形成填充满所述凹槽的第二导电膜；
    对所述第二功函数膜和所述第二导电膜进行回刻，形成所述第二栅极，所述第二栅极顶面低于所述基底表面。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，所述第二导电膜的材料与所述第一导电层的材料相同。
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