WO2022166117A1 - 互连结构及其制备方法、半导体结构 - Google Patents

互连结构及其制备方法、半导体结构 Download PDF

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WO2022166117A1
WO2022166117A1 PCT/CN2021/106429 CN2021106429W WO2022166117A1 WO 2022166117 A1 WO2022166117 A1 WO 2022166117A1 CN 2021106429 W CN2021106429 W CN 2021106429W WO 2022166117 A1 WO2022166117 A1 WO 2022166117A1
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layer
sub
dielectric layer
substrate
insulating layer
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PCT/CN2021/106429
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English (en)
French (fr)
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朱德龙
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长鑫存储技术有限公司
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Priority to US17/501,326 priority Critical patent/US20220246519A1/en
Publication of WO2022166117A1 publication Critical patent/WO2022166117A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric

Definitions

  • the present application relates to the technical field of semiconductors, and in particular, to an interconnection structure, a method for preparing the same, and a semiconductor structure.
  • interconnect structures are indispensable structures in semiconductor structures, for example, dynamic random access memory (Dynamic Random Access Memory, DRAM for short), the formed dynamic random access memory usually includes a core storage area and a peripheral area.
  • the circuit area wherein the core storage area is used for arranging a plurality of storage units for storing data information, and the core storage area and the peripheral circuit area usually include an interconnection structure, and the interconnection structure is used for electrical connection with the storage unit, so that the The storage unit completes the storage or reading of the data information.
  • an interconnection structure usually includes at least one interconnection layer, and the interconnection layer includes a plurality of metal lines arranged at intervals and a dielectric layer for isolating the respective metal lines.
  • the semiconductor structure develops in the direction of miniaturization and integration , so that the spacing between adjacent metal lines in the same interconnect layer is also reduced, and parasitic capacitance can be formed between adjacent metal lines. The existence of this parasitic capacitance will cause signal delay and reduce the semiconductor structure. performance.
  • a first aspect of the embodiments of the present application provides an interconnection structure, which includes:
  • a dielectric layer, the dielectric layer is arranged on the substrate, and a plurality of metal lines are arranged in the dielectric layer at intervals; grooves are arranged in the dielectric layer between the adjacent metal lines, and the concave The groove bottom of the groove exposes the surface of the substrate.
  • the insulating layer is disposed on the dielectric layer, the insulating layer has an extension part extending into the groove, and a gap is formed between the extension part and the substrate.
  • a second aspect of the embodiments of the present application provides a method for preparing an interconnect structure, comprising the following steps:
  • a dielectric layer is formed on the substrate, and a plurality of metal lines arranged at intervals are arranged in the dielectric layer.
  • the dielectric layer is patterned, a plurality of grooves are formed in the dielectric layer, the grooves are located between the adjacent metal lines, and the bottom of the grooves exposes the surface of the substrate.
  • An insulating layer is formed on the dielectric layer, the insulating layer has an extension portion extending into the groove, and a gap is formed between the extension portion and the substrate.
  • a third aspect of the embodiments of the present application provides a semiconductor structure, including the interconnect structure as described above.
  • a gap is formed between the insulating layer located between adjacent metal lines and the substrate, that is, there is a gap between the adjacent metal lines. Air gap, so that the dielectric constant of air can be lower than the dielectric constant of the insulating layer, the capacitance value of the parasitic capacitance between adjacent metal lines can be reduced, the signal delay of the interconnect structure can be reduced, and the performance of the semiconductor structure can be improved.
  • FIG. 1 is a schematic diagram of an interconnect structure provided in the related art
  • FIG. 2 is a schematic diagram of an interconnection structure provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for preparing an interconnect structure provided by an embodiment of the present application
  • FIG. 4 is a schematic diagram of forming a dielectric layer in a method for preparing an interconnect structure provided by an embodiment of the present application
  • FIG. 5 is a schematic diagram of forming a groove in a method for fabricating an interconnect structure provided by an embodiment of the present application
  • FIG. 6 is a schematic diagram of forming a metal wire in a method for preparing an interconnect structure provided by an embodiment of the present application
  • FIG. 7 is a schematic diagram of forming a barrier layer in a method for preparing an interconnect structure provided by an embodiment of the present application.
  • FIG. 8 is a process diagram of forming a sub-catalyst layer in the preparation method of the interconnect structure provided by the embodiment of the present application;
  • FIG. 9 is a schematic diagram of forming a sub-catalyst layer in the preparation method of the interconnect structure provided by the embodiment of the present application.
  • FIG. 10 is a schematic diagram of forming a sub-insulating layer in a method for fabricating an interconnect structure provided by an embodiment of the present application.
  • interconnect structure 10: substrate;
  • 60 barrier layer
  • 70 conductive plunger
  • the inventors of the present application found that, as shown in FIG. 1 , the smaller the size (such as thickness or length) of the semiconductor structure, the smaller the vertical distance and the horizontal distance between adjacent metal lines 30 in the interconnect structure 100 It will also decrease accordingly, and parasitic capacitances will be formed between the adjacent metal lines, and these parasitic capacitances will cause signal delays in the interconnection structure and reduce the performance of the semiconductor structure.
  • the embodiments of the present application provide an interconnection structure, a preparation method thereof, and a semiconductor structure.
  • the semiconductor structure may be a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the following description will take the semiconductor structure as a dynamic random access memory (DRAM) as an example, but this embodiment does not take this as an example.
  • the semiconductor structure in this embodiment may also be other structures.
  • the semiconductor structure may include a substrate, and the substrate may have an array area and a peripheral circuit area connected to the array area, wherein capacitors arranged in an array are arranged in the array area, and an interconnection structure is arranged on the peripheral circuit area, and through the interconnection
  • the connecting structure is electrically connected with the capacitor, so as to realize the storage or reading of data information by the dynamic random access memory.
  • the interconnection structure 100 may include a substrate 10 , a dielectric layer 20 having metal lines 30 , and an insulating layer 40 , wherein the substrate 10 serves as a supporting member of the interconnection structure 100 for supporting the
  • the substrate 10 may be an oxide layer, for example, the substrate 10 may be a silicon oxide layer.
  • a plurality of conductive plungers 70 may also be provided in the base 10 , the conductive plungers 70 correspond to the metal wires 30 one-to-one, one end of the conductive plungers 70 is connected to the metal wires 30 , and the other end of the conductive plungers 70 is connected to the metal wires 30 in the base 10 .
  • the active area connection is used to realize the connection between the metal line 30 and the active area in the substrate 10, so as to realize the performance of the semiconductor structure, that is, realize the storage or reading of data information by the dynamic random access memory.
  • the material of the conductive plunger 70 may include a conductive material such as metal tungsten.
  • the dielectric layer 20 is disposed on the substrate 10, and a plurality of metal wires 30 are arranged in the dielectric layer 20 at intervals. It should be noted that the plurality of metal wires 30 can be arranged at intervals along the horizontal direction of the substrate 10. The distance between them may be the same or different, which is not specifically limited in this embodiment.
  • the horizontal direction of the substrate 10 may be the X direction in FIG. 2 .
  • the material of the dielectric layer 20 may include silicon oxide or the like, and the insulating properties of the adjacent metal lines 30 are achieved by utilizing the insulating properties of silicon oxide.
  • a groove is provided in the dielectric layer 20 between the adjacent metal lines 30, and the groove can extend in a direction perpendicular to the substrate until the bottom of the groove exposes the surface of the substrate 10, that is, the groove is along a direction perpendicular to the substrate 10.
  • the direction of the substrate runs through the groove of the dielectric layer 20 , and the bottom of the groove is the upper surface of the substrate 10 .
  • the width of the groove may be smaller than the spacing between adjacent metal lines 30, so that the dielectric layer 20 covers the side of the metal line 30 facing the groove, so that the adjacent metal lines 30 can be protected. Insulation between wires 30 .
  • an insulating layer 40 is provided on the dielectric layer 20, wherein the material of the insulating layer 40 may include silicon oxide or the like, and the insulating property of the silicon oxide can be used to achieve the insulating property of the adjacent metal wires 30, and at the same time, the insulating property of the insulating layer 40 can be realized. Insulation between other metal lines above metal line 30 .
  • the insulating layer 40 has an extension portion 41 extending into the groove, and there is a gap 50 between the extension portion 41 and the substrate 10 , so that there is a certain distance between the end surface of the extension portion 41 facing the substrate 10 and the substrate 10 , that is, it is located adjacent to the substrate 10 .
  • the dielectric constant of the air is smaller than the dielectric constant of the insulating layer 40, which can reduce the capacitance value of the parasitic capacitance between the adjacent metal lines 30, so as to reduce the interconnection structure. the signal delay, thereby improving the performance of the semiconductor structure.
  • the distance between the end surface of the extension portion 41 facing the substrate 10 and the upper surface of the substrate 10 accounts for 2/3 ⁇ 3/4 of the depth of the groove, that is, H2 is equal to 2/3H1 ⁇ 3/ 4H1, the height of the gap 50 is limited in this embodiment, and it is necessary to avoid the height of the gap from being too large and to avoid the height of the gap from being too small.
  • the height of the gap 50 is too large, the height of the extension portion 41 will be too small, making it difficult to ensure the insulating performance of the insulating layer 40 , and at the same time, if the gap is too small, the dielectric constant between the adjacent metal lines 30 will still be large. , it is difficult to reduce the capacitance value of the parasitic capacitance between adjacent metal lines 30 . Therefore, the height of the gap is limited in this embodiment, which not only ensures the insulation performance of the insulating layer 40 but also reduces the adjacent metal lines 30 The capacitance value of the parasitic capacitance between them is used to reduce the signal delay of the interconnection structure, thereby improving the performance of the semiconductor structure.
  • the interconnect structure 100 further includes a barrier layer 60 disposed between the top surface of the dielectric layer 20 and the insulating layer 40, and between the top surface of the metal line 30 and the insulating layer 40, using the barrier The layer 60 is used to prevent the conductive material in the metal wire from diffusing into the insulating layer, so as to ensure the conductive performance of the metal wire.
  • the material of the barrier layer 60 may include silicon nitride or the like, and the configuration of the silicon nitride layer can not only realize the insulating arrangement between the metal wire and the conductive member disposed thereon, but also prevent the conductive material in the metal wire. diffuse into the insulating layer.
  • FIG. 3 is a flowchart of a method for fabricating an interconnect structure provided by an embodiment of the present application
  • FIGS. 4 to 10 are schematic diagrams of each stage of the method for fabricating an interconnect structure. The following describes the fabrication of the interconnect structure with reference to FIGS. 3 to 10 . method is introduced.
  • an embodiment of the present application provides a method for preparing an interconnect structure, including the following steps:
  • the substrate 10 is used as a supporting member of the interconnection structure 100 to support other components disposed thereon, wherein the substrate 10 may be an oxide layer, for example, the substrate 10 may be a silicon oxide layer .
  • a conductive plunger 70 is also disposed in the substrate 10 , and the conductive plunger 70 can be used to realize the electrical connection between the metal line in the interconnection structure 100 and the active area of the substrate.
  • a photoresist layer with a pattern can be formed on the substrate 10, and the photoresist layer is used as a mask to form a plurality of spaced accommodating grooves on the substrate 10, and then an atomic layer deposition process or a chemical deposition process is used.
  • a certain thickness of conductive material, such as metal tungsten, is deposited in the accommodating groove, and the conductive material constitutes the conductive plug 70 .
  • S200 forming a dielectric layer on the substrate, and a plurality of metal lines arranged at intervals are arranged in the dielectric layer.
  • the initial dielectric layer 23 is formed on the substrate 10 .
  • an atomic layer deposition process ALD for short
  • CVD chemical vapor deposition
  • PECAD plasma enhanced chemical deposition process
  • the initial dielectric layer 23 is patterned, and a part of the initial dielectric layer 23 is etched to form a plurality of spaced openings 21 in the initial dielectric layer 23 , and the remaining initial dielectric layer 23 constitutes the dielectric layer 20 .
  • a photoresist layer 80 is formed on the surface of the initial dielectric layer 23 away from the substrate 10 , and the photoresist layer 80 is patterned by exposing, developing or etching, so that the photoresist layer 80 is formed on the surface of the initial dielectric layer 23 .
  • a mask pattern is formed, and the mask pattern includes a plurality of shielding regions and a plurality of opening regions 81 arranged alternately.
  • the initial dielectric layer 23 is patterned along the opening area 81 , that is, the initial dielectric layer 23 exposed in the opening area 81 is removed by dry etching or wet etching, so as to form multiple layers of the initial dielectric layer 23 in the initial dielectric layer 23 .
  • the openings 21 are arranged at intervals, and the remaining initial dielectric layer 23 constitutes the dielectric layer 20 .
  • the portion above the dotted line in FIG. 5 is the opening area 81
  • the portion below the dotted line is the opening 21 .
  • the photoresist layer 80 located on the dielectric layer 20 is removed by a cleaning solution or a cleaning gas, and then a metal line 30 is formed in the opening 21 by an atomic layer deposition process or a chemical vapor deposition process, and the metal line 30 is away from the substrate.
  • the top surface of the dielectric layer 10 is flush with the top surface of the dielectric layer 20, wherein the metal wire 30 may include a conductive material such as metal tungsten.
  • a barrier layer 60 is formed on the dielectric layer 20 and the metal wire 30 in order to prevent the conductive material in the metal wire from diffusing to the insulating layer.
  • an atomic layer deposition process or a chemical vapor deposition process may be used to form a certain thickness of the barrier layer 60 on the top surfaces of the dielectric layer 20 and the metal line 30 , wherein the material of the barrier layer 60 may include silicon nitride or the like.
  • the dielectric layer 20 located between the adjacent metal lines 30 is patterned to form grooves 22 in the dielectric layer 20 , and the bottoms of the grooves 22 expose the surface of the substrate 10 , namely
  • the groove 22 may extend in a direction perpendicular to the substrate 10 until the bottom of the groove 22 exposes the surface of the substrate, that is, the groove 22 is a groove passing through the dielectric layer 20, and the bottom of the groove 22 is the upper surface of the substrate 10 .
  • the width of the grooves 22 may be smaller than the spacing between adjacent metal lines 30 , so that the dielectric layer 20 covers the side surfaces of the metal lines 30 facing the grooves 22 , which can ensure the adjacent metal lines 30 . insulation between the metal wires 30 .
  • the step of forming the insulating layer on the dielectric layer includes:
  • step a a sub-catalyst layer is formed on the side surface of the groove and the top surface of the dielectric layer, and there is a gap between the sub-catalyst layer located on the side surface of the groove and the substrate.
  • impurity elements are implanted into the side surfaces of the grooves 22 and the top surface of the dielectric layer 20 by a directional deposition technique. Impurity elements are injected into the top surface of the layer 20, wherein the impurity elements form a sub-catalyst layer 42 on the surface of the dielectric layer 20, and the sub-catalyst layer 42 has a strong adsorption capacity, which can enhance the connection between the dielectric layer 20 and the sub-filling layer formed subsequently. Binding force.
  • the impurity element may be at least one of a boron group element, boron trifluoride, aluminum trichloride, and sulfur trioxide, wherein the boron group element may include boron, aluminum, and chromium.
  • the above-mentioned elements are deposited on part of the side surfaces of the grooves 22 and the top surface of the dielectric layer 20 by directional deposition technology, and the above-mentioned impurity elements can react with the surface of the dielectric layer 20 to form an electron-withdrawing compound, and the electron-withdrawing compound constitutes an electron-withdrawing compound.
  • Catalytic layer 42 .
  • the distance between the end face of the sub-catalyst layer 42 facing the substrate 10 and the substrate 10 is denoted as H2, the depth of the groove 22 is H1, and H2 is equal to 2/3H1 to 3/4H1.
  • the distance between the sub-catalyst layer 42 facing the substrate 10 is The distance between the end face and the substrate 10 is designed to ensure that there is a gap between the end face of the insulating layer 40 that is subsequently formed on the sub-catalyst layer facing the substrate 10 and the substrate 10 .
  • the sub-catalyst layer 42 can be deposited by controlling the angle between the injection direction of the directional deposition technique and the direction perpendicular to the substrate 10 .
  • the angle ⁇ between the injection direction of the directional deposition technique and the direction perpendicular to the substrate 10 is an acute angle, for example, the angle ⁇ between the injection direction of the directional deposition technique and the direction perpendicular to the substrate 10 is 5°- 45°.
  • a gap can be ensured between the sub-catalyst layer 42 formed on the side surface of the groove 22 and the substrate 10 . , to ensure that a gap 50 is also formed between the insulating layer 40 and the substrate 10 subsequently formed, thereby reducing the capacitance value of the parasitic capacitance formed between adjacent metal lines and improving the performance of the semiconductor structure.
  • step b a sub-filling layer is formed on the sub-catalyzing layer, and the sub-filling layer reacts to form a sub-insulating layer.
  • a sub-filling layer with a certain thickness is deposited on the sub-catalyst layer 42 by a directional deposition technique.
  • a physical vapor deposition or plasma implantation process may be used to form a sub-filling layer on the sub-catalyst layer 42 , wherein , the material of the sub-filling layer can be a silicon oxide precursor, for example, the silicon oxide precursor can be a silicon-containing compound such as SiH4, TMS or 3-tert-butylsilanol and the like.
  • this embodiment utilizes the strong chemical bonding ability of the sub-catalyst layer, so that the sub-fill layer can only be deposited on the sub-catalyst layer 42, and then There is a gap between the prepared sub-insulating layer 43 and the substrate.
  • the temperature of the reaction chamber for depositing the sub-filling layer is increased, so that the conditions of the thermal oxidation process are satisfied in the reaction chamber, so that the sub-filling layer is reacted under high temperature conditions to form the sub-filling layer.
  • the insulating layer 43 wherein the material of the sub-insulating layer 43 is silicon oxide.
  • the reaction temperature at which the sub-filling layer reacts is 200°C-400°C, and the reaction temperature is controlled to ensure that the sub-filling layer and the sub-catalyst layer fully react to facilitate the formation of the sub-insulating layer.
  • step c a sub-catalytic layer and a sub-filling layer are sequentially formed on the sub-insulating layer, and the sub-filling layer reacts to form another sub-insulating layer.
  • an impurity element is injected into the sub-insulating layer 43 through a directional deposition technique, and the impurity element forms a sub-catalyst layer 42 on the surface of the sub-insulating layer 43, and the sub-catalyst layer 42 is used to enhance the bonding force between the sub-insulating layer 43 and the sub-filling layer.
  • the material and function of the neutron catalytic layer in this embodiment are the same as those of the sub catalytic layer in step a, which will not be repeated in this embodiment.
  • Step b and step c are repeated at least once more until the insulating layer 40 is formed, the structure of which is shown in FIG. 2 .
  • the insulating layer 40 may include a plurality of sub-insulating layers 43 that are stacked in sequence, and the portion of the insulating layer 40 located in the groove 22 constitutes the extension portion 41.
  • the insulating layer 40 is sequentially divided into a first sub-insulating layer, a second sub-insulating layer . . . and an n-th sub-insulating layer along the direction toward the groove 22 .
  • a first sub-catalyst layer is formed on the side surface of the groove 22 and the top surface of the dielectric layer 20 by using the directional deposition technology. Gap 50.
  • the directional deposition technology is used to inject a silicon oxide precursor onto the first sub-catalyst layer, and the silicon oxide precursor reacts at a certain temperature to form the first sub-insulating layer.
  • a second sub-catalytic layer is formed on the first sub-insulating layer by using a directional deposition technique.
  • a silicon oxide precursor is injected onto the second sub-catalyst layer using a directional deposition technique, and the silicon oxide precursor reacts at a certain temperature to form a second sub-insulating layer.
  • the third sub-catalytic layer, the third sub-insulating layer are formed on the second sub-insulating layer... and the n-th sub-catalytic layer and the n-th sub-insulating layer are formed on the n-1 th sub-insulating layer.
  • the number of sub-insulating layers, the second sub-insulating layer . . . and the n-th sub-insulating layer constitute the insulating layer 40, and n is a positive integer.
  • the insulating layer 40 can be formed by repeating the above-mentioned steps b and c for many times, or only the above-mentioned steps a and b can be used to directly form the insulating layer 40 that fills part of the groove 22 , which is not specifically limited in this embodiment.
  • the preparation method of the interconnect structure provided in this embodiment can make a gap between the insulating layer located between adjacent metal lines and the substrate, that is, there is an air gap between the adjacent metal lines, so that the use of The dielectric constant of the air is smaller than that of the insulating layer, which reduces the capacitance value of the parasitic capacitance between adjacent metal lines, so as to reduce the signal delay of the interconnect structure, thereby improving the performance of the semiconductor structure.

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Abstract

本申请提供一种互连结构及其制备方法、半导体结构，涉及半导体技术领域，该互连结构包括基底、设置在基底上的介质层以及绝缘层，所述介质层内间隔设置有多条金属线；相邻的所述金属线之间的所述介质层内设置有凹槽，所述凹槽的槽底暴露所述基底的表面；所述绝缘层具有延伸至所述凹槽内的延伸部，所述延伸部与所述基底之间具有间隙。本申请通过使位于相邻的金属线之间的绝缘层与基底之间具有间隙，即，位于相邻的金属线之间具有空气隙，这样可以利用空气的介电常数小于绝缘层的介电常数，降低相邻的金属线之间的寄生电容的电容值，以减小互连结构的信号延迟，进而提高半导体结构的性能。

Description

互连结构及其制备方法、半导体结构
本申请要求于2021年02月03日提交中国专利局、申请号为202110149536.X、申请名称为“互连结构及其制备方法、半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种互连结构及其制备方法、半导体结构。
背景技术
在半导体结构制作过程中，互连结构是半导体结构中不可或缺的结构，例如，动态随机存储器((Dynamic Random Access Memory，简称DRAM))，所形成的动态随机存储器通常包括核心存储区和外围电路区，其中，核心存储区用于设置多个存储单元，用于对数据信息进行存储，核心存储区和外围电路区通常包括互连结构，互连结构用于与存储单元电连接，以使得存储单元完成对数据信息的存储或者读取。
相关技术中，互连结构通常包括至少一个互连层，互连层包括多个间隔设置的金属线以及用于隔离各个金属线的介质层，随着半导体结构向小型化、集成化的方向发展，使得位于同一个互连层中的相邻金属线之间的间距也随之减小，相邻的金属线之间可以形成寄生电容，该寄生电容的存在会导致信号延迟，降低半导体结构的性能。
发明内容
本申请实施例的第一方面提供一种互连结构，其包括：
基底。
介质层，所述介质层设置在所述基底上，所述介质层内间隔设置有多条金属线；相邻的所述金属线之间的所述介质层内设置有凹槽，所述凹槽 的槽底暴露出所述基底的表面。
绝缘层，所述绝缘层设置在所述介质层上，所述绝缘层具有延伸至所述凹槽内的延伸部，所述延伸部与所述基底之间具有间隙。
本申请实施例的第二方面提供一种互连结构的制备方法，包括如下步骤：
提供基底。
在所述基底上形成介质层，所述介质层内设置有间隔设置的多条金属线。
图形化所述介质层，在所述介质层内形成多个凹槽，所述凹槽位于相邻的所述金属线之间，且所述凹槽的槽底暴露出所述基底的表面。
在所述介质层上形成绝缘层，所述绝缘层具有延伸至所述凹槽内的延伸部，所述延伸部与所述基底之间具有间隙。
本申请实施例的第三方面提供一种半导体结构，包括如上所述的互连结构。
本申请实施例所提供的互连结构及其制备方法、半导体结构中，通过使位于相邻的金属线之间的绝缘层与基底之间具有间隙，即，位于相邻的金属线之间具有空气隙，这样可以利用空气的介电常数小于绝缘层的介电常数，降低相邻的金属线之间的寄生电容的电容值，以减小互连结构的信号延迟，进而提高半导体结构的性能。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的互连结构及其制备方法、半导体结构所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
图1为相关技术中提供的互连结构的示意图；
图2为本申请实施例提供的互连结构的示意图；
图3为本申请实施例提供的互连结构的制备方法的流程图；
图4为本申请实施例提供的互连结构的制备方法中形成介质层的示意 图；
图5为本申请实施例提供的互连结构的制备方法中形成凹槽的示意图；
图6为本申请实施例提供的互连结构的制备方法中形成金属线的示意图；
图7为本申请实施例提供的互连结构的制备方法中形成阻挡层的示意图；
图8为本申请实施例提供的互连结构的制备方法中形成子催化层的过程图；
图9为本申请实施例提供的互连结构的制备方法中形成子催化层的示意图；
图10为本申请实施例提供的互连结构的制备方法中形成子绝缘层的示意图。
附图标记：
100：互连结构；              10：基底；
20：介质层；                 21：开口；
22：凹槽；                   23：初始介质层；
30：金属线；                 40：绝缘层；
41：延伸部；                 42：子催化层；
43：子绝缘层；               50：间隙；
60：阻挡层；                 70：导电柱塞；
80：光刻胶层；               81：开口区。
具体实施方式
本申请的发明人在实际的工作中发现，如图1所示，半导体结构的尺寸(如厚度或者长度)越小，互连结构100内相邻的金属线30之间的垂直距离和水平距离也会随之减小，该相邻的金属线之间会形成寄生电容，这些寄生电容会导致互连结构出现信号延迟，降低半导体结构的性能。
针对上述的技术问题，本申请实施例提供了一种互连结构及其制备方法、半导体结构，通过使位于相邻的金属线之间的绝缘层与基底之间具有间隙，即，位于相邻的金属线之间具有空气隙，这样可以利用空气的介电常数小于绝缘层的介电常数，降低相邻的金属线之间的寄生电容的电容值， 以减小互连结构的信号延迟，进而提高半导体结构的性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
本实施例提供一种半导体结构，例如，半导体结构可以为动态随机存储器(DRAM)，下面将以半导体结构为动态随机存取存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
示例性地，半导体结构可以包括基底，基底可以具有阵列区以及与阵列区连接的外围电路区，其中，阵列区内设置有阵列排布的电容器，外围电路区上设置有互连结构，通过互连结构与电容器电连接，以实现动态随机存储器对数据信息的存储或者读取。
如图2所示，互连结构100可以包括基底10、具有金属线30的介质层20，以及绝缘层40，其中，基底10作为互连结构100的支撑部件，用于支撑设置在其上的其他部件，基底10可以为氧化层，例如，基底10可以为氧化硅层。
基底10内还可以设置多个导电柱塞70，导电柱塞70与金属线30一一对应，且导电柱塞70的一端与金属线30连接，导电柱塞70的另一端与基底10内的有源区连接，用于实现金属线30与基底10内有源区之间的连接，以实现半导体结构性能，即实现动态随机存储器对数据信息的存储或者读取。其中，导电柱塞70的材质可以包括金属钨等导电材质。
介质层20设置在基底10上，介质层20内间隔设置有多条金属线30，需要说明的是，多条金属线30可以沿着基底10的水平方向间隔设置，相邻的金属线30之间的间距可以相同，也可以不同，本实施例在此不做具体的限定。
需要说明的是，在本实施例中基底10的水平方向可以为图2中X方向。
在本实施例中，介质层20的材质可以包括氧化硅等，利用氧化硅的绝缘性实现相邻的金属线30的绝缘性。
相邻的金属线30之间的介质层20内设置有凹槽，凹槽可以沿着垂直于基底的方向延伸，直至凹槽的槽底暴露出基底10的表面，即凹槽为沿垂直于基底的方向贯穿介质层20的沟槽，槽底为基底10的上表面。
示例性地，在本实施例中凹槽的宽度可以小于相邻的金属线30之间的间距，这样使得介质层20覆盖在金属线30朝向凹槽的侧面上，这样可以保证相邻的金属线30之间的绝缘性。
进一步地，介质层20上设置有绝缘层40，其中，绝缘层40的材质可以包括氧化硅等，利用氧化硅的绝缘性实现相邻的金属线30的绝缘性的同时，也可以实现位于该金属线30上方的其他金属线之间的绝缘性。
绝缘层40具有延伸至凹槽内的延伸部41，延伸部41与基底10之间具有间隙50，使得延伸部41朝向基底10的端面与基底10之间具有一定距离，即，位于相邻的金属线30之间具有空气隙，本实施例利用空气的介电常数小于绝缘层40的介电常数，可以降低相邻的金属线之30间的寄生电容的电容值，以减小互连结构的信号延迟，进而提高半导体结构的性能。
在一些实施例中，延伸部41朝向基底10的端面与基底10的上表面之间的距离占凹槽的深度的2/3～3/4，也就是说，H2等于2/3H1～3/4H1，本实施例对间隙50的高度进行了限定，既要避免间隙的高度过大，也要避免间隙的高度过小。
若间隙50的高度过大，会导致延伸部41的高度过小，难以保证绝缘层40的绝缘性能，同时，若间隙过小，会导致相邻金属线30之间的介电常数仍然较大，难以降低相邻的金属线30之间的寄生电容的电容值，因此，本实施例对间隙的高度进行了限定，既要保证绝缘层40的绝缘性能，也要降低相邻的金属线30之间的寄生电容的电容值，以减小互连结构的信号延迟，进而提高半导体结构的性能。
在一些实施例中，互连结构100还包括阻挡层60，阻挡层60设置在介质层20的顶面与绝缘层40之间，以及金属线30的顶面与绝缘层40之间，利用阻挡层60来防止金属线中的导电材料向绝缘层中扩散，保证了金属线的导电性能。
具体地，阻挡层60的材质可以包括氮化硅等，利用氮化硅层的设置既 可以实现金属线与设置在其上的导电部件之间的绝缘设置，也可以阻止金属线中的导电材料向绝缘层中扩散。
图3为本申请实施例提供的互连结构的制备方法的流程图；图4至图10为互连结构的制备方法的各阶段的示意图，下面结合图3至图10对互连结构的制造方法进行介绍。
如图3所示，本申请实施例提供了一种互连结构的制备方法，包括如下步骤：
S100：提供基底。
示例性地，如图4所示，基底10作为互连结构100的支撑部件，用于支撑设在其上的其他部件，其中，基底10可以为氧化层，例如，基底10可以为氧化硅层。
基底10内还设置有导电柱塞70，可以利用导电柱塞70实现互连结构100中的金属线与基底的有源区之间的电连接。
具体地，可以在基底10上形成具有图案的光刻胶层，利用光刻胶层作为掩膜版，在基底10上形成多个间隔设置容置槽，然后利用原子层沉积工艺或者化学沉积工艺在容置槽内沉积一定厚度的导电物质，例如，金属钨，该导电物质构成导电柱塞70。
S200：在基底上形成介质层，介质层内设置有间隔设置的多条金属线。
示例性地，在基底10上形成初始介质层23。
具体地，可以采用原子层沉积工艺(简称ALD)、化学气相沉积工艺(简称CVD)或者等离子体增强化学沉积工艺(简称PECAD)在基底10的上表面上形成一定厚度的初始介质层23；其中，初始介质层23的材质可以包括氧化硅或者氮化硅等材质。
图形化初始介质层23，刻蚀部分初始介质层23，以在初始介质层23内形成多个间隔设置的开口21，被保留下来的初始介质层23构成介质层20。具体地，如图4所示，在初始介质层23背离基底10的表面上形成光刻胶层80，采用曝光、显影或者蚀刻的方式图形化光刻胶层80，以在光刻胶层80形成掩膜图案，掩膜图案包括交替设置的多个遮挡区和多个开口区81。
如图5所示，沿开口区81图形化初始介质层23，即采用干法刻蚀或 者湿法刻蚀去除暴露在开口区81内的初始介质层23，以在初始介质层23内形成多个间隔设置的开口21，被保留下来的初始介质层23构成介质层20。
需要说明的是，位于图5中的虚线上方的部分为开口区81，位于虚线下方的部分为开口21。
如图6所示，采用清洗液或者清洗气体去除位于介质层20上的光刻胶层80，然后利用原子层沉积工艺或者化学气相沉积工艺在开口21内形成金属线30，金属线30背离基底10的顶面与介质层20的顶面平齐，其中，金属线30可以包括金属钨等导电材料。
进一步地，如图7所示，为了阻止金属线中的导电材料向绝缘层扩散，本实施例在介质层20和金属线30上形成阻挡层60。
具体地，可以采用原子层沉积工艺或者化学气相沉积工艺在介质层20和金属线30的顶面上形成一定厚度的阻挡层60，其中，阻挡层60的材质可以包括氮化硅等。
S300：图形化介质层，在介质层内形成多个凹槽，凹槽位于相邻的金属线之间，且凹槽的槽底暴露出基底的表面。
如图8所示，对位于相邻的金属线30之间的介质层20进行图形化处理，以在介质层20内形成凹槽22，凹槽22的槽底暴露出基底10的表面，即凹槽22可以沿着垂直于基底10的方向延伸，直至凹槽22的槽底暴露出基底的表面，也就是说，凹槽22为贯穿介质层20的沟槽，且凹槽22的槽底为基底10的上表面。
示例性地，在本实施例中凹槽22的宽度可以小于相邻的金属线30之间的间距，这样使得介质层20覆盖在金属线30朝向凹槽22的侧面上，这样可以保证相邻的金属线30之间的绝缘性。
S400：在介质层上形成绝缘层，绝缘层具有延伸至凹槽内的延伸部，延伸部与基底之间具有间隙。
示例性地，在介质层上形成绝缘层的步骤中包括：
步骤a，在凹槽的侧面和介质层的顶面上形成子催化层，位于凹槽的侧面上的子催化层与基底之间具有间隙。
具体地，如图9所示，通过定向沉积技术向凹槽22的侧面和介质层20的顶面上注入杂质元素，例如，可以采用物理气相沉积或者等离子注入 工艺向凹槽22的侧面和介质层20的顶面注入杂质元素，其中，杂质元素在介质层20表面上形成子催化层42，子催化层42有较强的吸合能力，能够增强介质层20与后续形成的子填充层的结合力。
在本实施例中，杂质元素可以为硼族元素、三氟化硼、三氯化铝以及三氧化硫中的至少一种，其中，硼族元素可以包括硼、铝以及铬。
通过定向沉积技术将上述的元素沉积在凹槽22的部分侧面和介质层20的顶面上，上述的杂质元素可以与介质层20的表面上发生反应形成吸电子化合物，该吸电子化合物构成子催化层42。
在本实施例中，位于凹槽22的侧面上的子催化层42与基底10之间具有间隙50，也就是说，位于凹槽22的侧面上的子催化层42的底面与衬底的顶面并不重合。
子催化层42朝向基底10的端面与基底10之间的间距记为H2，凹槽22的深度为H1，H2等于2/3H1～3/4H1，本实施例对子催化层42朝向基底10的端面与基底10之间的间距进行设计，用于保证后续在子催化层上形成的绝缘层40朝向基底10的端面与基底10之间具有间隙。
在具体实施时，可以通过控制定向沉积技术的注入方向与垂直于基底10的方向之间的夹角，来沉积子催化层42。
示例性地，定向沉积技术的注入方向与垂直于基底10的方向之间的夹角α为锐角，例如，定向沉积技术的注入方向与垂直于基底10的方向之间的夹角为5°-45°。
本实施例通过对定向沉积技术的注入方向与垂直于基底10的方向之间的夹角进行特殊的设计，可以保证在凹槽22的侧面上形成的子催化层42与基底10之间具有间隙，以保证后续所形成的绝缘层40与基底10之间也具有间隙50，进而可以降低相邻的金属线之间形成寄生电容的电容值，提高半导体结构的性能。
步骤b，在子催化层上形成子填充层，子填充层发生反应形成一层子绝缘层。
具体地，如图10所示，通过定向沉积技术在子催化层42上沉积一定厚度的子填充层，例如，可以采用物理气相沉积或者等离子注入工艺在子催化层42上形成子填充层，其中，子填充层的材质可以为氧化硅前驱体，例如，氧化硅前驱体可以为含硅的化合物如SiH4，TMS或3-叔丁基硅烷 醇基等。
鉴于前驱体的分子量较大，很难直接沉积在基底或者介质层上，因此，本实施例利用子催化层较强的化学键合能力，使得子填充层只能沉积在子催化层42上，进而使得制备出的子绝缘层43与基底之间具有间隙。
当子填充层沉积在子催化层上之后，增加用于沉积子填充层的反应腔室的温度，使得反应腔内满足热氧化工艺的条件，进而使得子填充层在高温条件下反应以形成子绝缘层43，其中，子绝缘层43的材质为氧化硅。
在本实施例中，子填充层发生反应的反应温度为200℃-400℃，通过对反应温度进行控制，以保证子填充层与子催化层充分反应，便于子绝缘层的形成。
步骤c，在子绝缘层上依次形成子催化层和子填充层，子填充层发生反应形成另一层子绝缘层。
具体地，通过定向沉积技术向子绝缘层43上注入杂质元素，杂质元素在子绝缘层43表面上形成子催化层42，子催化层42用于增强子绝缘层43与子填充层的结合力。其中，本实施例中子催化层与步骤a中的子催化层的材质和功能均相同，本实施例在此不再多加赘述。
至少重复一次以上的步骤b和步骤c，直至形成绝缘层40，其结构图2所示。
也就是说，绝缘层40可以包括多个依次层叠设置的子绝缘层43，且绝缘层40位于凹槽22内的部分构成延伸部41，为了便于对绝缘层40的形成过程进行详细的阐述，本实施例将绝缘层40沿朝向凹槽22的方向依次划分为第一个子绝缘层、第二个子绝缘层….以及第n个子绝缘层，各个子绝缘层的形成步骤如下：
采用定向沉积技术在凹槽22的侧面和介质层20的顶面上形成第一个子催化层，第一个子催化层具有吸电子化合物，且第一个子催化层与基底10之间具有间隙50。
再利用定向沉积技术向第一个子催化层上注入氧化硅前驱体，氧化硅前驱体在一定温度下发生反应，形成第一个子绝缘层。
待形成第一个子绝缘层之后，再利用定向沉积技术向第一个子绝缘层上形成第二个子催化层。
待形成第二个子催化层之后，利用定向沉积技术向第二个子催化层上 注入氧化硅前驱体，氧化硅前驱体在一定温度下发生反应，形成第二个子绝缘层。
依次类推，在第二个子绝缘层上形成第三个子催化层、第三个子绝缘层……在第n-1个子绝缘层上形成第n个子催化层和第n个子绝缘层，上述的第一个子绝缘层、第二个子绝缘层….以及第n个子绝缘层构成绝缘层40，且n为正整数。
需要说明的是，本实施例中绝缘层40可以通过多次重复上述的步骤b和步骤c来形成，也可以只采用上述的步骤a和步骤b直接形成填充满部分凹槽22的绝缘层40，本实施例在此不做具体限定。
本实施例所提供的互连结构的制备方法，能够使位于相邻的金属线之间的绝缘层与基底之间具有间隙，即，位于相邻的金属线之间具有空气隙，这样可以利用空气的介电常数小于绝缘层的介电常数，降低相邻的金属线之间的寄生电容的电容值，以减小互连结构的信号延迟，进而提高半导体结构的性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (17)

  1. 一种互连结构，包括：
    基底；
    介质层，所述介质层设置在所述基底上，所述介质层内间隔设置有多条金属线，相邻的所述金属线之间的所述介质层内设置有凹槽，所述凹槽的槽底暴露出所述基底的表面；
    绝缘层，所述绝缘层设置在所述介质层上，所述绝缘层具有延伸至所述凹槽内的延伸部，所述延伸部与所述基底之间具有间隙。
  2. 根据权利要求1所述的互连结构，其中，所述延伸部靠近所述基底的端面与所述基底之间的距离占所述凹槽的深度的2/3～3/4。
  3. 根据权利要求2所述的互连结构，其中，所述介质层的顶面和所述金属线的顶面与所述绝缘层之间均设置有阻挡层，所述阻挡层用于阻止所述金属线中的导电材料向所述绝缘层扩散。
  4. 根据权利要求3所述的互连结构，其中，所述阻挡层的材质为氮化硅。
  5. 根据权利要求1-4任一项所述的互连结构，其中，所述介质层和所述绝缘层的材质均为氧化硅。
  6. 根据权利要求1-4任一项所述的互连结构，其中，所述基底内还设置有与所述金属线一一对应设置的导电柱塞，所述导电柱塞的一端与所述金属线连接，所述导电柱塞的另一端用于与所述基底内的有源区连接。
  7. 一种互连结构的制备方法，包括如下步骤：
    提供基底；
    在所述基底上形成介质层，所述介质层内设置有间隔设置的多条金属线；
    图形化所述介质层，在所述介质层内形成多个凹槽，所述凹槽位于相邻的所述金属线之间，且所述凹槽的槽底暴露出所述基底的表面；
    在所述介质层上形成绝缘层，所述绝缘层具有延伸至所述凹槽内的延伸部，所述延伸部与所述基底之间具有间隙。
  8. 根据权利要求7所述的互连结构的制备方法，其中，在所述介质层上形成绝缘层的步骤中包括：
    步骤a，在所述凹槽的侧面和所述介质层的顶面上形成子催化层，位于所述凹槽的侧面上的所述子催化层与所述基底之间具有间隙；
    步骤b，在所述子催化层上形成子填充层，所述子填充层发生反应形成一层子绝缘层；
    步骤c，在所述子绝缘层上依次形成所述子催化层和所述子填充层，所述子填充层发生反应形成另一层所述子绝缘层；
    至少重复一次以上的步骤b和步骤c，直至形成所述绝缘层。
  9. 根据权利要求8所述的互连结构的制备方法，其中，多个所述子绝缘层依次层叠设置构成所述绝缘层，且所述绝缘层位于所述凹槽内的部分构成所述延伸部。
  10. 根据权利要求8或9所述的互连结构的制备方法，其中，所述步骤a包括：
    通过定向沉积技术向所述凹槽的侧面和所述介质层的顶面上注入杂质元素，所述杂质元素在所述介质层表面上形成子催化层，所述子催化层含有吸电子化合物，用于增强所述介质层与所述子填充层的结合力；
    所述步骤b包括：
    通过定向沉积技术向所述子催化层上沉积氧化硅前驱体，所述氧化硅前驱体在一定温度下发生反应形成所述子绝缘层，所述氧化硅前驱体构成所述子填充层；
    所述步骤c包括：
    通过定向沉积技术向所述子绝缘层上注入杂质元素，所述杂质元素在所述子绝缘层表面上形成子催化层，所述子催化层用于增强所述子绝缘层与所述子填充层的结合力。
  11. 根据权利要求10所述的互连结构的制备方法，其中，所述定向沉积技术的注入方向与垂直于所述基底的方向之间的夹角为锐角。
  12. 根据权利要求11所述的互连结构的制备方法，其中，所述定向沉积技术的注入方向与垂直于所述基底的方向之间的夹角为5°-45°。
  13. 根据权利要求12所述的互连结构的制备方法，其中，所述杂质元素包括硼族元素、三氟化硼、三氯化铝以及三氧化硫中的至少一种。
  14. 根据权利要求8或9所述的互连结构的制备方法，其中，所述子填充层发生反应的反应温度为200℃-400℃。
  15. 根据权利要求7-9任一项所述的互连结构的制备方法，其中，在所述基底上形成介质层，所述介质层内设置有间隔设置的多条金属线的步骤包括：
    在所述基底上形成初始介质层；
    图形化所述初始介质层，刻蚀部分所述初始介质层，以在所述初始介质层内形成多个间隔设置的开口，被保留下来的所述初始介质层构成所述介质层；
    在所述开口内形成金属线，所述金属线背离所述基底的顶面与所述初始介质层的顶面平齐。
  16. 根据权利要求9所述的互连结构的制备方法，其中，在所述基底上形成介质层的步骤之后，在图形化所述介质层的步骤之前，所述方法还包括：
    在所述初始介质层上形成阻挡层，所述阻挡层用于阻止所述金属线中的导电材料向所述绝缘层扩散。
  17. 一种半导体结构，包括如权利要求1-6任一项所述的互连结构。
PCT/CN2021/106429 2021-02-03 2021-07-15 互连结构及其制备方法、半导体结构 WO2022166117A1 (zh)

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