WO2022155944A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022155944A1
WO2022155944A1 PCT/CN2021/073524 CN2021073524W WO2022155944A1 WO 2022155944 A1 WO2022155944 A1 WO 2022155944A1 CN 2021073524 W CN2021073524 W CN 2021073524W WO 2022155944 A1 WO2022155944 A1 WO 2022155944A1
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WIPO (PCT)
Prior art keywords
layer
lens
definition
substrate
pixel
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PCT/CN2021/073524
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English (en)
French (fr)
Inventor
顾仁权
郭康
张锋
王美丽
黄海涛
姚琪
谷新
黄华
袁广才
董学
王利波
孟德天
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/073524 priority Critical patent/WO2022155944A1/zh
Priority to CN202180000066.9A priority patent/CN115136315B/zh
Priority to US17/608,985 priority patent/US20230255092A1/en
Priority to EP21920339.5A priority patent/EP4120353A4/en
Publication of WO2022155944A1 publication Critical patent/WO2022155944A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/879—Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFTs thin film transistors
  • Exemplary embodiments of the present disclosure provide a display substrate, including a substrate, a driving structure layer disposed on the substrate, a light-emitting element disposed on the driving structure layer, an encapsulation layer disposed on the light-emitting element, a circular polarizer layer provided on the encapsulation layer, and a lens definition layer and a lens structure layer provided on the circular polarizer layer, wherein: the light-emitting element includes a pixel definition layer provided with a plurality of sub-pixel openings; the The lens structure layer includes a plurality of lenses arranged at intervals, the lens definition layer is arranged in the gap area between the adjacent lenses, and the orthographic projection of each of the lenses on the substrate includes at least one of the sub-substrates. Orthographic projection of pixel openings on the substrate.
  • Exemplary embodiments of the present disclosure also provide a display device including the display substrate described in any one of the foregoing.
  • Exemplary embodiments of the present disclosure also provide a method for manufacturing a display substrate, the method comprising:
  • a driving structure layer, a light-emitting element, an encapsulation layer and a circular polarizer layer are sequentially formed on the substrate, and the light-emitting element includes a pixel definition layer provided with a plurality of sub-pixel openings;
  • a lens definition layer and a lens structure layer are formed on the circular polarizer layer, the lens structure layer includes a plurality of lenses arranged at intervals, and the lens definition layer is arranged in the gap area between the adjacent lenses, each Each of the orthographic projections of the lens on the substrate includes an orthographic projection of at least one of the sub-pixel openings on the substrate.
  • FIG. 1 is a schematic diagram of a 3D display effect of a display substrate
  • FIG. 2 is a schematic plan view of a display substrate according to an embodiment of the disclosure.
  • FIG. 3 is a schematic cross-sectional structural diagram of a display substrate according to an embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel driving circuit of a display substrate according to an embodiment of the disclosure.
  • FIG. 5 is a working timing diagram of a pixel driving circuit of a display substrate according to an embodiment of the disclosure
  • 6a and 6b are schematic diagrams of the formation process of the lens definition layer and the lens structure layer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a 3D display effect of a display substrate according to an embodiment of the disclosure.
  • FIG. 8 is a schematic flowchart of a method for fabricating a display substrate according to an embodiment of the disclosure.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • connection includes a case where constituent elements are connected together by means of an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • a lens is a very familiar optical element.
  • the same lenses are arranged on a plane according to a certain period to form a lens array.
  • the optical properties of the lens array composed of ordinary lenses are the synthesis of the functions of a single lens.
  • the shrinkage rate of the imprinted rubber material is relatively large due to the imprinting on the entire surface of the large-sized substrates (the specific shrinkage rate is related to the substrate, about 0.1% or more), resulting in large-sized substrates.
  • the process variation of the substrate lens array and the underlying device is large.
  • the 3D display effect can be seen in Figure 1. As shown in Figure 1, the sub-pixels of the display substrate have uneven brightness. Moreover, the displays of the sub-pixels have crosstalk with each other, and the 3D display effect is not good.
  • FIG. 2 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate according to an exemplary embodiment of the present disclosure
  • the display substrate includes a base 101 , a driving structure layer 102 disposed on the base 101 , a light-emitting element 103 disposed on the driving structure layer 102 , an encapsulation layer 104 disposed on the light-emitting element 103 , The circular polarizer layer 105 provided on the encapsulation layer 104 and the lens definition layer 106 and the lens structure layer 107 provided on the circular polarizer layer 105 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the light-emitting element 103 includes a pixel definition layer provided with a plurality of sub-pixel openings.
  • the lens structure layer 107 includes a plurality of spaced lenses, the lens definition layer 106 is disposed in the gap region between adjacent lenses, and the orthographic projection of each lens on the substrate 101 includes at least one orthographic projection of the sub-pixel opening on the substrate 101 . projection.
  • the lens definition layer 106 by disposing the lens definition layer 106, the plurality of lenses in the lens structure layer 107 are separated by the lens definition layer 106 and are independent of each other. 106 creates an isolation effect between adjacent lenses, the entire lens structure does not experience large-scale shrinkage, and the shrinkage of the imprinted material forming each lens is negligible, thereby realizing large-sized nano-imprinted lenses and luminescence.
  • the precise alignment of the components 103 improves the 3D display effect.
  • the angular deviation of the display substrate of the embodiment of the present disclosure is within the design requirement (0.008°), which is far less than 0.17°.
  • the lens defining layer 106 includes a plurality of first defining lines 1061 extending along the first direction D1 and a plurality of second defining lines 1062 extending along the second direction D2 , a plurality of The intersection of the first definition line 1061 and the plurality of second definition lines 1062 define a plurality of grid regions, and the plurality of lenses are arranged in the plurality of grid regions in a one-to-one correspondence.
  • the pixel definition layer further includes a plurality of retaining walls disposed around the sub-pixel openings, and the orthographic projection of the retaining walls on the substrate 101 includes the orthographic projection of the lens definition layer 106 on the substrate 101 .
  • the material of the lens definition layer 106 is a hydrophobic material.
  • the hydrophobic material includes any one or more of the following: Teflon, polyamide, polyolefin, siloxane, and the like.
  • the substrate 101 may be a flexible substrate, or it may be a rigid substrate.
  • the driving structure layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and FIG. 3 takes the example of including one driving transistor and one storage capacitor in each sub-pixel for illustration.
  • the light-emitting element 103 may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the drain electrode of the driving transistor through a via hole, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer is connected to the anode and the cathode.
  • the light of the corresponding color is emitted under the drive.
  • the encapsulation layer 104 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer It is arranged between the first encapsulation layer and the third encapsulation layer to ensure that outside water vapor cannot enter the light-emitting element 103 .
  • the organic light emitting layer may include a stacked hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer, referred to as HTL), an electron blocking layer (Electron Block Layer, referred to as HIL) EBL), Emitting Layer (EML), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL).
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron blocking layer
  • EML Emitting Layer
  • HBL Hole Block Layer
  • ETL Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and the electron injection layer of all subpixels may be a common layer connected together
  • the hole transport layer and the electron transport layer of all subpixels may be a common layer connected together
  • all The hole blocking layers of the subpixels may be a common layer connected together
  • the light emitting layers and the electron blocking layers of adjacent subpixels may overlap slightly, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4 , the pixel driving circuit may include seven switching transistors (the first transistor T1 to the seventh transistor T7 ), one storage capacitor C and seven signal lines (the data signal line D, the first scan signal line S1 , the The second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power supply line VDD, and the second power supply line VSS).
  • the first end of the storage capacitor C is connected to the first power supply line VDD
  • the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3 Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits an initialization voltage to the gate of the third transistor T3 to initialize the charge amount of the gate of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and enables the data voltage of the data signal line D to be input to the pixel driving circuit when an on-level scan signal is applied to the first scan signal line S1.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3 , and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element 103 .
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting element 103 emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element 103.
  • the seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting element 103 to initialize the amount of charge accumulated in the first electrode of the light emitting element 103 or The amount of charge accumulated in the first electrode of the light-emitting element 103 is released.
  • the second pole of the light-emitting element 103 is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a high-level signal continuously provided.
  • the first scan signal line S1 is the scan signal line in the pixel driving circuit of the display row
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scan signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display line is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display line
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first scan signal line S1, the second scan signal line S2, the light emitting signal line E and the initial signal line INIT extend along the first direction D1, the second power supply line VSS, the first power supply line VDD and the data
  • the signal line D extends along the second direction D2.
  • the light-emitting element 103 may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 5 is a working timing diagram of a pixel driving circuit. Exemplary embodiments of the present disclosure will be described below through the operation process of the pixel driving circuit illustrated in FIG. 4 .
  • the pixel driving circuit in FIG. 4 includes 7 transistors (the first transistor T1 to the sixth transistor T7 ), and 1 storage capacitors C and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), all seven transistors are is a P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are a high-level signal.
  • the signal of the second scanning signal line S2 is a low level signal, which turns on the first transistor T1, and the signal of the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are a high-level signal
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scan signal line S1 is a low level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output from the data signal line D is supplied to the second through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 node N2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, and the voltage of the second end (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, initializes (resets) the first electrode of the OLED, clears the internal pre-stored voltage, completes the initialization, and ensures that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, so that the first transistor T1 is turned off.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the fifth transistor T5, the third transistor T3 and the sixth transistor T5, which are turned on.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A is the same as the boundary of the orthographic projection of B.
  • the projected boundaries overlap.
  • a substrate 101 is prepared on a glass carrier.
  • the substrate 101 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer films, and the first and second inorganic materials
  • the material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material can be amorphous silicon (a-si).
  • the preparation process may include: firstly coating a layer of polyimide on a glass carrier, and curing to form a film Then a first flexible (PI1) layer is formed; then a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then an amorphous layer is deposited on the first barrier layer A silicon film to form an amorphous silicon (a-si) layer covering the first barrier layer; then a layer of polyimide is coated on the amorphous silicon layer, and a second flexible (PI2) layer is formed after curing into a film; Then, a barrier film is deposited on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer to complete the preparation of the substrate 101 .
  • the substrate 101 may also be a rigid substrate.
  • a pattern of the driving structure layer 102 is formed on the substrate 101 .
  • the preparation process of the driving structure layer 102 may include:
  • a first insulating film and an active layer film are sequentially deposited on the substrate 101, and the active layer film is patterned through a patterning process to form a first insulating layer covering the entire substrate 101, and an active layer disposed on the first insulating layer
  • the pattern, the active layer pattern includes a first active layer.
  • a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer covering the pattern of the active layer, and a first gate metal disposed on the second insulating layer layer pattern, the first gate metal layer pattern includes a first gate electrode, a first capacitor electrode and a plurality of gate lines (not shown).
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a third insulating layer covering the first gate metal layer, and a second gate disposed on the third insulating layer
  • the metal layer pattern, the second gate metal layer pattern includes a second capacitor electrode, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.
  • a fourth insulating film is deposited, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer pattern covering the second gate metal layer.
  • the fourth insulating layer is provided with a plurality of first via holes, a plurality of first The positions of a via hole correspond to the two ends of the first active layer respectively, and the fourth insulating layer, the third insulating layer and the second insulating layer in the plurality of first via holes are etched away, exposing the fourth insulating layer, the third insulating layer and the second insulating layer respectively. a surface of the active layer.
  • the source-drain metal layer may further include any one or more of a power supply line (VDD), a compensation line and an auxiliary cathode, and the source-drain metal layer is also referred to as the first source. Drain metal layer (SD1).
  • VDD power supply line
  • SD1 drain metal layer
  • the driving structure layer 102 includes: a first insulating layer disposed on the substrate, an active layer disposed on the first insulating layer, a second insulating layer covering the active layer, and a first gate metal disposed on the second insulating layer layer, the third insulating layer covering the first gate metal layer, the second gate metal layer disposed on the third insulating layer, the fourth insulating layer covering the second gate metal layer, the source and drain disposed on the fourth insulating layer metal layer.
  • the active layer includes at least a first active layer, the first gate metal layer includes at least a first gate electrode and a first capacitor electrode, the second gate metal layer includes at least a second capacitor electrode, and the source-drain metal layer includes at least a first source electrode ,
  • the first drain electrode, the first active layer, the first gate electrode, the first source electrode and the first drain electrode form the first transistor, and the first capacitor electrode and the second capacitor electrode form the first storage capacitor.
  • the first transistor may be a driving transistor in a pixel driving circuit, and the driving transistor may be a thin film transistor (Thin Film Transistor, TFT).
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may employ silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of them may be a single layer, multiple layers or composite layers.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the layer inter-insulation (ILD) layer.
  • the first metal thin film, the second metal thin film and the third metal thin film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or More, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or More, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene polythiophene and other materials
  • the fabrication process of the light-emitting element 103 may include:
  • a first flat film is coated on the substrate formed with the aforementioned pattern, and the first flat film is patterned through a patterning process to form a first flat (PLN) layer pattern.
  • a second via hole is formed on the first flat layer, and the first flat layer in the second via hole is etched away to expose the surface of the first drain electrode.
  • a transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the transparent conductive film is patterned through a patterning process to form an anode pattern.
  • the anode is formed on the first flat layer and connected to the first drain electrode through the second via hole.
  • a pixel definition film is coated on the substrate formed with the aforementioned pattern, and a pixel definition (PDL) layer pattern is formed by masking, exposing and developing processes.
  • the pixel definition layer is provided with sub-pixel openings, and the pixel-defining film in the sub-pixel openings is developed away to expose the surface of the anode.
  • a spacer column layer pattern is formed on the substrate on which the aforementioned pattern is formed.
  • the spacer column layer includes a plurality of support columns, and the support columns are arranged on the pixel definition layer at intervals.
  • An organic light-emitting layer and a cathode are sequentially formed on the substrate on which the aforementioned pattern is formed, and the organic light-emitting layer is formed at least in the pixel opening to realize the connection between the organic light-emitting layer and the anode. Since the anode is connected to the first drain electrode of the first transistor, the connection between the organic light-emitting layer and the first drain electrode of the first transistor is realized.
  • the cathode is formed on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer
  • the cathode may use magnesium (Mg), silver (Ag), aluminum Any one or more of (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.
  • the light-emitting element may include an anode, a pixel definition (PDL) layer, a spacer pillar (PS), an organic light-emitting layer, a cathode, and the like.
  • PDL pixel definition
  • PS spacer pillar
  • the anode is arranged on the first flat layer, and is connected to the first drain electrode of the driving transistor through a via hole opened on the first flat layer;
  • the pixel definition layer is arranged on the anode and the flat layer, and a sub-pixel opening is arranged on the pixel definition layer, The sub-pixel opening exposes the anode;
  • the organic light-emitting layer is at least partially disposed in the sub-pixel opening, and the organic light-emitting layer is connected to the anode;
  • the cathode is disposed on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer;
  • the organic light-emitting layer is driven by the anode and the cathode emit light of the corresponding color.
  • the encapsulation layer 104 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, wherein the first encapsulation layer and the third encapsulation layer are made of inorganic materials, and the second encapsulation layer is made of organic materials .
  • a pattern of a circular polarizer (Circular Polarizer, CPOL) layer 105 is formed on the substrate on which the aforementioned pattern is formed.
  • the circular polarizer layer 105 may include an adhesive layer disposed on the encapsulation layer, a barrier layer disposed on the adhesive layer, a retardation layer disposed on the barrier layer, and a retardation layer disposed on the Polarizer layer on layer.
  • the lens structure layer 107 includes a plurality of lenses arranged at intervals, the lens definition layer 106 is arranged in the gap area between adjacent lenses, and the orthographic projection of each lens on the substrate 101 includes at least one sub-pixel opening on the substrate 101 orthographic projection.
  • the preparation process of the lens definition layer 106 and the lens structure layer 107 may include:
  • a layer of hydrophobic material is coated on the circular polarizer layer 105 , and the hydrophobic material is patterned by exposure and development of a photomask to form a pattern of the lens definition layer 106 .
  • the lens definition layer 106 includes a plurality of first definition lines 1061 extending along the first direction D1 and a plurality of second definition lines 1062 extending along the second direction D2, a plurality of first definition lines 1061 and a plurality of second definition lines 1062 The intersection defines a plurality of grid areas, each grid area corresponds to one or more sub-pixels formed above, and each grid area corresponds to a subsequently formed lens one-to-one;
  • the imprinting material is patterned by mask exposure and development to form a grid-shaped imprinting material.
  • the area imprinting material with the hydrophobic material is removed, and the area imprinting material without the hydrophobic material is retained, so as to form a grid-shaped imprinting material, each grid of imprinting material formed within a grid area defined by the lens definition layer 106;
  • the grid-shaped imprint material is subjected to an imprinting process using an imprint stencil to form a plurality of grid-shaped lenses.
  • the lens definition layer 106 makes adjacent lenses independent of each other.
  • the embossing material shrinks, for each individual lens, the embossing material shrinks by about 0.058um, and for a large-sized lens structure of 166um, the embossing material for each lens shrinks by about 0.058um.
  • the amount of shrinkage does not affect the display effect of the overall lens structure.
  • the hydrophobic material includes any one or more of the following: Teflon, polyamide, polyolefin, siloxane, and the like.
  • the exemplary embodiments of the present disclosure prepare a layer of lens-defining layer patterns by using a hydrophobic material, so that a plurality of imprinted lenses are meshed, which is similar to that of the present disclosure.
  • the adjacent lenses are independent of each other.
  • the imprint material shrinks, the entire lens structure will not experience large-scale shrinkage due to the isolation of the lens-defining layer, while the shrinkage of the imprint material constituting each independent lens is negligible.
  • the precise alignment of the large-sized nano-imprint lens and the light-emitting element is realized, and the 3D display effect is improved.
  • the 3D display effect of the display substrate of the embodiment of the present disclosure is shown in FIG. 7 .
  • Exemplary embodiments of the present disclosure show the structure of the substrate and the fabrication process thereof are merely illustrative. In the exemplary embodiment, the corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs, which is not limited in the present disclosure.
  • the present disclosure also provides a preparation method of a display substrate, the preparation method includes the following steps:
  • Step S1 forming a driving structure layer, a light-emitting element, an encapsulation layer and a circular polarizer layer in sequence on the substrate, and the light-emitting element includes a pixel definition layer provided with a plurality of sub-pixel openings;
  • Step S2 forming a lens definition layer and a lens structure layer on the circular polarizer layer, the lens structure layer includes a plurality of lenses arranged at intervals, the lens definition layer is arranged in the gap area between adjacent lenses, and each lens is on the substrate The orthographic projection of the at least one sub-pixel opening on the substrate.
  • a lens-defining layer is formed on the circular polarizer layer, comprising:
  • the hydrophobic material is patterned to form a lens definition layer.
  • a lens structure layer is formed on the circular polarizer layer, including:
  • the imprinting material is patterned to form a grid-shaped imprinting material, and the grid-shaped imprinting material does not overlap with the lens definition layer;
  • the grid-shaped imprint material is imprinted by an imprint stencil to form a plurality of lenses arranged at intervals.
  • the hydrophobic material includes any one or more of the following: Teflon, polyamide, polyolefin, siloxane, and the like.
  • the pixel-defining layer further includes a plurality of retaining walls disposed around the sub-pixel openings, and the orthographic projection of the retaining walls on the substrate includes the orthographic projection of the lens-defining layer on the substrate.
  • Exemplary embodiments of the present disclosure also provide a display device including the display substrate of the foregoing embodiments.
  • the display device of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the display device may be a wearable display device, which can be worn on the human body in some ways, such as a smart watch, a smart bracelet, and the like.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括基底、设置在基底上的驱动结构层、设置在驱动结构层上的发光元件、设置在发光元件上的封装层、设置在封装层上的圆偏振片层以及设置在圆偏振片层上的透镜定义层和透镜结构层，其中：发光元件包括设置有多个子像素开口的像素定义层；透镜结构层包括多个间隔设置的透镜，透镜定义层设置于相邻的透镜之间的间隙区域，每个透镜在基底上的正投影包含一个子像素开口在基底上的正投影。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光元件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开示例性实施例提供了一种显示基板，包括基底、设置在所述基底上的驱动结构层、设置在所述驱动结构层上的发光元件、设置在所述发光元件上的封装层、设置在所述封装层上的圆偏振片层以及设置在所述圆偏振片层上的透镜定义层和透镜结构层，其中：所述发光元件包括设置有多个子像素开口的像素定义层；所述透镜结构层包括多个间隔设置的透镜，所述透镜定义层设置于相邻的所述透镜之间的间隙区域，每个所述透镜在所述基底上的正投影包含至少一个所述子像素开口在所述基底上的正投影。
本公开示例性实施例还提供了一种显示装置，包括前述任一项所述的显示基板。
本公开示例性实施例还提供了一种显示基板的制备方法，所述制备方法包括：
在基底上依次形成驱动结构层、发光元件、封装层和圆偏振片层，所述发光元件包括设置有多个子像素开口的像素定义层；
在所述圆偏振片层上形成透镜定义层和透镜结构层，所述透镜结构层包括多个间隔设置的透镜，所述透镜定义层设置于相邻的所述透镜之间的间隙区域，每个所述透镜在所述基底上的正投影包含至少一个所述子像素开口在所述基底上的正投影。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示基板的3D显示效果示意图；
图2为本公开实施例一种显示基板的平面结构示意图；
图3为本公开实施例一种显示基板的剖面结构示意图；
图4为本公开实施例一种显示基板的像素驱动电路的结构示意图；
图5为本公开实施例一种显示基板的像素驱动电路的工作时序图；
图6a和图6b为本公开实施例的透镜定义层和透镜结构层的形成过程示意图；
图7为本公开实施例一种显示基板的3D显示效果示意图；
图8为本公开实施例一种显示基板的制备方法的流程示意图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解 一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一 极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
透镜是一种人们非常熟悉的光学元件，相同的透镜按一定的周期排列在一个平面上便构成了透镜阵列，由普通的透镜组成的透镜阵列的光学性质就是单个透镜功能的合成。通过将透镜(Lens)阵列集成在OLED器件上，可以实现OLED屏的多视点(View)3D/2D可兼容的高分辨率、多应用场景的显示。在OLED器件上进行透镜阵列制作可以采用纳米压印的制备工艺。在采用纳米压印进行大尺寸基板透镜阵列制作时，由于在大尺寸基板整面压印，压印胶材的收缩率较大(具体收缩率与基板有关，约0.1％以上)，导致大尺寸基板透镜阵列与下层器件的工艺偏差很大。
示例性的，显示面板(Panel中)有1920个子像素，透镜阵列的口径约为166um，子像素与透镜一一对应，采用纳米压印制备工艺进行整面压印时，单个透镜的收缩偏差约为0.058um，因此，整个透镜阵列的工艺偏差约为0.058um*1920＝111.36um，而设计容忍值偏差约为-4.4～3.6μm，导致整个透镜阵列的对位角度偏差约为0.17°，而设计要求仅为0.008°。因此，由于压印材料的收缩性，整体透镜阵列与显示面板的子像素之间存在较大偏差， 其3D显示效果可参照图1，如图1所示，显示基板的子像素亮度不均，而且各子像素的显示之间互相有串扰，3D显示效果不佳。
图2为本公开示例性实施例一种显示基板的平面结构示意图，图3为本公开示例性实施例一种显示基板的剖面结构示意图。如图2和图3所示，该显示基板包括基底101、设置在基底101上的驱动结构层102、设置在驱动结构层102上的发光元件103、设置在发光元件103上的封装层104、设置在封装层104上的圆偏振片层105以及设置在圆偏振片层105上的透镜定义层106和透镜结构层107。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
其中，发光元件103包括设置有多个子像素开口的像素定义层。
透镜结构层107包括多个间隔设置的透镜，透镜定义层106设置于相邻的透镜之间的间隙区域，每个透镜在基底101上的正投影包含至少一个子像素开口在基底101上的正投影。
本公开实施例通过设置透镜定义层106，使得透镜结构层107中的多个透镜被透镜定义层106隔开，彼此之间相互独立，当形成透镜的压印材料发生收缩时，由于透镜定义层106在相邻透镜之间产生隔离作用，整个透镜结构不会出现大尺寸的收缩，而对于形成每个透镜的压印材料的收缩则可忽略不计，从而实现了大尺寸纳米压印透镜与发光元件103的精准对位，提高了3D显示效果。本公开实施例的显示基板的角度偏差在设计要求(0.008°)之内，远小于0.17°。
在示例性实施例中，如图2所示，透镜定义层106包括多条沿第一方向D1延伸的第一定义线1061和多条沿第二方向D2延伸的第二定义线1062，多条第一定义线1061和多条第二定义线1062交叉限定出多个网格区域，多个透镜一一对应地设置在多个网格区域内。
在示例性实施例中，像素定义层还包括多个围绕子像素开口设置的挡墙，挡墙在基底101上的正投影包含透镜定义层106在基底101上的正投影。
在示例性实施例中，透镜定义层106的材料为疏水材料。
在示例性实施例中，疏水材料包括以下任意一种或多种：特氟龙、聚酰胺、聚烯烃、硅氧烷类等。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动结构层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中以每个子像素中包括一个驱动晶体管和一个存储电容为例进行示意。发光元件103可以包括阳极、像素定义层、有机发光层和阴极，阳极通过过孔与驱动晶体管的漏电极连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光元件103。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个开关晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶 体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光元件103的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光元件103发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光元件103的 第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光元件103的第一极，以使发光元件103的第一极中累积的电荷量初始化或释放发光元件103的第一极中累积的电荷量。
在示例性实施方式中，发光元件103的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿第一方向D1延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿第二方向D2延伸。
在示例性实施方式中，发光元件103可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为 Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd)] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
(1)在玻璃载板上制备基底101。在示例性实施方式中，基底101可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1) 层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底101的制备。
在示例性实施方式中，基底101也可以是硬质基底。
(2)在基底101上形成驱动结构层102图案。在一种示例性实施方式中，驱动结构层102的制备过程可以包括：
在基底101上依次沉积第一绝缘薄膜和有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成覆盖整个基底101的第一绝缘层，以及设置在第一绝缘层上的有源层图案，有源层图案包括第一有源层。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层图案的第二绝缘层，以及设置在第二绝缘层上的第一栅金属层图案，第一栅金属层图案包括第一栅电极、第一电容电极和多条栅线(未示出)。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅金属层的第三绝缘层，以及设置在第三绝缘层上的第二栅金属层图案，第二栅金属层图案包括第二电容电极，第二电容电极的位置与第一电容电极的位置相对应。
随后，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖第二栅金属层的第四绝缘层图案，第四绝缘层上开设有多个第一过孔，多个第一过孔的位置分别与第一有源层的两端位置相对应，多个第一过孔内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，分别暴露出第一有源层的表面。
随后，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第四绝缘层上形成源漏金属层图案图案，源漏金属层图案包括第一源电极、第一漏电极和多条数据线(未示出)图案，第一源电极和第一漏电极分别通过第一过孔与第一有源层12A连接。在一示例性实施方式中，根据实际需 要，源漏金属层还可以包括电源线(VDD)、补偿线和辅助阴极中的任意一种或多种，源漏金属层也称之为第一源漏金属层(SD1)。
至此，在基底101上制备完成驱动结构层102图案。驱动结构层102包括：设置在基底上的第一绝缘层，设置在第一绝缘层上的有源层，覆盖有源层的第二绝缘层，设置在第二绝缘层上的第一栅金属层，覆盖第一栅金属层的第三绝缘层，设置在第三绝缘层上的第二栅金属层，覆盖第二栅金属层的第四绝缘层，设置在第四绝缘层上的源漏金属层。有源层至少包括第一有源层，第一栅金属层至少包括第一栅电极和第一电容电极，第二栅金属层至少包括第二电容电极，源漏金属层至少包括第一源电极、第一漏电极，第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管，第一电容电极和第二电容电极组成第一存储电容。在一示例性实施方式中，第一晶体管可以是像素驱动电路中的驱动晶体管，驱动晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
(3)在形成前述图案的基底上，制备发光元件103图案。在示例性实施方式中，发光元件103的制备过程可以包括：
在形成前述图案的基底上涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成第一平坦(PLN)层图案。第一平坦层上形成有第 二过孔，第二过孔内的第一平坦层被刻蚀掉，暴露出第一漏电极的表面。
在形成前述图案的基底上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成阳极图案。阳极形成在第一平坦层上，通过第二过孔与第一漏电极连接。
在形成前述图案的基底上涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义(PDL)层图案。像素定义层开设有子像素开口，子像素开口内的像素定义薄膜被显影掉，暴露出阳极的表面。
在形成前述图案的基底上形成隔垫柱层图案，隔垫柱层包括多个支撑柱，支撑柱间隔地设置于像素定义层上。
在形成前述图案的基底上依次形成有机发光层和阴极，有机发光层至少形成在像素开口内，实现有机发光层与阳极连接。由于阳极与第一晶体管的第一漏电极连接，因而实现了有机发光层与第一晶体管的第一漏电极的连接。阴极形成在有机发光层上，阴极与有机发光层连接。在示例性实施方式中，有机发光层可以包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
至此，在驱动结构层102上制备完成发光元件103图案。发光元件可以包括阳极、像素定义(PDL)层、隔垫柱(PS)、有机发光层、阴极等。阳极设置在第一平坦层上，通过第一平坦层上开设的过孔与驱动晶体管的第一漏电极连接；像素定义层设置在阳极和平坦层上，像素定义层上设置有子像素开口，子像素开口暴露出阳极；有机发光层至少部分设置在子像素开口内，有机发光层与阳极连接；阴极设置在有机发光层上，阴极与有机发光层连接；有机发光层在阳极和阴极驱动下出射相应颜色的光线。
(4)在形成前述图案的基底上，形成封装层104图案。在示例性实施方式中，封装层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层采用无机材料，第二封装层采用有机材料。
(5)在形成前述图案的基底上，形成圆偏振片(Circular Polarizer， CPOL)层105图案。
在示例性实施方式中，圆偏振片层105可以包括设置在封装层上的粘合剂层、设置在粘合剂层上的阻挡层、设置在阻挡层上的相位差层以及设置在相位差层上的起偏镜层。
(6)在形成前述图案的基底上，形成透镜定义层106和透镜结构层107图案，如图3所示。其中，透镜结构层107包括多个间隔设置的透镜，透镜定义层106设置于相邻的透镜之间的间隙区域，每个透镜在基底101上的正投影包含至少一个子像素开口在基底101上的正投影。
在示例性实施方式中，如图6a和图6b所示，透镜定义层106和透镜结构层107的制备过程可以包括：
在圆偏振片层105上涂敷一层疏水材料，通过掩膜版(Photo Mask)曝光显影对疏水材料进行图案化，形成透镜定义层106图案。透镜定义层106包括多条沿第一方向D1延伸的第一定义线1061和多条沿第二方向D2延伸的第二定义线1062，多条第一定义线1061和多条第二定义线1062交叉限定出多个网格区域，每个网格区域与前述形成的一个或多个子像素对应，且每个网格区域与后续形成的透镜一一对应；
在透镜定义层106上涂敷压印材料，并使压印材料膜厚均匀分布；
通过掩膜版曝光显影对压印材料进行图案化，形成网格状压印材料。本步骤中，在透镜定义层106上有疏水材料疏水材料的区域压印材料被去除，没有疏水材料的区域压印材料被保留，从而形成网格状压印材料，每个压印材料网格形成在透镜定义层106限定的一个网格区域内；
使用压印模版对网格状压印材料进行压印工艺，形成多个网格状透镜。透镜定义层106使相邻透镜相互独立，当压印材料发生收缩时，对于每个独立的透镜，压印材料收缩约0.058um，而对于166um的大尺寸透镜结构，每个透镜压印材料的收缩量不影响整体透镜结构的显示效果。
在一种示例性实施例中，疏水材料包括以下任意一种或多种：特氟龙、聚酰胺、聚烯烃、硅氧烷类等。
通过本公开示例性实施例显示基板的结构及其制备过程可以看出，本公开示例性实施例通过使用疏水材料制备一层透镜定义层图案，使得压印出的多个透镜网格化，相邻透镜相互独立，当压印材料收缩时，由于透镜定义层的隔离，整个透镜结构不会出现大尺寸的收缩，而对于构成每个独立的透镜的压印材料的收缩则可忽略不计，从而实现了大尺寸纳米压印透镜与发光元件精准对位，提高了3D显示效果，示例性的，本公开实施例显示基板的3D显示效果如图7所示。
本公开示例性实施例显示基板的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，本公开在此不做限定。
如图8所示，本公开还提供了一种显示基板的制备方法，所述制备方法包括如下步骤：
步骤S1：在基底上依次形成驱动结构层、发光元件、封装层和圆偏振片层，发光元件包括设置有多个子像素开口的像素定义层；
步骤S2：在圆偏振片层上形成透镜定义层和透镜结构层，透镜结构层包括多个间隔设置的透镜，透镜定义层设置于相邻的透镜之间的间隙区域，每个透镜在基底上的正投影包含至少一个子像素开口在基底上的正投影。
在示例性实施方式中，在圆偏振片层上形成透镜定义层，包括：
在圆偏振片层上涂敷一层疏水材料；
通过第一次构图工艺，对疏水材料进行图案化，形成透镜定义层。
在示例性实施方式中，在圆偏振片层上形成透镜结构层，包括：
在形成透镜定义层的基底上涂敷一层膜厚均匀分布的压印材料；
通过第二次构图工艺，对压印材料进行图案化，形成网格状压印材料，网格状压印材料与透镜定义层不重叠；
通过压印模版对网格状压印材料进行压印，形成多个间隔设置的透镜。
在示例性实施方式中，疏水材料包括以下任意一种或多种：特氟龙、聚酰胺、聚烯烃、硅氧烷类等。
在示例性实施方式中，像素定义层还包括多个围绕子像素开口设置的挡墙，挡墙在基底上的正投影包含透镜定义层在基底上的正投影。
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。本公开显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。在示例性实施方式中，显示装置可以为穿戴式显示装置，能通过某些方式佩戴在人体上，如智能手表、智能手环等。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (14)

  1. 一种显示基板，包括基底、设置在所述基底上的驱动结构层、设置在所述驱动结构层上的发光元件、设置在所述发光元件上的封装层、设置在所述封装层上的圆偏振片层以及设置在所述圆偏振片层上的透镜定义层和透镜结构层，其中：
    所述发光元件包括设置有多个子像素开口的像素定义层；
    所述透镜结构层包括多个间隔设置的透镜，所述透镜定义层设置于相邻的所述透镜之间的间隙区域，每个所述透镜在所述基底上的正投影包含至少一个所述子像素开口在所述基底上的正投影。
  2. 根据权利要求1所述的显示基板，其中，所述透镜定义层包括多条沿第一方向延伸的第一定义线和多条沿第二方向延伸的第二定义线，多条所述第一定义线和多条所述第二定义线交叉限定出多个网格区域，多个所述透镜一一对应地设置在多个所述网格区域内。
  3. 根据权利要求1所述的显示基板，其中，所述像素定义层还包括多个围绕所述子像素开口设置的挡墙，所述挡墙在所述基底上的正投影包含所述透镜定义层在所述基底上的正投影。
  4. 根据权利要求1所述的显示基板，其中，所述透镜定义层的材料为疏水材料。
  5. 根据权利要求4所述的显示基板，其中，所述疏水材料包括以下任意一种或多种：特氟龙、聚酰胺、聚烯烃、硅氧烷类。
  6. 根据权利要求1至5任一所述的显示基板，其中，所述驱动结构层包括薄膜晶体管，所述发光元件还包括阳极、有机发光层和阴极，其中：
    所述阳极设置在所述驱动结构层上，并与所述薄膜晶体管的漏电极连接；所述像素定义层设置在阳极和所述驱动结构层上，所述子像素开口暴露出所述阳极；所述有机发光层至少部分设置在所述子像素开口内，所述有机发光层与所述阳极连接；所述阴极设置在所述有机发光层上，所述阴极与所 述有机发光层连接。
  7. 一种显示装置，包括权利要求1至权利要求6任一项所述的显示基板。
  8. 一种显示基板的制备方法，包括：
    在基底上依次形成驱动结构层、发光元件、封装层和圆偏振片层，所述发光元件包括设置有多个子像素开口的像素定义层；
    在所述圆偏振片层上形成透镜定义层和透镜结构层，所述透镜结构层包括多个间隔设置的透镜，所述透镜定义层设置于相邻的所述透镜之间的间隙区域，每个所述透镜在所述基底上的正投影包含至少一个所述子像素开口在所述基底上的正投影。
  9. 根据权利要求8所述的制备方法，其中，所述在所述圆偏振片层上形成透镜定义层，包括：
    在所述圆偏振片层上涂敷一层疏水材料；
    通过第一次构图工艺，对所述疏水材料进行图案化，形成所述透镜定义层。
  10. 根据权利要求9所述的制备方法，其中，所述在所述圆偏振片层上形成透镜结构层，包括：
    在形成所述透镜定义层的基底上涂敷一层膜厚均匀分布的压印材料；
    通过第二次构图工艺，对所述压印材料进行图案化，形成网格状压印材料，所述网格状压印材料与所述透镜定义层不重叠；
    通过压印模版对所述网格状压印材料进行压印，形成多个间隔设置的透镜。
  11. 根据权利要求9或10任一所述的制备方法，其中，所述疏水材料包括以下任意一种或多种：特氟龙、聚酰胺、聚烯烃、硅氧烷类。
  12. 根据权利要求9或10任一所述的制备方法，其中，所述像素定义层 还包括多个围绕所述子像素开口设置的挡墙，所述挡墙在所述基底上的正投影包含所述透镜定义层在所述基底上的正投影。
  13. 根据权利要求8所述的制备方法，其中，所述透镜定义层包括多条沿第一方向延伸的第一定义线和多条沿第二方向延伸的第二定义线，多条所述第一定义线和多条所述第二定义线交叉限定出多个网格区域，多个所述透镜一一对应地设置在多个所述网格区域内。
  14. 根据权利要求8所述的制备方法，其中，所述驱动结构层包括薄膜晶体管，所述发光元件还包括阳极、有机发光层和阴极，其中：所述阳极设置在所述驱动结构层上，并与所述薄膜晶体管的漏电极连接；所述像素定义层设置在阳极和所述驱动结构层上，所述子像素开口暴露出所述阳极；所述有机发光层至少部分设置在所述子像素开口内，所述有机发光层与所述阳极连接；所述阴极设置在所述有机发光层上，所述阴极与所述有机发光层连接。
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