WO2022116336A1 - 薄膜晶体管及其制备方法 - Google Patents

薄膜晶体管及其制备方法 Download PDF

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Publication number
WO2022116336A1
WO2022116336A1 PCT/CN2020/141117 CN2020141117W WO2022116336A1 WO 2022116336 A1 WO2022116336 A1 WO 2022116336A1 CN 2020141117 W CN2020141117 W CN 2020141117W WO 2022116336 A1 WO2022116336 A1 WO 2022116336A1
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Prior art keywords
electrode
layer
film transistor
thin film
barrier layer
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English (en)
French (fr)
Inventor
胡小波
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Priority to US17/261,015 priority Critical patent/US12068416B2/en
Publication of WO2022116336A1 publication Critical patent/WO2022116336A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Definitions

  • the present application relates to the field of display technology, and in particular, to a thin film transistor and a preparation method thereof.
  • the copper (Cu) process has become the mainstream. Due to the poor adhesion of Cu, metal deposition is generally carried out with a barrier layer. However, it is difficult for common barrier layer materials to form a tail, and the barrier layer/copper structure will have an undercut (undercut structure).
  • the thin film transistor and the preparation method thereof described in the present application can prevent the barrier layer/electrode layer structure from being undercut by adopting the composite electrode of the barrier layer and the electrode layer prepared by using a specific material, and can also make the barrier layer and the electrode layer structure. Layers get longer protrusions, which can improve light leakage and improve product contrast.
  • the present application provides a thin film transistor, the thin film transistor includes at least one of the composite electrodes, the composite electrode includes a barrier layer and an electrode layer, wherein: the barrier layer has a protruding portion relative to the electrode layer, and the protruding portion The orthographic projection on the electrode layer protrudes from the electrode layer, and the length of the protruding portion ranges from 0.3um to 0.5um; and the material of the barrier layer includes at least one metal and at least one metal oxide material, wherein the mass content of the metal oxide is 1%-10%, and the material of the electrode layer is copper.
  • the metal is at least one of Mo, Ti, or Nb.
  • the metal oxide is at least one of TiO 2 , TaO 2 , WO 2 or Nb 2 O 5 .
  • the material of the barrier layer includes Mo, Ti and TiO 2 .
  • the thin film transistor includes a gate electrode, a source electrode and a drain electrode; the composite electrode includes at least one of the gate electrode, the source electrode and the drain electrode.
  • the present application provides a thin film transistor, the thin film transistor includes at least one of the composite electrodes, the composite electrode includes a barrier layer and an electrode layer, wherein: the barrier layer has a protruding portion relative to the electrode layer, and the protruding portion The orthographic projection on the electrode layer protrudes from the electrode layer, and the length of the protruding portion ranges from 0.3um to 0.5um.
  • the material of the barrier layer includes at least one metal and at least one metal oxide, wherein the mass content of the metal oxide is 1%-10%.
  • the metal is at least one of Mo, Ti, or Nb.
  • the metal oxide is at least one of TiO 2 , TaO 2 , WO 2 or Nb 2 O 5 .
  • the material of the barrier layer includes Mo, Ti and TiO 2 .
  • the material of the electrode layer is copper.
  • the thin film transistor includes a gate electrode, a source electrode and a drain electrode; the composite electrode includes at least one of the gate electrode, the source electrode and the drain electrode.
  • the present application also provides a method for preparing a thin film transistor, including a step of preparing a composite electrode on a substrate, wherein the composite electrode includes a barrier layer and an electrode layer, and the barrier layer has a protrusion relative to the electrode layer, The orthographic projection of the protruding portion on the electrode layer protrudes from the electrode layer, and the length of the protruding portion ranges from 0.3um to 0.5um.
  • the composite electrode is prepared by the following method: the step of preparing a target material layer on the substrate;
  • the composite layer is etched with a cupric acid etching solution of a hydrogen peroxide system to form the composite electrode.
  • the material of the target material layer includes metals and metal oxides, wherein the mass content of the metal oxides ranges from 1% to 10%.
  • the metal is at least one of Mo, Ti or Nb.
  • the metal oxide is at least one of TiO 2 , TaO 2 , WO 2 or Nb 2 O 5 .
  • the material of the target material layer includes Mo, Ti and TiO 2 .
  • the material of the conductive layer is copper.
  • the method for preparing at least one electrode includes: a step of preparing a target layer on a substrate, wherein the material of the target layer includes metals and metal oxides, wherein the mass of the metal oxides is The content ranges from 1% to 10%, and the metal is at least one of Mo, Ti or Nb, and the metal oxide is at least one of TiO 2 , TaO 2 , WO 2 or Nb 2 O 5 ; a step of preparing a conductive layer on the target layer, wherein the conductive layer material is copper; and, patterning the target layer and the conductive layer to obtain the barrier layer and the electrode, respectively A step of.
  • the thin film transistor and its preparation method described in the present application by selecting a barrier layer prepared from a specific material, the barrier layer can have a longer protrusion, which overcomes the problem that it is difficult to form a protrusion in the existing barrier layer , can improve light leakage and improve product contrast; in addition, the thin film transistor and the preparation method thereof described in the present application can also overcome the problem of undercut existing in the existing barrier layer/electrode layer structure.
  • FIG. 1 is a schematic structural diagram of the thin film transistor described in the application.
  • FIGS. 2A-2C are flow charts of the manufacturing process of the gate electrode of the thin film transistor described in the present application, wherein the gate electrode is a composite electrode with a gate pattern.
  • FIG. 1 is a schematic structural diagram of the thin film transistor described in the present application.
  • the present application provides a thin film transistor (Thin Film Transistor, TFT) 100
  • the thin film transistor 100 includes at least one composite electrode
  • the composite electrode includes an electrode layer 22 and a barrier layer 21, wherein the The barrier layer 21 has a protrusion 211 opposite to the electrode layer 22
  • the orthographic projection of the protrusion 211 on the composite electrode protrudes from the orthographic projection of the electrode layer 22 on the composite electrode.
  • the length of the protruding portion 211 ranges from 0.3um to 0.5um.
  • the thin film transistor 100 described in the present application can solve the problem of poor adhesion of the electrode layer 22 by forming the composite electrode with the barrier layer 21 .
  • the protruding part 211 blocks the edge of the electrode layer 22, so as to solve the light leakage phenomenon caused by the electrode layer 22 changing the polarization direction of the polarized light in the backlight, and prevent the product Contrast is reduced.
  • the material of the barrier layer 21 includes at least one metal and at least one metal oxide, wherein the mass content of the metal oxide ranges from 1% to 10%.
  • the barrier layer 21 has conductivity. Those skilled in the art can understand that the barrier layer 21 is formed of any one or more materials of metal oxide and metal, and these types of materials have electrical conductivity and do not affect the normal operation of the electrode layer 22. Some types of materials have better contact adhesion, which can increase the adhesion between the electrode layer 22 and other film layers of the thin film transistor 100 .
  • the metal may be at least one of Mo (molybdenum, molybdenum), Ti (Titanium, titanium) or Nb (niobium, niobium).
  • the metal oxide can be TiO 2 (Titanium Dioxide, titanium dioxide), TaO 2 (tantalum dioxide, tantalum dioxide), WO 2 (Tungsten oxide, tungsten dioxide) or Nb 2 O 5 (Niobium oxide, niobium pentoxide) ) at least one of them.
  • the metal may be, but not limited to, Mo, MoTi or MoNb.
  • the material of the barrier layer 21 is a MoTi-TiO2 target. Since the etching rate of MoTi-TiO 2 is low, a longer tail 211 can be obtained, which is beneficial to reduce the light leakage in the dark state of the LCD product, thereby improving the contrast ratio of the LCD product. It can be seen that by adjusting the material of the barrier layer 21 to improve the etching rate ratio of the barrier layer/electrode layer, the protrusion 211 with a longer length can be more easily formed while preventing the undercut structure from being generated.
  • the protruding portion 211 is formed by all or part of the thickness region of the barrier layer 21 .
  • the present application does not limit the specific shape or structure of the protruding portion 211, as long as the orthographic projection of the protruding portion 211 on the composite electrode protrudes from that of the electrode layer 22 on the composite electrode orthographic projection on it.
  • the protruding portion 211 may be formed by extending the entire thickness of the barrier layer 21 along an oblique direction intersecting with the composite electrode, and the side edge of the protruding portion 211 is in the shape of a fold line.
  • the protruding portion 211 is formed by the entire thickness region of the barrier layer 21 extending along an oblique direction intersecting with the composite electrode.
  • the protruding portion 211 is formed by all or part of the thickness region of the barrier layer 21 .
  • the side edge of the protruding portion 211 has a bent structure.
  • the protruding portion 211 is formed by the entire thickness region of the barrier layer 21 extending along an oblique direction intersecting with the composite electrode.
  • the barrier layer 21 may also extend along an oblique direction intersecting with the adhesion layer 10 to have the protrusions 211, as long as the protrusions 211 on the composite electrode are formed to have protrusions 211. It is sufficient that the orthographic projection protrudes from the orthographic projection of the electrode layer 22 on the composite electrode.
  • the material of the electrode layer 22 is copper.
  • the stability of the metal oxide material in the barrier layer 21 is stronger than that of copper, so that the etching rate of the barrier layer 21 is lower than that of the electrode layer 22 .
  • etching rate of MoTi-TiO2 is lower than that of copper, a longer tail 211 can be obtained, which is beneficial to reduce the dark-state light leakage of LCD products, thereby improving the contrast ratio of LCD products.
  • the present application does not limit the specific material or structure of the electrode layer 22 .
  • the electrode layer 22 may be a single-layer structure, or may be a multi-layer stack structure.
  • the electrode layer 22 has a single-layer structure.
  • the thin film transistor 100 includes a substrate 110 , a gate electrode 120 , a gate insulating layer 130 , an active layer 140 , a source electrode 150 and a drain electrode 160 .
  • the composite electrode includes at least one of a gate electrode 120 , a source electrode 150 and a drain electrode 160 .
  • the composite electrode includes a gate electrode 120 , a source electrode 150 and a drain electrode 160 . That is, the composite electrode includes a composite electrode 20a having a gate pattern, a composite electrode 20b having a source pattern, and a composite electrode 20c having a drain pattern.
  • the specific structure of the thin film transistor 100 described in the present application will be described in detail below with reference to FIG. 1 .
  • the base substrate 110 is a polymer material with light transmission and flexibility properties.
  • the base substrate 110 may include polyimide, polysiloxane, epoxy, acrylic, polyester, and/or similar materials.
  • the base substrate 110 may include polyimide.
  • the gate 120 is disposed on the substrate 110 .
  • the gate 120 is a composite electrode 20a having a gate pattern. That is, the gate electrode 120 includes a barrier layer 21 and an electrode layer 22 sequentially stacked on the substrate 110 .
  • the gate insulating layer 130 is disposed on the gate 120 and covers the barrier layer 21 of the gate 120 , the electrode layer 22 of the gate 120 and the substrate 110 .
  • the gate insulating layer 130 may include silicon oxide, silicon nitride, silicon oxynitride and/or similar materials. These materials can be used alone or in combination.
  • the active layer 140 is disposed on the gate insulating layer 130 .
  • the active layer 140 includes a channel region and source and drain regions around the channel region.
  • the channel region can be used as a channel through which charges can be moved or transported, and the source region and the drain region are used to electrically connect or contact the source electrode 150 and the drain electrode 160, respectively.
  • the active layer 140 may include a silicon compound such as polysilicon.
  • source and drain regions including p-type or n-type impurities may be formed at both ends of the active layer 140 .
  • the active layer 140 may further include an oxide semiconductor, such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin zinc oxide (ITZO) and/or similar materials.
  • IGZO indium gallium zinc oxide
  • ZTO zinc tin oxide
  • ITZO indium tin zinc oxide
  • the source electrode 150 and the drain electrode 160 are disposed on the active layer 140 .
  • the source electrode 150 is a composite electrode 20b having a source electrode pattern
  • the drain electrode 160 is a composite electrode 20c having a drain electrode pattern. That is, the source electrode 150 and the drain electrode 160 respectively include the barrier layer 21 and the electrode layer 22 .
  • the barrier layer 21 and the electrode layer 22 of the source electrode 150 are sequentially stacked on the source region of the active layer 140 .
  • the barrier layer 21 and the electrode layer 22 of the drain electrode 160 are sequentially stacked on the drain region of the active layer 140 .
  • the thin film transistor 100 further includes a planarization layer 170 , and the planarization layer 170 is disposed on the source electrode 150 and the drain electrode 160 and covers the active layer 140 , the The barrier layer 21 and the electrode layer 22 of the source electrode 150 , the barrier layer 21 and the electrode layer 22 of the drain electrode 160 , and the gate insulating layer 130 .
  • a first via hole 171 is provided in a region of the planarization layer 170 corresponding to the drain electrode 160 .
  • the first via hole 171 exposes the electrode layer 22 of the drain electrode 160 for electrical connection or contact between the drain electrode 160 and the subsequent pixel electrode layer 180 .
  • the planarization layer 170 may be formed of a polymer material or an inorganic material.
  • the thin film transistor 100 further includes a pixel electrode 180 .
  • the pixel electrode 180 is disposed on the planarization layer 170 and is electrically connected to the drain electrode 160 through the first via hole 171 . .
  • the material of the pixel electrode 180 is metal, alloy or metal nitride.
  • the pixel electrode 180 may include, for example, aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum ( Pt), tantalum (Ta) and neodymium (Nd) metals, their alloys and/or their nitrides. These can be used alone or in combination.
  • the pixel electrode 180 includes at least two metal layers having different physical and/or chemical properties.
  • the present application does not limit the type or structure of the thin film transistor 100.
  • the bottom gate structure thin film transistor shown in FIG. 1 is only an exemplary structural diagram of the thin film transistor of the present invention.
  • the thin film transistor 100 may also adopt other structures or types of thin film transistors.
  • the thin film transistor 100 may also be a top-gate IGZO (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide) TFT, a top-gate IGZTO (Indium Gallium Zinc Oxide) TFT Zinc Ti Oxide, indium gallium zinc titanium oxide) TFT, or BCE (Back Channel Etched, back channel etched) type IGZO TFT.
  • the present application does not limit the relationship between the barrier layers 21 and the electrode layers 22 of the plurality of composite electrodes in the thin film transistor 100 . That is to say, in specific implementation, the materials of the barrier layers 21 and the materials of the electrode layers 22 of different composite electrodes in the same thin film transistor 100 can be set separately, or can be set together for multiple composite electrodes. For example, in the same thin film transistor, the barrier layers 21 of the gate electrode 120 , the source electrode 150 and the drain electrode 160 can use different materials respectively.
  • the present application provides a method for preparing a thin film transistor, and the method includes the following steps: a step of preparing a composite electrode on a substrate, wherein the composite electrode includes a barrier layer and an electrode layer, and the barrier layer is opposite to the other.
  • the electrode layer has a protruding part, the orthographic projection of the protruding part on the electrode layer protrudes from the electrode layer, and the length of the protruding part ranges from 0.3um to 0.5um.
  • the preparation method of the thin film transistor described in the present application can obtain a barrier layer 21 with long protrusions 211, which can improve light leakage and improve product contrast; in addition, the preparation method described in the present application can also overcome the existing barrier layer/electrode layer There is an undercut problem in the structure.
  • the preparation method of the composite electrode comprises the following steps:
  • the step of preparing a target material layer on a substrate wherein the material of the target material layer includes at least one metal and at least one metal oxide, wherein the mass content of the metal oxide is in the range of 1%-10% , and the metal is at least one of Mo, Ti or Nb, and the metal oxide is at least one of TiO 2 , TaO 2 , WO 2 or Nb 2 O 5 ;
  • the preparation method of the thin film transistor described in the present application can make the barrier layer 21 have longer protrusions 211 by using a specific material to prepare the barrier layer 21, which overcomes the difficulty of forming protrusions in the existing barrier layer/electrode layer structure.
  • the problem of the part 211 can be improved, the light leakage can be improved, and the contrast of the product can be improved; in addition, the problem of undercut existing in the existing composite electrode can be overcome.
  • the preparation method of the thin film transistor includes the following steps:
  • Steps of preparing source and drain electrodes on the active layer are identical to Steps of preparing source and drain electrodes on the active layer.
  • the gate electrode 120 , the source electrode 150 and the drain electrode 160 in the thin film transistor 100 are independently the composite electrode described in the present application, and the gate electrode 120 is a composite electrode with a gate pattern.
  • the gate electrode 120 is a composite electrode with a gate pattern.
  • the source electrode 150 has a composite electrode 20b with a source electrode pattern
  • the drain electrode 160 has a composite electrode 20c with a drain pattern.
  • the gate electrode 120, the source electrode 150 and the drain electrode 160 can be obtained through the steps of preparing the composite electrode, respectively.
  • FIGS. 2A-2C are flowcharts of the manufacturing process of the gate electrode of the thin film transistor described in the present application, wherein the gate electrode is a with a gate pattern.
  • the method and process for preparing the composite electrode and the thin film transistor in this embodiment will be described in detail below with reference to FIGS. 2A-2C .
  • the preparation method of the gate electrode includes the following steps:
  • a target layer 210 for preparing the barrier layer 21 is prepared on the substrate 110 .
  • the material of the target material layer 210 includes at least one metal and at least one metal oxide, and the mass fraction of the metal oxide is 1%-10%.
  • the metal is at least one of Mo, Ti or Nb.
  • the metal oxide is at least one of TiO 2 , TaO 2 , WO 2 or Nb 2 O 5 .
  • the target material layer 210 for preparing the target material layer 210 is a MoTi-TiO 2 target material.
  • the MoTi-TiO 2 target can be obtained by the following methods: mixing Mo metal powder, Ti metal powder and TiO 2 powder in a certain proportion; then preparing through the processes of target sintering and bonding into a MoTi-TiO 2 target.
  • the ratio of Mo and Ti is not limited in the examples of the present application. During specific implementation, it can be adjusted according to the requirements of the barrier layer 21 . Among them, the processes such as target sintering and bonding can be realized by conventional processes, which will be repeated here.
  • the target material layer 210 is formed by sputtering.
  • a conductive layer 220 for preparing the electrode layer 22 is prepared on the target material layer 210, and a composite film layer 200 of the target material layer/conductive layer can be obtained .
  • the material of the conductive layer 220 may be copper.
  • a (MoTi-TiO 2 )/Cu composite film layer 200 can be obtained.
  • the composite film layer 200 obtained in the step S2 is etched to obtain a composite electrode 20a having a gate pattern, that is, the gate 120 is obtained.
  • the target material layer 210 forms the barrier layer 21
  • the conductive layer 220 forms the electrode layer 22 .
  • a photoresist layer 230 with a gate pattern is prepared on the conductive layer 220 through a yellow light process;
  • the film layer 200 is etched.
  • the metal oxide material in the target material layer 210 is relatively stable, the etching rate of the target material layer 210 is lower than that of the conductive layer 220 in a cupric acid environment. Therefore, in the process of etching the composite film layer 200 of the target material layer/conductive layer, a longer tail can be obtained.
  • the barrier layer 21 obtained by etching the MoTi-TiO 2 layer has a longer tail 211, which is beneficial to reduce LCD products Dark-state light leakage, thereby improving the contrast ratio of LCD products.
  • both the composite electrode 20b with a source pattern and the composite electrode 20c with a drain pattern can be realized by the above-mentioned method for preparing the composite electrode 20a with a gate pattern, which will not be repeated here.
  • the barrier layer 21 can have a longer protrusion 211, which can improve light leakage and improve product contrast.
  • the target material layer 210 of the specific material can also overcome the problem of undercut existing in the existing barrier layer/electrode layer structure.

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Abstract

一种薄膜晶体管及其制备方法，薄膜晶体管包括复合电极（20a/20b/20c），复合电极（20a/20b/20c）包括阻障层（21）和电极层（22），阻障层（21）相对于电极层（22）具有突出部（211），突出部（211）在复合电极（20a/20b/20c）上的正投影突出于电极层（22）在复合电极（20a/20b/20c）上正投影，突出部（211）的长度的范围为0.3μm~0.5μm。该薄膜晶体管及其制备方法可以改善漏光，提高产品对比度。

Description

薄膜晶体管及其制备方法
本申请要求于2020年12月03日提交中国国家知识产权局、申请号为202011404577.0、发明名称为“薄膜晶体管及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法。
 背景技术
随着显示技术的发展，人们对LCD显示器的画质要求越来越高，因此亟需提高LCD显示器的对比度。
然而，在LCD显示器中，当背光入射的偏振光的偏振方向不平行或不垂直金属边缘时，偏振光的电场会激发出金属边缘表面的电子，进而改变偏振光的偏振方向，最终导致部分偏振光由上偏光片中射出，造成漏光现象，从而导致暗态漏光，产品对比度降低。
此外，在现有TFT面板中，铜（Cu）制程成为主流。由于Cu附着力差，一般搭载阻障（barrier）层金属沉积。而常见的阻障层材料很难形成突出部（tail），且阻障层/铜结构会存在undercut（底切结构）。
因此，亟需提供一种薄膜晶体管及其制备方法，以解决上述技术问题。
 技术问题
为了解决上述技术问题，本申请所述薄膜晶体管及其制备方法，通过采用特定材料制备的阻障层和电极层的复合电极，能防止阻障层/电极层结构存在undercut，还能使阻障层获得长度较长的突出部，可以改善漏光，提高产品对比度。
 技术解决方案
本申请提供一种薄膜晶体管，薄膜晶体管包括至少一所述复合电极，所述复合电极包括阻障层和电极层，其中：所述阻障层相对所述电极层具有突出部，所述突出部在所述电极层上的正投影突出于所述电极层，所述突出部的长度范围为0.3um-0.5um；并且，所述阻障层的材料包括至少一种金属和至少一种金属氧化物，其中所述金属氧化物的质量含量为1%-10%，所述电极层的材料为铜。
进一步，所述金属为Mo、Ti、或Nb中的至少一种。
进一步，所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种。
进一步，所述阻障层的材料包括Mo、Ti和TiO 2。
进一步，所述薄膜晶体管包括栅极、源极和漏极；所述复合电极包括所述栅极、所述源极和所述漏极中的至少一种。
本申请提供一种薄膜晶体管，薄膜晶体管包括至少一所述复合电极，所述复合电极包括阻障层和电极层，其中：所述阻障层相对所述电极层具有突出部，所述突出部在所述电极层上的正投影突出于所述电极层，所述突出部的长度范围为0.3um-0.5um。
进一步，所述阻障层的材料包括至少一种金属和至少一种金属氧化物，其中所述金属氧化物的质量含量为1%-10%。
进一步，所述金属为Mo、Ti、或Nb中的至少一种。
进一步，所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种。
进一步，所述阻障层的材料包括Mo、Ti和TiO 2。
进一步，所述电极层的材料为铜。
进一步，所述薄膜晶体管包括栅极、源极和漏极；所述复合电极包括所述栅极、所述源极和所述漏极中的至少一种。
本申请还提供一种薄膜晶体管的制备方法，在一衬底上制备复合电极的步骤，其中所述复合电极包括阻障层和电极层，所述阻障层相对所述电极层具有突出部，所述突出部在所述电极层上的正投影突出于所述电极层，所述突出部的长度范围为0.3um-0.5um。
进一步，以以下方法制备所述复合电极：在所述衬底上制备靶材层的步骤；
在所述靶材层上制备导电层的步骤；以及，对所述靶材层和所述导电层进行图案化处理以分别获得所述阻障层和所述电极的步骤。
进一步，采用过氧化氢体系的铜酸刻蚀液对所述复合层进行蚀刻处理，形成所述复合电极。
进一步，所述靶材层的材料包括金属和金属氧化物，其中所述金属氧化物的质量含量的范围为1%-10%。
进一步，所述金属为Mo、Ti或Nb中的至少一种。
进一步，所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种。
进一步，所述靶材层的材料包括Mo、Ti和TiO 2。
进一步，所述导电层的材料为铜。
在一优选实施例中，至少一电极的制备方法包括：在一衬底上制备靶材层的步骤，其中所述靶材层的材料包括金属和金属氧化物，其中所述金属氧化物的质量含量的范围为1%-10%，并且所述金属为Mo、Ti或Nb中的至少一种，所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种；在所述靶材层上制备导电层的步骤，其中导电层材料为铜；以及，对所述靶材层和所述导电层进行图案化处理以分别获得所述阻障层和所述电极的步骤。
有益效果
本申请所述薄膜晶体管及其制备方法，通过选用特定材料制备的阻障层，能使所述阻障层具有较长的突出部，克服了现有阻障层中很难形成突出部的问题，能改善漏光，提高产品对比度；此外，本申请所述薄膜晶体管及其制备方法还能克服现有阻障层/电极层结构中存在undercut的问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请所述薄膜晶体管的结构示意图；
图2A-图2C为本申请所述薄膜晶体管的栅极的制备工艺流程图，其中所述栅极为具有栅极图案的复合电极。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1为本申请所述薄膜晶体管的结构示意图。如图1所示，本申请提供一种薄膜晶体管（Thin Film Transistor,TFT）100，所述薄膜晶体管100包括至少一复合电极，所述复合电极包括电极层22和阻障层21，其中所述阻障层21相对所述电极层22具有突出部211，所述突出部211在所述复合电极上的正投影突出于所述电极层22在所述复合电极上的正投影。所述突出部211的长度的范围为0.3um-0.5um。
至此，本申请所述薄膜晶体管100通过形成具有阻障层21的复合电极，能解决电极层22的附着力差的问题。同时，通过形成长度较长的所述突出部211，使突出部211遮挡所述电极层22的边缘，以解决由于所述电极层22改变背光中偏振光的偏振方向导致的漏光现象，防止产品对比度降低。
更进一步地，所述阻障层21的材料包括至少一种金属和至少一种金属氧化物，其中所述金属氧化物的质量含量的范围为1%-10%。
需要指出的是，所述阻障层21具有导电性。所述领域的技术人员可以理解，所述阻障层21采用金属氧化物和金属任意一种或多种材料形成，该些类型的材料具有导电性能，不影响电极层22的正常工作，另外该些类型的材料接触附着力较好，能够增加电极层22与薄膜晶体管100的其他膜层之间的附着力。
具体地，所述金属可以为Mo（molybdenum，钼）、Ti（Titanium，钛）或Nb（niobium，铌）中的至少一种。所述金属氧化物可以为TiO 2（Titanium Dioxide，二氧化钛）、TaO 2（tantalum dioxide，二氧化钽）、WO 2（Tungsten oxide，二氧化钨）或Nb 2O 5（Niobium oxide，五氧化二铌）中的至少一种。
在具体实施时，所述金属，可以为但不限于，Mo、MoTi或MoNb。例如，在本实施例中，所述阻障层21的材料选用MoTi-TiO2靶材。由于MoTi-TiO 2的蚀刻率较低，可以得到更长的突出部（tail）211，有利于减少LCD产品暗态漏光，从而提高LCD产品的对比度。可见，通过调整阻障层21的材料，提高阻障层/电极层的蚀刻率比，在防止产生底切结构的同时能更容易地形成具有较长长度的突出部211。
具体地，所述突出部211由所述阻障层21的全部或部分厚度区域形成。
同时，需要指出的是，本申请并未限定所述突出部211的具体形状或结构，只要使得所述突出部211在所述复合电极上的正投影突出于与电极层22在所述复合电极上的正投影即可。例如，所述突出部211可以由阻障层21整个厚度区域沿与复合电极相交的倾斜方向延伸构成，所述突出部211的侧边呈折线状。
在其它实施例中，所述突出部211由所述阻障层21的全部厚度区域沿与复合电极相交的倾斜方向延伸构成。
具体地，所述突出部211由所述阻障层21的全部或部分厚度区域形成。
例如，在本实施例中，所述突出部211侧边具有弯折结构。在其它实施例中，所述突出部211由所述阻障层21的全部厚度区域沿与复合电极相交的倾斜方向延伸构成。
需要指出的是，本申请公开实施例不局限于此，例如阻障层21也可以沿与附着层10相交的倾斜方向延伸以具有突出部211，只要使得突出部211在所述复合电极上的正投影突出于与电极层22在所述复合电极上的正投影即可。
具体地，所述电极层22的材料为铜。在蚀刻过程中，所述阻障层21中的金属氧化物材料稳定性比铜的稳定性强，使阻障层21的蚀刻率比电极层22的蚀刻率低。
例如，由于MoTi-TiO2的蚀刻率比铜低较低，可以得到更长的突出部（tail）211，有利于减少LCD产品暗态漏光，从而提高LCD产品的对比度。
需要指出的是，本申请并未限定所述电极层22的具体材料或结构。在具体实施时，所述电极层22可以为单层结构，还可以为多层层叠结构。例如，在本实施例中，所述电极层22为单层结构。
具体地，所述薄膜晶体管100包括衬底110、栅极120、栅极绝缘层130、有源层140、源极150和漏极160。所述复合电极包括栅极120、源极150和漏极160中的至少一种。
例如，如图1所示，在本实施例中，所述复合电极包括栅极120、源极150和漏极160。也就是说，所述复合电极包括具有栅极图案的复合电极20a、具有源极图案的复合电极20b和具有漏极图案的复合电极20c。以下将结合图1详细阐述本申请所述薄膜晶体管100的具体结构。
其中，所述衬底基板110采用具有透光和柔性性能的聚合物类材料。例如，所述衬底基板110可以包括聚酰亚胺、聚硅氧烷、环氧类树脂、丙烯酸类树脂、聚酯和/或类似材料。在一个实施例中，所述衬底基板110可以包括聚酰亚胺。
如图1所示，所述栅极120设置于所述衬底110上。所述栅极120为具有栅极图案的复合电极20a。也就是说，所述栅极120包括依次层叠于所述衬底110上的阻障层21和电极层22。
如图1所示，所述栅极绝缘层130设置于所述栅极120上并覆盖所述栅极120的阻障层21、所述栅极120的电极层22和所述衬底110。
在具体实施时，所述栅极绝缘层130可以包括氧化硅、氮化硅、氮氧化硅和/或类似材料。这些材料可以单独使用或以其组合使用。
如图1所示，所述有源层140设置于所述栅极绝缘层130上。所述有源层140包括沟道区和位于所述沟道区外围的源区和漏区。其中，沟道区可以用作电荷可以经其移动或传输的沟道，源区和漏区分别用于源极150和漏极160电性连接或接触。
在具体实施时，所述有源层140可以包括诸如多晶硅的硅化合物。在一些实施例中，包括p型或n型杂质的源区和漏区可以形成在所述有源层140的两端。在一些实施例中，所述有源层140还可以包括氧化物半导体，诸如氧化铟镓锌 (IGZO)、氧化锌锡(ZTO)、氧化铟锡锌(ITZO)和/或类似材料。
如图1所示，所述源极150和所述漏极160设置于所述有源层140上。所述源极150为具有源极图案的复合电极20b，所述漏极160为具有漏极图案的复合电极20c。也就是说，所述源极150和所述漏极160分别包括阻障层21和电极层22。具体地，所述源极150的阻障层21和电极层22依次层叠于所述有源层140的源区。所述漏极160的阻障层21和电极层22依次层叠于所述有源层140的漏区。
如图1所示，所述薄膜晶体管100还包括一平坦化层170，所述平坦化层170设置于所述源极150和所述漏极160上，并覆盖所述有源层140、所述源极150的阻障层21和电极层22、所述漏极160的阻障层21和电极层22以及所述栅极绝缘层130。
在所述平坦化层170的与所述漏极160相对应的区域设置有第一过孔171。所述第一过孔171暴露出所述漏极160的电极层22，以用于所述漏极160与后续的像素电极层180的电性连接或接触。
在具体实施时，所述平坦化层170可以由聚合物材料或无机材料来形成。
如图1所示，所述薄膜晶体管100还包括像素电极180，所述像素电极180设置于所述平坦化层170上，并通过所述第一过孔171电性连接于所述漏极160。
在具体实施时，所述像素电极180的材料为金属、合金或金属氮化物。例如，像素电极180可包括诸如铝(Al)、银(Ag)、钨(W)、铜(Cu)、镍(Ni)、铬(Cr)、钼(Mo)、钛(Ti)、铂(Pt)、钽(Ta)和钕(Nd)的金属、其合金和/或其氮化物。这些可以单独使用或以其组合使用。所述像素电极180包括具有不同的物理和/或化学性质的至少两个金属层。
需要指出的是，本申请并未限定所述薄膜晶体管100的类型或结构，图1所示的底栅结构薄膜晶体管仅仅为本发明所述薄膜晶体管的示例性结构图，在具体实施时，所述薄膜晶体管100还可以采用其它结构或类型的薄膜晶体管。例如，所述薄膜晶体管100还可以为顶栅型IGZO（Indium Gallium Zinc 0xide，铟镓锌氧化物） TFT、顶栅型IGZTO（Indium Gallium Zinc Ti Oxide，铟镓锌钛氧化物） TFT、或者BCE(Back Channel Etched，背沟道刻蚀型)型IGZO TFT。
此外，本申请也并未对所述薄膜晶体管100中多个复合电极的阻障层21和电极层22之间的关系进行限定。也就是说，在具体实施时，同一薄膜晶体管100内不同复合电极的阻障层21的材料和电极层22的材料能分别单独设置，也可以针对多个复合电极共同的设置。例如，在同一薄膜晶体管中，栅极120、源极150和漏极160的阻障层21能分别采用不同的材料。
本申请提供一种薄膜晶体管的制备方法，所述制备方法包括以下步骤：在一衬底上制备复合电极的步骤，其中所述复合电极包括阻障层和电极层，所述阻障层相对所述电极层具有突出部，所述突出部在所述电极层上的正投影突出于所述电极层，所述突出部的长度范围为0.3um-0.5um。
本申请所述薄膜晶体管的制备方法能获得具有较长突出部211的阻障层21，能改善漏光，提高产品对比度；此外，本申请所述制备方法还能克服现有阻障层/电极层结构中存在undercut的问题。
其中，所述复合电极的制备方法包括以下步骤：
在一衬底上制备靶材层的步骤，其中所述靶材层的材料包括至少一种金属和至少一种金属氧化物，其中所述金属氧化物的质量含量的范围为1%-10%，并且所述金属为Mo、Ti或Nb中的至少一种，所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种；
在所述靶材层上制备导电层的步骤，其中导电层的材料为铜；以及，
对所述靶材层和所述导电层进行图案化处理以分别获得所述阻障层和所述电极的步骤。
本申请所述薄膜晶体管的制备方法通过采用特定材料制备阻障层21能使所述阻障层21具有较长的突出部211，克服了现有阻障层/电极层结构中很难形成突出部211的问题，能改善漏光，提高产品对比度；此外，还能克服现有复合电极中存在undercut的问题。
具体地，所述薄膜晶体管的制备方法包括以下步骤：
在一衬底上制备栅极的步骤；
在所述栅极上制备栅极绝缘层的步骤；
在所述栅极绝缘层上制备有源层的步骤；以及，
在所述有源层上制备源极和漏极的步骤。
在一优选实施例中，所述薄膜晶体管100中的栅极120、源极150和漏极160分别独立地为本申请所述复合电极，则所述栅极120为具有栅极图案的复合电极20a，所述源极150具有源极图案的复合电极20b，所述漏极160具有漏极图案的复合电极20c。此时，所述栅极120、源极150和漏极160能分别通过制备所述复合电极的步骤获得。
图2A-图2C为本申请所述薄膜晶体管的栅极的制备工艺流程图，其中所述栅极为具有栅极图案的a。在以下将结合图2A-图2C，详细阐述所述复合电极和本实施例中所述薄膜晶体管的制备方法和工艺。
如图2A-图2C所示，所述栅极的制备方法包括以下步骤：
S1、在衬底上制备靶材层的步骤；
S2、在所述靶材层上制备导电层的步骤；以及，
S3、对所述靶材层和所述导电层进行图案化处理以分别获得所述阻障层和所述电极的步骤。
在所述步骤S1中，如图2A所示，在所述衬底110上制备一层用于制备阻障层21的靶材层210。其中，所述靶材层210的材料包括至少一种金属和至少一种金属氧化物，并且所述金属氧化物的质量分数为1%-10%。
具体地，所述金属为Mo、Ti或Nb中的至少一种。所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种。
例如，在本实施例中，用于制备所述靶材层210为MoTi-TiO 2靶材。在具体实施时，可以以下方法获得所述MoTi-TiO 2靶材：将Mo金属粉末、Ti金属粉末以及TiO 2粉末按照一定比例进行混合；接着经靶材烧结和绑定（bonding）等工序制备成MoTi-TiO 2靶材。
此处，需要指出的是，本申请实施例对Mo和Ti的比例不做限定。在具体实施时，能依据对阻障层21的需求进行调整。其中，靶材烧结和绑定（bonding）等工序均能通过常规的工艺实现，此处再赘述。
在具体实施时，采用溅射的方式形成所述靶材层210。
在所述步骤S2中，如图2B所示，在所述靶材层210上制备一层用于制备所述电极层22的导电层220，能获得靶材层/导电层的复合膜层200。
具体地，所述导电层220的材料可以为铜。在本实施例中，经所述步骤S2后，能获得（MoTi-TiO 2）/Cu的复合膜层200。
在所述步骤S3中，如图2C所示，对步骤S2获得所述复合膜层200进行蚀刻处理，以获得具有栅极图案的复合电极20a，即获得栅极120。具体地，在上述复合膜层200中，所述靶材层210形成所述阻障层21，所述导电层220形成所述电极层22。
如图2C所示，在具体实施时，先经黄光制程在所述导电层220上制备具有栅极图案的光阻层230；然后利用过氧化氢体系的铜酸刻蚀液对所述复合膜层200进行蚀刻处理。
在上述蚀刻过程中，由于靶材层210中的金属氧化物材料稳定性比较强，在铜酸环境中靶材层210的蚀刻率比导电层220的蚀刻率低。因此，在对所述靶材层/导电层的复合膜层200进行蚀刻的过程中，可以得到更长的tail。
例如，在本实施例中，由于MoTi-TiO 2的蚀刻率比铜低，经MoTi-TiO 2层蚀刻得到的阻障层21具有长度较长的突出部（tail）211，有利于减少LCD产品暗态漏光，从而提高LCD产品的对比度。
其中，所述具有源极图案的复合电极20b和所述具有漏极图案的复合电极20c均能通过上述制备所述具有栅极图案的复合电极20a的方法实现，此处不再赘述。
本申请所述薄膜晶体管的制备方法通过采用特定材料的靶材层210以及特定材料的导电层220，能使所述阻障层21获得有较长的突出部211，能改善漏光，提高产品对比度；此外，所述特定材料的靶材层210还能克服现有阻障层/电极层结构中存在undercut的问题。
以上对本申请实施例所提供的一种薄膜晶体管及其制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括至少一复合电极，所述复合电极包括阻障层和电极层，其中：
    所述阻障层相对所述电极层具有突出部，所述突出部在所述电极层上的正投影突出于所述电极层，所述突出部的长度范围为0.3um-0.5um；
    并且，所述阻障层的材料包括至少一种金属和至少一种金属氧化物，所述金属氧化物的质量含量为1%-10%，所述电极层的材料为铜。
  2. 如权利要求1所述的薄膜晶体管，其中，所述金属为Mo、Ti、或Nb中的至少一种。
  3. 如权利要求1所述的薄膜晶体管，其中，所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种。
  4. 如权利要求1所述的薄膜晶体管，其中，所述阻障层的材料包括Mo、Ti和TiO 2。
  5. 如权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管具有栅极、源极和漏极；
    所述复合电极包括所述栅极、所述源极和所述漏极中的至少一种。
  6. 一种薄膜晶体管，其中，所述薄膜晶体管包括至少一复合电极，所述复合电极包括阻障层和电极层，其中：
    所述阻障层相对所述电极层具有突出部，所述突出部在所述电极层上的正投影突出于所述电极层，所述突出部的长度范围为0.3um-0.5um。
  7. 如权利要求6所述的薄膜晶体管，其中，所述阻障层的材料包括至少一种金属和至少一种金属氧化物，其中所述金属氧化物的质量含量为1%-10%。
  8. 如权利要求7所述的薄膜晶体管，其中，所述金属为Mo、Ti、或Nb中的至少一种。
  9. 如权利要求7所述的薄膜晶体管，其中，所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种。
  10. 如权利要求8所述的薄膜晶体管，其中，所述阻障层的材料包括Mo、Ti和TiO 2。
  11. 如权利要求6所述的薄膜晶体管，其中，所述电极层的材料为铜。
  12. 如权利要求6所述的薄膜晶体管，其中，所述薄膜晶体管具有栅极、源极和漏极；
    所述复合电极包括所述栅极、所述源极和所述漏极中的至少一种。
  13. 一种薄膜晶体管的制备方法，其中，所述制备方法包括：
    在一衬底上制备复合电极的步骤，其中所述复合电极包括阻障层和电极层，所述阻障层相对所述电极层具有突出部，所述突出部在所述电极层上的正投影突出于所述电极层，所述突出部的长度的范围为0.3um-0.5um。
  14. 如权利要求13所述的薄膜晶体管的制备方法，其中，以以下方法制备所述复合电极：
    在所述衬底上制备靶材层的步骤；
    在所述靶材层上制备导电层的步骤；以及，
    对所述靶材层和所述导电层进行图案化处理以分别获得所述阻障层和所述电极层的步骤。
  15. 如权利要求14所述的薄膜晶体管的制备方法，其中，在对所述靶材层和所述导电层进行图案化处理的步骤中，采用过氧化氢体系的铜酸刻蚀液对所述靶材层和所述导电层进行蚀刻处理。
  16. 如权利要求13所述的薄膜晶体管的制备方法，其中，所述靶材层的材料包括至少一种金属和至少一种金属氧化物，其中所述金属氧化物的质量含量的范围为1%-10%。
  17. 如权利要求16所述的薄膜晶体管的制备方法，其中，所述金属为Mo、Ti、或Nb中的至少一种。
  18. 如权利要求16所述的薄膜晶体管的制备方法，其中，所述金属氧化物为TiO 2、TaO 2、WO 2或Nb 2O 5中的至少一种。
  19. 如权利要求16所述的薄膜晶体管，其中，所述靶材层的材料包括Mo、Ti和TiO 2。
  20. 如权利要求14所述的薄膜晶体管的制备方法，其中，所述导电层的材料为铜。
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