WO2022047973A1 - Oled 显示面板及其制作方法 - Google Patents

Oled 显示面板及其制作方法 Download PDF

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Publication number
WO2022047973A1
WO2022047973A1 PCT/CN2020/125163 CN2020125163W WO2022047973A1 WO 2022047973 A1 WO2022047973 A1 WO 2022047973A1 CN 2020125163 W CN2020125163 W CN 2020125163W WO 2022047973 A1 WO2022047973 A1 WO 2022047973A1
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Prior art keywords
layer
metal
display panel
oled display
film transistor
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PCT/CN2020/125163
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English (en)
French (fr)
Inventor
唐甲
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/056,455 priority Critical patent/US20220310740A1/en
Publication of WO2022047973A1 publication Critical patent/WO2022047973A1/zh

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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05573—Single external layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0568—Molybdenum [Mo] as principal constituent
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present invention relates to the field of display technology, in particular to an OLED display panel and a manufacturing method thereof.
  • OLED displays have attracted much attention as display devices for displaying images. OLED displays have self-luminous characteristics and do not use a separate light source, so they are more efficient than display devices using a separate light source. Thin and light.
  • OLED displays use Cu traces as gate, source and drain transistor devices in order to reduce trace resistance. Due to poor stability of Cu, it is easy to oxidize when exposed to the external environment, so it cannot be directly used for bonding Fixed metal, at present, an anode ITO layer is often used to cover Cu to improve the stability of the bound metal, but for top-emitting OLED displays, when the reflective metal layer (Ag or Al) is etched, the binding metal Cu is easily corroded by the etching solution, so that the stability of the bound metal obtained by covering the Cu with the ITO layer is also poor, and is easily corroded by the etching solution, thereby affecting the product yield.
  • the reflective metal layer Al
  • Embodiments of the present invention provide an OLED display panel and a manufacturing method thereof, which can solve the technical problem in the prior art that the bonding metal is easily corroded by etching solution during the manufacturing process and is unstable in the environment, thereby affecting product yield.
  • an embodiment of the present invention provides an OLED display panel, the OLED display panel includes a display area and a binding area at least on one side of the display area;
  • the OLED display panel further includes:
  • the first metal layer includes a light-shielding metal corresponding to the display area and a binding metal corresponding to the binding area;
  • the thin film transistor device layer is disposed on the first metal layer, and the thin film transistor device layer includes a thin film transistor corresponding to the top of the light-shielding metal and a spacer layer, and the spacer layer is formed with an opening in the binding area , to expose part of the upper surface of the bound metal;
  • the material of the first metal layer includes molybdenum-titanium alloy or aluminum-titanium alloy.
  • the thin film transistor device layer includes a second metal layer located above the first metal layer, and the second metal layer includes source and drain electrodes corresponding to the display region , and the signal traces corresponding to the binding area.
  • the source electrode is overlapped with the light-shielding metal through a via hole penetrating a part of the spacer layer, and the signal trace is connected to the light-shielding metal through a via hole penetrating a part of the spacer layer.
  • the bonding metal is overlapped, and the bonding metal is electrically connected to the thin film transistor through the signal wiring.
  • the OLED display panel further includes an inter-insulating layer, a planarization layer, an anode and a pixel definition layer sequentially disposed on the thin-film transistor device layer, and the inter-insulating layer, the The flat layer, the anode, and the pixel definition layer are all staggered from the opening to expose a part of the upper surface of the bonding metal.
  • the anode is overlapped with the source electrode through a via hole penetrating the flat layer and part of the inter-insulating layer.
  • the pixel definition layer has a pixel opening, and the pixel opening exposes the upper surface of the anode, and the OLED display panel further includes a pixel opening disposed in the pixel opening and covering the The light-emitting layer on the top surface of the anode.
  • an OLED display panel includes a display area and a binding area at least on one side of the display area;
  • the OLED display panel further includes:
  • the first metal layer includes a light-shielding metal corresponding to the display area and a binding metal corresponding to the binding area;
  • the thin film transistor device layer is disposed on the first metal layer, and the thin film transistor device layer includes a thin film transistor corresponding to the top of the light-shielding metal and a spacer layer, and the spacer layer is formed with an opening in the binding area , to expose part of the upper surface of the bonded metal.
  • the thin film transistor device layer includes a second metal layer located above the first metal layer, and the second metal layer includes source and drain electrodes corresponding to the display region , and the signal traces corresponding to the binding area.
  • the source electrode is overlapped with the light-shielding metal through a via hole penetrating a part of the spacer layer, and the signal trace is connected to the light-shielding metal through a via hole penetrating a part of the spacer layer.
  • the bonding metal is overlapped, and the bonding metal is electrically connected to the thin film transistor through the signal wiring.
  • the OLED display panel further includes an inter-insulating layer, a planarization layer, an anode and a pixel definition layer sequentially disposed on the thin-film transistor device layer, and the inter-insulating layer, the The flat layer, the anode, and the pixel definition layer are all staggered from the opening to expose a part of the upper surface of the bonding metal.
  • the anode is overlapped with the source electrode through a via hole penetrating the flat layer and part of the inter-insulating layer.
  • the pixel definition layer has a pixel opening, and the pixel opening exposes the upper surface of the anode, and the OLED display panel further includes a pixel opening disposed in the pixel opening and covering the The light-emitting layer on the top surface of the anode.
  • the OLED display panel includes a display area and a binding area at least on one side of the display area, and the method includes:
  • the first metal layer includes a light-shielding metal corresponding to the display area and a binding metal corresponding to the binding area;
  • the thin film transistor device layer includes a thin film transistor corresponding to the top of the light-shielding metal and a spacer layer, the spacer layer is formed in the binding region opening to expose part of the upper surface of the bonding metal.
  • the step S20 includes:
  • a first via hole and a second via hole penetrating through a part of the interlayer dielectric layer are prepared to expose two parts of the active layer respectively.
  • a third via hole and a fourth via hole penetrating the interlayer dielectric layer and part of the buffer layer are respectively prepared to expose the light-shielding metal, respectively. part of the upper surface and part of the upper surface of the bonded metal.
  • the source electrode and the drain electrode fill the first via hole and the second via hole respectively, and are connected to both sides of the active layer.
  • the source electrode is also filled with the third via hole and overlapped with the light-shielding metal
  • the signal trace is filled with the fourth via hole and overlapped with the bonding metal.
  • a photoresist material layer is prepared to cover part of the upper surface of the interlayer dielectric layer, and the interlayer not covered by the photoresist material layer is removed a dielectric layer and the corresponding buffer layer to form the opening.
  • the step S203 further includes sequentially preparing an inter-insulating layer, a flat layer, an anode and a pixel definition layer on the thin film transistor device layer, and the inter-insulating layer, the flat layer , the anode, and the pixel definition layer are all staggered from the opening, so as to expose a part of the upper surface of the bonding metal.
  • the anode is overlapped with the source electrode through a via hole penetrating the flat layer and part of the inter-insulating layer.
  • the material of the first metal layer includes a molybdenum-titanium alloy or an aluminum-titanium alloy.
  • the present invention uses the same layer of metal material of the light-shielding metal to make the binding metal while preparing the light-shielding metal, because the stability and corrosion resistance of the light-shielding metal are better, thereby improving the binding metal. Stability and corrosion resistance improve the reliability and yield of OLED display panels.
  • FIG. 1 is a schematic structural diagram of an OLED display panel provided by an embodiment of the present invention.
  • FIG. 2 is a flowchart of a manufacturing method of an OLED display panel provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a manufacturing process of an OLED display panel according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a manufacturing process of an OLED display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a manufacturing process of an OLED display panel according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a manufacturing process of an OLED display panel according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a manufacturing process of an OLED display panel according to an embodiment of the present invention.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present invention, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include the first and second features in direct contact, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • Embodiments of the present invention provide an OLED display panel and a manufacturing method thereof, which can solve the technical problem in the prior art that the bonding metal is easily corroded by etching solution during the manufacturing process and is unstable in the environment, thereby affecting product yield.
  • FIG. 1 is a schematic structural diagram of the OLED display panel provided by the embodiment of the present invention, wherein the OLED display panel includes a display area 10 and a At least the binding area 20 on one side of the display area 10 .
  • the OLED display panel further includes: a substrate 101; a first metal layer 102 disposed on the substrate 101, and the first metal layer 102 includes a light-shielding metal 1022 corresponding to the display area 10, and a metal layer 102 corresponding to the binding
  • the bonding metal 1021 of the fixed area 20; and the thin film transistor device layer 103 are disposed on the first metal layer 102, and the thin film transistor device layer 103 includes a thin film transistor and a spacer layer corresponding to the top of the light-shielding metal 1022 , the spacer layer is formed with an opening 109 in the bonding region 20 to expose part of the upper surface of the bonding metal 1021 .
  • the embodiment of the present invention provides an OLED display panel,
  • the bonding metal is prepared by using the same layer material of the shading metal to improve the corrosion resistance and stability of the bonding metal, thereby improving the reliability and yield of the OLED display panel.
  • the OLED display panel includes a substrate 101 , a first metal layer 102 disposed on the substrate 101 , and a thin film transistor device layer 103 disposed on the first metal layer 102 , wherein the first metal layer 102 includes a light-shielding metal 1022 corresponding to the display area 10 and a binding metal 1021 corresponding to the binding area 20 , and the material of the first metal layer 102 includes a molybdenum-titanium alloy or aluminum Titanium alloy, and is not limited to the single-layer or stacked alloy structure of molybdenum, titanium or aluminum, titanium, in addition, the material of the first metal layer 102 may also include other metal materials or alloy materials with strong acid resistance and reliability .
  • the thin film transistor device layer 103 includes a thin film transistor and a spacer layer correspondingly located above the light-shielding metal 1022. Specifically, the thin film transistor device layer 103 includes a buffer layer 1031 disposed on the first metal layer 102. The active layer 1033 on the buffer layer 1031 and above the light-shielding metal 1022, the gate insulating layer 1034 and the gate 1035 on the active layer 1033 are sequentially arranged on the active layer 1033 and the gate electrode 1035.
  • the interlayer dielectric layer 1032 on the gate 1035 is disposed on the second metal layer on the interlayer dielectric layer 1032, wherein the second metal layer is disposed above the first metal layer 102, and all the
  • the second metal layer includes a source electrode 1037 and a drain electrode 1036 corresponding to the display area 10, and a signal trace 110 corresponding to the bonding area 20, and the source electrode 1037 and the drain electrode 1036 pass through the through portion
  • the via holes of the interlayer dielectric layer 1032 are respectively overlapped with both sides of the active layer 1033, and the source electrode 1037 is also overlapped with the light-shielding metal 1022 through the via holes penetrating part of the spacer layer, which can be used for The electric charge on the light-shielding metal 1022 is conducted away to maintain the stability of the electrical characteristics of the thin film transistor.
  • the signal wire 110 is overlapped with the bonding metal 1021 through a via hole penetrating part of the spacer layer, Therefore, the bonding metal 1021 is electrically connected to the thin film transistor (not shown in the figure). In the subsequent process, the bonding metal 1021 is bound to the circuit board, so that the transmission of the display signal can be realized. , so as to realize the normal display function of the OLED display panel.
  • the thin film transistor includes the active layer 1033, the gate electrode 1035, the source electrode 1037 and the drain electrode 1036, the spacer layer includes the buffer layer 1031, the The interlayer dielectric layer 1032 and the gate insulating layer 1034 .
  • the OLED display panel further includes an inter-insulating layer 104 , a flat layer 105 , an anode 107 and a pixel definition layer 106 sequentially disposed on the thin film transistor device layer 103 , and the pixel definition layer 106 defines a plurality of pixel openings , each of the pixel openings exposes an upper surface of the anode 107, and at the same time, a light-emitting layer 108 is formed in the pixel opening and located on the anode 107, and the anode 107 also passes through the flat layer.
  • 105 and part of the via holes of the inter-insulating layer 104 are overlapped with the source electrode 1037 to realize the transmission of electrical signals, and the material of the pixel definition layer 106 is not limited to conventional non-hydrophobic materials or hydrophobic materials.
  • the inter-insulating layer 104 , the flat layer 105 , the anode 107 and the pixel definition layer 106 are all staggered from the opening 109 to expose part of the bonding metal 1021 upper surface.
  • the OLED display panel provided by the embodiment of the present invention uses the same layer of light-shielding metal to make the binding metal, so as to improve the acid resistance and reliability of the binding metal, thereby improving the reliability and quality of the OLED display panel. Rate.
  • an embodiment of the present invention also provides a manufacturing method of an OLED display panel, please refer to FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 10 and a binding area 20 at least on one side of the display area 10 .
  • the manufacturing method of the OLED display panel includes:
  • the first metal layer 102 includes a light-shielding metal 1022 corresponding to the display area 10 and a binding metal 1021 corresponding to the binding area 20 .
  • a substrate 101 is provided, and a patterned first metal layer 102 is prepared on the substrate 101, and the first metal layer 102 includes a light-shielding metal 1022 corresponding to the display area 10 and corresponding to the binding area and the substrate 101 includes a glass substrate, and the material of the first metal layer 102 includes molybdenum-titanium alloy or aluminum-titanium alloy, and is not limited to molybdenum, titanium or aluminum, or a single-layer or stacked alloy of titanium In addition, the material of the first metal layer 102 may also include other metal materials or alloy materials with strong acid resistance and high reliability.
  • the thin film transistor device layer 103 includes a thin film transistor corresponding to the top of the light-shielding metal 1022 and a spacer layer, the spacer layer is on the bonding
  • the fixed area 20 is formed with an opening 109 to expose a part of the upper surface of the bonding metal 1021 .
  • the step S20 includes:
  • a first via hole 1121 and a second via hole 1122 penetrating part of the interlayer dielectric layer 1032 are prepared to expose the upper surfaces on both sides of the active layer 1033 respectively, corresponding to the A third via hole 1123 and a fourth via hole 1124 are respectively prepared in the display area 10 and the bonding area 20 penetrating the interlayer dielectric layer 1032 and part of the buffer layer 101 to expose part of the light-shielding metal 1022 , respectively. the upper surface and part of the upper surface of the bonding metal 1021 .
  • the bonding metal 1021 is bound to the circuit board to realize the transmission of display signals. , to realize the display function of the OLED display panel.
  • an interlayer insulating layer 104 , a flat layer 105 , an anode 107 and a pixel definition layer 106 are sequentially prepared on the interlayer dielectric layer 1032 , and the interlayer insulating layer 104 , the flat layer 105 , the anode 107 and the The pixel definition layer 106 is staggered from the opening 109 to expose part of the upper surface of the bonding metal 1021 , and in the process of preparing the anode 107, since the first metal layer 102 has a higher Corrosion resistance, so that the bonding metal 1021 can resist the corrosion of the etching solution, and because the first metal layer 102 has better reliability, the bonding metal 1021 can be improved in the testing process or in the environment. reliability in the OLED display panel, which improves the reliability and stability of the OLED display panel.
  • the anode 107 is overlapped with the source electrode 1037 through a via hole passing through the flat layer 105 and part of the inter-insulating layer 104, and the pixel definition layer 106 defines a pixel opening through a retaining wall structure to expose all the the upper surface of the anode 107, and a light-emitting layer 108 is prepared in the pixel opening, the light-emitting layer 108 is correspondingly located on the anode 107, and the light-emitting layer 108 can be prepared by an evaporation process or an inkjet printing process , the material of the pixel definition layer 106 is not limited to non-hydrophobic material or hydrophobic material.
  • the metal material of the same layer of the light-shielding metal is used to make the binding metal. Since the stability and corrosion resistance of the light-shielding metal are better, the stability and resistance of the binding metal are improved. Corrosive, improving the reliability and yield of the OLED display panel.

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Abstract

本发明公开了一种OLED显示面板及其制作方法，OLED显示面板包括显示区以及至少位于显示区一侧的绑定区；OLED显示面板还包括基板以及设置于基板上的第一金属层，且第一金属层包括对应显示区的遮光金属，以及对应绑定区的绑定金属。

Description

OLED显示面板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED显示面板及其制作方法。
 背景技术
有机发光二极管(organic light emitting diode，OLED)显示器作为用于显示图像的显示设备已备受关注，OLED显示器具有自发光特性，并且不采用单独的光源，因此相对于采用单独光源的显示设备更加的薄和轻。
但是，现有技术中，OLED显示器为减少走线阻抗采用Cu走线作为栅极、源极以及漏极等晶体管器件，由于Cu稳定性差，暴露在外部环境时容易氧化，因此不能直接用作绑定金属，目前，常采用阳极ITO层覆盖Cu，以提高绑定金属的稳定性，但是，对于顶发光OLED显示器中，在对反射金属层(Ag或Al)进行蚀刻时，绑定金属中的Cu容易被蚀刻液所腐蚀，进而使得由ITO层覆盖Cu所得到的绑定金属的稳定性同样不佳，易受蚀刻液腐蚀，进而影响产品良率。
 技术问题
本发明实施例提供一种OLED显示面板及其制作方法，能够解决现有技术中，由于绑定金属在制程中易受蚀刻液腐蚀，在环境中不稳定，进而影响产品良率的技术问题。
 技术解决方案
为解决上述技术问题，本发明实施例提供一种OLED显示面板，所述OLED显示面板包括显示区以及至少位于所述显示区一侧的绑定区；
所述OLED显示面板还包括：
基板；
第一金属层，设置于所述基板上，且所述第一金属层包括对应所述显示区的遮光金属，以及对应所述绑定区的绑定金属；以及
薄膜晶体管器件层，设置于所述第一金属层上，且所述薄膜晶体管器件层包括对应位于所述遮光金属上方的薄膜晶体管以及间隔层，所述间隔层于所述绑定区形成有开口，以暴露所述绑定金属的部分上表面；
其中，所述第一金属层的材料包括钼钛合金或铝钛合金。
在本发明的一种实施例中，所述薄膜晶体管器件层包括位于所述第一金属层上方的第二金属层，且所述第二金属层包括对应所述显示区的源极和漏极，以及对应所述绑定区的信号走线。
在本发明的一种实施例中，所述源极通过贯穿部分所述间隔层的过孔与所述遮光金属搭接，所述信号走线通过贯穿部分所述间隔层的过孔与所述绑定金属搭接，且所述绑定金属通过所述信号走线与所述薄膜晶体管电连接。
在本发明的一种实施例中，所述OLED显示面板还包括依次设置于所述薄膜晶体管器件层上的间绝缘层、平坦层、阳极和像素定义层，且所述间绝缘层、所述平坦层、所述阳极以及所述像素定义层均与所述开口错开设置，以暴露所述绑定金属的部分上表面。
在本发明的一种实施例中，所述阳极通过贯穿所述平坦层以及部分所述间绝缘层的过孔与所述源极搭接。
在本发明的一种实施例中，所述像素定义层具有像素开口，所述像素开口暴露所述阳极的上表面，且所述OLED显示面板还包括设置于所述像素开口内并覆盖所述阳极上表面的发光层。
根据本发明的上述目的，提供一种OLED显示面板，所述OLED显示面板包括显示区以及至少位于所述显示区一侧的绑定区；
所述OLED显示面板还包括：
基板；
第一金属层，设置于所述基板上，且所述第一金属层包括对应所述显示区的遮光金属，以及对应所述绑定区的绑定金属；以及
薄膜晶体管器件层，设置于所述第一金属层上，且所述薄膜晶体管器件层包括对应位于所述遮光金属上方的薄膜晶体管以及间隔层，所述间隔层于所述绑定区形成有开口，以暴露所述绑定金属的部分上表面。
在本发明的一种实施例中，所述薄膜晶体管器件层包括位于所述第一金属层上方的第二金属层，且所述第二金属层包括对应所述显示区的源极和漏极，以及对应所述绑定区的信号走线。
在本发明的一种实施例中，所述源极通过贯穿部分所述间隔层的过孔与所述遮光金属搭接，所述信号走线通过贯穿部分所述间隔层的过孔与所述绑定金属搭接，且所述绑定金属通过所述信号走线与所述薄膜晶体管电连接。
在本发明的一种实施例中，所述OLED显示面板还包括依次设置于所述薄膜晶体管器件层上的间绝缘层、平坦层、阳极和像素定义层，且所述间绝缘层、所述平坦层、所述阳极以及所述像素定义层均与所述开口错开设置，以暴露所述绑定金属的部分上表面。
在本发明的一种实施例中，所述阳极通过贯穿所述平坦层以及部分所述间绝缘层的过孔与所述源极搭接。
在本发明的一种实施例中，所述像素定义层具有像素开口，所述像素开口暴露所述阳极的上表面，且所述OLED显示面板还包括设置于所述像素开口内并覆盖所述阳极上表面的发光层。
根据本发明的上述目的，提供一种OLED显示面板的制作方法，所述OLED显示面板包括显示区以及至少位于所述显示区一侧的绑定区，且所述方法包括：
S10、制备第一金属层于基板上，且所述第一金属层包括对应所述显示区的遮光金属，以及对应所述绑定区的绑定金属；以及
S20、制备薄膜晶体管器件层于所述第一金属层上，且所述薄膜晶体管器件层包括对应位于所述遮光金属上方的薄膜晶体管以及间隔层，所述间隔层于所述绑定区形成有开口，以暴露所述绑定金属的部分上表面。
在本发明的一种实施例中，所述步骤S20包括：
S201、依次制备缓冲层、有源层、栅绝缘层、栅极以及层间介质层于所述第一金属层上；
S202、制备第二金属层于所述层间介质层上，且所述第二金属层包括对应所述显示区的源极和漏极，以及对应所述绑定区的信号走线；以及
S203、至少去除所述绑定金属上方的所述缓冲层以及所述层间介质层以形成开口，并暴露所述绑定金属的部分上表面。
在本发明的一种实施例中，所述步骤S201中，对应所述显示区制备贯穿部分所述层间介质层的第一过孔以及第二过孔，以分别暴露所述有源层两侧的上表面，对应所述显示区和所述绑定区分别制备贯穿所述层间介质层、部分所述缓冲层的第三过孔和第四过孔，以分别暴露所述遮光金属的部分上表面以及所述绑定金属的部分上表面。
在本发明的一种实施例中，所述步骤S202中，所述源极和所述漏极分别填充所述第一过孔与所述第二过孔，并与所述有源层两侧搭接，所述源极还填充所述第三过孔与所述遮光金属搭接，所述信号走线填充所述第四过孔与所述绑定金属搭接。
在本发明的一种实施例中，所述步骤S203中，制备光阻材料层以覆盖所述层间介质层的部分上表面，并去除未被所述光阻材料层覆盖的所述层间介质层以及相对应的所述缓冲层，以形成所述开口。
在本发明的一种实施例中，所述步骤S203还包括依次制备间绝缘层、平坦层、阳极和像素定义层于所述薄膜晶体管器件层上，且所述间绝缘层、所述平坦层、所述阳极以及所述像素定义层均与所述开口错开设置，以暴露所述绑定金属的部分上表面。
在本发明的一种实施例中，所述阳极通过贯穿所述平坦层以及部分所述间绝缘层的过孔与所述源极搭接。
在本发明的一种实施例中，所述第一金属层的材料包括钼钛合金或铝钛合金。
 有益效果
相对于现有技术，本发明通过在制备遮光金属的同时，利用遮光金属的同层金属材料制作绑定金属，由于遮光金属的稳定性和耐腐蚀性均较佳，进而提高了绑定金属的稳定性和耐腐蚀性，提高了OLED显示面板的可靠性和良品率。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为本发明实施例提供的OLED显示面板的结构示意图。
图2为本发明实施例提供的OLED显示面板的制作方法流程图。
图3为本发明实施例提供的OLED显示面板的制作流程结构示意图。
图4为本发明实施例提供的OLED显示面板的制作流程结构示意图。
图5为本发明实施例提供的OLED显示面板的制作流程结构示意图。
图6为本发明实施例提供的OLED显示面板的制作流程结构示意图。
图7为本发明实施例提供的OLED显示面板的制作流程结构示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本发明实施例提供一种OLED显示面板及其制作方法，能够解决现有技术中，由于绑定金属在制程中易受蚀刻液腐蚀，在环境中不稳定，进而影响产品良率的技术问题。
为解决上述技术问题，本发明实施例提供一种OLED显示面板，请参照图1所示，为本发明实施例提供的OLED显示面板的结构示意图，其中，所述OLED显示面板包括显示区10以及至少位于所述显示区10一侧的绑定区20。
所述OLED显示面板还包括：基板101；第一金属层102，设置于所述基板101上，且所述第一金属层102包括对应所述显示区10的遮光金属1022，以及对应所述绑定区20的绑定金属1021；以及薄膜晶体管器件层103，设置于所述第一金属层102上，且所述薄膜晶体管器件层103包括对应位于所述遮光金属1022上方的薄膜晶体管以及间隔层，所述间隔层于所述绑定区20形成有开口109，以暴露所述绑定金属1021的部分上表面。
在实施应用过程中，现有的OLED显示面板，由于绑定金属的材质在制程中易受腐蚀，且在环境中亦不能稳定的存在，因此，本发明实施例提供一种OLED显示面板，通过采用遮光金属的同层材料制备绑定金属，以提高绑定金属的耐腐蚀性和稳定性，进而提高了OLED显示面板的可靠性和良品率。
更进一步地，请参照图1所示，所述OLED显示面板包括基板101、设置于所述基板101上的第一金属层102以及设置于所述第一金属层102上的薄膜晶体管器件层103，其中，所述第一金属层102包括对应所述显示区10的遮光金属1022以及对应所述绑定区20的绑定金属1021，所述第一金属层102的材料包括钼钛合金或铝钛合金，且不限于钼、钛或铝、钛的单层或层叠的合金结构，另外，所述第一金属层102的材料还可以包括其他耐酸性强、可靠性强的金属材料或合金材料。
所述薄膜晶体管器件层103包括对应位于所述遮光金属1022上方的薄膜晶体管以及间隔层，具体地，所述薄膜晶体管器件层103包括设置于所述第一金属层102上的缓冲层1031，设置于所述缓冲层1031上并位于所述遮光金属1022上方的有源层1033，依次设置于所述有源层1033上的栅绝缘层1034以及栅极1035，设置于所述有源层1033和所述栅极1035上的层间介质层1032，设置于所述层间介质层1032上的第二金属层，其中，所述第二金属层设置于所述第一金属层102上方，且所述第二金属层包括对应所述显示区10的源极1037和漏极1036，以及对应所述绑定区20的信号走线110，且所述源极1037和所述漏极1036通过贯穿部分所述层间介质层1032的过孔分别与所述有源层1033两侧搭接，所述源极1037还通过贯穿部分所述间隔层的过孔与所述遮光金属1022搭接，可用于导走所述遮光金属1022上的电荷，以保持所述薄膜晶体管电学特性的稳定性，另外，所述信号导线110通过贯穿部分所述间隔层的过孔与所述绑定金属1021搭接，从而使得所述绑定金属1021与所述薄膜晶体管电连接（图中并未示出），在后续制程中，所述绑定金属1021再与电路板进行绑定，从而可以实现显示信号的传输，以实现所述OLED显示面板的正常显示功能。
在本发明实施例中，所述薄膜晶体管包括所述有源层1033、所述栅极1035、所述源极1037以及所述漏极1036，所述间隔层包括所述缓冲层1031、所述层间介质层1032以及所述栅绝缘层1034。
另外，所述OLED显示面板还包括依次设置于所述薄膜晶体管器件层103上的间绝缘层104、平坦层105、阳极107以及像素定义层106，所述像素定义层106限定出多个像素开口，每个所述像素开口均暴露一个所述阳极107的上表面，同时形成发光层108于所述像素开口内，并位于所述阳极107上，且所述阳极107还通过贯穿所述平坦层105以及部分所述间绝缘层104的过孔与所述源极1037搭接，以实现电信号的传输，且所述像素定义层106的材料不限于常规的非疏水性材料或疏水性材料。
在本发明实施例中，所述间绝缘层104、所述平坦层105、所述阳极107以及所述像素定义层106均与所述开口109错开设置，以暴露所述绑定金属1021的部分上表面。
综上所述，本发明实施例提供的OLED显示面板通过采用遮光金属的同层材料制作绑定金属，以提高绑定金属的耐酸性和可靠性，进而提高了OLED显示面板的可靠性和良品率。
另外，本发明实施例还提供一种OLED显示面板的制作方法，请参照图1、图2、图3、图4、图5、图6以及图7所示，所述OLED显示面板包括显示区10以及至少位于所述显示区10一侧的绑定区20。
所述OLED显示面板的制作方法包括：
S10、制备第一金属层102于基板101上，且所述第一金属层102包括对应所述显示区10的遮光金属1022，以及对应所述绑定区20的绑定金属1021。
提供基板101，并制备图案化的第一金属层102于所示基板101上，且所述第一金属层102包括对应位于所述显示区10的遮光金属1022，以及对应位于所述绑定区的绑定金属1021，且所述基板101包括玻璃基板，所述第一金属层102的材料包括钼钛合金或铝钛合金，且不限于钼、钛或铝、钛的单层或层叠的合金结构，另外，所述第一金属层102的材料还可以包括其他耐酸性强、可靠性强的金属材料或合金材料。
S20、制备薄膜晶体管器件层103于所述第一金属层102上，且所述薄膜晶体管器件层103包括对应位于所述遮光金属1022上方的薄膜晶体管以及间隔层，所述间隔层于所述绑定区20形成有开口109，以暴露所述绑定金属1021的部分上表面。
具体地，所述步骤S20包括：
S201、在所述基板101上制备缓冲层1031，在所述缓冲层1031上制备有源层1033，且所述有源层1033位于所述遮光金属1022上方，在所述有源层1033上依次制备栅绝缘层1034和栅极1035，在所述有源层1033和所述栅极1035上制备层间介质层1032。
进一步地，对应所述显示区10制备贯穿部分所述层间介质层1032的第一过孔1121以及第二过孔1122，以分别暴露所述有源层1033两侧的上表面，对应所述显示区10和所述绑定区20分别制备贯穿所述层间介质层1032、部分所述缓冲层101的第三过孔1123和第四过孔1124，以分别暴露所述遮光金属1022的部分上表面以及所述绑定金属1021的部分上表面。
S202、制备第二金属层于所述层间介质层1032上，且对所述第二金属层进行蚀刻处理，以得到对应所述显示区10的源极1037和漏极1036，以及对应所述绑定区20的信号走线110，其中，所述源极1037和所述漏极1036分别填充所述第一过孔1121与所述第二过孔1122，并与所述有源层1033两侧搭接，所述源极1037还填充所述第三过孔1123与所述遮光金属1022搭接，所述信号走线110填充所述第四过孔1124与所述绑定金属1021搭接，以使得所述绑定金属1021可以通过所述信号走线110与所述薄膜晶体管电连接，在后续制程中，所述绑定金属1021再与电路板进行绑定，以实现显示信号的传输，实现所述OLED显示面板的显示功能。
S203、于所述层间介质层1032上涂布光阻材料层111，以覆盖部分所述层间介质层1032的表面，并对未被所述光阻材料层111所覆盖的层间介质层1032进行开口处理，至少去除所述绑定金属1021上方的所述缓冲层1031以及所述层间介质层1032以形成开口109，并暴露所述绑定金属1021的部分上表面，本发明实施例通过在完成所述第二金属层的蚀刻之后再进行开口处理，进而防止了所述绑定金属1021在所述第二金属层的蚀刻过程中被其Cu酸蚀刻液所腐蚀，进一步提高了产品良率。
进一步地，在所述层间介质层1032上依次制备间绝缘层104、平坦层105、阳极107以及像素定义层106，且所述间绝缘层104、所述平坦层105、所述阳极107以及所述像素定义层106均与所述开口109错开设置，以暴露所述绑定金属1021的部分上表面，且制备所述阳极107的过程中，由于所述第一金属层102具有较高的耐腐蚀性，进而使得所述绑定金属1021可以抵抗蚀刻液的腐蚀，且由于所述第一金属层102具有较佳的可靠性，提高了所述绑定金属1021在测试过程中或在环境中的可靠性，提高了所述OLED显示面板的可靠性和稳定性。
其中，所述阳极107通过贯穿所述平坦层105以及部分所述间绝缘层104的过孔与所述源极1037搭接，所述像素定义层106通过挡墙结构限定出像素开口以暴露所述阳极107的上表面，并于所述像素开口内制备发光层108，所述发光层108对应位于所述阳极107上，且所述发光层108可采用蒸镀工艺或喷墨打印工艺进行制备，所述像素定义层106的材料不限于非疏水性材料或疏水性材料。
本发明实施例通过在制备遮光金属的同时，利用遮光金属的同层金属材料制作绑定金属，由于遮光金属的稳定性和耐腐蚀性均较佳，进而提高了绑定金属的稳定性和耐腐蚀性，提高了OLED显示面板的可靠性和良品率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本发明实施例所提供的一种OLED显示面板及其制作方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (20)

  1. 一种OLED显示面板，所述OLED显示面板包括显示区以及至少位于所述显示区一侧的绑定区；
    所述OLED显示面板还包括：
    基板；
    第一金属层，设置于所述基板上，且所述第一金属层包括对应所述显示区的遮光金属，以及对应所述绑定区的绑定金属；以及
    薄膜晶体管器件层，设置于所述第一金属层上，且所述薄膜晶体管器件层包括对应位于所述遮光金属上方的薄膜晶体管以及间隔层，所述间隔层于所述绑定区形成有开口，以暴露所述绑定金属的部分上表面；
    其中，所述第一金属层的材料包括钼钛合金或铝钛合金。
  2. 根据权利要求1所述的OLED显示面板，其中，所述薄膜晶体管器件层包括位于所述第一金属层上方的第二金属层，且所述第二金属层包括对应所述显示区的源极和漏极，以及对应所述绑定区的信号走线。
  3. 根据权利要求2所述的OLED显示面板，其中，所述源极通过贯穿部分所述间隔层的过孔与所述遮光金属搭接，所述信号走线通过贯穿部分所述间隔层的过孔与所述绑定金属搭接，且所述绑定金属通过所述信号走线与所述薄膜晶体管电连接。
  4. 根据权利要求2所述的OLED显示面板，其中，所述OLED显示面板还包括依次设置于所述薄膜晶体管器件层上的间绝缘层、平坦层、阳极和像素定义层，且所述间绝缘层、所述平坦层、所述阳极以及所述像素定义层均与所述开口错开设置，以暴露所述绑定金属的部分上表面。
  5. 根据权利要求4所述的OLED显示面板，其中，所述阳极通过贯穿所述平坦层以及部分所述间绝缘层的过孔与所述源极搭接。
  6. 根据权利要求4所述的OLED显示面板，其中，所述像素定义层具有像素开口，所述像素开口暴露所述阳极的上表面，且所述OLED显示面板还包括设置于所述像素开口内并覆盖所述阳极上表面的发光层。
  7. 一种OLED显示面板，所述OLED显示面板包括显示区以及至少位于所述显示区一侧的绑定区；
    所述OLED显示面板还包括：
    基板；
    第一金属层，设置于所述基板上，且所述第一金属层包括对应所述显示区的遮光金属，以及对应所述绑定区的绑定金属；以及
    薄膜晶体管器件层，设置于所述第一金属层上，且所述薄膜晶体管器件层包括对应位于所述遮光金属上方的薄膜晶体管以及间隔层，所述间隔层于所述绑定区形成有开口，以暴露所述绑定金属的部分上表面。
  8. 根据权利要求7所述的OLED显示面板，其中，所述薄膜晶体管器件层包括位于所述第一金属层上方的第二金属层，且所述第二金属层包括对应所述显示区的源极和漏极，以及对应所述绑定区的信号走线。
  9. 根据权利要求8所述的OLED显示面板，其中，所述源极通过贯穿部分所述间隔层的过孔与所述遮光金属搭接，所述信号走线通过贯穿部分所述间隔层的过孔与所述绑定金属搭接，且所述绑定金属通过所述信号走线与所述薄膜晶体管电连接。
  10. 根据权利要求8所述的OLED显示面板，其中，所述OLED显示面板还包括依次设置于所述薄膜晶体管器件层上的间绝缘层、平坦层、阳极和像素定义层，且所述间绝缘层、所述平坦层、所述阳极以及所述像素定义层均与所述开口错开设置，以暴露所述绑定金属的部分上表面。
  11. 根据权利要求10所述的OLED显示面板，其中，所述阳极通过贯穿所述平坦层以及部分所述间绝缘层的过孔与所述源极搭接。
  12. 根据权利要求10所述的OLED显示面板，其中，所述像素定义层具有像素开口，所述像素开口暴露所述阳极的上表面，且所述OLED显示面板还包括设置于所述像素开口内并覆盖所述阳极上表面的发光层。
  13. 一种OLED显示面板的制作方法，所述OLED显示面板包括显示区以及至少位于所述显示区一侧的绑定区，且所述方法包括：
    S10、制备第一金属层于基板上，且所述第一金属层包括对应所述显示区的遮光金属，以及对应所述绑定区的绑定金属；以及
    S20、制备薄膜晶体管器件层于所述第一金属层上，且所述薄膜晶体管器件层包括对应位于所述遮光金属上方的薄膜晶体管以及间隔层，所述间隔层于所述绑定区形成有开口，以暴露所述绑定金属的部分上表面。
  14. 根据权利要求13所述的OLED显示面板的制作方法，其中，所述步骤S20包括：
    S201、依次制备缓冲层、有源层、栅绝缘层、栅极以及层间介质层于所述第一金属层上；
    S202、制备第二金属层于所述层间介质层上，且所述第二金属层包括对应所述显示区的源极和漏极，以及对应所述绑定区的信号走线；以及
    S203、至少去除所述绑定金属上方的所述缓冲层以及所述层间介质层以形成开口，并暴露所述绑定金属的部分上表面。
  15. 根据权利要求14所述的OLED显示面板的制作方法，其中，所述步骤S201中，对应所述显示区制备贯穿部分所述层间介质层的第一过孔以及第二过孔，以分别暴露所述有源层两侧的上表面，对应所述显示区和所述绑定区分别制备贯穿所述层间介质层、部分所述缓冲层的第三过孔和第四过孔，以分别暴露所述遮光金属的部分上表面以及所述绑定金属的部分上表面。
  16. 根据权利要求15所述的OLED显示面板的制作方法，其中，所述步骤S202中，所述源极和所述漏极分别填充所述第一过孔与所述第二过孔，并与所述有源层两侧搭接，所述源极还填充所述第三过孔与所述遮光金属搭接，所述信号走线填充所述第四过孔与所述绑定金属搭接。
  17. 根据权利要求14所述的OLED显示面板的制作方法，其中，所述步骤S203中，制备光阻材料层以覆盖所述层间介质层的部分上表面，并去除未被所述光阻材料层覆盖的所述层间介质层以及相对应的所述缓冲层，以形成所述开口。
  18. 根据权利要求14所述的OLED显示面板的制作方法，其中，所述步骤S203还包括依次制备间绝缘层、平坦层、阳极和像素定义层于所述薄膜晶体管器件层上，且所述间绝缘层、所述平坦层、所述阳极以及所述像素定义层均与所述开口错开设置，以暴露所述绑定金属的部分上表面。
  19. 根据权利要求18所述的OLED显示面板的制作方法，其中，所述阳极通过贯穿所述平坦层以及部分所述间绝缘层的过孔与所述源极搭接。
  20. 根据权利要求13所述的OLED显示面板的制作方法，其中，所述第一金属层的材料包括钼钛合金或铝钛合金。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112366218A (zh) * 2020-11-05 2021-02-12 Tcl华星光电技术有限公司 一种显示面板的制作方法及显示面板
CN113192979A (zh) * 2021-04-13 2021-07-30 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法
CN113193012A (zh) * 2021-04-13 2021-07-30 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示装置
CN113192982A (zh) * 2021-04-14 2021-07-30 深圳市华星光电半导体显示技术有限公司 有机发光显示器件的阵列基板及其制备方法
CN114695494A (zh) * 2022-03-23 2022-07-01 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其制作方法
CN116456769A (zh) * 2023-04-20 2023-07-18 惠科股份有限公司 显示面板和显示终端

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150084239A (ko) * 2014-01-13 2015-07-22 삼성디스플레이 주식회사 유기발광 디스플레이 장치의 제조방법
CN107039491A (zh) * 2015-12-29 2017-08-11 乐金显示有限公司 有机发光显示装置及其制造方法
CN109728188A (zh) * 2017-10-31 2019-05-07 乐金显示有限公司 显示设备和用于制造该显示设备的方法
CN110071147A (zh) * 2019-04-09 2019-07-30 深圳市华星光电半导体显示技术有限公司 显示面板和电子设备
CN111223817A (zh) * 2018-11-26 2020-06-02 三星显示有限公司 显示基底、制造显示基底的方法和显示装置
CN111445846A (zh) * 2019-01-17 2020-07-24 三星显示有限公司 显示设备
CN112234080A (zh) * 2019-07-15 2021-01-15 乐金显示有限公司 有机发光显示装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100194679B1 (ko) * 1996-05-21 1999-07-01 윤종용 박막 트랜지스터 및 그 제조 방법
KR101972463B1 (ko) * 2011-02-18 2019-08-19 삼성디스플레이 주식회사 유기전계발광 표시장치 및 그 제조방법
CN103094354B (zh) * 2013-01-28 2015-08-12 合肥京东方光电科技有限公司 阵列基板及其制造方法、显示装置
KR102139972B1 (ko) * 2013-12-31 2020-07-31 엘지디스플레이 주식회사 유기전계 발광표시소자 및 이의 제조방법
JP2017111296A (ja) * 2015-12-16 2017-06-22 株式会社ジャパンディスプレイ 表示装置
US10241609B2 (en) * 2015-12-30 2019-03-26 Lg Display Co., Ltd. Display device with touch sensor
KR102400022B1 (ko) * 2015-12-30 2022-05-19 엘지디스플레이 주식회사 측부 구부림 구조를 갖는 플렉서블 유기발광 다이오드 표시장치
CN107910301B (zh) * 2017-11-23 2020-08-04 合肥鑫晟光电科技有限公司 显示基板的制作方法、显示基板及显示装置
TWI678579B (zh) * 2017-12-19 2019-12-01 友達光電股份有限公司 顯示面板以及顯示裝置
KR20200019309A (ko) * 2018-08-13 2020-02-24 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조방법
KR20200033662A (ko) * 2018-09-20 2020-03-30 엘지디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN109300917B (zh) * 2018-09-30 2021-01-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN109273365A (zh) * 2018-10-23 2019-01-25 惠科股份有限公司 薄膜晶体管的制备方法、薄膜晶体管及显示面板
KR20200049115A (ko) * 2018-10-31 2020-05-08 엘지디스플레이 주식회사 투명 유기 발광 표시 장치 및 이의 제조방법
KR102652572B1 (ko) * 2018-12-03 2024-03-28 엘지디스플레이 주식회사 플렉서블 전계 발광 표시장치
KR102169567B1 (ko) * 2018-12-21 2020-10-23 엘지디스플레이 주식회사 유기 발광 소자
KR20200102572A (ko) * 2019-02-21 2020-09-01 삼성디스플레이 주식회사 표시장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150084239A (ko) * 2014-01-13 2015-07-22 삼성디스플레이 주식회사 유기발광 디스플레이 장치의 제조방법
CN107039491A (zh) * 2015-12-29 2017-08-11 乐金显示有限公司 有机发光显示装置及其制造方法
CN109728188A (zh) * 2017-10-31 2019-05-07 乐金显示有限公司 显示设备和用于制造该显示设备的方法
CN111223817A (zh) * 2018-11-26 2020-06-02 三星显示有限公司 显示基底、制造显示基底的方法和显示装置
CN111445846A (zh) * 2019-01-17 2020-07-24 三星显示有限公司 显示设备
CN110071147A (zh) * 2019-04-09 2019-07-30 深圳市华星光电半导体显示技术有限公司 显示面板和电子设备
CN112234080A (zh) * 2019-07-15 2021-01-15 乐金显示有限公司 有机发光显示装置

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