WO2022021619A1 - 存储位元的制备方法及mram的制备方法 - Google Patents

存储位元的制备方法及mram的制备方法 Download PDF

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WO2022021619A1
WO2022021619A1 PCT/CN2020/121944 CN2020121944W WO2022021619A1 WO 2022021619 A1 WO2022021619 A1 WO 2022021619A1 CN 2020121944 W CN2020121944 W CN 2020121944W WO 2022021619 A1 WO2022021619 A1 WO 2022021619A1
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tunnel junction
magnetic tunnel
preparation
oxide layer
layer
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PCT/CN2020/121944
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English (en)
French (fr)
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李辉辉
王曙光
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浙江驰拓科技有限公司
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Publication of WO2022021619A1 publication Critical patent/WO2022021619A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/01—Manufacture or treatment

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  • the present disclosure relates to the field of semiconductor memory chip manufacturing, and in particular, to a method for preparing storage bits and a method for preparing MRAM.
  • Magnetic random access memory uses a magnetic tunnel junction (MTJ) as an information storage bit, and uses the high and low states of its TMR resistance to record information 0 and 1. It has excellent properties such as fast read and write speed, non-volatile, and radiation resistance. It is the next-generation non-volatile storage technology with great potential.
  • MTJ magnetic tunnel junction
  • the fabrication process integration technology of MRAM faces many difficulties:
  • MTJ etching is difficult. In order to avoid RIE chemical corrosion destroying its electromagnetic properties, MTJ etching generally adopts IBE method. However, because the top metal electrode is covered on top, and the material forming MTJ also has metal elements, IBE etching is accompanied by Sidewall metal deposition and plasma bombardment, which can cause severe short circuit and magnetic damage;
  • the main purpose of the present disclosure is to provide a preparation method of a storage bit and a preparation method of an MRAM, so as to solve the problem that the preparation process of the storage bit in the prior art easily leads to the magnetic damage of the device.
  • a method for preparing a storage bit cell including the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method further includes the following steps: The sidewalls of the junction are oxidized to form an oxide layer outside the magnetic tunnel junction; the oxide layer is removed.
  • the step of forming the tunnel junction includes: sequentially forming a tunnel junction material layer and a top electrode material layer on the bottom electrode; patterning the top electrode material layer to form a top electrode; The layer is etched to form a magnetic tunnel junction, preferably a first ion beam etch of the tunnel junction material.
  • the thickness of the oxide layer is less than 5 nm.
  • the magnetic tunnel junction is placed in a first gas atmosphere containing oxygen to oxidize the sidewall, preferably the temperature of the first gas atmosphere is 20-250°C.
  • oxygen-containing plasma is used to perform surface oxidation treatment on the magnetic tunnel junction to oxidize the sidewalls.
  • the temperature of the surface oxidation treatment is 20-250°C.
  • a second ion beam etching is performed on the oxide layer to remove the oxide layer, and preferably, the energy of the second ion beam etching is 20-500W.
  • the preparation method before the step of oxidizing the sidewall of the magnetic tunnel junction, or after the step of removing the oxide layer, the preparation method further includes the following step: performing a surface reduction treatment on the magnetic tunnel junction to repair the surface of the magnetic tunnel junction. broken bonds and dangling bonds; preferably, the magnetic tunnel junction is annealed after the step of surface reduction treatment.
  • the magnetic tunnel junction is placed in a second gas atmosphere containing hydrogen to perform surface reduction treatment, preferably the temperature of the second gas atmosphere is 150-250°C.
  • a hydrogen-containing plasma is used to perform surface reduction treatment on the magnetic tunnel junction, and the temperature of the surface reduction treatment is preferably 150-250°C.
  • the preparation method further includes the following step: forming a protective film covering the tunnel junction and the top electrode on the bottom electrode.
  • a method for manufacturing an MRAM which includes the step of forming at least one storage bit, and the storage bit is formed by using the above-mentioned preparation method.
  • a preparation method of a storage bit which includes the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method oxidizes the sidewall of the magnetic tunnel junction to form a magnetic tunnel junction. The oxide layer outside the magnetic tunnel junction is then removed.
  • the above preparation method avoids short circuit phenomenon and magnetic damage caused by metal deposition in the process of etching the sidewall to form the magnetic tunnel junction, and ensures the performance of the memory.
  • FIG. 1 shows a cross-sectional structure of a substrate after sequentially forming a tunnel junction material, a top electrode material, a mask material layer and a patterned photoresist on the bottom electrode in the method for preparing a memory bit provided by the embodiment of the present application schematic diagram;
  • FIG. 2 shows a schematic diagram of the cross-sectional structure of the substrate after the mask material layer shown in FIG. 1 is formed into a hard mask layer;
  • FIG. 3 shows a schematic diagram of the cross-sectional structure of the substrate after the top electrode material shown in FIG. 2 is formed into a top electrode;
  • FIG. 4 shows a schematic cross-sectional structure diagram of the substrate after the sidewall of the magnetic tunnel junction shown in FIG. 3 is oxidized
  • Fig. 5 shows the schematic diagram of the cross-sectional structure of the substrate after removing the oxide layer shown in Fig. 4;
  • FIG. 6 is a schematic diagram showing the cross-sectional structure of the substrate after forming the protective film covering the tunnel junction and the top electrode shown in FIG. 4 .
  • insulating medium layer 10
  • connecting metal layer 20, bottom electrode; 30, magnetic tunnel junction; 301, tunnel junction material layer; 310, fixed layer; 320, barrier layer; 330, free layer; 40, top electrode 410, top electrode material layer; 50, hard mask layer; 510, mask material layer; 60, photoresist; 70, oxide layer; 80, protective film.
  • the preparation process of the storage bit in the prior art easily leads to the magnetic damage of the device.
  • the applicant of the present disclosure provides a preparation method of a storage bit cell, which includes the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method further includes the following steps: The sidewalls of the magnetic tunnel junction are oxidized to form an oxide layer outside the magnetic tunnel junction; the oxide layer is removed.
  • the above preparation method avoids short circuit phenomenon and magnetic damage caused by metal deposition in the process of etching the sidewall to form the magnetic tunnel junction, and ensures the performance of the memory.
  • FIGS. 1 to 6 Exemplary embodiments of the method for fabricating storage bits provided according to the present disclosure will be described in more detail below with reference to FIGS. 1 to 6 . These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
  • the step of forming the magnetic tunnel junction 30 may include: sequentially forming a tunnel junction material layer 301 and a top electrode material layer 410 on the bottom electrode 20, and the bottom electrode 20 may be formed on the surface of the connection metal layer 10 in the insulating medium layer 100, such as As shown in FIG. 1; the top electrode material layer 410 is patterned to form the top electrode 40, as shown in FIG. 2 and FIG. 3; the tunnel junction material layer 301 is etched with the top electrode 40 as a mask to form a magnetic tunnel At the junction 30, as shown in FIG. 4, the etching stays at and below the bottom electrode 20, so as to achieve complete conductive separation between the memory bits.
  • the above-mentioned magnetic tunnel junction 30 can have various forms according to the application, including but not limited to in-plane MTJ, vertical MTJ, top-pinned MTJ, bottom-pinned MTJ, double-layer MgO MTJ, single-layer MgO MTJ and multi-state MTJ.
  • the fixed layer material, the barrier layer material and the free layer material are sequentially deposited on the bottom electrode 20, and after etching, the magnetic tunnel junction 30 including the fixed layer 310, the barrier layer 320 and the free layer 330 is obtained, As shown in Figure 1 to Figure 4.
  • the step of forming the above-mentioned top electrode 40 includes: depositing a mask material layer 510 on the top electrode material layer 410, and covering the photoresist 60 on the mask material layer 510, by photolithography 2.
  • the photoresist 60 is patterned in the developing process, and the mask material layer 510 is etched with the photoresist 60 as a mask to obtain a hard mask layer 50 with a pattern consistent with the photoresist 60, as shown in FIG. 2 ;
  • the top electrode material layer 410 is etched through the hard mask layer 50 to transfer the pattern of the patterned photoresist 60 to obtain the top electrode 40, as shown in FIG. 3 .
  • the above-mentioned top electrode 40 material can be Ta, TaN, TiN and other materials.
  • the material can be SiO x , SiN x and other materials; those skilled in the art can also reasonably set the process conditions of the above-mentioned photolithography process according to the prior art, which will not be repeated here.
  • the tunnel junction material is subjected to first ion beam etching.
  • first ion beam etching ion beam etching process
  • IBE ion beam etching process
  • the energy of the first ion beam etching is 500-2000W.
  • the sidewalls of the magnetic tunnel junction 30 are oxidized to form an oxide layer 70 located outside the magnetic tunnel junction 30 , as shown in FIG. 5 . Since the formation of the magnetic tunnel junction 30 by IBE etching in the prior art is accompanied by sidewall metal deposition and plasma bombardment, serious short circuit and magnetic damage will be brought, and the above-mentioned oxidation step of the present disclosure can make the magnetic tunnel junction 30 side The metal covering the walls is oxidized to form an insulating metal oxide layer, thus avoiding short circuits.
  • the thickness of the oxide layer 70 is less than 5 nm.
  • the magnetic tunnel junction 30 is placed in a first gas atmosphere containing oxygen to oxidize the sidewalls; in order to improve the oxidation effect, more preferably, the above-mentioned first
  • the temperature of the gas atmosphere is 20 to 250°C.
  • oxygen-containing plasma is used to perform surface oxidation treatment on the magnetic tunnel junction 30 to oxidize the sidewalls; in order to improve the oxidation effect, more preferably, the above-mentioned surface oxidation
  • the temperature of the treatment is 20 to 250°C.
  • the oxide layer 70 is removed, as shown in FIG. 5 .
  • the removal of the metal on the sidewall is achieved by first oxidizing the metal deposited on the sidewall of the magnetic tunnel junction 30, and then removing the surface-deposited metal oxide layer 70 rich in oxygen elements.
  • the oxide layer 70 can be removed by performing a secondary etching on the magnetic tunnel junction 30.
  • the secondary etching is not limited to RIE etching or IBE etching, and the etching depth should ensure that the surface oxide layer 70 is completely removed.
  • the oxide layer 70 is subjected to a second ion beam etching to remove the oxide layer 70; in order to avoid the damage to the surface magnetic layer of the sidewall of the magnetic tunnel junction 30 caused by the above IBE etching, it is more preferred , the energy of the second ion beam etching is lower than the energy of the first ion beam etching that forms the magnetic tunnel junction 30 ; further preferably, the energy of the second ion beam etching is 20-500W.
  • the above-mentioned preparation method of the present disclosure may further include performing surface reduction treatment on the magnetic tunnel junction 30 to repair the broken bonds and dangling bonds on the surface of the magnetic tunnel junction 30 .
  • the magnetic tunnel junction 30 is placed in a second gas atmosphere containing hydrogen for surface reduction treatment;
  • the processing temperature should be higher than the moisture vaporization temperature in the corresponding vacuum environment; in order to improve the reduction efficiency, more preferably, the temperature of the second gas atmosphere is 150-250°C.
  • the surface of the magnetic tunnel junction 30 is reduced by using hydrogen-containing plasma; preferably, the hydrogen treatment process temperature should be high Water vaporization temperature in a corresponding vacuum environment; in order to improve the reduction efficiency, more preferably, the temperature of the above-mentioned surface reduction treatment is 150-250°C.
  • the above-mentioned preparation method of the present disclosure further includes the step of annealing the magnetic tunnel junction 30; more preferably, the annealing temperature is 150-250° C., and the annealing time is 5-60 s .
  • the annealing temperature is 150-250° C.
  • the annealing time is 5-60 s .
  • High-temperature annealing with appropriate temperature and time can make the effect of the surface reduction treatment better, so as to more effectively restore the TMR performance of the magnetic tunnel junction 30 itself.
  • the above step of repairing broken bonds and dangling bonds on the surface of the magnetic tunnel junction 30 may also be performed before the step of oxidizing the sidewall of the magnetic tunnel junction 30.
  • the magnetic tunnel junction 30 Hydrogen treatment is performed on the sidewall to repair the broken bonds and dangling bonds on the surface of the magnetic tunnel junction 30, and then the magnetic tunnel junction 30 is oxidized, and then the magnetic tunnel junction 30 is etched a second time to remove the metal deposited on the surface. ion.
  • the above-mentioned preparation method of the present disclosure may further include the following step: forming a protective film 80 covering the tunnel junction and the top electrode 40 on the bottom electrode 20 , as shown in FIG. 6 .
  • the protective film 80 is used to protect the top electrode 40 and the magnetic tunnel junction 30 in subsequent processes.
  • the above protective film 80 is non-conductive and non-magnetic, and those skilled in the art can reasonably select its specific type according to the prior art, such as silicon oxide, silicon nitride, silicon carbide or a compound thereof.
  • a method for manufacturing an MRAM including the step of forming at least one storage bit, where the storage bit is formed by the above-mentioned preparation method.
  • a fixed layer material (CoFeB and corresponding SAF layer and seed layer), a barrier layer material (MgO) and a free layer material (CoFeB) are sequentially formed on the bottom electrode 20 made of TiN to form a tunnel junction material layer 301, and then depositing Ta on the tunnel junction material layer 301 to form a top electrode material layer 410;
  • SiO2 is deposited on the top electrode material layer 410 to form a mask material layer 510, and the photoresist 60 is covered on the mask material layer 510.
  • the mask material layer 510 is etched for the mask to obtain a hard mask layer 50 with a pattern consistent with the photoresist 60, as shown in FIG. 1 and FIG. 2;
  • 410 is etched to transfer the pattern of the patterned photoresist 60 to obtain the top electrode 40, as shown in FIG. 3; then the tunnel junction material layer 301 is etched through the top electrode 40 to form the magnetic tunnel junction 30, including
  • the reference layer 310, the barrier layer 320 and the free layer 330 are etched to stay at the bottom electrode 20 to achieve complete conductive separation between storage bits, as shown in FIG. 4;
  • the magnetic tunnel junction 30 is placed in an oxygen-containing atmosphere to oxidize the sidewall of the magnetic tunnel junction 30 to form an oxide layer 70 located outside the magnetic tunnel junction 30.
  • the temperature of the oxygen-containing atmosphere is 200°C, and the thickness of the formed oxide layer 70 is 3nm;
  • the above oxide layer 70 is removed by IBE etching, the ion beam energy is 20-500W, and the etching depth should ensure that the surface oxide layer 70 is completely removed;
  • a protective film 80 covering the tunnel junction and the top electrode 40 is formed on the bottom electrode 20 by PECVD.
  • the gas pressure is 8.5 Torr
  • the power is 75 W
  • the temperature is 200° C.
  • the time is 25 s.
  • the temperature of the oxygen-containing atmosphere was 250°C.
  • the temperature of the oxygen-containing atmosphere was 20°C.
  • the surface oxidation treatment of the magnetic tunnel junction 30 was performed with oxygen-containing plasma to oxidize the sidewalls at a temperature of 20° C. and a power of 50W.
  • the surface oxidation treatment of the magnetic tunnel junction 30 was performed with oxygen-containing plasma to oxidize the sidewalls at a temperature of 250° C. and a power of 50W.
  • the magnetic tunnel junction 30 is placed in a hydrogen-containing atmosphere for surface reduction treatment at a temperature of 200° C. for 5 s, and then the magnetic tunnel junction 30 is annealed at a temperature of 200° C. , the annealing time is 30s.
  • the surface reduction treatment of the magnetic tunnel junction 30 is carried out by using hydrogen-containing plasma, the temperature is 200° C., the power is 50W, and the time is 3s.
  • the temperature of the surface reduction treatment was 250°C.
  • the temperature of the surface reduction treatment was 150°C.
  • the sidewalls of the magnetic tunnel junction 30 are not oxidized, and the protective film 80 covering the tunnel junction 30 and the top electrode 40 is directly formed.
  • the storage bits in the above-mentioned embodiments 1 to 9 are prepared into MTJ devices, and then the above-mentioned embodiments 1 to 9 and comparative example 1 are used.
  • the properties of the MTJ device such as short Ratio, tunneling magnetoresistance ratio (TMR), free layer coercivity (Hc), and endurance (Endurance) were tested. The test results are shown in the table below.
  • the oxidized surface damage layer is removed by secondary cleaning and etching to improve the stability and life of the device;

Abstract

一种存储位元的制备方法及MRAM的制备方法，该制备方法包括形成磁隧道结（30）的步骤，在形成磁隧道结（30）的步骤之后，制备方法还包括以下步骤：对磁隧道结（30）的侧壁进行氧化，以形成位于磁隧道结（30）外侧的氧化层（70）；去除氧化层（70）。上述制备方法通过对磁隧道结（30）表面的氧化处理，避免了侧壁由于刻蚀形成磁隧道结（30）的工艺中金属沉积而造成的短路现象和磁性破坏，保证了存储器的性能。

Description

存储位元的制备方法及MRAM的制备方法
本公开以2020年07月29日递交的、申请号为202010747301.6且名称为“存储位元的制备方法及MRAM的制备方法”的专利文件为优先权文件，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体存储芯片制造领域，具体而言，涉及一种存储位元的制备方法及MRAM的制备方法。
背景技术
磁性随机存储器(MRAM)以磁性隧道结(MTJ)作为信息存储位元，利用其TMR电阻值的高低态记录信息0和1，具有读写速度快，非易失，抗辐照等优良属性，是极具潜力的下一代非易失性存储技术。然而，MRAM的制备工艺集成技术面临着诸多难题：
1)MTJ刻蚀难度大，为了避免RIE化学腐蚀破坏其电磁性能，MTJ刻蚀一般采用IBE方法，然而由于上方覆盖金属顶电极，且形成MTJ的材料也具有金属元素，导致IBE刻蚀伴随着侧壁金属沉积和等离子体轰击现象，会带来严重的短路和磁性破坏；
2)RIE化学刻蚀中的化学腐蚀或者IBE等离子体物理刻蚀中的等离子体轰击会破坏MTJ侧壁的表面磁性层，磁性破坏层的电阻、TMR及热稳定性等性能相对于正常MTJ都有恶化；同时，磁性破坏层内存在的卤素元素或者氧、氮离子会在后续的高温处理或者使用过程中通过扩散等形式影响成品器件的性能或寿命。
发明内容
本公开的主要目的在于提供一种存储位元的制备方法及MRAM的制备方法，以解决现有技术中存储位元的制备工艺易导致器件磁性破坏的问题。
为了实现上述目的，根据本公开的一个方面，提供了一种存储位元的制备方法，包括形成磁隧道结的步骤，在形成磁隧道结的步骤之后，制备方法还包括以下步骤：对磁隧道结的侧壁进行氧化，以形成位于磁隧道结外侧的氧化层；去除氧化层。
可选地，形成隧道结的步骤包括：在底电极上顺序形成隧道结材料层和顶电极材料层；将顶电极材料层图形化，以形成顶电极；以顶电极为掩膜对隧道结材料层进行刻蚀，以形成磁隧道结，优选地，对隧道结材料进行第一离子束刻蚀。
可选地，氧化层的厚度小于5nm。
可选地，将磁隧道结放置于包含氧气的第一气体氛围下以将侧壁氧化，优选第一气体氛围的温度为20～250℃。
可选地，采用含氧等离子体对磁隧道结进行表面氧化处理以将侧壁氧化，优选表面氧化处理的温度为20～250℃。
可选地，对氧化层进行第二离子束刻蚀，以去除氧化层，优选第二离子束刻蚀的能量为20～500W。
可选地，在对磁隧道结的侧壁进行氧化的步骤之前，或在去除氧化层的步骤之后，制备方法还包括以下步骤：对磁隧道结进行表面还原处理，以修复磁隧道结表面的断键和悬挂键；优选地，在表面还原处理的步骤之后，对磁隧道结进行退火处理。
可选地，将磁隧道结放置于包含氢气的第二气体氛围下以进行表面还原处理，优选第二气体氛围的温度为150～250℃。
可选地，采用含氢等离子体对磁隧道结进行表面还原处理，优选表面还原处理的温度为150～250℃。
可选地，在去除氧化层的步骤之后，制备方法还包括以下步骤：在底电极上形成覆盖隧道结和顶电极的保护膜。
根据本公开的另一方面，提供了一种MRAM的制备方法，包括形成至少一个存储位元的步骤，采用上述的制备方法形成存储位元。
应用本公开的技术方案，提供了一种存储位元的制备方法，包括形成磁隧道结的步骤，在形成磁隧道结的步骤之后，该制备方法对磁隧道结的侧壁进行氧化，以形成位于磁隧道结外侧的氧化层，然后去除氧化层。上述制备方法通过对磁隧道结表面的氧化处理，避免了侧壁由于刻蚀形成磁隧道结的工艺中金属沉积而造成的短路现象和磁性破坏，保证了存储器的性能。
附图说明
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1示出了在本申请实施方式所提供的存储位元的制备方法中，在底电极上顺序形成隧道结材料、顶电极材料、掩膜材料层和图形化光刻胶后的基体剖面结构示意图；
图2示出了将图1所示的掩膜材料层形成硬掩膜层后的基体剖面结构示意图；
图3示出了将图2所示的顶电极材料形成顶电极后的基体剖面结构示意图；
图4示出了对图3所示的磁隧道结的侧壁进行氧化后的基体剖面结构示意图；
图5示出了去除图4所示的氧化层后的基体剖面结构示意图；
图6示出了形成覆盖图4所示的隧道结和顶电极的保护膜后的基体剖面结构示意图。
其中，上述附图包括以下附图标记：
100、绝缘介质层；10、连接金属层；20、底电极；30、磁隧道结；301、隧道结材料层；310、固定层；320、势垒层；330、自由层；40、顶电极；410、顶电极材料层；50、硬掩膜层；510、掩膜材料层；60、光刻胶；70、氧化层；80、保护膜。
具体实施方式
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
为了使本技术领域的人员更好地理解本公开方案，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分的实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本公开保护的范围。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
正如背景技术中所介绍的，现有技术中存储位元的制备工艺易导致器件磁性破坏。本公开的申请人为了解决上述技术问题，提供了一种存储位元的制备方法，包括形成磁隧道结的步骤，在形成磁隧道结的步骤之后，制备方法还包括以下步骤：对磁隧道结的侧壁进行氧化，以形成位于磁隧道结外侧的氧化层；去除氧化层。
上述制备方法通过对磁隧道结表面的氧化处理，避免了侧壁由于刻蚀形成磁隧道结的工艺中金属沉积而造成的短路现象和磁性破坏，保证了存储器的性能。
下面将结合附图1至图6更详细地描述根据本公开提供的存储位元的制备方法的示例性实施方式。然而，这些示例性实施方式可以由多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的实施方式。应当理解的是，提供这些实施方式是为了使得本申请的公开彻底且完整，并且将这些示例性实施方式的构思充分传达给本领域普通技术人员。
首先，形成磁隧道结30。形成该磁隧道结30的步骤可以包括：在底电极20上顺序形成隧道结材料层301和顶电极材料层410，上述底电极20可以形成于绝缘介质层100中的连接金属层10表面，如图1所示；将顶电极材料层410图形化，以形成顶电极40，如图2和图3 所示；以顶电极40为掩膜对隧道结材料层301进行刻蚀，以形成磁隧道结30，如图4所示，刻蚀停留在底电极20及底电极20以下，以使存储位元间实现完全的导电分离。
本领域技术人员可以根据实际所需的磁隧道结30(MTJ)的种类对上述隧道结材料层301中各层的材料进行合理选取。上述磁隧道结30根据应用情况可以有多种形式，包括但不限于面内MTJ，垂直MTJ，顶部钉扎MTJ，底部钉扎MTJ，双层MgO MTJ，单层MgO MTJ以及多态MTJ。在一个实施例中，在底电极20上顺序沉积固定层材料、势垒层材料和自由层材料，在刻蚀后得到包括固定层310、势垒层320和自由层330的磁隧道结30，如图1至图4所示。
在一种优选的实施方式中，形成上述顶电极40的步骤包括：在顶电极材料层410上沉积形成掩膜材料层510，并在掩膜材料层510上覆盖光刻胶60，通过光刻、显影工艺将光刻胶60图形化，以光刻胶60为掩膜对掩膜材料层510进行刻蚀，以得到图案与光刻胶60一致的硬掩膜层50，如图2所示；然后通过该硬掩膜层50对顶电极材料层410进行刻蚀，以将图形化光刻胶60的图案转移得到顶电极40，如图3所示。
在上述优选的实施方式中，本领域技术人员可以根据现有技术对上述顶电极40材料和掩膜材料进行合理选取，如上述顶电极40材料可以为Ta、TaN、TiN等材料，上述掩膜材料可以为SiO x，SiN x等材料；本领域技术人员也可以根据现有技术对上述光刻工艺的工艺条件进行合理设定，在此不再赘述。
在上述形成磁隧道结30的步骤中，优选地，对隧道结材料进行第一离子束刻蚀。采用离子束刻蚀工艺(IBE)能够避免现有技术中采用反应离子腐蚀工艺(RIE)由于化学腐蚀而导致的对磁隧道结30(MTJ)电磁性能的破坏。为了避免上述IBE刻蚀对磁隧道结30侧壁的表面磁性层的破坏，更为优选地，上述第一离子束刻蚀的能量为500～2000W。
在形成上述磁隧道结30的步骤之后，对磁隧道结30的侧壁进行氧化，以形成位于磁隧道结30外侧的氧化层70，如图5所示。由于现有技术中采用IBE刻蚀形成磁隧道结30伴随着侧壁金属沉积和等离子体轰击现象，会带来严重的短路和磁性破坏，而本公开的上述氧化步骤能够将磁隧道结30侧壁覆盖的金属氧化，形成绝缘的金属氧化物层，从而避免了短路现象。
由于上述沉积在磁隧道结30侧壁的金属通常厚度不会太大，为了避免过度氧化对磁隧道结30本身结构的影响，优选地，上述氧化层70的厚度小于5nm。
为了形成上述氧化层70，在一种优选的实施方式中，将磁隧道结30放置于包含氧气的第一气体氛围下以将侧壁氧化；为了提高氧化效果，更为优选地，上述第一气体氛围的温度为20～250℃。
为了形成上述氧化层70，在另一种优选的实施方式中，采用含氧等离子体对磁隧道结30进行表面氧化处理以将侧壁氧化；为了提高氧化效果，更为优选地，上述表面氧化处理的温度为20～250℃。
在形成位于磁隧道结30外侧的氧化层70的步骤之后，去除上述氧化层70，如图5所示。通过先将沉积在磁隧道结30侧壁的金属氧化，再去除掉富含氧元素的表面沉积金属氧化层70，以实现对侧壁上金属的去除。可以通过对磁隧道结30进行二次刻蚀去除上述氧化层70，上述二次刻蚀不限于RIE刻蚀或者IBE刻蚀，刻蚀深度应该保证完全去除表面氧化层70。
在上述步骤中，优选地，对氧化层70进行第二离子束刻蚀，以去除氧化层70；为了避免上述IBE刻蚀对磁隧道结30侧壁的表面磁性层的破坏，更为优选地，上述第二离子束刻蚀的能量低于形成磁隧道结30的第一离子束刻蚀的能量；进一步优选地，上述第二离子束刻蚀的能量为20～500W。
由于对磁隧道结30刻蚀的工艺中，RIE的化学腐蚀或者IBE中的等离子体轰击会破坏磁隧道结30侧壁的表面磁性层，导致出现断键和悬挂键，在去除上述氧化层70的步骤之后，本公开的上述制备方法中还可以包括通过对磁隧道结30进行表面还原处理，以修复磁隧道结30表面的断键和悬挂键。
为了实现对磁隧道结30表面断键和悬挂键的修复，在一种优选的实施方式中，将磁隧道结30放置于包含氢气的第二气体氛围下以进行表面还原处理；优选地，氢处理工艺温度应该高于相应真空环境下的水分汽化温度；为了提高还原效率，更为优选地，上述第二气体氛围的温度为150～250℃。
为了实现对磁隧道结30表面断键和悬挂键的修复，在另一种优选的实施方式中，采用含氢等离子体对磁隧道结30进行表面还原处理；优选地，氢处理工艺温度应该高于相应真空环境下的水分汽化温度；为了提高还原效率，更为优选地，上述表面还原处理的温度为150～250℃。
优选地，在上述表面还原处理的步骤之后，本公开的上述制备方法还包括对磁隧道结30进行退火处理的步骤；更为优选地，退火温度为150～250℃，退火时间为5～60s。辅以适当温度和时间的高温退火，能够使表面还原处理的效果更佳，从而更为有效地修复磁隧道结30本身的TMR性能。
需要注意的是，上述对磁隧道结30表面断键和悬挂键进行修复的步骤还可以在对磁隧道结30的侧壁进行氧化的步骤之前，在一个实施例中，先对磁隧道结30侧壁进行氢处理，以修复磁隧道结30表面的断键和悬挂键，再对磁隧道结30进行氧化处理，然后再对磁隧道结30进行二次刻蚀，以去除其表面沉积的金属离子。
在去除氧化层70的步骤之后，本公开的上述制备方法还可以包括以下步骤：在底电极20上形成覆盖隧道结和顶电极40的保护膜80，如图6所示。该保护膜80用于在后续工艺中起到对顶电极40和磁隧道结30的保护作用。上述保护膜80不导电且无磁性，本领域技术人员可以根据现有技术对其具体种类进行合理选取，如氧化硅、氮化硅、碳化硅或者其化合物。
根据本公开的另一方面，还提供了一种MRAM的制备方法，包括形成至少一个存储位元的步骤，该存储位元采用上述的制备方法形成。
下面将结合实施例和对比例对本公开上述存储位元的制备方法进行进一步说明。
实施例1
本实施例提供的存储位元的制备方法包括以下步骤：
在材料为TiN的底电极20上顺序形成沉积固定层材料(CoFeB及相应SAF层和种子层)、势垒层材料(MgO)和自由层材料(CoFeB)，以形成隧道结材料层301，然后在隧道结材料层301上沉积Ta形成顶电极材料层410；
在顶电极材料层410上沉积SiO 2形成掩膜材料层510，并在掩膜材料层510上覆盖光刻胶60，通过光刻、显影工艺将光刻胶60图形化，以光刻胶60为掩膜对掩膜材料层510进行刻蚀，以得到图案与光刻胶60一致的硬掩膜层50，如图1和图2所示；通过该硬掩膜层50对顶电极材料层410进行刻蚀，以将图形化光刻胶60的图案转移得到顶电极40，如图3所示；然后通过顶电极40对隧道结材料层301进行刻蚀，以形成磁隧道结30，包括参考层310、势垒层320和自由层330，刻蚀停留在底电极20，以使存储位元间实现完全的导电分离，如图4所示；
将磁隧道结30放置于含氧氛围下将磁隧道结30的侧壁氧化，以形成位于磁隧道结30外侧的氧化层70，含氧氛围的温度为200℃，形成的氧化层70厚度为3nm；
采用IBE刻蚀去除上述氧化层70，离子束能量为20～500W，刻蚀深度应该保证完全去除表面氧化层70；
采用PECVD在底电极20上形成覆盖隧道结和顶电极40的保护膜80，沉积时气压8.5Torr，功率75W，温度200℃，时间为25s。
实施例2
本实施例提供的存储位元的制备方法与实施例1的区别在于：
含氧氛围的温度为250℃。
实施例3
本实施例提供的存储位元的制备方法与实施例1的区别在于：
含氧氛围的温度为20℃。
实施例4
本实施例提供的存储位元的制备方法与实施例1的区别在于：
采用含氧等离子体对磁隧道结30进行表面氧化处理以将侧壁氧化，温度为20℃，功率为50W。
实施例5
本实施例提供的存储位元的制备方法与实施例1的区别在于：
采用含氧等离子体对磁隧道结30进行表面氧化处理以将侧壁氧化，温度为250℃，功率为50W。
实施例6
本实施例提供的存储位元的制备方法与实施例1的区别在于：
在去除上述氧化层70的步骤之后，将磁隧道结30放置于含氢氛围下进行表面还原处理，温度为200℃，时间为5s，然后对磁隧道结30进行退火处理，退火温度为200℃，退火时间为30s。
实施例7
本实施例提供的存储位元的制备方法与实施例6的区别在于：
采用含氢等离子体对磁隧道结30进行表面还原处理，温度为200℃，功率为50W，时间为3s。
实施例8
本实施例提供的存储位元的制备方法与实施例7的区别在于：
表面还原处理的温度为250℃。
实施例9
本实施例提供的存储位元的制备方法与实施例7的区别在于：
表面还原处理的温度为150℃。
对比例1
本对比例提供的存储位元的制备方法与实施例1的区别在于：
在形成磁隧道结30之后，不对磁隧道结30的侧壁进行氧化，直接形成覆盖隧道结30和顶电极40的保护膜80。
结合现有技术中常规的半导体制造相关工艺如光刻、刻蚀等技术将上述实施例1～9中的存储位元制备成MTJ器件，然后对采用上述实施例1～9以及对比例1中MTJ器件的短路率(short Ratio)、隧穿磁电阻比(TMR)、自由层矫顽力(Hc)、耐擦写次数(Endurance)等性能进行测试，测试结果如下表所示。
表1
Figure PCTCN2020121944-appb-000001
Figure PCTCN2020121944-appb-000002
从上述测试结果可以看出，通过隧道结侧壁氧化可以解决个别bit的短路问题，同时有效降低磁性损伤，带来TMR和Hc的显著上升。但是残存的氧元素也会造成磁性材料的氧化从而带来一定的磁性性能损失，进一步施加氢处理步骤后，TMR和Hc达到更高的水平，从而获得更好的读窗口和数据保持度，但是由于氢元素会与MgO绝缘层反应，所以随着氢处理的加强(更高的处理温度和更长的处理时间)，耐擦写次数有了一定的下降。综上，表面氧化处理和氢处理在磁性和耐擦写次数等方面有一定的互相折衷，具体应用中需要根据期间性能需求来进行选择和处理温度/时间控制。
从以上的描述中，可以看出，本公开上述的实施例实现了如下技术效果：
1、通过磁隧道结表面氧化处理避免侧壁金属沉积造成的短路现象；
2、通过二次清洗刻蚀去除氧化后的表面破坏层，提升器件稳定性和寿命；
3、对磁隧道结进行表面处理可以有效修复断键和悬挂键，并去除游离的氧元素。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (11)

  1. 一种存储位元的制备方法，包括形成磁隧道结的步骤，其特征在于，在形成所述磁隧道结的步骤之后，所述制备方法还包括以下步骤：
    对所述磁隧道结的侧壁进行氧化，以形成位于所述磁隧道结外侧的氧化层；
    去除所述氧化层。
  2. 根据权利要求1所述的制备方法，其特征在于，形成所述隧道结的步骤包括：
    在底电极上顺序形成隧道结材料层和顶电极材料层；
    将所述顶电极材料层图形化，以形成顶电极；
    以所述顶电极为掩膜对所述隧道结材料层进行刻蚀，以形成所述磁隧道结，优选地，对所述隧道结材料进行第一离子束刻蚀。
  3. 根据权利要求1所述的制备方法，其特征在于，所述氧化层的厚度小于5nm。
  4. 根据权利要求1所述的制备方法，其特征在于，将所述磁隧道结放置于包含氧气的第一气体氛围下以将所述侧壁氧化，优选所述第一气体氛围的温度为20～250℃。
  5. 根据权利要求1所述的制备方法，其特征在于，采用含氧等离子体对所述磁隧道结进行表面氧化处理以将所述侧壁氧化，优选所述表面氧化处理的温度为20～250℃。
  6. 根据权利要求1至5中任一项所述的制备方法，其特征在于，对所述氧化层进行第二离子束刻蚀，以去除所述氧化层，优选所述第二离子束刻蚀的能量为20～500W。
  7. 根据权利要求1至5中任一项所述的制备方法，其特征在于，在对所述磁隧道结的侧壁进行氧化的步骤之前，或在去除所述氧化层的步骤之后，所述制备方法还包括以下步骤：
    对所述磁隧道结进行表面还原处理，以修复所述磁隧道结表面的断键和悬挂键；
    优选地，在所述表面还原处理的步骤之后，对所述磁隧道结进行退火处理。
  8. 根据权利要求7所述的制备方法，其特征在于，将所述磁隧道结放置于包含氢气的第二气体氛围下以进行所述表面还原处理，优选所述第二气体氛围的温度为150～250℃。
  9. 根据权利要求7所述的制备方法，其特征在于，采用含氢等离子体对所述磁隧道结进行表面还原处理，优选所述表面还原处理的温度为150～250℃。
  10. 根据权利要求2所述的制备方法，其特征在于，在去除所述氧化层的步骤之后，所述制备方法还包括以下步骤：
    在所述底电极上形成覆盖所述隧道结和所述顶电极的保护膜。
  11. 一种MRAM的制备方法，包括形成至少一个存储位元的步骤，其特征在于，采用权利要求1至10中任一项所述的制备方法形成所述存储位元。
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