WO2022021620A1 - 存储位元的制备方法及mram的制备方法 - Google Patents

存储位元的制备方法及mram的制备方法 Download PDF

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WO2022021620A1
WO2022021620A1 PCT/CN2020/121946 CN2020121946W WO2022021620A1 WO 2022021620 A1 WO2022021620 A1 WO 2022021620A1 CN 2020121946 W CN2020121946 W CN 2020121946W WO 2022021620 A1 WO2022021620 A1 WO 2022021620A1
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gas
tunnel junction
preparation
layer
magnetic tunnel
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PCT/CN2020/121946
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English (en)
French (fr)
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王曙光
李辉辉
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浙江驰拓科技有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/01—Manufacture or treatment

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  • the present disclosure relates to the field of semiconductor memory chip manufacturing, and in particular, to a method for preparing storage bits and a method for preparing MRAM.
  • Memory chips are an important part of a computer, affecting the speed, integration, and power consumption of the entire computer.
  • the memory is divided into two parts, the hard disk and the cache.
  • the hard disk has a large capacity, and the data is not lost when the power is turned off, but the speed is slow. Even the more advanced solid state drives, NAND Flash, cannot be avoided.
  • the cache speed is fast, such as DRAM and SRAM, but the capacity is small, and the data is lost when the power is turned off.
  • NAND, DRAM and SRAM face a series of insurmountable difficulties such as high power consumption and large area.
  • MRAM is currently the most potential next-generation memory chip. It brings together the high integration characteristics of DRAM, the high-speed characteristics of SRAM, and the non-volatility of Flash. In theory, it has the ability to read and write infinite times and has low power consumption. At present, the world's leading semiconductor companies have started trial production or mass production of MRAM.
  • Tunnel junction etching is one of the two major challenges in MRAM fabrication.
  • the tunnel junction is the core device layer of MRAM. It consists of more than a dozen metals stacked into a film structure of dozens of layers. The thinnest layer is only a few angstroms thick. It is the carrier of data preservation.
  • the task of tunnel junction etching is to etch the continuous tunnel junction film into discrete bits. There are two major difficulties in tunnel junction etching: short circuits and damage. Etching residues tend to adhere to the sidewalls of the bit cells, causing short circuits in the device.
  • the reactants in the etching process will cause damage to the surface layer of the device, thereby reducing the performance of the device; the halogen gas in the reactive ion etching will continuously penetrate into the device, causing the magnetic properties of the bit element to be damaged. Ion beam etching will destroy the lattice structure on the surface of the bit element and form a damaged layer on the surface, which will also cause magnetic damage. These damages cannot be completely eliminated, but can only be gradually controlled and reduced.
  • the main purpose of the present disclosure is to provide a method for preparing a storage bit and a method for preparing an MRAM, so as to solve the problem of serious magnetic damage caused by tunnel junction etching in the prior art.
  • a method for preparing a storage bit cell including the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method further includes the following steps:
  • the sidewalls of the junction are gas passivated to reduce dangling bonds on the sidewall surfaces.
  • the step of forming the tunnel junction includes: sequentially forming a tunnel junction material layer and a first mask material layer on the bottom electrode; patterning the first mask material layer to form a first mask layer; The mask layer etches the tunnel junction material layer to form a magnetic tunnel junction.
  • ion beam etching is performed on the tunnel junction material layer to form a magnetic tunnel junction, preferably using an inert gas to perform ion beam etching.
  • reactive ion etching is performed on the tunnel junction material layer to form a magnetic tunnel junction
  • the plasma source of reactive ion etching is selected from any one of capacitive coupling source, inductive coupling source and electron cyclotron resonance source
  • the reactive gas for reactive ion etching is a fluorine-based gas and/or a chlorine-based gas.
  • gas passivation treatment is performed on the magnetic tunnel junction using a passivation gas including a passivation gas, preferably the passivation gas is selected from any one or more of hydrogen, deuterium, ammonia and deuterated ammonia.
  • the passivation gas also includes a carrier gas, preferably any one or more of the carrier gases helium, neon, argon, xenon and nitrogen.
  • gas passivation treatment is performed on the magnetic tunnel junction by using a plasma formed by a passivation gas, preferably the power of the plasma is 10-200W, the flow rate of the passivation gas is preferably 10-500 sccm, and the pressure of the plasma is preferably 1 ⁇ 50 Torr, preferably the temperature of the gas passivation treatment is 20-300°C, and the preferably time of the gas passivation treatment is 10 ⁇ 500s.
  • a plasma formed by a passivation gas preferably the power of the plasma is 10-200W, the flow rate of the passivation gas is preferably 10-500 sccm, and the pressure of the plasma is preferably 1 ⁇ 50 Torr, preferably the temperature of the gas passivation treatment is 20-300°C, and the preferably time of the gas passivation treatment is 10 ⁇ 500s.
  • the preparation method further includes the following step: forming an encapsulation layer covering the tunnel junction and the first mask layer on the bottom electrode.
  • an insulating dielectric material is deposited on the bottom electrode to form an encapsulation layer, preferably the insulating dielectric material is selected from any one of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide
  • the insulating dielectric material is selected from any one of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide
  • One or more, preferably chemical vapor deposition or atomic layer deposition is used to form the encapsulation layer.
  • the thickness of the encapsulation layer is 5-50 nm.
  • the preparation method further includes the step of performing gas passivation treatment on the surface of the insulating dielectric material.
  • a method for manufacturing an MRAM including the step of forming at least one storage bit, wherein the storage bit is formed by using the above-mentioned preparation method.
  • a method for preparing a storage bit which includes the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method performs gas passivation treatment on the sidewall of the magnetic tunnel junction , to reduce dangling keys on the sidewall surface.
  • the present disclosure can not only reduce the dangling bonds on the sidewall surface, but also remove the surface impurities and fill the vacancies in the surface layer and the surface through the above-mentioned gas passivation treatment, thereby reducing the defect density, improving the device stability and alleviating the etching damage
  • the influence on TMR and other performance parameters can reduce the TMR loss rate, TMR discrete value, and critical voltage discrete value of the device array, and improve the critical magnetic field.
  • FIG. 1 shows that in the method for preparing a storage bit provided by the embodiment of the present application, a tunnel junction material, a first mask layer material, a second mask material layer and a patterned photoresist are sequentially formed on the bottom electrode Schematic diagram of the cross-sectional structure of the rear substrate;
  • FIG. 2 shows a schematic cross-sectional structure diagram of the substrate after the second mask material layer and the first mask material layer shown in FIG. 1 are sequentially formed into the second mask layer and the first mask layer;
  • FIG. 3 shows a schematic diagram of the cross-sectional structure of the substrate after etching the tunnel junction material layer with the first mask layer and the second mask layer shown in FIG. 2 as masks;
  • FIG. 4 shows a schematic cross-sectional structure diagram of the substrate after gas passivation treatment is performed on the sidewall of the magnetic tunnel junction shown in FIG. 3;
  • FIG. 5 shows a schematic cross-sectional structure diagram of the substrate after forming the encapsulation layer covering the tunnel junction and the first mask layer shown in FIG. 4 .
  • 100 insulating medium layer; 10, connecting metal layer; 20, bottom electrode; 30, magnetic tunnel junction; 301, tunnel junction material layer; 310, reference layer; 311, reference material layer; 320, barrier layer; 321, potential barrier material layer; 330, free layer; 331, free material layer; 40, first mask layer; 410, first mask material layer; 50, second mask layer; 510, second mask material layer; 60 , photoresist; 70, encapsulation layer.
  • the preparation process of the storage bit in the prior art easily leads to the magnetic damage of the device.
  • the applicant of the present disclosure provides a method for preparing a storage bit cell, which includes the step of forming a magnetic tunnel junction, and after the step of forming the magnetic tunnel junction, the preparation method further includes the following steps:
  • the sidewalls of the junction are gas passivated to reduce dangling bonds on the sidewall surfaces.
  • the present disclosure can not only reduce the dangling bonds on the sidewall surface, but also remove the surface impurities and fill the vacancies in the surface layer and the surface through the above-mentioned gas passivation treatment, thereby reducing the defect density, improving the device stability and alleviating the etching damage
  • the influence on TMR and other performance parameters can reduce the TMR loss rate, TMR discrete value, and critical voltage discrete value of the device array, and improve the critical magnetic field.
  • FIGS. 1 to 5 Exemplary embodiments of the method for fabricating storage bits provided according to the present disclosure will be described in more detail below with reference to FIGS. 1 to 5 . These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
  • the step of forming the magnetic tunnel junction 30 may include: sequentially forming a tunnel junction material layer 301 and a first mask material layer 410 on the bottom electrode 20 , and the bottom electrode 20 may be formed on the surface of the connection metal layer 10 in the insulating medium layer 100 , as shown in FIG. 1; the first mask material layer 410 is patterned to form the first mask layer 40, as shown in FIG. 2 and FIG. 3; Etching to form the magnetic tunnel junction 30, as shown in FIG.
  • the etching stays on the surface of the bottom electrode 20 or below the surface of the bottom electrode 20, so as to achieve complete conductive separation between the storage bits, the magnetic tunnel junction 30 can be etched
  • the first mask layer 40 after the etching process serves as the top electrode of the storage bit cell.
  • the thickness of the magnetic tunnel junction 30 can be 5-50 nm, and those skilled in the art can reasonably select the materials of each layer in the tunnel junction material layer 301 according to the type of the magnetic tunnel junction 30 (MTJ) actually required.
  • the above-mentioned magnetic tunnel junction 30 can have various forms according to the application, including but not limited to in-plane MTJ, vertical MTJ, top-pinned MTJ, bottom-pinned MTJ, double-layer MgO MTJ, single-layer MgO MTJ and multi-state MTJ.
  • a reference material layer 311 , a barrier material layer 321 and a free material layer 331 are sequentially deposited on the bottom electrode 20 , and a magnetic tunnel including the reference layer 310 , the barrier layer 320 and the free layer 330 is obtained after etching junction 30, as shown in FIGS. 1-3.
  • the barrier layer 320 in the magnetic tunnel junction 30 can also be the first barrier layer, and a second barrier layer, a pinning layer, a capping layer can be added.
  • the material for forming the reference layer 310 may include magnetic metals such as cobalt iron boron, and the material for forming the barrier layer 320 may be a dielectric material such as magnesium oxide or aluminum oxide.
  • the steps of forming the above-mentioned first mask layer 40 and the above-mentioned second mask layer 50 include: depositing and forming a second mask material layer 510 on the first mask material layer 410, and forming a second mask material layer 510 on the first mask material layer 410
  • the photoresist 60 is covered on the second mask material layer 510, and the photoresist 60 is patterned by photolithography and developing processes, as shown in FIG. layer 510 and etching the first masking material layer 410 to transfer the pattern of the patterned photoresist 60 to obtain the second masking layer 50 and the first masking layer 40 , as shown in FIG. 2 .
  • the above-mentioned first mask layer 40 material can be Ta, TaN, TiN and other materials
  • the above-mentioned mask material can be SiO x , SiN x and other materials
  • those skilled in the art can also reasonably set the process conditions of the above-mentioned lithography process according to the prior art, which will not be repeated here.
  • Ion beam etching is performed on the tunnel junction material layer 301 to form the above-mentioned magnetic tunnel junction 30 , as shown in FIG. 3 .
  • Ion beam etching uses argon or other inert gas plasma, which is accelerated by an electric field and incident on the surface of the structure to perform physical etching of the tunnel junction.
  • IBE ion beam etching process
  • RIE reactive ion etching
  • the above-mentioned ion beam etching is carried out using an inert gas. Due to the high cost of xenon gas, argon gas or krypton gas is preferably used as the main gas. Add a certain amount of neon gas. More preferably, the acceleration voltage of the ion beam etching is 50-1600V, and the energy of the ion beam etching is 50-1600eV.
  • reactive ion etching can also be performed on the above-mentioned tunnel junction material layer 301, and the plasma source of the above-mentioned reactive ion etching can be selected from any one of capacitive coupling source, inductive coupling source and electron cyclotron resonance source. A sort of.
  • the reactive gas of the above-mentioned reactive ion etching is a fluorine-based gas and/or a chlorine-based gas; and, preferably, the above-mentioned reactive gas
  • the pressure is 1 ⁇ 50mTorr.
  • a gas passivation process is performed on the sidewall of the magnetic tunnel junction 30 to reduce dangling bonds on the sidewall surface.
  • the above-mentioned gas passivation treatment can not only reduce the dangling bonds on the sidewall surface, but also remove surface impurities and fill the vacancies inside and on the surface layer, thereby reducing defect density, improving device stability, and alleviating the effect of magnetic damage on TMR and other performance parameters. Influence.
  • a passivation gas including passivation gas is used to perform gas passivation treatment on the magnetic tunnel junction 30, in order to improve the treatment of surface defects and dangling bonds Effect, preferably, the above-mentioned passivation gas is selected from any one or more of hydrogen, deuterium, ammonia and deuterated ammonia.
  • the above-mentioned passivation gas can also include a carrier gas.
  • a carrier gas preferably, any one of the above-mentioned carrier gases helium, neon, argon, xenon and nitrogen is used. one or more; preferably, the above-mentioned passivation gas accounts for 1-100% of the molar concentration of the above-mentioned carrier gas.
  • the magnetic tunnel junction 30 is gas passivated by using the plasma formed by the above passivation gas; more preferably , the power of the above-mentioned plasma is 10-200W, the flow rate of the passivation gas is 10-500sccm, the pressure is 1-50Tor, the temperature of the gas passivation treatment is 20-300°C, and the time is 10-500s.
  • the above-mentioned preparation method of the present disclosure may further include the following steps: at the bottom An encapsulation layer 70 covering the magnetic tunnel junction 30 and the first mask layer 40 is formed on the electrode 20 , as shown in FIG. 5 .
  • the encapsulation layer 70 is used to protect the first mask layer 40 and the magnetic tunnel junction 30 in subsequent processes.
  • the encapsulation layer 70 may have a thickness of 5 to 50 nm. When the deposition thickness is less than 50 nm, during the deposition of the insulating dielectric material, or during the deposition
  • the above-mentioned preparation method of the present disclosure further includes the step of performing gas passivation treatment on the surface of the insulating medium material.
  • the above passivation treatment can reduce the roughness, defect density and the number of interface dangling bonds of the encapsulation layer 70, thereby reducing the leakage current of the device.
  • the above-mentioned encapsulation layer 70 is non-conductive and non-magnetic, preferably, the above-mentioned insulating dielectric material is selected from any one or more of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide, However, it is not limited to the above-mentioned preferred types, and those skilled in the art can reasonably select the specific types according to the prior art. Those skilled in the art can also reasonably select the process of depositing and forming the encapsulation layer 70 according to the prior art, for example, chemical vapor deposition or atomic layer deposition to form the encapsulation layer.
  • a method for manufacturing an MRAM including the step of forming at least one storage bit, where the storage bit is formed by the above-mentioned preparation method.
  • a second mask material layer 510 is deposited on the first mask material layer 410, and the photoresist 60 is covered on the second mask material layer 510.
  • the photoresist 60 is used as a mask to etch the second mask material layer 510 to obtain a second mask layer 50 having a pattern consistent with the photoresist 60, as shown in FIG. 1 and FIG. 2;
  • the mask layer 50 etches the first mask material layer 410 to transfer the pattern of the patterned photoresist 60 to obtain the first mask layer 40;
  • the tunnel junction material layer 301 is etched through the first mask layer 40 to form the magnetic tunnel junction 30, including the reference layer 310, the barrier layer 320 and the free layer 330, and the etching stays at the bottom electrode 20 and below the bottom electrode 20 , so as to achieve complete conductive separation between storage bits;
  • the surface of the magnetic tunnel junction 30 is subjected to gas passivation treatment by using the plasma formed by the passivation gas.
  • the passivation gas hydrogen is used as the passivation gas, and argon is used as the carrier gas. 8.5Torr, power 75W, temperature 200°C, processing time 180s.
  • Plasma-enhanced chemical vapor deposition is used to deposit silicon nitride on the bottom electrode 20 to form an encapsulation layer 70 covering the magnetic tunnel junction 30 and the first mask layer 40.
  • the reactive gases are silane and ammonia, and nitrogen and argon are used as carriers. gas.
  • the gas pressure was 8.5 Torr
  • the power was 75 W
  • the temperature was 200 °C
  • the time was 25 s.
  • the flow rate of hydrogen gas was 10 sccm
  • the flow rate of argon gas was 5000 sccm
  • the pressure was 1 Torr
  • the power was 10 W
  • the temperature was 20 °C
  • the processing time was 500 s.
  • Ammonia gas was used as passivation gas, argon gas was used as carrier gas, the flow rate of ammonia gas was 500 sccm, the flow rate of argon gas was 5000 sccm, the pressure was 50 Torr, the power was 200 W, the temperature was 300 °C, and the processing time was 10 s.
  • a gas passivation step is introduced: the encapsulation layer is silicon nitride, the reaction device is plasma enhanced chemical vapor deposition, the reaction gases are silane, ammonia, and nitrogen and argon are used as carrier gases.
  • the pressure was 8.5 Torr, the power was 75W, the temperature was 200°C, and the time was 5s; then the deposited silicon nitride was subjected to gas passivation treatment, using hydrogen as the passivation gas, argon as the carrier gas, the flow rate of hydrogen was 100sccm, and the argon gas was used as the carrier gas.
  • the flow rate was 5000sccm, the pressure was 8.5 Torr, the power was 75W, the temperature was 200°C, and the treatment time was 30s. After the gas passivation treatment, the silicon nitride was continued to grow under the same process conditions for 20s.
  • the surface of the magnetic tunnel junction 30 is not subjected to gas passivation treatment, and the encapsulation layer 70 covering the magnetic tunnel junction 30 and the first mask layer 40 is directly formed.
  • the storage bits in the above-mentioned embodiments 1 to 4 are prepared into MTJ devices, and then the above-mentioned embodiments 1 to 4 and comparative example 1 are used.
  • the performances such as TMR impairment rate of MTJ devices are tested, and the test results are shown in the following table.
  • the gas passivation treatment on the sidewall of the magnetic tunnel junction can effectively reduce the TMR impairment rate, TMR dispersion value, critical magnetic field and critical voltage dispersion value of the MTJ device.
  • the above-mentioned gas passivation treatment can not only reduce the dangling bonds on the sidewall surface, but also remove the surface impurities and fill the vacancies in the surface layer and the surface, thereby reducing the defect density, improving the stability of the device, and alleviating the magnetic field.
  • the impact of damage on TMR and other performance parameters can reduce the TMR impairment rate, TMR discrete value, and critical voltage discrete value of the device array, and improve the critical magnetic field;
  • the encapsulation layer By covering the encapsulation layer on the tunnel junction and the first mask layer (top electrode), when a voltage is applied across the tunnel junction, the encapsulation layer bears most of the partial voltage, resulting in a strong local electric field;
  • the gas passivation treatment of the encapsulation layer material can reduce the roughness of the encapsulation layer, the defect density and the number of interface dangling bonds, thereby reducing the leakage current of the device.

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Abstract

本公开提供了一种存储位元的制备方法及MRAM的制备方法。该制备方法包括形成磁隧道结的步骤，在形成磁隧道结的步骤之后，制备方法还包括以下步骤：对磁隧道结的侧壁进行气体钝化处理，以减少侧壁表面的悬挂键。本公开通过上述气体钝化处理，不仅能够减少侧壁表面的悬挂键，还能够去除表面杂质，并填充表层内部、表面的空位，从而降低缺陷密度，提高了器件稳定性，缓解了刻蚀损伤对TMR等性能参数的影响，能够降低器件阵列的TMR减损率、TMR离散值、临界电压离散值，提高临界磁场。

Description

存储位元的制备方法及MRAM的制备方法
本公开以2020年07月29日递交的、申请号为202010747304.X且名称为“存储位元的制备方法及MRAM的制备方法”的专利文件为优先权文件，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体存储芯片制造领域，具体而言，涉及一种存储位元的制备方法及MRAM的制备方法。
背景技术
存储芯片是计算机的重要组成部分，影响着整个计算机的速度、集成和功耗。在目前的计算机内部，存储器分为两部分，硬盘和缓存。硬盘容量大、断电数据不丢失，但速度慢。即使是较先进的固态硬盘NAND Flash也不能避免。缓存速度快，如DRAM和SRAM，但容量小、断电数据丢失。随着芯片特征尺寸的逐渐缩小，NAND、DRAM和SRAM面临功耗大、面积大等一系列难以克服的困难。
MRAM是目前最有潜力的下一代存储芯片。它汇集了DRAM的高集成特性、SRAM的高速特性，还拥有Flash的非易失性，理论上具有无限次数读写能力，具备功耗低的特点，有望成为下一代“通用存储器”。目前，世界上领先的半导体公司都开始了MRAM的试制或量产。
隧道结刻蚀是MRAM制造当中的两大难题之一。隧道结是MRAM的核心器件层，由十几种金属，堆叠成几十层的膜结构，最薄的一层厚度只有几个埃米。它是数据保存的载体。隧道结刻蚀的任务是将连续的隧道结薄膜刻蚀成为分立的位元。隧道结刻蚀中有两大困难：短路和损伤。刻蚀残渣容易附着在位元侧壁，造成器件短路。其次，刻蚀过程中的反应物，会对器件表层物质造成损伤，从而使器件性能降低；反应离子刻蚀中的卤素气体会不断渗入器件内部，造成位元的磁性受到破坏。离子束刻蚀则会破坏位元表面的晶格结构，在表面形成损伤层，同样会造成磁性损伤。这些破坏不能完全消除，只能逐步控制、降低。
为了解决短路问题，人们普遍采取的措施是增大刻蚀剂量。这样进一步导致了磁损伤现象的加剧。一般情况下，磁损伤带来的TMR减损率达到20～30％。
隧道结刻蚀带来的磁损伤严重制约着MRAM的良率，限制了其进一步发展。
发明内容
本公开的主要目的在于提供一种存储位元的制备方法及MRAM的制备方法，以解决现有技术中隧道结刻蚀带来的磁损伤严重的问题。
为了实现上述目的，根据本公开的一个方面，提供了一种存储位元的制备方法，包括形成磁隧道结的步骤，在形成磁隧道结的步骤之后，制备方法还包括以下步骤：对磁隧道结的侧壁进行气体钝化处理，以减少侧壁表面的悬挂键。
可选地，形成隧道结的步骤包括：在底电极上顺序形成隧道结材料层和第一掩膜材料层；将第一掩膜材料层图形化，以形成第一掩膜层；通过第一掩膜层对隧道结材料层进行刻蚀，以形成磁隧道结。
可选地，对隧道结材料层进行离子束刻蚀，以形成磁隧道结，优选采用惰性气体进行离子束刻蚀。
可选地，对隧道结材料层进行反应离子刻蚀，以形成磁隧道结，优选反应离子刻蚀的等离子体源选自电容耦合源、电感耦合源和电子回旋共振源中的任一种，优选反应离子刻蚀的反应气体为氟基气体和/或氯基气体。
可选地，采用包括钝化气体的钝化用气体对磁隧道结进行气体钝化处理，优选钝化气体选自氢气、氘气、氨气和氘化氨中的任一种或多种。
可选地，钝化用气体还包括载气，优选载气氦气、氖气、氩气、氙气和氮气中的任一种或多种。
可选地，采用钝化气体形成的等离子体对磁隧道结进行气体钝化处理，优选等离子体的功率为10～200W，优选钝化气体的流量为10～500sccm，优选等离子体的压强为1～50Torr，优选气体钝化处理的温度为20～300℃，优选气体钝化处理的时间为10～500s。
可选地，在对磁隧道结进行气体钝化处理的步骤之后，制备方法还包括以下步骤：在底电极上形成覆盖隧道结和第一掩膜层的封装层。
可选地，在底电极上沉积绝缘介质材料，以形成封装层，优选绝缘介质材料选自氧化硅、氮化硅、氮化碳、碳氮化硅、氮氧化硅和氧化铝中的任一种或多种，优选采用化学气相沉积或原子层沉积形成封装层。
可选地，封装层的厚度为5～50nm，优选在沉积绝缘介质材料的过程中，或在沉积绝缘介质材料之后，制备方法还包括对绝缘介质材料表面进行气体钝化处理的步骤。
根据本公开的另一方面，提供了一种MRAM的制备方法，包括形成至少一个存储位元的步骤，其特征在于，采用上述的制备方法形成存储位元。
应用本公开的技术方案，提供了一种存储位元的制备方法，包括形成磁隧道结的步骤，在形成磁隧道结的步骤之后，该制备方法对磁隧道结的侧壁进行气体钝化处理，以减少侧壁表面的悬挂键。无论采取何种刻蚀方式，刻蚀时都会有大量的高能粒子辐照隧道结，导致刻蚀完的隧道结不仅表面凹凸不平、比表面积较大，而且表层晶格混乱，位错、杂质、空位密度较高，表面区域的磁各向异性表现不强，容易发生多畴反转，影响器件性能、稳定性。本公开通过上述气体钝化处理，不仅能够减少侧壁表面的悬挂键，还能够去除表面杂质，并填 充表层内部、表面的空位，从而降低缺陷密度，提高了器件稳定性，缓解了刻蚀损伤对TMR等性能参数的影响，能够降低器件阵列的TMR减损率、TMR离散值、临界电压离散值，提高临界磁场。
附图说明
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1示出了在本申请实施方式所提供的存储位元的制备方法中，在底电极上顺序形成隧道结材料、第一掩膜层材料、第二掩膜材料层和图形化光刻胶后的基体剖面结构示意图；
图2示出了将图1所示的第二掩膜材料层和第一掩膜材料层顺序形成第二掩膜层和第一掩膜层后的基体剖面结构示意图；
图3示出了以图2所示的第一掩膜层和第二掩膜层为掩膜对隧道结材料层进行刻蚀后的基体剖面结构示意图；
图4示出了对图3所示的磁隧道结的侧壁进行气体钝化处理后的基体剖面结构示意图；
图5示出了形成覆盖图4所示的隧道结和第一掩膜层的封装层后的基体剖面结构示意图。
其中，上述附图包括以下附图标记：
100、绝缘介质层；10、连接金属层；20、底电极；30、磁隧道结；301、隧道结材料层；310、参考层；311、参考材料层；320、势垒层；321、势垒材料层；330、自由层；331、自由材料层；40、第一掩膜层；410、第一掩膜材料层；50、第二掩膜层；510、第二掩膜材料层；60、光刻胶；70、封装层。
具体实施方式
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
为了使本技术领域的人员更好地理解本公开方案，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分的实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本公开保护的范围。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、 方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
正如背景技术中所介绍的，现有技术中存储位元的制备工艺易导致器件磁性破坏。本公开的申请人为了解决上述技术问题，提供了一种存储位元的制备方法，包括形成磁隧道结的步骤，在形成磁隧道结的步骤之后，制备方法还包括以下步骤：对上述磁隧道结的侧壁进行气体钝化处理，以减少其侧壁表面的悬挂键。
无论采取何种刻蚀方式，刻蚀时都会有大量的高能粒子辐照隧道结，导致刻蚀完的隧道结不仅表面凹凸不平、比表面积较大，而且表层晶格混乱，位错、杂质、空位密度较高，表面区域的磁各向异性表现不强，容易发生多畴反转，影响器件性能、稳定性。本公开通过上述气体钝化处理，不仅能够减少侧壁表面的悬挂键，还能够去除表面杂质，并填充表层内部、表面的空位，从而降低缺陷密度，提高了器件稳定性，缓解了刻蚀损伤对TMR等性能参数的影响，能够降低器件阵列的TMR减损率、TMR离散值、临界电压离散值，提高临界磁场。
下面将结合附图1至图5更详细地描述根据本公开提供的存储位元的制备方法的示例性实施方式。然而，这些示例性实施方式可以由多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的实施方式。应当理解的是，提供这些实施方式是为了使得本申请的公开彻底且完整，并且将这些示例性实施方式的构思充分传达给本领域普通技术人员。
首先，形成磁隧道结30。形成该磁隧道结30的步骤可以包括：在底电极20上顺序形成隧道结材料层301和第一掩膜材料层410，上述底电极20可以形成于绝缘介质层100中的连接金属层10表面，如图1所示；将第一掩膜材料层410图形化，以形成第一掩膜层40，如图2和图3所示；通过第一掩膜层40对隧道结材料层301进行刻蚀，以形成磁隧道结30，如图4所示，刻蚀停留在底电极20表面或底电极20表面以下，以使存储位元间实现完全的导电分离，可以将磁隧道结30刻蚀工艺后的第一掩膜层40作为存储位元的顶电极。
上述磁隧道结30的厚度可以为5～50nm，本领域技术人员可以根据实际所需的磁隧道结30(MTJ)的种类对上述隧道结材料层301中各层的材料进行合理选取。上述磁隧道结30根据应用情况可以有多种形式，包括但不限于面内MTJ，垂直MTJ，顶部钉扎MTJ，底部钉扎MTJ，双层MgO MTJ，单层MgO MTJ以及多态MTJ。
在一个实施例中，在底电极20上顺序沉积参考材料层311、势垒材料层321和自由材料层331，在刻蚀后得到包括参考层310、势垒层320和自由层330的磁隧道结30，如图1至图3所示。
在上述实施例中，通过自由层330自旋方向来存储数据，还可以使磁隧道结30中的势垒层320为第一势垒层，并加入第二势垒层、钉扎层、覆盖层和缓冲层等，形成参考层310的材料可以包含钴铁硼等磁性金属，形成势垒层320的材料可以为氧化镁或氧化铝等介质材料。
在一种优选的实施方式中，形成上述第一掩膜层40和上述第二掩膜层50的步骤包括：在第一掩膜材料层410上沉积形成第二掩膜材料层510，并在第二掩膜材料层510上覆盖光刻 胶60，通过光刻、显影工艺将光刻胶60图形化，如图1所示，然后以光刻胶60为掩膜顺序对第二掩膜材料层510和对第一掩膜材料层410进行刻蚀，以将图形化光刻胶60的图案转移得到第二掩膜层50和第一掩膜层40，如图2所示。
在上述优选的实施方式中，本领域技术人员可以根据现有技术对上述第一掩膜层40材料和掩膜材料进行合理选取，如上述第一掩膜层40材料可以为Ta、TaN、TiN等材料，上述掩膜材料可以为SiO x，SiN x等材料；本领域技术人员也可以根据现有技术对上述光刻工艺的工艺条件进行合理设定，在此不再赘述。
优选地，对隧道结材料层301进行离子束刻蚀，以形成上述磁隧道结30，如图3所示。离子束刻蚀使用氩气或其他惰性气体的等离子体，经过电场加速后，入射到结构表面，进行隧道结的物理刻蚀。采用离子束刻蚀工艺(IBE)能够避免现有技术中采用反应离子刻蚀工艺(RIE)由于化学腐蚀而导致的对磁隧道结30(MTJ)电磁性能的破坏。
为了避免上述IBE刻蚀对磁隧道结30侧壁的表面磁性层的破坏，采用惰性气体进行上述离子束刻蚀，由于氙气成本较高，优选以氩气或是氪气为主，可选地掺入一定量的氖气。更为优选地，该离子束刻蚀的加速电压为50～1600V，该离子束刻蚀的能量为50～1600eV。
为了形成上述磁隧道结30，还可以对上述隧道结材料层301进行反应离子刻蚀，上述反应离子刻蚀的等离子体源可以选自电容耦合源、电感耦合源和电子回旋共振源中的任一种。为了避免上述IBE刻蚀对磁隧道结30侧壁的表面磁性层的破坏，优选地，上述反应离子刻蚀的反应气体为氟基气体和/或氯基气体；并且，优选地，上述反应气体的压强为1～50mTorr。
在形成上述磁隧道结30的步骤之后，对上述磁隧道结30的侧壁进行气体钝化处理，以减少侧壁表面的悬挂键。上述气体钝化处理不仅能够减少侧壁表面的悬挂键，还能够去除表面杂质，并填充表层内部、表面的空位，从而降低缺陷密度，提高了器件稳定性，缓解磁损伤对TMR等性能参数的影响。
在上述对磁隧道结30的侧壁进行气体钝化处理的过程中，采用包括钝化气体的钝化用气体对磁隧道结30进行气体钝化处理，为了提高对表面缺陷和悬挂键的处理效果，优选地，上述钝化气体选自氢气、氘气、氨气和氘化氨中的任一种或多种。
上述钝化用气体还可以包括载气，为了避免载气与磁隧道结30发生反应所带来的影响，优选地，上述载气氦气、氖气、氩气、氙气和氮气中的任一种或多种；优选地，上述钝化气体占上述载气摩尔浓度的1～100％。
为了提高消除磁隧道结30表面的缺陷和悬挂键的工艺效率，在一种优选的实施方式中，采用上述钝化气体形成的等离子体对磁隧道结30进行气体钝化处理；更为优选地，上述等离子体的功率为10～200W，钝化气体的流量为10～500sccm，压强为1～50Tor，气体钝化处理的温度为20～300℃，时间为10～500s。
在对所示磁隧道结30的侧壁进行气体钝化处理的步骤之后，将上述第一掩膜层40作为存储位元的顶电极，本公开的上述制备方法还可以包括以下步骤：在底电极20上形成覆盖磁 隧道结30和第一掩膜层40的封装层70，如图5所示。该封装层70用于在后续工艺中起到对第一掩膜层40和磁隧道结30的保护作用。
在底电极20上沉积绝缘介质材料，以形成上述封装层70，上述封装层70的厚度可以为5～50nm，当在沉积厚度小于50nm时，在沉积上述绝缘介质材料的过程中，或在沉积上述绝缘介质材料之后，优选地，本公开的上述制备方法还包括对绝缘介质材料表面进行气体钝化处理的步骤。上述钝化处理可以使得封装层70粗糙度、缺陷密度和界面悬挂键数量减小，从而降低器件的漏电流。
上述封装层70不导电且无磁性，优选地，上述绝缘介质材料选自氧化硅、氮化硅、氮化碳、碳氮化硅、氮氧化硅和氧化铝中的任一种或多种，但并不局限于上述优选的种类，本领域技术人员可以根据现有技术对其具体种类进行合理选取。本领域技术人员也可以根据现有技术对沉积形成上述封装层70的工艺进行合理选取，例如采用化学气相沉积或原子层沉积形成封装层。
根据本公开的另一方面，还提供了一种MRAM的制备方法，包括形成至少一个存储位元的步骤，该存储位元采用上述的制备方法形成。
下面将结合实施例进一步说明本公开提供的上述存储位元的制备方法。
实施例1
本实施例提供的存储位元的制备方法包括以下步骤：
在第一掩膜材料层410上沉积形成第二掩膜材料层510，并在第二掩膜材料层510上覆盖光刻胶60，通过光刻、显影工艺将光刻胶60图形化，以光刻胶60为掩膜对第二掩膜材料层510进行刻蚀，以得到图案与光刻胶60一致的第二掩膜层50，如图1和图2所示；然后通过该第二掩膜层50对第一掩膜材料层410进行刻蚀，以将图形化光刻胶60的图案转移得到第一掩膜层40；
通过第一掩膜层40对隧道结材料层301进行刻蚀，以形成磁隧道结30，包括参考层310、势垒层320和自由层330，刻蚀停留在底电极20及底电极20以下，以使存储位元间实现完全的导电分离；
采用钝化用气体形成的等离子体对磁隧道结30表面进行气体钝化处理，钝化用气体中氢气作为钝化气体、氩气作为载气，氢气流量为100sccm，氩气流量为5000sccm，气压8.5Torr，功率75W，温度200℃，处理时间为180s。
采用等离子体增强化学气相沉积在底电极20上沉积氮化硅，以形成覆盖磁隧道结30和第一掩膜层40的封装层70，反应气体为硅烷、氨气，氮气、氩气作为载气。沉积时气压8.5Torr，功率75W，温度200℃，时间为25s。
实施例2
本实施例提供的存储位元的制备方法与实施例1的区别在于：
氢气流量为10sccm，氩气流量为5000sccm，气压1Torr，功率10W，温度20℃，处理时间500s。
实施例3
本实施例提供的存储位元的制备方法与实施例1的区别在于：
采用氨气作为钝化气体，氩气作为载气，氨气流量为500sccm，氩气流量为5000sccm，气压50Torr，功率200W，温度300℃，处理时间为10s。
实施例4
本实施例提供的存储位元的制备方法与实施例1的区别在于：
在沉积封装层步骤中引入气体钝化步骤：封装层为氮化硅，反应装置为等离子体增强化学气相沉积，反应气体为硅烷、氨气，氮气、氩气作为载气。沉积时气压8.5Torr，功率75W，温度200℃，时间为5s；然后对沉积的氮化硅进行气体钝化处理，采用氢气作为钝化气体，氩气作为载气，氢气流量为100sccm，氩气流量为5000sccm，气压8.5Torr，功率75W，温度200℃，处理时间为30s；气体钝化处理结束后，再以相同工艺条件继续生长氮化硅，时间为20s。
对比例1
本对比例提供的存储位元的制备方法与实施例1的区别在于：
在形成磁隧道结30之后，不对磁隧道结30表面进行气体钝化处理，直接形成覆盖磁隧道结30和第一掩膜层40的封装层70。
结合现有技术中常规的半导体制造相关工艺如光刻、刻蚀等技术将上述实施例1～4中的存储位元制备成MTJ器件，然后对采用上述实施例1～4以及对比例1中MTJ器件的TMR减损率等性能进行测试，测试结果如下表所示。
表1
Figure PCTCN2020121946-appb-000001
从上述测试结果可以看出，通过对磁隧道结的侧壁进行气体钝化处理，能够有效地降低MTJ器件的TMR减损率、TMR离散值、临界磁场以及临界电压离散值。
从以上的描述中，可以看出，本公开上述的实施例实现了如下技术效果：
1、通过上述气体钝化处理，不仅能够减少侧壁表面的悬挂键，还能够去除表面杂质，并填充表层内部、表面的空位，从而降低了缺陷密度，提高了器件稳定性，还缓解了磁损伤对TMR等性能参数的影响，能够降低器件阵列的TMR减损率、TMR离散值、临界电压离散值，提高临界磁场；
2、通过在隧道结和第一掩膜层(顶电极)上覆盖封装层，隧道结两端施加电压时，封装层承担了大部分分压，产生很强的局部电场；
3、对封装层材料的气体钝化处理可以使得封装层粗糙度、缺陷密度和界面悬挂键数量减小，从而降低器件漏电流。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (11)

  1. 一种存储位元的制备方法，包括形成磁隧道结的步骤，其特征在于，在形成所述磁隧道结的步骤之后，所述制备方法还包括以下步骤：
    对所述磁隧道结的侧壁进行气体钝化处理，以减少所述侧壁表面的悬挂键。
  2. 根据权利要求1所述的制备方法，其特征在于，形成所述隧道结的步骤包括：
    在底电极上顺序形成隧道结材料层和第一掩膜材料层；
    将所述第一掩膜材料层图形化，以形成第一掩膜层；
    通过所述第一掩膜层对所述隧道结材料层进行刻蚀，以形成所述磁隧道结。
  3. 根据权利要求2所述的制备方法，其特征在于，对所述隧道结材料层进行离子束刻蚀，以形成所述磁隧道结，优选采用惰性气体进行所述离子束刻蚀。
  4. 根据权利要求2所述的制备方法，其特征在于，对所述隧道结材料层进行反应离子刻蚀，以形成所述磁隧道结，优选所述反应离子刻蚀的等离子体源选自电容耦合源、电感耦合源和电子回旋共振源中的任一种，优选所述反应离子刻蚀的反应气体为氟基气体和/或氯基气体。
  5. 根据权利要求1所述的制备方法，其特征在于，采用包括钝化气体的钝化用气体对所述磁隧道结进行气体钝化处理，优选所述钝化气体选自氢气、氘气、氨气和氘化氨中的任一种或多种。
  6. 根据权利要求5所述的制备方法，其特征在于，所述钝化用气体还包括载气，优选所述载气氦气、氖气、氩气、氙气和氮气中的任一种或多种。
  7. 根据权利要求5所述的制备方法，其特征在于，采用所述钝化气体形成的等离子体对所述磁隧道结进行气体钝化处理，优选所述等离子体的功率为10～200W，优选所述钝化气体的流量为10～500sccm，优选所述等离子体的压强为1～50Torr，优选所述气体钝化处理的温度为20～300℃，优选所述气体钝化处理的时间为10～500s。
  8. 根据权利要求2所述的制备方法，其特征在于，在对所述磁隧道结进行气体钝化处理的步骤之后，所述制备方法还包括以下步骤：
    在所述底电极上形成覆盖所述隧道结和所述第一掩膜层的封装层。
  9. 根据权利要求8所述的制备方法，其特征在于，在所述底电极上沉积绝缘介质材料，以形成所述封装层，优选所述绝缘介质材料选自氧化硅、氮化硅、氮化碳、碳氮化硅、氮氧化硅和氧化铝中的任一种或多种，优选采用化学气相沉积或原子层沉积形成所述封装层。
  10. 根据权利要求9所述的制备方法，其特征在于，所述封装层的厚度为5～50nm，优选在沉积所述绝缘介质材料的过程中，或在沉积所述绝缘介质材料之后，所述制备方法还包括对绝缘介质材料表面进行气体钝化处理的步骤。
  11. 一种MRAM的制备方法，包括形成至少一个存储位元的步骤，其特征在于，采用权利要求1至10中任一项所述的制备方法形成所述存储位元。
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