WO2023193738A1 - 一种磁存储器的制造方法 - Google Patents

一种磁存储器的制造方法 Download PDF

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Publication number
WO2023193738A1
WO2023193738A1 PCT/CN2023/086439 CN2023086439W WO2023193738A1 WO 2023193738 A1 WO2023193738 A1 WO 2023193738A1 CN 2023086439 W CN2023086439 W CN 2023086439W WO 2023193738 A1 WO2023193738 A1 WO 2023193738A1
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layer
etching
protective layer
sidewalls
manufacturing
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PCT/CN2023/086439
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English (en)
French (fr)
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郑枝源
彭泰彦
杨宇新
许开东
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江苏鲁汶仪器股份有限公司
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Publication of WO2023193738A1 publication Critical patent/WO2023193738A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices

Definitions

  • the present application relates to the field of semiconductors, and in particular to a method of manufacturing a magnetic memory.
  • Random Access Memory includes dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random-Access Memory, SRAM), flash memory (Flash Memory) and magnetic memory (Magnetic Random Access Memory, MRAM).
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • flash memory Flash Memory
  • MRAM Magnetic Random Access Memory
  • magnetic memory has higher read and write speeds than flash memory, as well as radiation resistance and non-volatility that SRAM and DRAM do not have. Therefore, many storage needs that currently require a combination of the three current memory types can be realized by MRAM alone.
  • embodiments of the present application provide a manufacturing method of a magnetic memory, which can improve the yield of the magnetic memory.
  • An embodiment of the present application provides a method for manufacturing a magnetic memory.
  • the method includes:
  • the MTJ stack including a free layer, an oxide layer and a fixed layer stacked in sequence;
  • the protective layer covers the sidewalls of the free layer and the fixed layer. and covering the metal layer;
  • the sidewalls of the protective layer and the oxide layer are etched to remove contaminants on the sidewalls of the oxide layer.
  • oxidizing or nitriding the sidewalls of the free layer and the fixed layer and the metal layer exposed by etching to obtain a protective layer includes:
  • Oxidizing gas, nitriding gas or alcohol gas is introduced to oxidize or nitride the sidewalls of the free layer and the fixed layer and the metal layer exposed by etching to obtain a protective layer.
  • the oxidizing gas is any one or more of O 2 , H 2 O 2 , O 3 , N 2 O, and NO
  • the nitriding gas is one or more of NH 3 , N 2 or There are many kinds
  • the alcohol gas is ethanol or methanol.
  • the gas flow rate range of the oxidizing gas, nitriding gas or alcohol gas is 10-1000 sccm.
  • the oxidizing gas, nitriding gas or alcohol gas is introduced to oxidize or nitride the sidewalls of the free layer and the fixed layer and the metal layer exposed by etching to obtain a protective layer.
  • a protective layer include:
  • ion beam etching equipment inductively coupled plasma equipment or capacitively coupled plasma equipment to introduce oxidizing gas body, nitriding gas or alcohol gas to oxidize or nitride the sidewalls of the free layer and the fixed layer and the metal layer exposed by etching to obtain a protective layer.
  • the protective layer includes a sidewall protective layer and a bottom protective layer; the sidewall protective layer is located on the sidewalls of the free layer and the fixed layer, and the bottom protective layer covers the metal layer;
  • Etching the sidewalls of the protective layer and the oxide layer to remove contaminants on the sidewalls of the oxide layer includes:
  • the etching angle is adjusted so that the etching speed of the sidewall protective layer and the oxide layer is greater than the etching speed of the bottom protective layer.
  • adjusting the etching angle so that the etching speed of the sidewall protective layer and the oxide layer is greater than the etching speed of the bottom protective layer includes:
  • the etching angle at which the longitudinal etching rate is maximum is set so that the etching speed of the sidewall protective layer and the oxide layer is greater than the etching speed of the bottom protective layer.
  • the etching angle range is -75°-75°.
  • etching the sidewalls of the protective layer and the oxide layer to remove contaminants on the sidewalls of the oxide layer includes:
  • the magnetic tunnel junction MTJ stack is also covered with a patterned mask layer;
  • the etching of the magnetic tunnel junction MTJ stack to the metal layer includes:
  • the magnetic tunnel junction MTJ stack is etched to the metal layer.
  • the protective layer covers the sidewalls and top of the mask layer.
  • the thickness of the protective layer is determined based on the contaminated thickness of the oxide layer and the thickness of the metal layer.
  • the thickness of the protective layer is smaller than the thickness of the metal layer and larger than the thickness of the contaminated oxide layer.
  • the thickness of the protective layer ranges from 0.5 to 50 nm.
  • the protective layer is an oxide layer, a nitride layer or an oxynitride layer, and the oxide layer is magnesium oxide.
  • the material of the oxide layer in the magnetic tunnel junction MTJ stack is magnesium oxide.
  • the free layer and the fixed layer are made of metal material, and the material of the metal layer is tantalum.
  • etching the magnetic tunnel junction MTJ stack to the metal layer includes:
  • the magnetic tunnel junction MTJ stack is etched to the metal layer using an ion beam etching process, an inductively coupled plasma process or a capacitively coupled plasma process.
  • the etching rate of the protective layer is lower than the etching rate of the metal layer.
  • the time range for oxidizing or nitriding the sidewalls of the free layer and the fixed layer and the metal layer exposed by etching is 5-1000 s.
  • Embodiments of the present application provide a method for manufacturing a magnetic memory.
  • the magnetic tunnel junction MTJ stack is etched to the metal layer.
  • the MTJ stack includes a free layer, an oxide layer and a fixed layer stacked in sequence.
  • the free layer and the fixed layer are The sidewalls and the metal layer exposed by etching are oxidized or nitrided to obtain a protective layer.
  • the protective layer covers the sidewalls of the free layer and the fixed layer and the covering layer. Cover the metal layer, and etch the sidewalls of the protective layer and oxide layer to remove contaminants on the sidewalls of the oxide layer.
  • the protective layer when etching to remove contaminants on the sidewalls of the oxide layer, the protective layer is used to protect the sidewalls of the free layer and the fixed layer.
  • the etching residues of the free layer and the fixed layer will not adhere to the oxide layer, and at the same time, The contaminants on the side walls of the oxide layer are removed by etching, and the metal layer is covered by the protective layer.
  • the protective layer will be etched first, and the etching amount of the metal layer is low to avoid etching the contaminants on the side walls of the oxide layer. Large damage to the metal layer or even carving through the metal layer.
  • the manufacturing method of the magnetic memory provided by the embodiments of the present application can not only remove the contaminants on the side walls of the oxide layer by etching, improve the performance and yield of the device, but also prevent the metal layer from being over-etched, further improving the performance of the device. Device yield.
  • Figure 1 is a schematic diagram of the working principle of a magnetic memory based on spin-orbit torque
  • Figure 2 is a flow chart of a manufacturing method of a magnetic memory gate provided by an embodiment of the present application
  • Figures 3-5 are schematic structural diagrams of the manufacturing method of the magnetic memory provided by the embodiment of the present application.
  • Figure 6 is a schematic structural diagram of a magnetic memory provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another magnetic memory provided by an embodiment of the present application.
  • Random Access Memory includes dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random-Access Memory, SRAM), flash memory (Flash Memory) and magnetic memory (Magnetic Random Access Memory, MRAM).
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • flash memory Flash Memory
  • MRAM Magnetic Random Access Memory
  • magnetic memory has higher read and write speeds than flash memory, as well as radiation resistance and non-volatility that SRAM and DRAM do not have. Therefore, many storage needs that currently require a combination of the three current memory types can be realized by MRAM alone.
  • the memory unit of MRAM is a magnetic tunnel junction (MTJ), which is an oxide layer, such as magnesium oxide (MgO), sandwiched between two magnetic films.
  • MTJ magnetic tunnel junction
  • MgO magnesium oxide
  • the resistance (Rp) presented by the MTJ is small, the current easily passes from the fixed layer through the free layer, and the tunneling current (Ip) is relatively small.
  • the entire MTJ can be regarded as a conductive state, representing the "1" of the binary byte.
  • the entire MTJ can be regarded as a non-conducting state, representing a binary byte. "0". This is used to distinguish 0 and 1 in MTJ stored information.
  • STT-MRAM also known as the third generation MRAM
  • MRAM has the advantage of increasing the magnetization density by using the magnetic anisotropy (Interfacial magnetic anisotropy) between magnesium oxide and the magnetic film to let the magnetic moment stand up, that is, the magnetic moment perpendicular to the film surface.
  • the high density of magnetic moments helps extend data storage time and can also be used to reduce size.
  • SOT-MRAM Spin Orbit Torque
  • Figure 1 is a schematic diagram of the working principle of a magnetic memory MTJ based on spin-orbit torque SOT.
  • the read (read) current of SOT-MRAM passes vertically through the MTJ junction, but the write (write) current depends on the material adjacent to the free layer in parallel, such as the current flowing in the metal layer, driving both The torque generated by the spin-orbit interaction on the interface is used to reverse the magnetic moment of the free layer.
  • the key process nodes are: (1) The metal layers below the fixed layer between multiple MTJ junctions need to be connected to each other, and the film layer of the metal layer cannot be broken, otherwise it will affect the writing of MRAM function, resulting in reduced device yield. (2) There should be no metal contamination on the side walls of the MTJ junction to prevent the upper part of the MTJ from being connected to the lower part, that is, the fixed layer and the free layer are connected, causing the magnetic memory to malfunction.
  • the current solution to process node (1) is to optimize the program parameters during the etching process to ensure that the etching end point can stop at the metal layer and not penetrate the lower electrode below.
  • the current solution to process node (2) is to modify the sidewall through ion beam etching (Ion Beam Etching, IBE), inductive coupled plasma (Inductive Coupled Plasma, ICP) or capacitive coupled plasma (Capacitive Coupled Plasma, CCP) , to remove metal contamination on the side wall of MgO, but this method will cause the etching amount of the bottom film layer to increase, that is, the etching amount of the metal layer will increase, and it cannot stop at the expected film layer, eventually causing the metal layer to be etched through. .
  • the solutions to process node (1) and process node (2) are incompatible, resulting in a low manufacturing yield when manufacturing magnetic memories. Therefore, how to improve the yield of magnetic memories is an urgent need. solved problem.
  • inventions of the present application provide a method for manufacturing a magnetic memory.
  • the magnetic tunnel junction MTJ stack is etched to the metal layer.
  • the MTJ stack includes a free layer, an oxide layer and a fixed layer stacked in sequence.
  • the free layer is and the sidewalls of the fixed layer and the metal layer exposed by etching are oxidized or nitrided to obtain a protective layer.
  • the protective layer covers the sidewalls of the free layer and the fixed layer and covers the metal layer.
  • the sidewalls of the protective layer and the oxide layer are Etch to remove contaminants from the sidewalls of the oxide layer.
  • the protective layer when etching to remove contaminants on the sidewalls of the oxide layer, the protective layer is used to protect the sidewalls of the free layer and the fixed layer.
  • the etching residues of the free layer and the fixed layer will not adhere to the oxide layer, and at the same time, The contaminants on the side walls of the oxide layer are removed by etching, and the metal layer is covered by the protective layer.
  • the protective layer will be etched first, and the etching amount of the metal layer is low to avoid etching the contaminants on the side walls of the oxide layer. Large damage to the metal layer or even carving through the metal layer.
  • the manufacturing method of the magnetic memory provided by the embodiment of the present application can not only remove the contaminants on the side walls of the oxide layer by etching, improve the performance and yield of the device, but also avoid the metal layer from being over-etched, further improving the performance of the device. Device yield.
  • FIG. 2 is a flow chart of a manufacturing method of a magnetic memory provided by an embodiment of the present application.
  • the manufacturing method of the magnetic memory provided by this embodiment includes the following steps:
  • S101 Etch the MTJ stack 120 to the metal layer 110, as shown in FIG. 3 .
  • the magnetic memory includes a substrate 100, a metal layer 110 and an MTJ stack 120 that are stacked in sequence.
  • the MTJ stack 120 includes a free layer 121, an oxide layer 122 and a fixed layer 123 stacked in sequence.
  • the oxide layer 122 may be magnesium oxide, and the free layer 121 and the fixed layer 123 are usually made of metal.
  • the material of the metal layer 110 may be tantalum (Ta).
  • the substrate 100 may be an oxide, and the substrate 100 may be subsequently etched and then filled with metal material to form a lower electrode.
  • the MTJ stack 120 can be etched to the metal layer 110 to obtain an opening 130 , and the opening 130 exposes the sidewalls of the MTJ stack and the upper surface of the metal layer 110 .
  • a patterned mask layer 140 is formed on the MTJ stack 120 , and the patterned mask layer 140 can be used as a mask to etch the MTJ stack 120 to the metal layer 110 .
  • the MTJ stack 120 can be etched using machines such as IBE, ICP or CCP. Since the MTJ film layer is composed of a variety of metals and metal oxides, after the MTJ stack 120 is etched, the side walls of the oxide layer 122 will There is a certain amount of metal contamination, that is, there are contaminants. These contaminants will cause the fixed layer and the free layer to conduct, causing the magnetic memory to malfunction, ultimately affecting the device yield.
  • the sidewalls of the oxide layer 122 may be etched to remove contaminants on the sidewalls of the oxide layer 122 .
  • a protective layer 150 may be formed on the sidewalls of the free layer 121 and the fixed layer 132 and the metal layer 110 exposed by etching, that is, the protective layer 150 covers the free layer 121 and the fixed layer 123 sidewalls and covering metal layer 110 .
  • the etching rate of the protective layer 150 is lower than the etching rate of the metal layer 110 , so that when the contaminants on the sidewalls of the oxide layer 122 are removed by subsequent etching, the metal layer 110 is protected by the protective layer 150 above the metal layer 110 .
  • the etching damage is small, and the etching amount of the metal layer 110 is low, which avoids the metal layer 110 being etched through when the contaminants on the side walls of the oxide layer 122 are removed by etching.
  • the protective layer 150 also plays a role in protecting the side walls of the free layer 121 and the fixed layer 132 when the contaminants on the side walls of the oxide layer 122 are etched to prevent the metal residues of the free layer 121 and the fixed layer 132 from adhering to the oxide layer. 122, causing the fixed layer 121 and the free layer 123 to be conductive, causing the magnetic memory to malfunction, and ultimately affecting the device yield.
  • the process of forming the protective layer 150 may be to oxidize or nitride the sidewalls and bottom of the opening 130 , that is, to oxidize the free layer. 121 and the sidewalls of the fixed layer 132 and the metal layer 110 exposed by etching are oxidized or nitrided to obtain the protective layer 150.
  • a protective layer 150 is also formed on the sidewalls and top of the mask layer 140 A protective layer 150 is provided.
  • oxidizing gas, nitriding gas or alcohol gas can be introduced to oxidize or nitride the sidewalls of the free layer 121 and the fixed layer 123 and the metal layer 110 exposed by etching to obtain a protective layer.
  • the protective layer 150 may be an oxide layer, a nitride layer, or an oxynitride layer. That is, the material of the protective layer 150 may be an oxide, a nitride, or an oxynitride, depending on which gas is used to form the protective layer.
  • the oxidizing gas can be any one or more of O 2 , H 2 O 2 , O 3 , N 2 O, and NO.
  • the nitriding gas can be one or more of NH 3 and N 2 .
  • Alcohol gas is ethanol or methanol.
  • the equipment for oxidation or nitridation can be IBE, ICP, CCP or HMOP.
  • the oxidation or nitridation process parameters can be set as follows:
  • Acceleration grid voltage BMV 50V-1500V.
  • the process parameters of oxidation or nitridation can be set as follows:
  • Bottom electrode power Wb 0-1500W.
  • the process parameters of oxidation or nitridation can be set as follows:
  • Electrode power Ws 50-3000W.
  • the purpose of setting the oxidation or nitridation process parameters in the above example is to form the protective layer 150 on the sidewalls and bottom of the opening 130 to slow down the etching rate of the bottom of the opening 130 during subsequent etching.
  • S103 Etch the sidewalls of the protective layer 150 and the oxide layer 122, as shown in FIG. 5 .
  • the sidewalls of the protective layer 150 and the oxide layer 122 may be etched to remove contaminants on the sidewalls of the oxide layer 122 . Since the protective layer 150 is formed on the metal layer 110, it is ensured that The etching rate of the protective layer 150 is low, and the etching rate (ER1) of the film layer at the bottom of the opening 130 will slow down. In this way, the time for etching through the metal layer 110 at the bottom of the opening 130 will increase, and the contaminants on the side walls of the oxide layer 122 will be removed. The purpose is to be cleaner and the metal layer 110 will not be engraved.
  • the protective layer 150 may include a sidewall protective layer 151 and a bottom protective layer 152.
  • the sidewall protective layer 151 is located on the sidewalls of the free layer 121 and the fixed layer 123.
  • the bottom protective layer 152 covers the metal layer 110. That is to say, the sidewall protective layer 151 is located on the sidewall of the opening 130 , and the bottom protective layer 152 is located on the bottom of the opening 130 .
  • the first implementation method is to increase the etching time, and completely remove the contaminants on the sidewalls of the oxide layer 122 when etching the sidewalls of the protective layer 150 and the oxide layer 122. At this time, there will be a bottom protective layer 152 or sidewall protection. When layer 151 is completely etched away, there may even be situations where the bottom protective layer 150 is completely etched away, and the metal layer 110 continues to be etched, although the metal layer 110 will not be etched through due to the protection of the bottom protective layer 150. , but it will still result in a large etching amount of the metal layer 110 .
  • the second implementation method is to adjust the etching angle so that the etching speed of the sidewall protective layer 151 and the sidewall of the oxide layer 122 is greater than the etching speed of the bottom protective layer 152, so that the contaminants on the sidewall of the oxide layer 122 are completely removed.
  • the etching amount at the bottom of the opening 130 is small, further protecting the metal layer 110 and preventing the metal layer 110 from being etched from a large amount.
  • the etching angle at which the longitudinal etching rate is maximum can be set so that the etching speed of the sidewall protective layer 151 and the oxide layer 122 is greater than the etching speed of the bottom protective layer 152 . That is to say, by setting an angle with a larger etching rate for the sidewalls of the opening 130, the etching rate for the bottom of the opening 130 is lower at this time, which can satisfy the requirement that after the contaminants on the sidewalls of the oxide layer 122 are etched, For the purpose of etching less amount at the bottom of the opening 130 .
  • the etching angle range can be -75° ⁇ 75°.
  • the thickness of the protective layer 150 can be determined according to the thickness of the contaminated oxide layer and the thickness of the metal layer 110. That is to say, the thickness of the protective layer 150 is smaller than the thickness of the metal layer 110 to prevent the metal layer 110 from being completely oxidized. The thickness of 150 is greater than the thickness of the oxide layer 122 that is contaminated.
  • the thickness of the protective layer may range from 0.5 to 50 nm.
  • the thickness of the metal layer 110 is 10 nm
  • the thickness of the contaminated oxide layer 122 is 3-4 nm
  • the thickness of the protective layer may be 5-6 nm.
  • the first possible implementation method is to use an etching machine to etch the MTJ stack 120.
  • the etching process parameters may be: ICP: 5mT/0C/250Ws/260Wb/150Ar/8s, IBE: 400VBMV/400V ACV /-75D/42s and IBE:100V BMV/400V/ACV/70D/1002s.
  • oxidation is performed.
  • the process parameters of the oxidation can be: ICP: 5mT/0C/300Ws/0Wb/150O 2 /720s.
  • the thickness of the protective layer 150 obtained by oxidation is about 5nm. Afterwards, the sidewalls of the protective layer 150 and the oxide layer 122 are processed.
  • Etching the specific etching process parameters can be: IBE: 400VBMV/400V ACV/-35D/200s. It can be seen from the parameters that the etching time is 200s. The etching effect is shown in Figure 6. You can see from the figure It is shown that after the oxidation treatment, the etching can stop at the metal layer 110, and the sidewalls of the oxide layer 122 are relatively clean. That is, after the oxidation treatment, the yield rate of the SOT-MRAM device can be improved. After etching, the top of the metal layer 110 and the mask layer Part of the oxide remains on the top of 140, the sidewalls of mask layer 140, and the sidewalls of free layer 121 and fixed layer 123.
  • the second possible implementation method is to use an etching machine to etch the MTJ stack 120.
  • the etching process parameters can be: ICP: 5mT/0C/250Ws/260Wb/150Ar/8s, IBE: 400VBMV/400V ACV /-75D/42s and IBE:100V BMV/400V/ACV/70D/1002s.
  • oxidation is performed.
  • the process parameters of the oxidation can be: ICP: 5mT/0C/300Ws/0Wb/150O 2 /360s.
  • the thickness of the protective layer 150 obtained by oxidation is about 2.5nm. Afterwards, the sidewalls of the protective layer 150 and the oxide layer 122 are Carry out etching.
  • the specific etching process parameters can be: IBE: 400VBMV/400V ACV/-35D/200s. It can be seen from the parameters that the etching time is 200s.
  • the etching effect is shown in Figure 7. It can be seen from the figure It can be seen that after the oxidation treatment, the etching can stop at the metal layer 110, and the sidewalls of the oxide layer 122 are relatively clean. That is, after the oxidation treatment, the yield rate of the SOT-MRAM device can be improved.
  • the oxides on the top of the mask layer 140 and the top of the metal layer 110 are etched clean, and some oxide remains on the side walls of the mask layer 140 and the side walls of the free layer 121 and the fixed layer 123 .
  • the third possible implementation method is to use an etching machine to etch the MTJ stack 120.
  • the etching process parameters may be: ICP: 5mT/0C/250Ws/260Wb/150Ar/8s, IBE: 400VBMV/400V ACV /-75D/42s and IBE:100V BMV/400V/ACV/70D/1002s.
  • oxidation is performed.
  • the process parameters of the oxidation can be: ICP: 5mT/0C/300Ws/0Wb/150O 2 /360s.
  • the thickness of the protective layer 150 obtained by oxidation is about 2.5nm. Afterwards, the sidewalls of the protective layer 150 and the oxide layer 122 are Carry out etching.
  • the specific etching process parameters can be: IBE: 400V BMV/400V ACV/-65D/400s. From these parameters, it can be seen that the etching angle increases from -35D to -65D, and the etching time is 400s. , the etching effect is shown in Figure 5. It can be seen from the figure that after the oxidation treatment, the etching can stop at the metal layer 110, and the side walls of the oxide layer 122 are relatively clean. That is, after the oxidation treatment, the SOT-MRAM device can be improved. yield rate. The oxides on the top of the mask layer 140, the sidewalls of the mask layer 140, the sidewalls of the free layer 121 and the fixed layer 123 are etched clean, and some oxide remains on the top of the metal layer 110.
  • the fourth possible implementation method is to use an etching machine to etch the MTJ stack 120.
  • the etching process parameters may be: ICP: 5mT/0C/250Ws/260Wb/150Ar/8s, IBE: 400VBMV/400V ACV /-75D/42s and IBE:100V BMV/400V/ACV/70D/1002s.
  • nitriding is performed.
  • the process parameters of nitriding can be: ICP: 5mT/0C/300Ws/0Wb/150N 2 /360s.
  • the thickness of the protective layer 150 obtained by nitriding is about 4nm. Afterwards, the protective layer 150 and the oxide layer 122 are The side wall is etched.
  • the specific etching process parameters can be: IBE: 400VBMV/400V ACV/-35D/200s. From these parameters, it can be seen that the etching angle is -35D, the etching time is 200s, and the etching effect is Referring to Figure 6, it can be seen from the figure that after the nitridation treatment, the etching can stop at the metal layer 110, and the sidewalls of the oxide layer 122 are relatively clean. That is, after the nitridation treatment, the quality of the SOT-MRAM device can be improved. Rate. Part of the nitride remains on the top of the mask layer 140, the sidewalls of the mask layer 140, and the top of the metal layer 110.
  • the fifth possible implementation method is to use an etching machine to etch the MTJ stack 120.
  • the etching process parameters can be: ICP: 5mT/0C/250Ws/260Wb/150Ar/8s, IBE: 400VBMV/400V ACV /-75D/42s and IBE:100V BMV/400V/ACV/70D/1002s.
  • nitriding is performed.
  • the process parameters of nitriding can be: ICP: 5mT/0C/300Ws/0Wb/150N 2 /360s.
  • the thickness of the protective layer 150 obtained by nitriding is about 4nm. Afterwards, the protection layer The sidewalls of layer 150 and oxide layer 122 are etched.
  • the specific etching process parameters can be: IBE: 400VBMV/400V ACV/-15D/400s. It can be seen from the parameters that the etching angle is -15D and the etching time is 400s.
  • the etching effect is shown in Figure 7. It can be seen from the figure that after the nitriding treatment, the etching can stop at the metal layer 110, and the side walls of the oxide layer 122 are relatively clean. That is, after the nitriding treatment, the etching can be improved. Yield of SOT-MRAM devices. Part of the nitride remains on the sidewalls of the mask layer 140, the free layer 121 and the fixed layer 123, but no nitride remains on the top of the metal layer 110.
  • the sixth possible implementation method is to use an etching machine to etch the MTJ stack 120.
  • the etching process parameters can be: ICP: 5mT/0C/250Ws/260Wb/150Ar/8s, IBE: 400VBMV/400V ACV /-75D/42s and IBE:100V BMV/400V/ACV/70D/1002s.
  • nitriding is performed.
  • the process parameters of nitriding can be: ICP: 5mT/0C/300Ws/0Wb/150N 2 /360s.
  • the thickness of the protective layer 150 obtained by nitriding is about 4nm. Afterwards, the protective layer 150 and the oxide layer 122 are The side wall is etched.
  • the specific etching process parameters can be: IBE: 400V BMV/400V ACV/-65D/400s. From the parameters, it can be seen that the etching angle is -65D, the etching time is 400s, and the etching time is -65D. The effect is shown in Figure 5. It can be seen from the figure that after the nitridation treatment, the etching can stop at the metal layer 110, and the sidewalls of the oxide layer 122 are relatively clean. That is, after the nitridation treatment, the SOT-MRAM device can be improved. Yield. There is no nitride residue on the sidewalls of the mask layer 140, the free layer 121 and the fixed layer 123, but there is nitride residue on the top of the metal layer 110.
  • Embodiments of the present application provide a method for manufacturing a magnetic memory.
  • the magnetic tunnel junction MTJ stack is etched to the metal layer.
  • the MTJ stack includes a free layer, an oxide layer and a fixed layer stacked in sequence.
  • the free layer and the fixed layer are The sidewalls and the metal layer exposed by etching are oxidized or nitrided to obtain a protective layer.
  • the protective layer covers the sidewalls of the free layer and the fixed layer and covers the metal layer.
  • the sidewalls of the protective layer and the oxide layer are etched. to remove contaminants from the sidewalls of the oxide layer. That is to say, when etching to remove contaminants on the sidewalls of the oxide layer, the protective layer is used to protect the sidewalls of the free layer and the fixed layer.
  • the etching residues of the free layer and the fixed layer will not adhere to the oxide layer, and at the same time, The contaminants on the side walls of the oxide layer are removed by etching, and the metal layer is covered by the protective layer.
  • the protective layer will be etched first, and the etching amount of the metal layer is low to avoid etching the contaminants on the side walls of the oxide layer. Large damage to the metal layer or even carving through the metal layer. It can be seen that the manufacturing method of the magnetic memory provided by the embodiments of the present application can not only remove the contaminants on the side walls of the oxide layer by etching, improve the performance and yield of the device, but also prevent the metal layer from being over-etched, further improving the performance of the device. Device yield.

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Abstract

本申请实施例公开了一种磁存储器的制造方法，对磁隧穿结叠层进行刻蚀至金属层，对自由层和固定层的侧壁以及金属层进行氧化或氮化，得到保护层，对保护层和氧化层的侧壁进行刻蚀，以去除氧化层侧壁的污染物。在刻蚀去除氧化层侧壁的污染物时，利用保护层保护自由层和固定层的侧壁，自由层和固定层的刻蚀残渣不会附着在氧化层上，同时也能刻蚀去除氧化层侧壁的污染物，并且金属层被保护层覆盖，会首先刻蚀保护层，对金属层的刻蚀量较低，避免在刻蚀去除氧化层侧壁的污染物时，对金属层的较大损伤甚至刻穿金属层的情况，既能够实现刻蚀去除氧化层侧壁的污染物，提高器件的性能和良率，又能够避免金属层被过度刻蚀，进一步提高器件的良率。

Description

一种磁存储器的制造方法
本申请要求于2022年04月08日提交中国国家知识产权局、申请号为CN202210366451.1、发明名称为“一种磁存储器的制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，尤其涉及一种磁存储器的制造方法。
背景技术
随着半导体相关技术的发展，随机存储器(Random Access Memory，RAM)也有了很大发展。随机存储器包括动态随机存取存储器(Dynamic Random Access Memory，DRAM)，静态随机存取存储器(Static Random-Access Memory，SRAM)、闪存(Flash Memory)和磁存储器(Magnetic Random Access Memory，MRAM)。其中，磁存储器拥有高于闪存的读写速度，以及SRAM和DRAM所不具备的抗辐射和非易失性。因此，当前很多需要目前三种存储器的组合才能够满足的存储需求，可以被MRAM单独实现。
但是当前在制造磁存储器时，存在制造良率较低的情况，因此如何提高磁存储器的良率，是一个亟待解决的问题。
发明内容
基于此，本申请实施例提供一种磁存储器的制造方法，能够提高磁存储器的良率。
本申请实施例提供一种磁存储器的制造方法，所述方法包括：
对磁隧穿结MTJ叠层进行刻蚀至金属层，所述MTJ叠层包括依次层叠的自由层、氧化层和固定层；
对所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层进行氧化或氮化，得到保护层，所述保护层覆盖所述自由层和所述固定层的侧壁以及覆盖所述金属层；
对所述保护层和所述氧化层的侧壁进行刻蚀，以去除所述氧化层侧壁的污染物。
可选地，所述对所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层进行氧化或氮化，得到保护层包括：
通入氧化气体、氮化气体或醇类气体，以氧化或氮化所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层，得到保护层。
可选地，所述氧化气体为O2、H2O2、O3、N2O、NO中的任意一种或多种，所述氮化气体为NH3、N2中的一种或多种，所述醇类气体为乙醇或甲醇。
可选地，所述氧化气体、氮化气体或醇类气体的气体流量范围为10-1000sccm。
可选地，所述通入氧化气体、氮化气体或醇类气体，以氧化或氮化所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层，得到保护层包括：
利用离子束刻蚀设备、感应耦合等离子体设备或电容耦合等离子体设备，通入氧化气 体、氮化气体或醇类气体，以氧化或氮化所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层，得到保护层。
可选地，所述保护层包括侧壁保护层和底部保护层；所述侧壁保护层位于所述自由层和所述固定层的侧壁，所述底部保护层覆盖所述金属层；
所述对所述保护层和所述氧化层的侧壁进行刻蚀，以去除所述氧化层侧壁的污染物包括：
通过调整刻蚀角度，以便所述侧壁保护层和所述氧化层的刻蚀速度大于所述底部保护层的刻蚀速度。
可选地，所述通过调整刻蚀角度，以便所述侧壁保护层和所述氧化层的刻蚀速度大于所述底部保护层的刻蚀速度包括：
设定纵向刻蚀速率最大的刻蚀角度，以便所述侧壁保护层和所述氧化层的刻蚀速度大于所述底部保护层的刻蚀速度。
可选地，所述刻蚀角度范围为-75°-75°。
可选地，所述对所述保护层和所述氧化层的侧壁进行刻蚀，以去除所述氧化层侧壁的污染物包括：
增加刻蚀时间，在对所述保护层和所述氧化层的侧壁进行刻蚀时完全去除所述氧化层侧壁的污染物。
可选地，所述磁隧穿结MTJ叠层上还覆盖有图案化的掩模层；
所述对磁隧穿结MTJ叠层进行刻蚀至金属层包括：
以所述图案化的掩模层为掩蔽，刻蚀所述磁隧穿结MTJ叠层至所述金属层。
可选地，所述保护层覆盖所述掩模层的侧壁和顶部。
可选地，所述保护层的厚度根据所述氧化层被污染的厚度和所述金属层的厚度进行确定。
可选地，所述保护层的厚度小于所述金属层的厚度，大于所述氧化层被污染的厚度。
可选地，所述保护层的厚度范围为0.5-50nm。
可选地，所述保护层为氧化层、氮化层或氮氧化层，所述氧化层为氧化镁。
可选地，所述磁隧穿结MTJ叠层中的氧化层的材料为氧化镁。
可选地，所述自由层和所述固定层为金属材料，所述金属层的材料为钽。
可选地，所述对磁隧穿结MTJ叠层进行刻蚀至金属层包括：
利用离子束刻蚀工艺、感应耦合等离子体工艺或电容耦合等离子体工艺对磁隧穿结MTJ叠层进行刻蚀至金属层。
可选地，对所述保护层的刻蚀速率小于对所述金属层的刻蚀速率。
可选地，对所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层进行氧化或氮化的时间范围为5-1000s。
本申请实施例提供一种磁存储器的制造方法，对磁隧穿结MTJ叠层进行刻蚀至金属层，MTJ叠层包括依次层叠的自由层、氧化层和固定层，对自由层和固定层的侧壁以及通过刻蚀暴露的金属层进行氧化或氮化，得到保护层，保护层覆盖自由层和固定层的侧壁以及覆 盖金属层，对保护层和氧化层的侧壁进行刻蚀，以去除氧化层侧壁的污染物。也就是说，在刻蚀去除氧化层侧壁的污染物时，利用保护层保护自由层和固定层的侧壁，自由层和固定层的刻蚀残渣不会附着在氧化层上，同时也能刻蚀去除氧化层侧壁的污染物，并且金属层被保护层覆盖，会首先刻蚀保护层，对金属层的刻蚀量较低，避免在刻蚀去除氧化层侧壁的污染物时，对金属层的较大损伤甚至刻穿金属层的情况。由此可见，利用本申请实施例提供的磁存储器的制造方法，既能够实现刻蚀去除氧化层侧壁的污染物，提高器件的性能和良率，又能够避免金属层被过度刻蚀，进一步提高器件的良率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为一种基于自旋轨道转矩的磁存储器的工作原理示意图；
图2为本申请实施例提供的一种磁存储器栅的制造方法的流程图；
图3-5为本申请实施例提供的磁存储器的制造方法的结构示意图；
图6为本申请实施例提供的一种磁存储器的结构示意图；
图7为本申请实施例提供的另一种磁存储器的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请结合示意图进行详细描述，在详述本申请实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本申请保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
随着半导体相关技术的发展，随机存储器(Random Access Memory，RAM)也有了很大发展。随机存储器包括动态随机存取存储器(Dynamic Random Access Memory，DRAM)，静态随机存取存储器(Static Random-Access Memory，SRAM)、闪存(Flash Memory)和磁存储器(Magnetic Random Access Memory，MRAM)。其中，磁存储器拥有高于闪存的读写速度，以及SRAM和DRAM所不具备的抗辐射和非易失性。因此，当前很多需要目前三种存储器的组合才能够满足的存储需求，可以被MRAM单独实现。
MRAM的存储单元是磁隧穿结(Magnetic Tunnel Junction，MTJ)，是两层磁性薄膜中间夹一层氧化层，例如氧化镁(MgO)。有一层磁性薄膜的磁矩是被固定住的，叫固定层(Pinned layer)，有一层是可以翻转的，叫自由层(Free layer)。当两层磁性薄膜的磁矩方向平行(Parallel，P)，MTJ呈现出来的电阻(Rp)较小，电流容易从固定层通过自由层，隧穿电流(Ip)较 大，这时整个MTJ可被视为导通态，代表着二进制字节的“1”。而当两层磁性材料磁极方向相反时(Anti-parallel)，电阻(Rap)较大，隧穿电流(Ip)较小，这时整个MTJ可被视为不导通态，代表着二进制字节的“0”。以此来区别MTJ存储信息中的0和1。
STT-MRAM，又被称为第三代MRAM，其优点为增加了磁化密度，方法是利用氧化镁与磁性薄膜之间的磁各向异性(Interfacial magnetic anisotropy)让磁矩站起来，即磁矩垂直于薄膜面。磁矩的密度大，对延长数据保存时间有帮助，也可用以减少尺寸。
对于目前STT的规格，虽然数据保存时间较长，可靠性高，但是在写入电流(～50μA)、功耗、写入速度(～10ns)等参数与理想数字有差距。主要原因是STT反转机制中携带自旋流的电子其质量只有质子的1/1840。力或者转矩与质量成正比，因此即使电流可以携带自旋流而对磁矩产生转矩，效率也不会太高。因为翻转效率低导致写入速度慢，电流大，功耗大。又因为要提供较大电流，需要较大晶体管，比MTJ还要大，是存储器件进行微缩的瓶颈。
自旋与原子轨域的角动量可以交互作用，但这力或转矩的根源是原子核。而原子序越大的原子，自旋轨道交互作用越大，有些特殊的物质，譬如拓扑绝缘体(Topological insulator)，其表面也有异常大的自旋轨道交互作用。利用自旋轨道转矩(Spin Orbit Torque，SOT)效应来翻转MTJ中自由层的磁矩，就是第四代SOT-MRAM。SOT-MRAM器件的特点是通过在相邻的SOT层中注入面内电流来完成自由磁层的切换。
参考图1所示，为一种基于自旋轨道转矩SOT的磁存储器MTJ的工作原理示意图。由图可以看出，SOT-MRAM的读取(read)电流垂直穿过MTJ结，但写入(write)电流则依靠与自由层平行邻接的材料，例如金属层中流过的电流，带动二者界面上的自旋轨道作用所产生的转矩，用以翻转自由层的磁矩。
因此，在制造SOT-MRAM时，关键的工艺节点在于：(1)多个MTJ结之间固定层下方的金属层需要互相连通，金属层的膜层不能出现断裂，否则会影响MRAM的写入功能，造成器件良率降低。(2)MTJ结的侧壁不能有金属沾污，以避免MTJ的上部分与下部分导通，即固定层和自由层导通，造成磁存储器失灵。
当前解决工艺节点(1)的方案是优化刻蚀过程中的程序参数，保证刻蚀终点能够停在金属层，不刻穿到下面的下电极。当前解决工艺节点(2)的方案是通过离子束刻蚀(Ion Beam Etching，IBE)、感应耦合等离子体(Inductive Coupled Plasma，ICP)或电容耦合等离子体(Capacitive Coupled Plasma，CCP)对侧壁修饰，以清除MgO侧壁的金属沾污，但是这种方法会导致底部膜层的刻蚀量增大，即金属层的刻蚀量增大，无法停在预想膜层，最终导致金属层刻穿。也就是说，解决工艺节点(1)和工艺节点(2)的方案无法兼容，导致当前在制造磁存储器时，存在制造良率较低的情况，因此如何提高磁存储器的良率，是一个亟待解决的问题。
基于此，本申请实施例提供一种磁存储器的制造方法，对磁隧穿结MTJ叠层进行刻蚀至金属层，MTJ叠层包括依次层叠的自由层、氧化层和固定层，对自由层和固定层的侧壁以及通过刻蚀暴露的金属层进行氧化或氮化，得到保护层，保护层覆盖自由层和固定层的侧壁以及覆盖金属层，对保护层和氧化层的侧壁进行刻蚀，以去除氧化层侧壁的污染物。 也就是说，在刻蚀去除氧化层侧壁的污染物时，利用保护层保护自由层和固定层的侧壁，自由层和固定层的刻蚀残渣不会附着在氧化层上，同时也能刻蚀去除氧化层侧壁的污染物，并且金属层被保护层覆盖，会首先刻蚀保护层，对金属层的刻蚀量较低，避免在刻蚀去除氧化层侧壁的污染物时，对金属层的较大损伤甚至刻穿金属层的情况。由此可见，利用本申请实施例提供的磁存储器的制造方法，既能够实现刻蚀去除氧化层侧壁的污染物，提高器件的性能和良率，又能够避免金属层被过度刻蚀，进一步提高器件的良率。
参见图2，该图为本申请实施例提供的一种磁存储器的制造方法的流程图。本实施例提供的磁存储器的制造方法包括如下步骤：
S101，对MTJ叠层120进行刻蚀至金属层110，参考图3所示。
在本申请的实施例中，磁存储器包括依次层叠的衬底100、金属层110和MTJ叠层120。其中，MTJ叠层120包括依次层叠的自由层121、氧化层122和固定层123。氧化层122可以是氧化镁，自由层121和固定层123的材料通常为金属。金属层110的材料可以是钽(Ta)。衬底100可以是氧化物，后续可以对衬底100进行刻蚀，而后填充金属材料，形成下电极。
在本申请的实施例中，可以对MTJ叠层120进行刻蚀至金属层110，得到开口130，开口130暴露MTJ叠层的侧壁和金属层110的上表面。
在进行刻蚀之前，在MTJ叠层120上形成图案化的掩模层140，可以以图案化的掩模层140为掩蔽，刻蚀MTJ叠层120至金属层110。
可以利用IBE、ICP或CCP等机台对MTJ叠层120进行刻蚀，由于MTJ膜层由多种金属及金属氧化物组成，在刻蚀完毕MTJ叠层120后，氧化层122的侧壁会存在一定的金属沾污，即存在污染物，这些污染物会导致固定层和自由层导通，造成磁存储器失灵，最终影响器件良率。
S102，对自由层121和固定层132的侧壁以及通过刻蚀暴露的金属层110进行氧化或氮化，得到保护层150，参考图4所示。
在本申请的实施例中，可以对氧化层122的侧壁进行刻蚀，以去除氧化层122侧壁的污染物。在对氧化层122的侧壁刻蚀之前，可以在自由层121和固定层132的侧壁以及通过刻蚀暴露的金属层110形成保护层150，即保护层150覆盖自由层121和固定层123的侧壁以及覆盖金属层110。
保护层150的刻蚀速率小于金属层110的刻蚀速率，这样能够使得在后续刻蚀去除氧化层122侧壁的污染物时，金属层110上方由于有保护层150的保护，对金属层110的刻蚀损伤较小，金属层110的刻蚀量较低，避免在刻蚀去除氧化层122侧壁的污染物时，金属层110被刻穿的情况。
由于保护层150还在刻蚀去除氧化层122侧壁的污染物时，起到保护自由层121和固定层132的侧壁的作用，避免自由层121和固定层132的金属残渣附着在氧化层122，造成固定层121和自由层123导通，造成磁存储器失灵，最终影响器件良率。
形成保护层150的工艺可以是对开口130的侧壁和底部进行氧化或氮化，即对自由层 121和固定层132的侧壁以及通过刻蚀暴露的金属层110进行氧化或氮化，得到保护层150。
具体的，在氧化或氮化时，除了在自由层121和固定层132的侧壁以及通过刻蚀暴露的金属层110形成保护层150之外，在掩模层140的侧壁和顶部也形成了保护层150。
在本申请的实施例中，可以通入氧化气体、氮化气体或醇类气体，以氧化或氮化自由层121和固定层123的侧壁以及通过刻蚀暴露的金属层110，得到保护层150。保护层150可以为氧化层、氮化层或氮氧化层，即保护层150的材料可以是氧化物、氮化物或氮氧化物，具体取决于利用何种气体形成保护层。
氧化气体可以为O2、H2O2、O3、N2O、NO中的任意一种或多种，氮化气体可以为NH3、N2中的一种或多种，醇类气体为乙醇或甲醇。
氧化或氮化的设备可以是IBE、ICP、CCP或HMOP等机台。
作为一种示例，氧化或氮化的设备为IBE设备，则氧化或氮化的工艺参数可以如下设置：
1.加速栅网电压BMV：50V-1500V。
2.偏转栅网电压ACV：50-1500V。
3.气体流量：10-500sccm。
4.角度：-45°到45°
5.时间：10s-1000s。
作为另一种示例，氧化或氮化的设备为ICP设备，则氧化或氮化的工艺参数可以如下设置：
1.上电极功率Ws：50-3000W。
2.底电极功率Wb：0-1500W。
3.气体流量：10-1000sccm。
4.时间：5s-1000s。
5.腔内压力：1-100mT。
6.温度：0-80℃。
作为又一种示例，氧化或氮化的设备为CCP设备，则氧化或氮化的工艺参数可以如下设置：
1.电极功率Ws：50-3000W。
2.气体流量：10-1000sccm。
3.时间：5s-1000s。
4.腔内压力：10-200mT。
5.温度：0-80℃。
以上示例的氧化或氮化的工艺参数进行设置的目的是为了在开口130的侧壁和底部形成保护层150，以减慢后续在刻蚀时对于开口130底部的刻蚀速率。
S103，对保护层150和氧化层122的侧壁进行刻蚀，参考图5所示。
在本申请的实施例中，在形成保护层150之后，可以对保护层150和氧化层122的侧壁进行刻蚀，以便去除氧化层122侧壁的污染物。由于在金属层110上形成保护层150，保 护层150的刻蚀速率较低，开口130底部的膜层的刻蚀速率(ER1)会变慢，这样刻穿开口130底部金属层110的时间增加，达到氧化层122侧壁的污染物清除得更干净同时金属层110也不会被刻穿的目的。
在本申请的实施例中，保护层150可以包括侧壁保护层151和底部保护层152，侧壁保护层151位于自由层121和固定层123的侧壁，底部保护层152覆盖金属层110，也就是说，侧壁保护层151位于开口130的侧壁，底部保护层152位于开口130的底部。
为了完全去除氧化层122侧壁的污染物，有以下两种可能的实现方式：
第一种实现方式为增加刻蚀时间，在对保护层150和氧化层122的侧壁进行刻蚀时完全去除氧化层122侧壁的污染物，此时会存在底部保护层152或侧壁保护层151被完全刻蚀掉的情况，甚至会出现底部保护层150完全被刻蚀掉，继续刻蚀金属层110的情况，虽然金属层110由于底部保护层150的保护不会被刻蚀穿透，但是依旧会导致金属层110的刻蚀量较大。
第二种实现方式为通过调整刻蚀角度，以便侧壁保护层151和氧化层122侧壁的刻蚀速度大于底部保护层152的刻蚀速度，以便在完全去除氧化层122侧壁的污染物时，对于开口130底部的刻蚀量较小，进一步保护金属层110，避免金属层110的刻蚀量较大。
具体的，可以设定纵向刻蚀速率最大的刻蚀角度，以便侧壁保护层151和氧化层122的刻蚀速度大于底部保护层152的刻蚀速度。也就是说，可以通过设定开口130的侧壁刻蚀速率较大的角度，此时对于开口130的底部刻蚀速率较低，能够满足在刻蚀完毕氧化层122侧壁的污染物后，对于开口130底部的刻蚀量较少的目的。刻蚀角度范围可以是-75°～75°。
在实际应用中，需要设计合适的保护层150厚度，以避免保护层150过厚，后续不易清理侧壁保护层151，也要避免保护层150过薄，导致氧化层122侧壁的污染物还没完全刻蚀去除就暴露自由层121和固定层123的侧壁。因此，保护层150的厚度可以根据氧化层被污染的厚度和金属层110的厚度进行确定，也就是说，保护层150的厚度小于金属层110的厚度，避免金属层110完全被氧化，保护层150的厚度大于氧化层122被污染的厚度。
具体的，保护层的厚度范围可以为0.5-50nm。
作为一种示例，金属层110的厚度为10nm，氧化层122被污染的厚度为3-4nm，则保护层的厚度可以是5-6nm。
为了对刻蚀效果进行验证，本申请实施例提供了以下6种可能的实现方式进行介绍：
第一种可能的实现方式为利用刻蚀机台对MTJ叠层120进行刻蚀，刻蚀的工艺参数可以是：ICP:5mT/0C/250Ws/260Wb/150Ar/8s、IBE:400VBMV/400V ACV/-75D/42s和IBE:100V BMV/400V/ACV/70D/1002s。而后进行氧化，氧化的工艺参数可以是：ICP:5mT/0C/300Ws/0Wb/150O2/720s，氧化得到的保护层150的厚度约为5nm，之后对保护层150和氧化层122侧壁进行刻蚀，具体刻蚀的工艺参数可以是：IBE:400VBMV/400V ACV/-35D/200s，由此参数可以看出，刻蚀时间为200s，刻蚀效果参考图6所示，由图可以看出，经过氧化处理后，刻蚀可以停在金属层110，氧化层122侧壁清除较为干净，即经过氧化处理，可以提高SOT-MRAM器件的良率。经过刻蚀后，金属层110顶部、掩模层 140顶部、掩模层140侧壁及自由层121和固定层123侧壁均残留部分氧化物。
第二种可能的实现方式为利用刻蚀机台对MTJ叠层120进行刻蚀，刻蚀的工艺参数可以是：ICP:5mT/0C/250Ws/260Wb/150Ar/8s、IBE:400VBMV/400V ACV/-75D/42s和IBE:100V BMV/400V/ACV/70D/1002s。而后进行氧化，氧化的工艺参数可以是：ICP:5mT/0C/300Ws/0Wb/150O2/360s，氧化得到的保护层150的厚度约为2.5nm，之后对保护层150和氧化层122侧壁进行刻蚀，具体刻蚀的工艺参数可以是：IBE:400VBMV/400V ACV/-35D/200s，由此参数可以看出，刻蚀时间为200s，刻蚀效果参考图7所示，由图可以看出，经过氧化处理后，刻蚀可以停在金属层110，氧化层122侧壁清除较为干净，即经过氧化处理，可以提高SOT-MRAM器件的良率。掩模层140顶部和金属层110顶部氧化物被刻蚀干净，掩模层140侧壁以及自由层121和固定层123侧壁残留有部分氧化物。
第三种可能的实现方式为利用刻蚀机台对MTJ叠层120进行刻蚀，刻蚀的工艺参数可以是：ICP:5mT/0C/250Ws/260Wb/150Ar/8s、IBE:400VBMV/400V ACV/-75D/42s和IBE:100V BMV/400V/ACV/70D/1002s。而后进行氧化，氧化的工艺参数可以是：ICP:5mT/0C/300Ws/0Wb/150O2/360s，氧化得到的保护层150的厚度约为2.5nm，之后对保护层150和氧化层122侧壁进行刻蚀，具体刻蚀的工艺参数可以是：IBE:400V BMV/400V ACV/-65D/400s，由此参数可以看出，刻蚀角度由-35D增大至-65D，刻蚀时间为400s，刻蚀效果参考图5所示，由图可以看出，经过氧化处理后，刻蚀可以停在金属层110，氧化层122侧壁清除较为干净，即经过氧化处理，可以提高SOT-MRAM器件的良率。掩模层140顶部、掩模层140侧壁、自由层121和固定层123侧壁的氧化物被刻蚀干净，金属层110顶部残留有部分氧化物。
由上述三个实施效果可以看出，改变氧化时间，可以得到不同厚度的保护层150，不同厚度的保护层150会影响最终刻蚀完毕保护层150的残留形貌，在相同的氧化条件下，延长刻蚀时间或增大刻蚀角度均可以减少保护层150在器件表面的残留，尤其是会减少自由层121和固定层123侧壁的保护层150残留。
第四种可能的实现方式为利用刻蚀机台对MTJ叠层120进行刻蚀，刻蚀的工艺参数可以是：ICP:5mT/0C/250Ws/260Wb/150Ar/8s、IBE:400VBMV/400V ACV/-75D/42s和IBE:100V BMV/400V/ACV/70D/1002s。而后进行氮化，氮化的工艺参数可以是：ICP:5mT/0C/300Ws/0Wb/150N2/360s，氮化得到的保护层150的厚度约为4nm，之后对保护层150和氧化层122侧壁进行刻蚀，具体刻蚀的工艺参数可以是：IBE:400VBMV/400V ACV/-35D/200s，由此参数可以看出，刻蚀角度为-35D，刻蚀时间为200s，刻蚀效果参考图6所示，由图可以看出，经过氮化处理后，刻蚀可以停在金属层110，氧化层122侧壁清除较为干净，即经过氮化处理，可以提高SOT-MRAM器件的良率。掩模层140顶部、掩模层140侧壁、金属层110顶部均残留有部分氮化物。
第五种可能的实现方式为利用刻蚀机台对MTJ叠层120进行刻蚀，刻蚀的工艺参数可以是：ICP:5mT/0C/250Ws/260Wb/150Ar/8s、IBE:400VBMV/400V ACV/-75D/42s和IBE:100V BMV/400V/ACV/70D/1002s。而后进行氮化，氮化的工艺参数可以是：ICP:5mT/0C/300Ws/0Wb/150N2/360s，氮化得到的保护层150的厚度约为4nm，之后对保护 层150和氧化层122侧壁进行刻蚀，具体刻蚀的工艺参数可以是：IBE:400VBMV/400V ACV/-15D/400s，由此参数可以看出，刻蚀角度为-15D，刻蚀时间为400s，刻蚀效果参考图7所示，由图可以看出，经过氮化处理后，刻蚀可以停在金属层110，氧化层122侧壁清除较为干净，即经过氮化处理，可以提高SOT-MRAM器件的良率。掩掩模层140侧壁、自由层121和固定层123侧壁均残留有部分氮化物，但是金属层110顶部无氮化物残留。
第六种可能的实现方式为利用刻蚀机台对MTJ叠层120进行刻蚀，刻蚀的工艺参数可以是：ICP:5mT/0C/250Ws/260Wb/150Ar/8s、IBE:400VBMV/400V ACV/-75D/42s和IBE:100V BMV/400V/ACV/70D/1002s。而后进行氮化，氮化的工艺参数可以是：ICP:5mT/0C/300Ws/0Wb/150N2/360s，氮化得到的保护层150的厚度约为4nm，之后对保护层150和氧化层122侧壁进行刻蚀，具体刻蚀的工艺参数可以是：IBE:400V BMV/400V ACV/-65D/400s，由此参数可以看出，刻蚀角度为-65D，刻蚀时间为400s，刻蚀效果参考图5所示，由图可以看出，经过氮化处理后，刻蚀可以停在金属层110，氧化层122侧壁清除较为干净，即经过氮化处理，可以提高SOT-MRAM器件的良率。掩模层140侧壁、自由层121和固定层123侧壁均无氮化物残留，但是金属层110顶部存在氮化物残留。
由上述三个实施效果可以看出，在相同的氮化条件下，延长刻蚀时间，氮化物在器件表面的残留量会减少，并且在相同氮化条件下，改变IBE主刻角度，即增大IBE主刻角度，会使自由层121和固定层123侧壁的氮化物残留的更少，同时金属层110顶部的氮化物残留量会增多。
本申请实施例提供一种磁存储器的制造方法，对磁隧穿结MTJ叠层进行刻蚀至金属层，MTJ叠层包括依次层叠的自由层、氧化层和固定层，对自由层和固定层的侧壁以及通过刻蚀暴露的金属层进行氧化或氮化，得到保护层，保护层覆盖自由层和固定层的侧壁以及覆盖金属层，对保护层和氧化层的侧壁进行刻蚀，以去除氧化层侧壁的污染物。也就是说，在刻蚀去除氧化层侧壁的污染物时，利用保护层保护自由层和固定层的侧壁，自由层和固定层的刻蚀残渣不会附着在氧化层上，同时也能刻蚀去除氧化层侧壁的污染物，并且金属层被保护层覆盖，会首先刻蚀保护层，对金属层的刻蚀量较低，避免在刻蚀去除氧化层侧壁的污染物时，对金属层的较大损伤甚至刻穿金属层的情况。由此可见，利用本申请实施例提供的磁存储器的制造方法，既能够实现刻蚀去除氧化层侧壁的污染物，提高器件的性能和良率，又能够避免金属层被过度刻蚀，进一步提高器件的良率。
当介绍本申请的各种实施例的元件时，冠词“一”、“一个”、“这个”和“所述”都意图表示有一个或多个元件。词语“包括”、“包含”和“具有”都是包括性的并意味着除了列出的元件之外，还可以有其它元件。
以上所述仅是本申请的优选实施方式，虽然本申请已以较佳实施例披露如上，然而并非用以限定本申请。任何熟悉本领域的技术人员，在不脱离本申请技术方案范围情况下，都可利用上述揭示的方法和技术内容对本申请技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本申请技术方案保护的范围内。

Claims (20)

  1. 一种磁存储器的制造方法，其特征在于，所述方法包括：
    对磁隧穿结MTJ叠层进行刻蚀至金属层，所述MTJ叠层包括依次层叠的自由层、氧化层和固定层；
    对所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层进行氧化或氮化，得到保护层，所述保护层覆盖所述自由层和所述固定层的侧壁以及覆盖所述金属层；
    对所述保护层和所述氧化层的侧壁进行刻蚀，以去除所述氧化层侧壁的污染物。
  2. 根据权利要求1所述的制造方法，其特征在于，所述对所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层进行氧化或氮化，得到保护层包括：
    通入氧化气体、氮化气体或醇类气体，以氧化或氮化所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层，得到保护层。
  3. 根据权利要求2所述的制造方法，其特征在于，所述氧化气体为O2、H2O2、O3、N2O、NO中的任意一种或多种，所述氮化气体为NH3、N2中的一种或多种，所述醇类气体为乙醇或甲醇。
  4. 根据权利要求2所述的制造方法，其特征在于，所述氧化气体、氮化气体或醇类气体的气体流量范围为10-1000sccm。
  5. 根据权利要求2所述的制造方法，其特征在于，所述通入氧化气体、氮化气体或醇类气体，以氧化或氮化所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层，得到保护层包括：
    利用离子束刻蚀设备、感应耦合等离子体设备或电容耦合等离子体设备，通入氧化气体、氮化气体或醇类气体，以氧化或氮化所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层，得到保护层。
  6. 根据权利要求1所述的制造方法，其特征在于，所述保护层包括侧壁保护层和底部保护层；所述侧壁保护层位于所述自由层和所述固定层的侧壁，所述底部保护层覆盖所述金属层；
    所述对所述保护层和所述氧化层的侧壁进行刻蚀，以去除所述氧化层侧壁的污染物包括：
    通过调整刻蚀角度，以便所述侧壁保护层和所述氧化层的刻蚀速度大于所述底部保护层的刻蚀速度。
  7. 根据权利要求6所述的制造方法，其特征在于，所述通过调整刻蚀角度，以便所述侧壁保护层和所述氧化层的刻蚀速度大于所述底部保护层的刻蚀速度包括：
    设定纵向刻蚀速率最大的刻蚀角度，以便所述侧壁保护层和所述氧化层的刻蚀速度大于所述底部保护层的刻蚀速度。
  8. 根据权利要求6或7所述的制造方法，其特征在于，所述刻蚀角度范围为-75°-75°。
  9. 根据权利要求1所述的制造方法，其特征在于，所述对所述保护层和所述氧化层的侧壁进行刻蚀，以去除所述氧化层侧壁的污染物包括：
    增加刻蚀时间，在对所述保护层和所述氧化层的侧壁进行刻蚀时完全去除所述氧化层 侧壁的污染物。
  10. 根据权利要求1-9任意一项所述的制造方法，其特征在于，所述磁隧穿结MTJ叠层上还覆盖有图案化的掩模层；
    所述对磁隧穿结MTJ叠层进行刻蚀至金属层包括：
    以所述图案化的掩模层为掩蔽，刻蚀所述磁隧穿结MTJ叠层至所述金属层。
  11. 根据权利要求10所述的制造方法，其特征在于，所述保护层覆盖所述掩模层的侧壁和顶部。
  12. 根据权利要求1-9任意一项所述的制造方法，其特征在于，所述保护层的厚度根据所述氧化层被污染的厚度和所述金属层的厚度进行确定。
  13. 根据权利要求12所述的制造方法，其特征在于，所述保护层的厚度小于所述金属层的厚度，大于所述氧化层被污染的厚度。
  14. 根据权利要求1-9任意一项所述的制造方法，其特征在于，所述保护层的厚度范围为0.5-50nm。
  15. 根据权利要求1-9任意一项所述的制造方法，其特征在于，所述保护层为氧化层、氮化层或氮氧化层，所述氧化层为氧化镁。
  16. 根据权利要求1-9任意一项所述的制造方法，其特征在于，所述磁隧穿结MTJ叠层中的氧化层的材料为氧化镁。
  17. 根据权利要求1-9任意一项所述的制造方法，其特征在于，所述自由层和所述固定层为金属材料，所述金属层的材料为钽。
  18. 根据权利要求1-9任意一项所述的制造方法，其特征在于，所述对磁隧穿结MTJ叠层进行刻蚀至金属层包括：
    利用离子束刻蚀工艺、感应耦合等离子体工艺或电容耦合等离子体工艺对磁隧穿结MTJ叠层进行刻蚀至金属层。
  19. 根据权利要求1-9任意一项所述的制造方法，其特征在于，对所述保护层的刻蚀速率小于对所述金属层的刻蚀速率。
  20. 根据权利要求1-9任意一项所述的制造方法，其特征在于，对所述自由层和所述固定层的侧壁以及通过刻蚀暴露的所述金属层进行氧化或氮化的时间范围为5-1000s。
PCT/CN2023/086439 2022-04-08 2023-04-06 一种磁存储器的制造方法 WO2023193738A1 (zh)

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US20170069834A1 (en) * 2015-09-09 2017-03-09 Headway Technologies, Inc. Method to Minimize MTJ Sidewall Damage and Bottom Electrode Redeposition Using IBE Trimming
CN110945673A (zh) * 2017-05-15 2020-03-31 台湾积体电路制造股份有限公司 结合物理及化学蚀刻图案化磁穿隧接面
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JP2021190656A (ja) * 2020-06-04 2021-12-13 三星電子株式会社Samsung Electronics Co., Ltd. 磁気抵抗素子，磁気メモリ及び磁気抵抗素子の製造方法
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US20170069834A1 (en) * 2015-09-09 2017-03-09 Headway Technologies, Inc. Method to Minimize MTJ Sidewall Damage and Bottom Electrode Redeposition Using IBE Trimming
CN110945673A (zh) * 2017-05-15 2020-03-31 台湾积体电路制造股份有限公司 结合物理及化学蚀刻图案化磁穿隧接面
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