WO2022012147A1 - 封装芯片的测试方法、系统、计算机设备和存储介质 - Google Patents

封装芯片的测试方法、系统、计算机设备和存储介质 Download PDF

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Publication number
WO2022012147A1
WO2022012147A1 PCT/CN2021/094113 CN2021094113W WO2022012147A1 WO 2022012147 A1 WO2022012147 A1 WO 2022012147A1 CN 2021094113 W CN2021094113 W CN 2021094113W WO 2022012147 A1 WO2022012147 A1 WO 2022012147A1
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data retention
retention time
test
storage unit
time
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PCT/CN2021/094113
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English (en)
French (fr)
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杨正杰
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长鑫存储技术有限公司
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Priority to US17/615,566 priority Critical patent/US11862269B2/en
Publication of WO2022012147A1 publication Critical patent/WO2022012147A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1206—Location of test circuitry on chip or wafer

Definitions

  • the present application relates to the field of integrated circuit burn-in testing, and in particular, to a testing method, testing system, computer equipment and computer-readable storage medium of a packaged chip.
  • the finished product test is carried out to screen out the unqualified products.
  • the data retention time of the memory chip will deteriorate to a certain extent.
  • the finished product test it is necessary to add the test memory chip.
  • the data retention time of the memory chip conforms to the specification and is judged as a qualified product, otherwise it is judged as a secondary product or a failed product. Secondary products or failed products are screened out during the finished product test after being tested layer by layer, which is not conducive to the improvement of product yield and the reduction of production costs.
  • a test method for a packaged chip comprising:
  • the target chip is a qualified chip.
  • the testing method further includes: after acquiring the target chip,
  • the testing method further includes: after testing the first data retention time of each memory cell on the target chip,
  • the deterioration of the data retention time of the storage unit is acquired.
  • the testing method further includes:
  • the storage unit is an abnormal storage unit
  • the target chip is a failed chip.
  • the determining that the storage unit is an abnormal storage unit if the first data retention time is less than the preset reference time includes:
  • the target chip is a failed chip
  • the preset repair time is less than the preset reference time.
  • the repairing the abnormal storage unit includes:
  • the target chip has idle redundant storage cells, and the number of idle redundant storage cells is not less than the number of abnormal storage cells, the abnormal storage cells are replaced with redundant storage cells, wherein the abnormal storage cells are replaced by redundant storage cells.
  • the storage unit and the redundant storage unit One-to-one correspondence between the storage unit and the redundant storage unit;
  • the third data retention time is adjusted through the fuses of the redundant memory cells.
  • the above-mentioned testing method for a packaged chip includes: acquiring a target chip; in the post-collapse testing process, testing the first data retention time of each storage unit on the target chip; comparing the first data retention time of each of the storage units and a preset reference time; if the first data retention time is not less than the preset reference time, it is determined that the target chip is a qualified chip.
  • the first data retention time of each storage unit on the target chip is tested during the post-collapse test, and when the first data retention time is not less than the preset reference time, the target chip is determined to be a qualified chip, and the process is continued. Subsequent tests; the present application can screen out the products that meet the requirements during the collapse test process, which reduces the test cost and improves the test efficiency compared with the prior art.
  • a test system for packaging chips, used for testing target chips, the system includes:
  • test module for testing the data retention time of each storage unit on the target chip
  • control module connected with the test module, for controlling the test module to test the data retention time of each of the storage units in the post-collapse test process to obtain the first data retention time
  • a setting module for setting the preset reference time of the storage unit
  • control module connected to the test module, the setting module and the control module respectively, for comparing the first data retention time and the preset reference time of each of the storage units, and sending the comparison result To the control module, the control module is configured to determine that the target chip is a qualified chip when the first data retention time is not less than the preset reference time.
  • control module is further configured to control the test module to test the data retention time of each of the storage units during the pre-collapse test process to obtain the second data retention time;
  • the calculation module is further configured to compare the first data retention time with the second data retention time, and send the comparison result to the control module, and the control module is configured to obtain the storage according to the comparison result. Degradation of the data retention time of the cell.
  • the setting module is further configured to set a preset repair time of the storage unit
  • the calculation module is further configured to compare the first data retention time with the preset repair time, and send the comparison result to the control module, and the control module is further configured to perform a comparison when the first data retention time is less than During the preset repair time, it is determined that the target chip is a failed chip;
  • the preset repair time is less than the preset reference time.
  • a computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of any one of the testing methods described above are implemented.
  • the test system, computer equipment and computer-readable storage medium of the above-mentioned packaged chip by testing the first data retention time of each storage unit on the target chip in the post-collapse test process, the first data retention time is not less than the preset reference.
  • the application can screen out the products that meet the requirements during the collapse test process, which reduces the test cost and improves the test compared with the prior art. efficient.
  • FIG. 1 is an exemplary temperature profile of a target chip collapse test
  • FIG. 2 is a schematic flowchart of a method for testing a packaged chip in one embodiment
  • FIG. 3 is a schematic flowchart of a method for testing a packaged chip in another embodiment
  • FIG. 4 is a schematic flowchart of a step of repairing the abnormal storage unit in one embodiment
  • FIG. 5 is a structural block diagram of a testing system for packaging chips in one embodiment.
  • connection in the following embodiments should be understood as “electrical connection”, “communication connection” and the like if there is transmission of electrical signals or data between the objects to be connected.
  • the collapse test process of electronic products is as follows: after heating the electronic product to a predetermined temperature, apply a voltage to the electronic product and input test data to make it work for a certain period of time to accelerate its aging process, and observe whether it fails during the test. The product is then eliminated to prevent it from flowing into the hands of customers.
  • Figure 1 which is an exemplary temperature curve of the target chip crash test
  • the temperature T1 corresponds to the temperature during the crash pre-test
  • the crash pre-test is used to confirm whether the target chip has functional defects before the crash test. , such as poor contact.
  • the temperature T2 corresponds to the temperature during the pre-collapse test, and the pre-collapse test is used to confirm whether the target chip has a functional loss of the chip at the temperature T2.
  • the temperature T3 corresponds to the temperature during the collapse test. Under the acceleration factor test of the high temperature and high pressure of the collapse test, the manufacturing defects of the target chip can be detected early.
  • the temperature T4 corresponds to the temperature of the post-collapse test, and the post-collapse test is used to confirm whether the target chip still has functional defects at the temperature T4.
  • the temperature T5 corresponds to the temperature at which the temperature drops after the collapse test.
  • a method for testing a packaged chip including:
  • the first data retention time of each memory cell on the target chip is tested.
  • the target chip includes a storage unit, and the first data retention time refers to the time during which data stored in the storage unit remains unchanged.
  • the method for testing the data retention time of the storage unit is: write the test data into the target storage unit, read the stored data in the target storage unit after the reference time, and compare the stored data with the test data. If the saved data read from the storage unit is the same as the test data, the data retention time of the target storage unit is equal to or greater than the reference time; if the saved data read from the target storage unit is different from the test data, the data of the target storage unit The hold time is less than the reference time.
  • the storage units on the target chip are respectively used as target storage units, and the preset reference time is used as the reference time. If the saved data read from the storage unit after the preset reference time is the same as the test data, it is considered that the first storage unit of the storage unit is the same as the test data.
  • the data retention time is not less than the preset reference time; otherwise, it is considered that the first data retention time of the storage unit is less than the preset reference time, and the first data retention time and preset reference time of each storage unit on the target chip can be obtained by the above method. The relationship between.
  • the preset reference time means that when the data retention time of the storage unit on the target chip reaches the value, the target chip is considered to meet the requirements and is a qualified product.
  • the preset reference time is determined according to customer requirements or JEDC standards.
  • the preset reference time may be 96ms, 128ms, or the like.
  • the target chip is a qualified chip.
  • the first data retention time of each storage unit on the target chip is tested, and then whether the target chip is a qualified chip is determined according to the first data retention time and the preset reference time. When the chip is qualified, continue with the follow-up test. In this way, a target chip whose data retention time meets the requirements can be obtained during the collapse test process, which improves the test efficiency and reduces the test cost.
  • the testing method further includes: after acquiring the target chip:
  • the testing method further includes: after testing the first data retention time of each storage unit on the target chip,
  • the deterioration of the data retention time of the storage unit is acquired.
  • the data retention time of each memory cell before and after the crash test can be obtained.
  • the testing method further includes:
  • the target chip whose data retention time of the abnormal storage and storage cells after restoration is not less than the preset reference time is used as a secondary chip, thereby improving the target chip performance. yield and reduce production costs.
  • determining that the storage unit is an abnormal storage unit includes:
  • the target chip is a failed chip
  • the preset repair time is less than the preset reference time.
  • the preset repair time refers to that when the data retention time of the abnormal storage unit is greater than or equal to the preset repair time, the data retention time of the abnormal storage unit can be repaired to the preset reference time through the redundant storage unit in the target chip; when When the data retention time of the abnormal storage unit is less than the preset repair time, the data retention time of the abnormal storage unit cannot be repaired to the preset reference time by the redundant storage unit in the target chip.
  • the target chip When the target chip includes abnormal memory cells, and the data retention time of the abnormal memory cells is greater than or equal to the preset repair time and less than the preset reference time, if the data retention time of the abnormal memory cells is stored by redundant memory cells in the target chip If it is repaired to a value greater than or equal to the preset reference time, the target chip is a secondary chip; if the data retention time of the abnormal storage unit is repaired to a value less than the preset reference time through the redundant storage unit in the target chip, the target chip The chip is a failed chip.
  • the target chip is a failed chip.
  • the repairing the abnormal storage unit includes:
  • the abnormal storage unit is replaced with a redundant storage unit.
  • the target chip has idle redundant storage cells, and the number of idle redundant storage cells is not less than the number of abnormal storage cells, the abnormal storage cells are replaced with redundant storage cells, wherein the abnormal storage cells are replaced by redundant storage cells.
  • the storage units are in one-to-one correspondence with the redundant storage units.
  • the target chip When the target chip has abnormal storage cells whose data retention time is less than the preset reference time, check whether the target chip has idle redundant storage cells and the number of idle redundant storage cells.
  • the number of abnormal storage cells in the target chip is greater than or equal to
  • the abnormal memory cells in the target chip are replaced with redundant memory cells, and the abnormal memory cells are in one-to-one correspondence with the redundant memory cells, and the redundant memory cells are used instead of abnormal memory cells for data storage.
  • the redundant storage unit that replaced the abnormal storage unit After replacing the abnormal storage unit with the redundant storage unit, use the redundant storage unit that replaced the abnormal storage unit as a new storage unit, and test the third data retention time of these redundant storage units during the post-collapse test.
  • the third data retention time is adjusted by using the fuses of the remaining memory cells. If the data storage time of these redundant memory cells is not less than the preset reference time, it is determined that the target chip has been repaired through these redundant memory cells. It is a secondary chip; otherwise, it is determined that the target chip has not been repaired, and the target chip is a failed chip.
  • the test process of the test method for the packaged chip is exemplified below.
  • the second data retention time of each storage unit on the target chip is tested, and the location information of each storage unit is recorded; after the collapse During the test, the first data retention time of each storage unit on the target chip is tested, and the location information of each storage unit is recorded; by comparing the first data retention time and the second data retention time of the storage units with the same location information, we can obtain The deterioration of the data retention time of each storage unit is obtained, and the monitoring of the manufacturing process is realized.
  • the target chip is a qualified chip; when the first data retention time is less than the preset reference time and not less than the preset repair time (the preset repair time is less than the preset reference time) time), it is determined that the storage unit with abnormal data retention time on the target chip can be repaired through redundant storage units, and if the third data retention time measured in the repair process is not less than the preset reference time, it is determined that the target chip It has been repaired as a secondary chip, otherwise the target chip is determined to be a failed chip. When the first data retention time is less than the preset repair time, it is determined that the target chip is a failed chip.
  • the above-mentioned testing method for a packaged chip includes: acquiring a target chip; in the post-collapse testing process, testing the first data retention time of each storage unit on the target chip; comparing the first data retention time of each of the storage units and a preset reference time; if the first data retention time is not less than the preset reference time, it is determined that the target chip is a qualified chip.
  • the first data retention time of each storage unit on the target chip is tested during the post-collapse test, and when the first data retention time is not less than the preset reference time, the target chip is determined to be a qualified chip, and the process is continued. Subsequent tests; the present application can screen out the products that meet the requirements during the collapse test process, which reduces the test cost and improves the test efficiency compared with the prior art.
  • a test system for packaging chips for testing target chips, and the system includes:
  • the test module 102 is used to test the data retention time of each storage unit on the target chip.
  • the control module 104 is connected to the test module 102, and is used for controlling the test module 102 to test the data retention time of each of the storage units during the post-collapse test process to obtain the first data retention time.
  • the setting module 106 is configured to set the preset reference time of the storage unit.
  • the calculation module 108 is respectively connected with the test module 102, the setting module 106 and the control module 104, and is used to compare the first data retention time and the preset reference time of each storage unit, and compare the The result is sent to the control module 104, and the control module 104 is configured to determine that the target chip is a qualified chip when the first data retention time is not less than the preset reference time.
  • control module 104 is further configured to control the test module 102 to test the data retention time of each of the storage units during the pre-collapse test process to obtain the second data retention time;
  • the calculation module 108 is further configured to compare the first data retention time with the second data retention time, and send the comparison result to the control module 104, and the control module 104 is configured to, according to the comparison result, The deterioration of the data retention time of the storage unit is acquired.
  • the setting module 106 is further configured to set a preset repair time of the storage unit
  • the computing module is further configured to compare the first data retention time with the preset repair time, and send the comparison result to the control module 104, and the control module 104 is further configured to hold the first data during the first data retention period. When the time is less than the preset repair time, it is determined that the target chip is a failed chip;
  • the preset repair time is less than the preset reference time.
  • the testing system for packaged chips of the present invention corresponds to the testing method for packaged chips one-to-one.
  • the technical features and beneficial effects described in the above embodiments of the testing method for packaged chips are applicable to the embodiments of the testing system for packaged chips. , hereby declares.
  • a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above-mentioned testing methods when the processor executes the computer program.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps of any of the methods described above.
  • the test system, computer equipment and computer-readable storage medium of the above-mentioned packaged chip by testing the first data retention time of each storage unit on the target chip in the post-collapse test process, the first data retention time is not less than the preset reference.
  • the application can screen out the products that meet the requirements during the collapse test process, which reduces the test cost and improves the test compared with the prior art. efficient.
  • Non-volatile memory may include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, or optical memory, and the like.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • the RAM may be in various forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

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Abstract

本申请涉及一种封装芯片的测试方法、系统、计算机设备和存储介质。所述方法包括：获取目标芯片；在崩应后测试过程中，测试所述目标芯片上各个存储单元的第一数据保持时间；比较各个所述存储单元的所述第一数据保持时间和预设参考时间；若所述第一数据保持时间均不小于预设参考时间，则判定所述目标芯片为合格芯片。本申请通过在崩应后测试过程中测试目标芯片上各个存储单元的第一数据保持时间，在第一数据保持时间均不小于预设参考时间时，判定所述目标芯片为合格芯片，继续进行后续的测试，在崩应测试过程中即可筛选出符合要求的产品，与现有技术相比，降低了测试成本，提高了测试效率。

Description

封装芯片的测试方法、系统、计算机设备和存储介质
本申请要求于2020年7月17日提交中国专利局，申请号为2020106896899，申请名称为“封装芯片的测试方法、系统、计算机设备和存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路老化测试领域，特别是涉及封装芯片的测试方法、测试系统、计算机设备及计算机可读存储介质。
背景技术
包括芯片在内的电子产品生产出来后在出厂之前需要进行崩应测试即老化测试(BI：Burn In)，以筛选出在正常使用过程中会早期失效的电子产品，避免把这些会早期失效的电子产品交付给客户。因此，崩应测试是电子产品在出厂之前的一个必不可少的处理。
崩应测试之后进行成品测试，筛选出不合格的产品，对于存储芯片来说，经过崩应测试，存储芯片的数据保持时间会出现一定程度的劣化，在成品测试中还需要加入测试存储芯片的数据保持时间的步骤，存储芯片的数据保持时间符合规格判定为合格产品，否则判定为次级产品或失效产品。次级产品或失效产品在经过层层测试后，在成品测试时才被筛选出来，不利于产品良率的提高和生产成本的降低。
发明内容
基于此，有必要针对上述技术问题，提供一种封装芯片的测试方法，测试系统、计算机设备及计算机可读存储介质。
一种封装芯片的测试方法，包括：
获取目标芯片；
在崩应后测试过程中，测试所述目标芯片上各个存储单元的第一数据保持时间；
比较各个所述存储单元的所述第一数据保持时间和预设参考时间；
若所述第一数据保持时间均不小于预设参考时间，则判定所述目标芯片为合格芯片。
在其中一个实施例中，所述测试方法还包括：在获取目标芯片之后，
在崩应前测试过程中，测试所述目标芯片上各个存储单元的第二数据保持时间；
所述测试方法还包括：在测试所述目标芯片上各个存储单元的第一数据保持时间之后，
根据所述第一数据保持时间、第二数据保持时间，获取所述存储单元的数据保持时间的劣化情况。
在其中一个实施例中，所述测试方法还包括：
若所述第一数据保持时间小于所述预设参考时间，则判定所述存储单元为异常存储单元；
对所述异常存储单元进行修复；
测试所述异常存储单元的第三数据保持时间；
若所述第三数据保持时间小于所述预设参考时间，则判定所述目标芯片为失效芯片。
在其中一个实施例中，所述若所述第一数据保持时间小于所述预设参考时间，则判定所述存储单元为异常存储单元，包括：
若所述第一数据保持时间小于预设修复时间，则判定所述目标芯片为失 效芯片；
其中，所述预设修复时间小于所述预设参考时间。
在其中一个实施例中，所述对所述异常存储单元进行修复，包括：
当目标芯片具有闲置的冗余存储单元，且所述闲置的冗余存储单元的数量不小于所述异常存储单元的数量时，使用冗余存储单元替换所述异常存储单元，其中，所述异常存储单元和所述冗余存储单元一一对应；
通过所述冗余存储单元的熔丝调整所述第三数据保持时间。
上述封装芯片的测试方法包括：获取目标芯片；在崩应后测试过程中，测试所述目标芯片上各个存储单元的第一数据保持时间；比较各个所述存储单元的所述第一数据保持时间和预设参考时间；若所述第一数据保持时间均不小于预设参考时间，则判定所述目标芯片为合格芯片。本申请通过在崩应后测试过程中测试目标芯片上各个存储单元的第一数据保持时间，在第一数据保持时间均不小于预设参考时间时，判定所述目标芯片为合格芯片，继续进行后续的测试；本申请在崩应测试过程中即可筛选出符合要求的产品，与现有技术相比，降低了测试成本，提高了测试效率。
一种封装芯片的测试系统，用于测试目标芯片，所述系统包括：
测试模块，用于测试所述目标芯片上各个存储单元的数据保持时间；
控制模块，与所述测试模块连接，用于在崩应后测试过程中，控制所述测试模块对各个所述存储单元的数据保持时间进行测试，得到第一数据保持时间；
设置模块，用于设置所述存储单元的预设参考时间；
计算模块，分别与所述测试模块、所述设置模块和所述控制模块连接，用于比较各个所述存储单元的所述第一数据保持时间和所述预设参考时间，并将比较结果发送给所述控制模块，所述控制模块用于在所述第一数据保持 时间均不小于所述预设参考时间时，判定所述目标芯片为合格芯片。
在其中一个实施例中，所述控制模块还用于在崩应前测试过程中，控制所述测试模块对各个所述存储单元的数据保持时间进行测试，得到第二数据保持时间；
所述计算模块还用于比较所述第一数据保持时间和所述第二数据保持时间，并将比较结果发送给所述控制模块，所述控制模块用于根据所述比较结果获取所述存储单元的数据保持时间的劣化情况。
在其中一个实施例中，所述设置模块还用于设置所述存储单元的预设修复时间；
所述计算模块还用于比较所述第一数据保持时间和所述预设修复时间，并将比较结果发送给所述控制模块，所述控制模块还用于在所述第一数据保持时间小于所述预设修复时间时，判定所述目标芯片为失效芯片；
其中，所述预设修复时间小于所述预设参考时间。
一种计算机设备，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时实现上述任一项所述的测试方法的步骤。
一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述任一项所述的测试方法的步骤。
上述封装芯片的测试系统、计算机设备及计算机可读存储介质，通过在崩应后测试过程中测试目标芯片上各个存储单元的第一数据保持时间，在第一数据保持时间均不小于预设参考时间时，判定所述目标芯片为合格芯片，继续进行后续的测试；本申请在崩应测试过程中即可筛选出符合要求的产品，与现有技术相比，降低了测试成本，提高了测试效率。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为示例性的对目标芯片崩应测试的温度曲线图；
图2为一个实施例中封装芯片的测试方法的流程示意图；
图3为另一个实施例中封装芯片的测试方法的流程示意图；
图4为一个实施例中对所述异常存储单元进行修复的步骤的流程示意图；
图5为一个实施例中封装芯片的测试系统的结构框图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
可以理解，本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件 与另一个元件区分。
需要说明的是，当一个元件被认为是“连接”另一个元件时，它可以是直接连接到另一个元件，或者通过居中元件连接另一个元件。此外，以下实施例中的“连接”，如果被连接的对象之间具有电信号或数据的传递，则应理解为“电连接”、“通信连接”等。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。
电子产品的崩应测试过程具体如下：把电子产品加热到预定温度之后，向电子产品施加电压和输入测试数据使其工作一定时间以加速其老化过程，在测试期间观察其是否失效，如果其失效则将该产品剔除避免流入客户手中。如图1所示，为对目标芯片崩应测试的示例性的温度曲线图，温度T1对应崩应预测试时的温度，崩应预测试用于确认目标芯片崩应测试前是否已有功能性缺失，例如接触不良。温度T2对应崩应前测试时的温度，崩应前测试用于确认目标芯片在温度T2时是否已产生芯片功能性缺失。温度T3对应崩应测试时的温度，在崩应测试的高温及高压的加速因子测试下，目标芯片的制造缺陷能早期侦测出来。温度T4对应崩应后测试的温度，崩应后测试用于确认目标芯片在温度T4时是否仍有功能性缺失。温度T5对应崩应测试后降温的温度。
如图2所示，在其中一个实施例中，提供一种封装芯片的测试方法，包括：
S102，获取目标芯片。
S104，获取目标芯片上各个存储单元的第一数据保持时间。
在崩应后测试过程中，测试所述目标芯片上各个存储单元的第一数据保持时间。
目标芯片包括存储单元，第一数据保持时间是指存储单元上存储的数据保持不变的时间。
S106，比较各个所述存储单元的所述第一数据保持时间和预设参考时间。
测试存储单元的数据保持时间的方法为：将测试数据写入目标存储单元中，经过参考时间后读取目标存储单元内的保存数据，并将所述保存数据与测试数据进行比较，若从目标存储单元中读取的保存数据与测试数据相同，则目标存储单元的数据保持时间等于或大于参考时间；若从目标存储单元中读取的保存数据与测试数据不相同，则目标存储单元的数据保持时间小于参考时间。
将目标芯片上的存储单元分别作为目标存储单元，预设参考时间作为参考时间，若经过预设参考时间后从存储单元上读取的保存数据与测试数据相同，则认为该存储单元的第一数据保持时间不小于预设参考时间；否则，认为该存储单元的第一数据保持时间小于预设参考时间，通过上述方法可以得到目标芯片上各个存储单元的第一数据保持时间和预设参考时间之间的关系。
S108，若所述第一数据保持时间均不小于预设参考时间，则判定所述目标芯片为合格芯片。
预设参考时间是指当目标芯片上的存储单元的数据保持时间达到该值时，认为该目标芯片符合要求，为合格产品。预设参考时间是根据客户要求或者JEDC标准确定的。例如预设参考时间可以是96ms、128ms等。
当目标芯片上各个存储单元的第一数据保持时间均不小于预设参考时间，则判定所述目标芯片为合格芯片。
在目标芯片的崩应后测试过程中，测试目标芯片上各个存储单元的第一 数据保持时间，然后根据第一数据保持时间和预设参考时间来判定目标芯片是否为合格芯片，当目标芯片为合格芯片时，继续进行后续测试。通过该方式在崩应测试过程中即可得到数据保持时间符合要求的目标芯片，提高了测试效率，降低了测试成本。
在其中一个实施例中，该测试方法还包括：在获取目标芯片之后：
在崩应前测试过程中，测试所述目标芯片上各个存储单元的第二数据保持时间；
该测试方法还包括：在测试所述目标芯片上各个存储单元的第一数据保持时间之后，
根据所述第一数据保持时间、第二数据保持时间，获取所述存储单元的数据保持时间的劣化情况。
通过比较目标芯片上各个存储单元在崩应前测试过程中的第一数据保持时间和在崩应后测试过程中的第二数据保持时间的变化，可以获取各个存储单元在崩应测试前后数据保持时间的劣化情况，当存储单元的数据保持时间变化较大时，可以推断崩应测试前的工艺出现了问题，需要检查和调整崩应测试前的工艺，因此，可以通过前后数据保持时间的对比，达到及时发现工艺异常，降低异常对目标芯片的影响的目的。
如图3所示，在其中一个实施例中，所述测试方法还包括：
S202，若所述第一数据保持时间小于所述预设参考时间，则判定所述存储单元为异常存储单元。
S204，对所述异常存储单元进行修复。
S206，测试所述异常存储单元的第三数据保持时间。
S208，若所述第三数据保持时间小于所述预设参考时间，则判定所述目标芯片为失效芯片。
通过对第一数据保持时间小于预设参考时间的存储单元进行修复，将修复后异常储存储单元的数据保持时间均不小于预设参考时间的目标芯片作为次级芯片进行使用，提高了目标芯片的良率，降低了生产成本。
在其中一个实施例中，若所述第一数据保持时间小于所述预设参考时间，则判定所述存储单元为异常存储单元，包括：
若所述第一数据保持时间小于预设修复时间，则判定所述目标芯片为失效芯片；
其中，所述预设修复时间小于所述预设参考时间。
预设修复时间指的是当异常存储单元的数据保持时间大于或等于预设修复时间时，通过目标芯片中的冗余存储单元可以将异常存储单元的数据保持时间修复为预设参考时间；当异常存储单元的数据保持时间小于预设修复时间时，通过目标芯片中的冗余存储单元不能将异常存储单元的数据保持时间修复为预设参考时间。
当目标芯片中包括异常存储单元，且异常存储单元的数据保持时间大于或等于预设修复时间且小于预设参考时间时，若通过目标芯片中的冗余存储单元将异常存储单元的数据保持时间修复为大于或等于预设参考时间的数值，则目标芯片为次级芯片；若通过目标芯片中的冗余存储单元将异常存储单元的数据保持时间修复为小于预设参考时间的数值，则目标芯片为失效芯片。
当目标芯片中存储单元的第一数据保持时间小于预设修复时间时，判定数据保持异常的存储单元不能被修复，目标芯片为失效芯片。
如图4所示，在其中一个实施例中，所述对所述异常存储单元进行修复，包括：
S302，使用冗余存储单元替换异常存储单元。
当目标芯片具有闲置的冗余存储单元，且所述闲置的冗余存储单元的数量不小于所述异常存储单元的数量时，使用冗余存储单元替换所述异常存储单元，其中，所述异常存储单元和所述冗余存储单元一一对应。
当目标芯片存在数据保持时间小于预设参考时间的异常存储单元时，检查目标芯片是否存在闲置的冗余存储单元以及闲置的冗余存储单元的数量，当目标芯片存在数量大于或等于异常存储单元数量的冗余存储单元时，将目 标芯片中的异常存储单元替换成冗余存储单元，异常存储单元与冗余存储单元一一对应，使用冗余存储单元代替异常存储单元进行数据的存储。
S304，通过所述冗余存储单元的熔丝调整所述第三数据保持时间。
使用冗余存储单元替换异常存储单元后，将替换异常存储单元的冗余存储单元作为新的存储单元，在崩应后测试过程中测试这些冗余存储单元的第三数据保持时间，同时通过冗余存储单元的熔丝来调整第三数据保持时间，若这些冗余存储单元的数据存储时间均不小于预设参考时间，则判定通过这些冗余存储单元实现了对目标芯片的修复，目标芯片为次级芯片；否则，判定未实现对目标芯片的修复，目标芯片为失效芯片。
以下对封装芯片的测试方法的测试过程进行实例性说明，在崩应前测试过程中，测试目标芯片上各个存储单元的第二数据保持时间，并记录各个存储单元的位置信息；在崩应后测试过程中，测试目标芯片上各个存储单元的第一数据保持时间，并记录各个存储单元的位置信息；通过比较位置信息相同的存储单元的第一数据保持时间和第二数据保持时间，可以得出各个存储单元的数据保持时间的劣化情况，实现对制程工艺的监控。当第一数据保持时间均不小于预设参考时间时，判定该目标芯片为合格芯片；当第一数据保持时间小于预设参考时间且不小于预设修复时间(预设修复时间小于预设参考时间)时，判定可以通过冗余存储单元对该目标芯片上数据保持时间异常的存储单元进行修复，若修复过程中测得的第三数据保持时间均不小于预设参考时间，判定该目标芯片已修复为次级芯片，否则判定该目标芯片为失效芯片。第一数据保持时间小于预设修复时间时，判定该目标芯片为失效芯片。
上述封装芯片的测试方法包括：获取目标芯片；在崩应后测试过程中，测试所述目标芯片上各个存储单元的第一数据保持时间；比较各个所述存储单元的所述第一数据保持时间和预设参考时间；若所述第一数据保持时间均不小于预设参考时间，则判定所述目标芯片为合格芯片。本申请通过在崩应后测试过程中测试目标芯片上各个存储单元的第一数据保持时间，在第一数 据保持时间均不小于预设参考时间时，判定所述目标芯片为合格芯片，继续进行后续的测试；本申请在崩应测试过程中即可筛选出符合要求的产品，与现有技术相比，降低了测试成本，提高了测试效率。
如图5所示，在其中一个实施例中，提供一种封装芯片的测试系统，用于测试目标芯片，所述系统包括：
测试模块102，用于测试所述目标芯片上各个存储单元的数据保持时间。
控制模块104，与所述测试模块102连接，用于在崩应后测试过程中，控制所述测试模块102对各个所述存储单元的数据保持时间进行测试，得到第一数据保持时间。
设置模块106，用于设置所述存储单元的预设参考时间。
计算模块108，分别与所述测试模块102、所述设置模块106和所述控制模块104连接，用于比较各个存储单元的所述第一数据保持时间和所述预设参考时间，并将比较结果发送给控制模块104，所述控制模块104用于在所述第一数据保持时间均不小于所述预设参考时间时，判定所述目标芯片为合格芯片。
在其中一个实施例中，所述控制模块104还用于在崩应前测试过程中，控制所述测试模块102对各个所述存储单元的数据保持时间进行测试，得到第二数据保持时间；
所述计算模块108还用于比较所述第一数据保持时间和所述第二数据保持时间，并将比较结果发送给所述控制模块104，所述控制模块104用于根据所述比较结果，获取所述存储单元的数据保持时间的劣化情况。
在其中一个实施例中，所述设置模块106还用于设置所述存储单元的预设修复时间；
所述计算模块还用于比较所述第一数据保持时间和所述预设修复时间，并将比较结果发送给所述控制模块104，所述控制模块104还用于在所述第一数据保持时间小于所述预设修复时间时，判定所述目标芯片为失效芯片；
其中，所述预设修复时间小于所述预设参考时间。
本发明的封装芯片的测试系统与封装芯片的测试方法一一对应，在上述封装芯片的测试方法的实施例阐述的技术特征及其有益效果均适用于所述封装芯片的测试系统的实施例中，特此声明。
在其中一个实施例中，提供一种计算机设备，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时实现上述任一项所述的测试方法的步骤。
在其中一个实施例中，提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述任一项所述的方法的步骤。
上述封装芯片的测试系统、计算机设备及计算机可读存储介质，通过在崩应后测试过程中测试目标芯片上各个存储单元的第一数据保持时间，在第一数据保持时间均不小于预设参考时间时，判定所述目标芯片为合格芯片，继续进行后续的测试；本申请在崩应测试过程中即可筛选出符合要求的产品，与现有技术相比，降低了测试成本，提高了测试效率。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和易失性存储器中的至少一种。非易失性存储器可包括只读存储器(Read-Only  Memory，ROM)、磁带、软盘、闪存或光存储器等。易失性存储器可包括随机存取存储器(Random Access Memory，RAM)或外部高速缓冲存储器。作为说明而非局限，RAM可以是多种形式，比如静态随机存取存储器(Static Random Access Memory，SRAM)或动态随机存取存储器(Dynamic Random Access Memory，DRAM)等。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种封装芯片的测试方法，包括：
    获取目标芯片；
    在崩应后测试过程中，测试所述目标芯片上各个存储单元的第一数据保持时间；
    比较各个所述存储单元的所述第一数据保持时间和预设参考时间；
    若所述第一数据保持时间均不小于预设参考时间，则判定所述目标芯片为合格芯片。
  2. 根据权利要求1所述的测试方法，还包括：在所述获取目标芯片之后，
    在崩应前测试过程中，测试所述目标芯片上各个存储单元的第二数据保持时间；
    还包括：在所述测试所述目标芯片上各个存储单元的第一数据保持时间之后，
    根据所述第一数据保持时间、第二数据保持时间，获取所述存储单元的数据保持时间的劣化情况。
  3. 根据权利要求1所述的测试方法，还包括：
    若所述第一数据保持时间小于所述预设参考时间，则判定所述存储单元为异常存储单元；
    对所述异常存储单元进行修复；
    测试所述异常存储单元的第三数据保持时间；
    若所述第三数据保持时间小于所述预设参考时间，则判定所述目标芯片为失效芯片。
  4. 根据权利要求3所述的测试方法，其中，所述若所述第一数据保持时 间小于所述预设参考时间，则判定所述存储单元为异常存储单元，包括：
    若所述第一数据保持时间小于预设修复时间，则判定所述目标芯片为失效芯片；
    其中，所述预设修复时间小于所述预设参考时间。
  5. 根据权利要求3所述的测试方法，其中，所述对所述异常存储单元进行修复，包括：
    当目标芯片具有闲置的冗余存储单元，且所述闲置的冗余存储单元的数量不小于所述异常存储单元的数量时，使用冗余存储单元替换所述异常存储单元，其中，所述异常存储单元和所述冗余存储单元一一对应；
    通过所述冗余存储单元的熔丝调整所述第三数据保持时间。
  6. 一种封装芯片的测试系统，用于测试目标芯片，所述系统包括：
    测试模块，用于测试所述目标芯片上各个存储单元的数据保持时间；
    控制模块，与所述测试模块连接，用于在崩应后测试过程中，控制所述测试模块对各个所述存储单元的数据保持时间进行测试，得到第一数据保持时间；
    设置模块，用于设置所述存储单元的预设参考时间；
    计算模块，分别与所述测试模块、所述设置模块和所述控制模块连接，用于比较各个所述存储单元的所述第一数据保持时间和所述预设参考时间，并将比较结果发送给所述控制模块，所述控制模块用于在所述第一数据保持时间均不小于所述预设参考时间时，判定所述目标芯片为合格芯片。
  7. 根据权利要求6所述的测试系统，其中，所述控制模块还用于在崩应前测试过程中，控制所述测试模块对各个所述存储单元的数据保持时间进行测试，得到第二数据保持时间；
    所述计算模块还用于比较所述第一数据保持时间和所述第二数据保持时间，并将比较结果发送给所述控制模块，所述控制模块用于根据所述比较结果获取所述存储单元的数据保持时间的劣化情况。
  8. 根据权利要求6所述的测试系统，其中，所述设置模块还用于设置所述存储单元的预设修复时间；
    所述计算模块还用于比较所述第一数据保持时间和所述预设修复时间，并将比较结果发送给所述控制模块，所述控制模块还用于在所述第一数据保持时间小于所述预设修复时间时，判定所述目标芯片为失效芯片；
    其中，所述预设修复时间小于所述预设参考时间。
  9. 一种计算机设备，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时实现权利要求1至5中任一项所述的测试方法的步骤。
  10. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1至5中任一项所述的测试方法的步骤。
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