WO2022011896A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022011896A1
WO2022011896A1 PCT/CN2020/126713 CN2020126713W WO2022011896A1 WO 2022011896 A1 WO2022011896 A1 WO 2022011896A1 CN 2020126713 W CN2020126713 W CN 2020126713W WO 2022011896 A1 WO2022011896 A1 WO 2022011896A1
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WIPO (PCT)
Prior art keywords
insulating layer
layer
thin film
electrode plate
electrode
Prior art date
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Ceased
Application number
PCT/CN2020/126713
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English (en)
French (fr)
Inventor
龚吉祥
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/274,690 priority Critical patent/US11895870B2/en
Publication of WO2022011896A1 publication Critical patent/WO2022011896A1/zh
Anticipated expiration legal-status Critical
Priority to US18/391,996 priority patent/US12156432B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel and a display device.
  • Low temperature polysilicon low temperature polysilicon
  • LTPS temperature poly-silicon
  • LTPO low temperature polycrystalline oxide
  • FIG. 1 is a schematic diagram of the film layer structure of a display panel using low temperature polycrystalline oxide technology in the prior art.
  • the semiconductor layers of the driving thin film transistor 11 and the switching thin film transistor 12 are respectively a polysilicon semiconductor layer and an oxide semiconductor layer.
  • layer, the storage capacitor 13 of the display panel is composed of a first gate 111 arranged on the first gate insulating layer 14 and a second gate 112 arranged on the second gate insulating layer 15, respectively.
  • the switching thin film transistor 12 The third gate 121 is separated from the metal layer where the first gate 111 and the second gate 112 are located by the third gate insulating layer 16, so that the number of film layers in the display panel is larger and the film The thickness of the laminated structure is relatively large, which leads to a complicated manufacturing process of the display panel, and also reduces the bending ability of the display panel.
  • the existing display panels adopting the low temperature polycrystalline oxide technology have the problems of a large number of film layers and a large thickness of the film layer structure, which lead to the complicated manufacturing process of the display panel and the reduced bending ability of the display panel. Therefore, it is necessary to provide a display panel and a display device to improve this defect.
  • Embodiments of the present application provide a display panel, a method for manufacturing the same, and a display device, which are used to solve the problem that the existing display panel using low temperature polycrystalline oxide technology has a large number of film layers and a large thickness of the film layer structure, which leads to the production of the display panel.
  • the problem is that the process flow is complicated and the bending ability of the display panel is reduced.
  • Embodiments of the present application provide a display panel, including:
  • the thin film transistor array layer is disposed on the base substrate, and the thin film transistor array layer is provided with a plurality of first thin film transistors, second thin film transistors and storage capacitors arranged at intervals;
  • the first thin film transistor includes a stacked polysilicon semiconductor layer and a first gate
  • the second thin film transistor includes a stacked oxide semiconductor layer and a second gate
  • the storage capacitor includes a The first grid is away from the first electrode plate on the side of the base substrate, the first grid and the first electrode plate constitute the storage capacitor, and the first electrode plate and the second grid Very homogenous settings.
  • the distance between the surface of the oxide semiconductor layer close to the base substrate and the base substrate is greater than the distance between the surface of the polysilicon semiconductor layer close to the base substrate and the base substrate The distance between the substrate substrates.
  • the thin film transistor array layer includes a first gate insulating layer and a first interlayer insulating layer that are sequentially stacked on the polysilicon semiconductor layer, and the first gate is disposed on the first gate insulating layer. Between a gate insulating layer and the first interlayer insulating layer, the oxide semiconductor layer is disposed on a side of the first interlayer insulating layer away from the first gate insulating layer.
  • the first interlayer insulating layer is a stacked structure formed of silicon nitride and silicon oxide materials, and the atomic percentage of silicon-hydrogen bonds in the first interlayer insulating layer is between 20% ⁇ 30%.
  • the thin film transistor array layer further includes a second gate insulating layer and a second interlayer stacked on a side of the first interlayer insulating layer away from the first gate insulating layer an insulating layer, the first electrode plate and the second gate electrode are both disposed between the second gate insulating layer and the second interlayer insulating layer.
  • the first electrode plate and the second gate electrode are made of the same layer of metal.
  • the storage capacitor includes a first capacitor and a second capacitor connected in parallel, a second electrode plate is provided between the first gate and the first electrode plate, and the second electrode plate The first capacitor and the second capacitor are respectively formed with the first grid and the first electrode plate.
  • the orthographic projection area of the second electrode plate on the base substrate overlaps with the orthographic projection area of the first grid or the first electrode plate on the base substrate .
  • the second electrode plate and the oxide semiconductor layer are disposed in the same layer.
  • the second electrode plate and the oxide semiconductor layer are made of the same layer of oxide material.
  • the first thin film transistor includes a first source electrode and a first drain electrode
  • the second thin film transistor includes a second source electrode and a second drain electrode
  • the first source electrode and the The first drain is connected to the polysilicon semiconductor layer through first vias penetrating the second interlayer insulating layer, the second gate insulating layer, the first interlayer insulating layer and the first gate insulating layer, respectively, so that the The second source electrode and the second drain electrode are connected to the oxide semiconductor layer through second via holes penetrating through the second interlayer insulating layer and the second gate insulating layer, respectively.
  • An embodiment of the present application provides a display device, including a device body and a display panel disposed on the device body, the display panel comprising:
  • the thin film transistor array layer is disposed on the base substrate, and the thin film transistor array layer is provided with a plurality of first thin film transistors, second thin film transistors and storage capacitors arranged at intervals;
  • the first thin film transistor includes a stacked polysilicon semiconductor layer and a first gate
  • the second thin film transistor includes a stacked oxide semiconductor layer and a second gate
  • the storage capacitor includes a The first grid is away from the first electrode plate on the side of the base substrate, the first grid and the first electrode plate constitute the storage capacitor, and the first electrode plate and the second grid Very homogenous settings.
  • the distance between the surface of the oxide semiconductor layer close to the base substrate and the base substrate is greater than the distance between the surface of the polysilicon semiconductor layer close to the base substrate and the base substrate The distance between the substrate substrates.
  • the thin film transistor array layer includes a first gate insulating layer and a first interlayer insulating layer that are sequentially stacked on the polysilicon semiconductor layer, and the first gate is disposed on the first gate insulating layer. Between a gate insulating layer and the first interlayer insulating layer, the oxide semiconductor layer is disposed on a side of the first interlayer insulating layer away from the first gate insulating layer.
  • the first interlayer insulating layer is a stacked structure formed of silicon nitride and silicon oxide materials, and the atomic percentage of silicon-hydrogen bonds in the first interlayer insulating layer is between 20% ⁇ 30%.
  • the thin film transistor array layer further includes a second gate insulating layer and a second interlayer stacked on a side of the first interlayer insulating layer away from the first gate insulating layer an insulating layer, the first electrode plate and the second gate electrode are both disposed between the second gate insulating layer and the second interlayer insulating layer.
  • the first electrode plate and the second gate electrode are made of the same layer of metal.
  • the storage capacitor includes a first capacitor and a second capacitor connected in parallel, a second electrode plate is provided between the first gate and the first electrode plate, and the second electrode plate The first capacitor and the second capacitor are respectively formed with the first grid and the first electrode plate.
  • the orthographic projection area of the second electrode plate on the base substrate overlaps with the orthographic projection area of the first grid or the first electrode plate on the base substrate .
  • Embodiments of the present application further provide a display device, including a device body and a display panel disposed on the device body, the display panel including:
  • the thin film transistor array layer is disposed on the base substrate, and the thin film transistor array layer is provided with a plurality of first thin film transistors, second thin film transistors and storage capacitors arranged at intervals;
  • the first thin film transistor includes a stacked polysilicon semiconductor layer and a first gate electrode
  • the second thin film transistor includes a stacked oxide semiconductor layer and a second gate electrode
  • the thin film transistor array layer further includes sequentially A first gate insulating layer, a first interlayer insulating layer, a second gate insulating layer and a second interlayer insulating layer are stacked on the polysilicon semiconductor layer
  • the storage capacitor includes a first gate insulating layer arranged on the first gate
  • the first electrode plate on the side far away from the base substrate, the first grid electrode and the first electrode plate constitute the storage capacitor, and the first electrode plate and the second grid electrode are in the same layer is disposed between the second gate insulating layer and the second interlayer insulating layer.
  • Embodiments of the present application also provide a method for manufacturing a display panel, including:
  • a metal material is deposited on the side of the second gate insulating layer away from the base substrate, and a plurality of spaced first electrode plates and second grid electrodes are formed through a patterning process, the first electrode plate forming a storage capacitor with the first gate;
  • a first source electrode, a first drain electrode, a second source electrode and a second drain electrode are formed on the side of the second gate electrode away from the second gate insulating layer.
  • a drain electrode, a first gate electrode, and the polysilicon semiconductor layer constitute a first thin film transistor, and the second source electrode, the second drain electrode, the second gate electrode, and the oxide semiconductor layer constitute a second thin film transistor. thin film transistor.
  • the step of forming the oxide semiconductor layer includes:
  • a plurality of the oxide semiconductor layers and the second electrode plates are formed at intervals, and the second electrode plates and the first gate electrode and the first electrode plate respectively constitute the storage capacitor the first capacitor and the second capacitor.
  • the first gate electrode and the first electrode plate of the first thin film transistor are used to form a storage capacitor, and at the same time, the first electrode plate and the second gate electrode of the second thin film transistor are arranged in the same layer.
  • the gate insulating layer used to separate the first electrode plate from the first gate electrode and the second gate electrode can be omitted, thereby reducing the number of film layers in the display panel and the thickness of the film layer structure, thereby reducing the display
  • FIG. 1 is a schematic diagram of a film layer structure of a display panel in the prior art
  • FIG. 2 is a schematic diagram of a film layer structure of a first display panel provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of a film layer structure of a second display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 5A to FIG. 5I are schematic diagrams of the film layer structure of the display panel corresponding to the first method for fabricating the display panel provided by the embodiments of the present application.
  • FIGS. 6A to 6B are schematic diagrams of the film layer structure of the display panel corresponding to the second method for fabricating the display panel provided by the embodiments of the present application.
  • FIG. 2 is a schematic diagram of a film layer structure of the display panel provided by the embodiment of the present application.
  • the display panel provided by the embodiment of the present application includes a base substrate 20 , a thin film transistor array layer 21 disposed on the base substrate 20 , and a display device layer disposed on a side of the thin film transistor array layer 21 away from the base substrate 20 .
  • the substrate substrate 20 includes a first substrate, a barrier layer, a second substrate, a buffer layer, and a third substrate (not shown in the figure) that are stacked in sequence.
  • the first substrate and the second substrate The substrates are all made of polyimide material, and the third substrate is a laminated structure formed of silicon nitride, silicon oxide and amorphous silicon materials.
  • the material and structure of the base substrate 20 are not limited to the materials and structures provided in the embodiments of the present application. In other embodiments, the base substrate 20 may also be of other structures and materials, which are not limited here.
  • the display panel provided by the embodiment of the present application may be an organic light emitting diode display panel, and the display device layer includes a flat layer 22 disposed on the side of the thin film transistor array layer 21 away from the base substrate 20, a pixel definition layer 23, A plurality of spacers 24 on the surface of one side of the layer 23 and the anode 25, the light-emitting layer 26 and the cathode 27 on the side of the flat layer 22 away from the base substrate 20 are stacked and arranged, and their structures and materials are similar to the organic light-emitting diodes in the prior art The display devices are the same, and are not repeated here.
  • the display devices in the display device layer are not limited to the organic light emitting diode devices in the embodiments of the present application.
  • the display devices in the display device layer may also include but are not limited to micro light emitting diodes and mini light emitting diodes. and other light-emitting display devices, the types of display devices can be selected according to actual needs, which is not limited here.
  • the thin film transistor array layer 21 is provided with a plurality of first thin film transistors T1 , second thin film transistors T2 and storage capacitors C arranged at intervals.
  • the thin film transistor T2, the storage capacitor C and the circuit traces disposed in the thin film transistor array layer 21 constitute a pixel driving circuit of each sub-pixel unit in the display panel.
  • the pixel driving circuit provided by the embodiment of the present application is a 7T1C pixel driving circuit, including one driving thin film transistor, six switching thin film transistors, and one storage capacitor C, wherein the first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 is a switching thin film transistor.
  • the pixel driving circuit of the display panel may also have other circuit structures, and the number of its internal driving thin film transistors, switching thin film transistors and capacitors is not limited to the number provided in the embodiments of the present application, and the specific structure can be based on The actual needs are set, and there are no restrictions here.
  • the first thin film transistor T1 includes a stacked polysilicon semiconductor layer 210 , a first gate GE1 , a first source S1 and a first source electrode S1 disposed on a side of the first gate GE1 away from the polysilicon semiconductor layer 210 .
  • the drain D1, the second thin film transistor T2 includes a stacked oxide semiconductor layer 217, a second gate GE2, and a second source S2 and a second source S2 disposed on the side of the second gate GE2 away from the oxide semiconductor layer 217
  • the storage capacitor C includes a first electrode plate 216 disposed on the side of the first gate GE1 away from the base substrate 20, and the orthographic projection area of the first electrode plate 216 and the first gate GE1 on the base substrate 20 Both overlap with the orthographic projection area of the channel region of the polysilicon semiconductor layer 210 on the base substrate 20 , and the orthographic projection area of the second gate GE2 on the base substrate 20 and the orthographic projection area of the oxide semiconductor layer 217 on the base substrate 20 .
  • the orthographic projection area overlaps, the first electrode plate 216 and the first gate GE1 of the first thin film transistor T1 form the storage capacitor C, and the first electrode plate 216 and the second gate GE2 are disposed on the same film layer.
  • the polycrystalline silicon semiconductor layer 210 is a low temperature polycrystalline silicon semiconductor layer, and the material of the oxide semiconductor layer 217 is preferably indium gallium zinc oxide (IGZO).
  • the material of the oxide semiconductor layer 217 may also include but not limited to oxide semiconductor materials such as indium gallium oxide or indium zinc oxide. limit.
  • the distance between the surface of the oxide semiconductor layer 217 of the second thin film transistor T2 close to the base substrate 20 and the base substrate is greater than that of the polysilicon semiconductor layer 210 of the first thin film transistor T1 close to the base substrate 20 The distance between the side surface and the base substrate.
  • the thin film transistor array layer 21 includes a first gate insulating layer 211 and a first interlayer insulating layer 212 which are sequentially stacked on the polysilicon semiconductor layer 210 , and the first gate insulating layer 211 covers the polysilicon semiconductor layer.
  • the first gate GE1 is disposed between the first gate insulating layer 211 and the first interlayer insulating layer 212
  • the oxide semiconductor layer 217 is disposed on the first interlayer insulating layer 212 away from the first gate insulating layer 211 on the side.
  • the material of the first gate insulating layer 211 is silicon oxide
  • the first interlayer insulating layer 212 is a laminated structure formed of silicon nitride and silicon oxide materials
  • the silicon nitride film layer is disposed on the silicon oxide.
  • the atomic percentage of the silicon-hydrogen bond content in the first interlayer insulating layer 212 between the film layer and the first gate insulating layer 211 is 25%.
  • the atomic percentage of the silicon-hydrogen bond content in the first interlayer insulating layer 212 is not limited to the settings provided in the embodiments of the present application. In other embodiments, the silicon-hydrogen bonds in the first interlayer insulating layer 212
  • the value of the atomic percentage of the content can also include but is not limited to 20% or 30%, and its value is preferably between 20% and 30%, and the specific value can be set according to actual needs, which is not limited here.
  • the thin film transistor array layer 21 further includes a second gate insulating layer 213 and a second interlayer insulating layer 214 that are stacked on the side of the first interlayer insulating layer 212 away from the first gate insulating layer 211 .
  • the electrode plate 216 and the second gate GE2 are both disposed between the second gate insulating layer 213 and the second interlayer insulating layer 214 .
  • the display panel provided by the embodiment of the present application disposes the first electrode plate 216 of the storage capacitor and the second gate GE2 of the second thin film transistor T2 on the same layer, and uses the second gate
  • the second gate insulating layer 213 under the electrode GE2 separates the film layer where the second gate electrode GE2 and the first electrode plate 216 are located from the metal film layer where the first gate electrode GE1 is located, so that the original use for the A gate insulating layer formed of an inorganic insulating material is separated from the metal film layer where the gate electrode GE1 is located and the metal film layer where the first electrode plate 216 is located, thereby reducing the number of film layers in the display panel and the thickness of the film layer structure , thereby reducing the complexity of the display panel process and improving the bending capability of the display panel.
  • the first electrode plate 216 and the second grid electrode GE2 are made of the same layer of metal, so a mask can be used to simultaneously form the first electrode plate 216 and the second grid electrode GE2 , so that the mask and related processes required for preparing the first electrode plate 216 alone can be omitted, thereby reducing the complexity of the display panel process and the production cost.
  • the first electrode plate 216 and the second gate electrode GE2 are disposed on the same layer, they can be fabricated by using different materials and through different processes, which is not limited here.
  • the first source electrode S1 , the first drain electrode D1 , the second source electrode S2 and the second drain electrode D2 are all disposed between the second interlayer insulating layer 214 and the passivation protection layer 215 , the first source S1 and the first drain D1 pass through the second interlayer insulating layer 214 , the second gate insulating layer 213 , the first interlayer insulating layer 212 and the first gate insulating layer 211 through a plurality of first
  • the via holes are respectively connected to the first source region and the first drain region of the polycrystalline silicon semiconductor 210 , and the anode 25 disposed between the flat layer 22 and the pixel defining layer 23 is connected to the first drain electrode D1 through the via holes.
  • the second source electrode S2 and the second drain electrode D2 pass through a plurality of second via holes penetrating the second interlayer insulating layer 214 and the second gate insulating layer 213 and the second source electrode region and the second source electrode region of the oxide semiconductor layer 217 Drain region connection.
  • the first gate electrode and the first electrode plate of the first thin film transistor are used to form a storage capacitor, and at the same time, the first electrode plate and the second gate electrode of the second thin film transistor are arranged in the same layer.
  • the gate insulating layer used to separate the first gate electrode and the first electrode plate in layers and the mask plate required for preparing the first electrode plate can be omitted, thereby reducing the film layer in the display panel
  • the number and thickness of the film layer structure are reduced, thereby reducing the complexity of the display panel process flow and the production cost, and improving the bending ability of the display panel.
  • the embodiment of the present application further provides a display panel, which will be described in detail below with reference to FIG. 3 , which is a schematic diagram of the film layer structure of the display panel provided by the embodiment of the present application.
  • the structure of the display panel provided by the embodiment of the present application is substantially the same as that of the display panel provided by the above-mentioned embodiment, and details are not described herein again.
  • the difference between the display panel provided by the embodiment of the present application and the display panel provided by the above-mentioned embodiments is that the storage capacitor C in the embodiment of the present application includes a first capacitor and a second capacitor connected in parallel, and the first gate GE1 is connected to the second capacitor in parallel.
  • a second electrode plate 218 is disposed between one of the electrode plates 216 , and the orthographic projection area of the second electrode plate 218 on the base substrate 20 is respectively the same as that of the first electrode plate 216 and the first grid GE1 on the base substrate 20 , respectively.
  • the orthographic regions overlap.
  • the first gate GE1 and the second electrode plate 218 form a first capacitor
  • the first electrode plate 216 and the second electrode plate 218 form a second capacitor
  • the first capacitor and the second capacitor pass through the signal provided in the thin film transistor array layer 21
  • the second electrode plate 218 is disposed in the same layer as the oxide semiconductor layer 217 of the second thin film transistor T2, so that the original display panel can be maintained when the second electrode plate 218 is added.
  • the number of film layers and the structure of the film layers remain unchanged, so that the bending performance of the display panel is not affected.
  • the position of the second electrode plate 218 is not limited to the same layer as the oxide semiconductor stack 217 provided in the embodiment of the present application.
  • the second electrode plate 218 may be disposed on the first gate GE1
  • it can also achieve the same technical effect as the above-mentioned embodiment, and the specific film layer position can be selected according to the actual situation. , there is no restriction here.
  • the second electrode plate 218 and the oxide semiconductor layer 217 are made of the same layer of oxide material, so a mask can be used to simultaneously prepare and form the oxide semiconductor layer 217 and the second electrode
  • the plate 218 can be omitted, and the mask and related processes required for preparing the second plate 218 can be omitted, thereby reducing the complexity of the display panel process and the production cost.
  • the second electrode plate 218 and the second gate electrode GE2 are disposed on the same layer, they can be fabricated by using different materials and through different processes, which is not limited here.
  • the embodiment of the present application uses the first gate and the first plate of the first thin film transistor to form a storage capacitor, and at the same time, a second plate is arranged between the first grid and the first plate, The second electrode plate and the first grid electrode and the first electrode plate respectively form a parallel first capacitor and a second capacitor of the storage capacitor, and at the same time, the first electrode plate and the second grid electrode of the second thin film transistor are arranged in the same layer, And the second pole plate and the oxide semiconductor layer are arranged in the same layer, the gate insulating layer for separating the first gate and the first pole plate in layers and the gate insulating layer for preparing the first pole plate and the second pole plate respectively can be omitted.
  • a mask for the electrode plate so as to reduce the number of film layers in the display panel and the thickness of the film layer structure, thereby reducing the complexity and production cost of the display panel process, and improving the bending ability of the display panel and the display of the display panel. Effect.
  • FIG. 4 is a schematic structural diagram of the display device provided by the embodiment of the present application.
  • the display device 3 includes a device main body 31 and a display panel 32 .
  • the device main body 31 includes a frame assembly and components such as a power supply, a processor, and a camera (not shown in the figure) disposed in the frame assembly.
  • the display panel 32 is provided on the apparatus main body 31 .
  • the display panel 32 provided by the embodiment of the present application is any one of the display panels provided by the above embodiments, and the display device 3 provided by the embodiment of the present application can also achieve the same technical effect as the display panel provided by the above embodiments. , and will not be repeated here.
  • Embodiments of the present application also provide a method for manufacturing a display panel, which will be described in detail below with reference to FIGS. 5A to 5I .
  • FIGS. 5A to 5I are film layers of a display panel corresponding to the method for manufacturing a display panel provided by an embodiment of the present application.
  • a schematic diagram of the structure, the manufacturing method of the display panel provided by the embodiment of the present application includes:
  • Step S1 as shown in FIG. 5A , a base substrate 40 is provided, and a polysilicon semiconductor layer 410 is formed on the base substrate 40 ;
  • Step S2 as shown in FIG. 5B , forming a first gate insulating layer 411 covering the polysilicon semiconductor layer 410 on the base substrate 40 ;
  • Step S3 as shown in FIG. 5C , depositing a metal material on the side of the first gate insulating layer 411 away from the base substrate 40 , and forming a patterned first gate GE1 through a patterning process, the first gate GE1
  • the orthographic projection area on the base substrate 40 overlaps with the orthographic projection area of the channel region of the polycrystalline silicon semiconductor layer 410 on the base substrate 40;
  • Step S4 as shown in FIG. 5D , forming a first interlayer insulating layer 412 covering the first gate GE1 on the side of the first gate insulating layer 411 away from the base substrate 40 ;
  • Step S5 as shown in FIG. 5E , an oxide semiconductor layer 417 is formed on the side of the first interlayer insulating layer 412 away from the first gate insulating layer 411 ;
  • Step S6 as shown in FIG. 5F, forming a second gate insulating layer 413 covering the oxide semiconductor layer 417 on the side of the first interlayer insulating layer 412 away from the gate insulating layer;
  • Step S7 deposit a metal material on the side of the second gate insulating layer 413 away from the base substrate 40 , and form a plurality of spaced first electrode plates 416 and second gate electrodes through a patterning process electrode GE2, the orthographic projection area of the first electrode plate 416 on the base substrate 20 overlaps with the orthographic projection area of the first grid electrode GE1 on the base substrate, and the first electrode plate 416 and the first grid electrode GE1 form a storage capacitor C ;
  • Step S8 as shown in FIG. 5H , a second interlayer insulating layer 414 covering the second gate GE2 and the first electrode plate 416 is formed on the side of the second gate GE2 away from the second gate insulating layer 413 , and etched A plurality of first via holes penetrating the second interlayer insulating layer 414, the second gate insulating layer 413, the first interlayer insulating layer 412, and the first gate insulating layer 411 and penetrating the second interlayer insulating layer 414 and 411 are formed.
  • the second via hole of the second gate insulating layer 413 forms a first source S1 , a first drain D1 , a second source S2 and a second drain D2 on the second interlayer insulating layer 414 , the first source
  • the electrode S1 and the first drain D1, the first gate GE1 and the polysilicon semiconductor layer 410 constitute the first thin film transistor T1, the second source S2 and the second drain D2, the second gate GE2 and the oxide semiconductor layer 417 constitute the second thin film transistor T2;
  • Step S9 As shown in FIG. 5I, a passivation protection layer 415 covering the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2 is formed on the second interlayer insulating layer 414, And on the side of the passivation protection layer 415 away from the second interlayer insulating layer 414, a flat layer 42, an anode 45, a pixel definition layer 43, a light emitting layer 46, a cathode 47, and a surface of the pixel definition layer 43 are sequentially formed. A plurality of spacers 44 .
  • the manufacturing method in step S9 is the same as the manufacturing method in the prior art, and details are not described here.
  • the formed first interlayer insulating layer 412 is a laminated structure of silicon nitride and silicon oxide materials, and the silicon nitride film layer is located between the silicon oxide film layer and the first gate insulating layer 411 between.
  • the silicon nitride film layer needs to be made in a gas atmosphere of SiH4+NH3+N2, and the atomic percentage of silicon-hydrogen bonds in the first interlayer insulating layer 412 is controlled at 20% ⁇ 30% by the ratio of SiH4 in the gas atmosphere.
  • the silicon oxide film in the first interlayer insulating layer 412 can be used to prevent the hydrogen ions in the silicon nitride film from diffusing into the oxide semiconductor layer 417 to ensure oxidation.
  • the stability of the material semiconductor layer 417 is not affected.
  • the deposited metal material may be a stacked layer structure formed by a variety of metal materials such as Cu, Al, and Mo.
  • the second grid GE2 and the first electrode plate 416 may also be other conductive materials and structures, which are not limited here.
  • the patterning process of the second gate GE2 is used to form the first electrode plate 416 of the storage capacitor C at the same time, and the mask used to form the first electrode plate 416 and related processes can be omitted.
  • the gate insulating layer used to separate the metal film layer where the first electrode plate 416 is located from the metal film layer where the first gate electrode GE1 is located can also be omitted, thereby not only reducing the complexity of the display panel manufacturing process, but also reducing the complexity of the display panel.
  • the number of film layers in the display panel and the thickness of the film layer structure can be reduced, thereby improving the bending ability of the display panel.
  • the method for fabricating a display panel utilizes the process of preparing the second gate to simultaneously fabricate the first electrode plate for forming the storage capacitor, so that the first electrode plate for forming the first electrode can be omitted.
  • the mask of the panel and related processes reduce the complexity of the display panel manufacturing process, and at the same time reduce the number of film layers in the display panel and the thickness of the film layer structure, thereby improving the bending ability of the display panel.
  • An embodiment of the present application further provides a method for fabricating a display panel, the steps of which are substantially the same as those in the fabrication method mentioned in the above-mentioned embodiments, and are not repeated here.
  • the difference between the manufacturing method of the display panel provided by the embodiment of the present application and the manufacturing method of the display panel provided by the above-mentioned embodiment is that, as shown in FIG. 6A and FIG. 6B , FIG. 6A and FIG. 6B are provided by the embodiment of the present application
  • the schematic diagram of the film layer structure of the display panel corresponding to the display panel manufacturing method, the step S5 of forming the oxide semiconductor layer includes:
  • Step S501 depositing a layer of oxide semiconductor material 401 on the side of the first interlayer insulating layer 412 away from the first gate insulating layer 411 ;
  • Step S502 as shown in FIG. 6B , through a patterning process, a plurality of oxide semiconductor layers 417 and second electrode plates 418 are formed at intervals, and the orthographic projection area of the second electrode plate 418 on the base substrate 40 and the The orthographic projection area of a gate GE1 on the base substrate 40 overlaps.
  • step S502 can respectively form the first capacitor and the second capacitor in parallel in the storage capacitor with the first grid GE1 and the first electrode plate 416, so that the unit capacitance value of the storage capacitor C can be increased. , so that the size of the storage capacitor C can be compressed while the capacitance value of the storage capacitor C remains unchanged, thereby reducing the area occupied by the pixel circuit and improving the resolution of the display panel.
  • the size of the storage capacitor C can be kept unchanged.
  • the capacitance value of the storage capacitor C is increased, so that when the storage capacitor C stores the potential signal, the influence of the leakage current is reduced, thereby improving the display effect of the display panel in the state of low refresh rate or low power consumption. stability.
  • the material of the oxide semiconductor layer 417 is preferably IGZO.
  • the material of the oxide semiconductor layer 417 may also include but not limited to oxide semiconductor materials such as indium gallium oxide or indium zinc oxide. limit.
  • the second electrode plate 418 is simultaneously formed by the process of preparing the oxide semiconductor layer 417, so that the original number of film layers and film thickness of the display panel are maintained when the second electrode plate 418 is increased. remain unchanged, thereby ensuring the bending performance of the display panel, and at the same time omitting the mask and related process flow separately used for preparing the second electrode plate 418, thereby reducing the complexity of the display panel process flow and production cost.
  • the method for manufacturing a display panel uses the process of preparing the second gate electrode and the oxide semiconductor layer to simultaneously manufacture the first electrode plate and the second electrode plate, so that the Reduce the number of masks and related processes, and also reduce the number of film layers in the display panel and the thickness of the film layer structure, thereby reducing the complexity of the display panel process and production costs, while improving the display panel. capabilities and display panel display effects.

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Abstract

本申请提供一种显示面板及显示装置，通过利用第一薄膜晶体管的第一栅极与第一极板构成存储电容，将第一极板与第二薄膜晶体管的第二栅极同层设置，省略用于将第一极板与第一栅极和第二栅极分层隔开的栅极绝缘层，减少显示面板中的膜层数量以及膜层叠构的厚度，从而降低显示面板工艺流程的复杂程度，并提高显示面板的弯折能力。

Description

显示面板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
随着可穿戴设备技术的发展，以及在目前电池领域技术未得到显著突破的背景下，人们对于显示设备的功耗要求越来越高。目前用于驱动薄膜晶体管和开关薄膜晶体管的低温多晶硅（low temperature poly-silicon, LTPS）技术由于其功耗较低的特点，仍为主流技术趋势。但是由于LTPS载流子迁移率较大，存在漏电流较高的问题，因此低温多晶氧化物（low temperature polycrystalline-si oxide, LTPO）技术应运而生，其结合了LTPS和氧化物两者的优异点，可在提升显示设备响应速度的同时，降低显示设备的功耗。
 技术问题
如图1所示，图1为现有技术中采用低温多晶氧化物技术的显示面板的膜层结构示意图，驱动薄膜晶体管11和开关薄膜晶体管12的半导体层分别为多晶硅半导体层和氧化物半导体层，显示面板的存储电容13则由分别设置于第一栅极绝缘层14上的第一栅极111和设置于第二栅极绝缘层15上的第二栅极112构成，开关薄膜晶体管12的第三栅极121则通过第三栅极绝缘层16将其与第一栅极111和第二栅极112所在的金属层隔开，由此使得显示面板内的膜层数量较多、膜层叠构的厚度较大，导致显示面板的制作工艺流程较为复杂，此外还会降低显示面板的弯折能力。
综上，现有采用低温多晶氧化物技术的显示面板存在膜层数量较多、膜层叠构厚度较大导致的显示面板制作工艺流程复杂且显示面板弯折能力降低的问题。故，有必要提供一种显示面板及显示装置来改善这一缺陷。
 技术解决方案
本申请实施例提供一种显示面板及其制作方法、显示装置，用于解决现有采用低温多晶氧化物技术的显示面板存在的膜层数量较多、膜层叠构厚度较大导致显示面板制作工艺流程复杂且显示面板弯折能力降低的问题。
本申请实施例提供一种显示面板，包括：
衬底基板；
薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层内设有多个间隔排布的第一薄膜晶体管、第二薄膜晶体管和存储电容；
其中，所述第一薄膜晶体管包括层叠设置的多晶硅半导体层和第一栅极，所述第二薄膜晶体管包括层叠设置的氧化物半导体层和第二栅极，所述存储电容包括设置于所述第一栅极远离所述衬底基板一侧上的第一极板，所述第一栅极与所述第一极板构成所述存储电容，所述第一极板与所述第二栅极同层设置。
根据本申请一实施例，所述氧化物半导体层靠近所述衬底基板一侧表面与所述衬底基板之间的距离大于所述多晶硅半导体层靠近所述衬底基板一侧表面与所述衬底基板之间的距离。
根据本申请一实施例，所述薄膜晶体管阵列层包括依次层叠设置于所述多晶硅半导体层上的第一栅极绝缘层和第一层间绝缘层，所述第一栅极设置于所述第一栅极绝缘层与所述第一层间绝缘层之间，所述氧化物半导体层设置于所述第一层间绝缘层远离所述第一栅极绝缘层的一侧上。
根据本申请一实施例，所述第一层间绝缘层为氮化硅和氧化硅材料形成的叠层结构，且所述第一层间绝缘层中硅-氢键的原子百分比取值介于20%~30%。
根据本申请一实施例，所述薄膜晶体管阵列层还包括层叠设置于所述第一层间绝缘层远离所述第一栅极绝缘层一侧上的第二栅极绝缘层和第二层间绝缘层，所述第一极板和所述第二栅极均设置于所述第二栅极绝缘层与所述第二层间绝缘层之间。
根据本申请一实施例，所述第一极板与所述第二栅极由同层金属制成。
根据本申请一实施例，所述存储电容包括并联的第一电容和第二电容，所述第一栅极与所述第一极板之间设有第二极板，所述第二极板分别与所述第一栅极和所述第一极板构成所述第一电容和所述第二电容。
根据本申请一实施例，所述第二极板在所述衬底基板上的正投影区域与所述第一栅极或所述第一极板在所述衬底基板上的正投影区域重叠。
根据本申请一实施例，所述第二极板与所述氧化物半导体层同层设置。
根据本申请一实施例，所述第二极板与所述氧化物半导体层由同层氧化物材料制成。
根据本申请一实施例，所述第一薄膜晶体管包括第一源极和第一漏极，所述第二薄膜晶体管包括第二源极和第二漏极，所述第一源极和所述第一漏极分别通过贯穿所述第二层间绝缘层、第二栅极绝缘层、第一层间绝缘层和第一栅极绝缘层的第一过孔与所述多晶硅半导体层连接，所述第二源极和所述第二漏极分别通过贯穿所述第二层间绝缘层和所述第二栅极绝缘层的第二过孔与所述氧化物半导体层连接。
本申请实施例提供一种显示装置，包括装置主体以及设置于所述装置主体上的显示面板，所述显示面板包括：
衬底基板；
薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层内设有多个间隔排布的第一薄膜晶体管、第二薄膜晶体管和存储电容；
其中，所述第一薄膜晶体管包括层叠设置的多晶硅半导体层和第一栅极，所述第二薄膜晶体管包括层叠设置的氧化物半导体层和第二栅极，所述存储电容包括设置于所述第一栅极远离所述衬底基板一侧上的第一极板，所述第一栅极与所述第一极板构成所述存储电容，所述第一极板与所述第二栅极同层设置。
根据本申请一实施例，所述氧化物半导体层靠近所述衬底基板一侧表面与所述衬底基板之间的距离大于所述多晶硅半导体层靠近所述衬底基板一侧表面与所述衬底基板之间的距离。
根据本申请一实施例，所述薄膜晶体管阵列层包括依次层叠设置于所述多晶硅半导体层上的第一栅极绝缘层和第一层间绝缘层，所述第一栅极设置于所述第一栅极绝缘层与所述第一层间绝缘层之间，所述氧化物半导体层设置于所述第一层间绝缘层远离所述第一栅极绝缘层的一侧上。
根据本申请一实施例，所述第一层间绝缘层为氮化硅和氧化硅材料形成的叠层结构，且所述第一层间绝缘层中硅-氢键的原子百分比取值介于20%~30%。
根据本申请一实施例，所述薄膜晶体管阵列层还包括层叠设置于所述第一层间绝缘层远离所述第一栅极绝缘层一侧上的第二栅极绝缘层和第二层间绝缘层，所述第一极板和所述第二栅极均设置于所述第二栅极绝缘层与所述第二层间绝缘层之间。
根据本申请一实施例，所述第一极板与所述第二栅极由同层金属制成。
根据本申请一实施例，所述存储电容包括并联的第一电容和第二电容，所述第一栅极与所述第一极板之间设有第二极板，所述第二极板分别与所述第一栅极和所述第一极板构成所述第一电容和所述第二电容。
根据本申请一实施例，所述第二极板在所述衬底基板上的正投影区域与所述第一栅极或所述第一极板在所述衬底基板上的正投影区域重叠。
本申请实施例还提供一种显示装置，包括装置主体以及设置于所述装置主体上的显示面板，所述显示面板包括：
衬底基板；
薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层内设有多个间隔排布的第一薄膜晶体管、第二薄膜晶体管和存储电容；
其中，所述第一薄膜晶体管包括层叠设置的多晶硅半导体层和第一栅极，所述第二薄膜晶体管包括层叠设置的氧化物半导体层和第二栅极，所述薄膜晶体管阵列层还包括依次层叠设置于所述多晶硅半导体层上的第一栅极绝缘层、第一层间绝缘层、第二栅极绝缘层和第二层间绝缘层，所述存储电容包括设置于所述第一栅极远离所述衬底基板一侧上的第一极板，所述第一栅极与所述第一极板构成所述存储电容，所述第一极板与所述第二栅极同层设置，且位于所述第二栅极绝缘层与所述第二层间绝缘层之间。
本申请实施例还提供一种显示面板的制作方法，包括：
提供衬底基板，在所述衬底基板上形成多晶硅半导体层；
在所述衬底基板上形成覆盖所述多晶硅半导体层的第一栅极绝缘层；
在所述第一栅极绝缘层远离所述衬底基板的一侧形成第一栅极；
在所述第一栅极绝缘层远离所述衬底基板的一侧上形成覆盖所述第一栅极的第一层间绝缘层；
在所述第一层间绝缘层远离所述第一栅极绝缘层的一侧上形成氧化物半导体层；
在所述第一层间绝缘层远离所述栅极绝缘层的一侧上形成覆盖所述氧化物半导体层的第二栅极绝缘层；
在所述第二栅极绝缘层远离所述衬底基板的一侧上沉积金属材料，通过图案化工艺形成多个间隔排布的第一极板和第二栅极，所述第一极板与所述第一栅极构成存储电容；以及
在所述第二栅极远离所述第二栅极绝缘层的一侧形成第一源极、第一漏极、第二源极以及第二漏极，所述第一源极与所述第一漏极、第一栅极以及所述多晶硅半导体层构成第一薄膜晶体管，所述第二源极与所述第二漏极、所述第二栅极以及所述氧化物半导体层构成第二薄膜晶体管。
根据本申请一实施例，形成所述氧化物半导体层的步骤包括：
在所述第一层间绝缘层远离所述第一栅极绝缘层的一侧沉积一层氧化物半导体材料；以及
通过图案化工艺，形成多个间隔排布的所述氧化物半导体层和第二极板，所述第二极板分别与所述第一栅极和所述第一极板构成所述存储电容的第一电容和第二电容。
 有益效果
本申请实施例的有益效果：本申请实施通过利用第一薄膜晶体管的第一栅极与第一极板构成存储电容，同时将第一极板与第二薄膜晶体管的第二栅极同层设置，可以省略用于将第一极板与第一栅极和第二栅极分层隔开的栅极绝缘层，以此减少显示面板中的膜层数量以及膜层叠构的厚度，从而降低显示面板工艺流程的复杂程度，并提高显示面板的弯折能力。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的显示面板的膜层结构示意图；
图2为本申请实施例提供的第一种显示面板的膜层结构示意图；
图3为本申请实施例提供的第二种显示面板的膜层结构示意图；
图4为本申请实施例提供的显示装置的结构示意图；
图5A至图5I为本申请实施例提供的第一种显示面板的制作方法对应的显示面板的膜层结构示意图；以及
图6A至图6B为本申请实施例提供的第二种显示面板的制作方法对应的显示面板的膜层结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本申请做进一步的说明：
本申请实施例提供一种显示面板，下面结合图2进行详细说明，图2为本申请实施例提供的显示面板的膜层结构示意图。本申请实施例提供的显示面板包括衬底基板20、设置于衬底基板20上的薄膜晶体管阵列层21以及设置于薄膜晶体管阵列层21远离衬底基板20一侧上的显示器件层。
本申请实施例中，衬底基板20包括依次层叠设置的第一衬底、阻隔层、第二衬底、缓冲层以及第三衬底（图中未示出），第一衬底和第二衬底均由聚酰亚胺材料制备而成，第三衬底则由氮化硅、氧化硅以及非晶硅材料形成的叠层结构。当然，衬底基板20的材料和结构不仅限于本申请实施例所提供的材料以及结构，在其他的一些实施例中，衬底基板20也可以为其他结构以及材料，此处不做限制。
本申请实施例所提供的显示面板可以为有机发光二极管显示面板，显示器件层包括设置于薄膜晶体管阵列层21远离衬底基板20一侧上的平坦层22、像素定义层23、设置于像素定义层23一侧表面的多个隔垫物24以及层叠设置平坦层22远离衬底基板20一侧上的阳极25、发光层26和阴极27，其结构以及材料与现有技术中的有机发光二极管显示器件相同，此处不做赘述。当然，显示器件层内的显示器件不仅限于本申请实施例中的有机发光二极管器件，在其他一些实施例中，显示器件层内的显示器件同样也可以包括但不限于微发光二极管、迷你发光二极管等发光显示器件，显示器件的种类可以根据实际需求进行选择，此处不做限制。
如图2所示，本申请实施例中，薄膜晶体管阵列层21内设有间隔排布的多个第一薄膜晶体管T1、第二薄膜晶体管T2以及存储电容C，第一薄膜晶体管T1与第二薄膜晶体管T2、存储电容C以及设置于薄膜晶体管阵列层21内的电路走线构成显示面板内各个子像素单元的像素驱动电路。
本申请实施例所提供的像素驱动电路为7T1C像素驱动电路，包括1个驱动薄膜晶体管、6个开关薄膜晶体管以及1个存储电容C，其中第一薄膜晶体管T1为驱动薄膜晶体管，第二薄膜晶体管T2为开关薄膜晶体管。当然，在其他实施例中，显示面板的像素驱动电路也可以为其他电路结构，其内部驱动薄膜晶体管、开关薄膜晶体管以及电容的数量也不仅限于本申请实施例所提供的数量，具体结构可以根据实际需求进行设定，此处不做限制。
在本申请实施例中，第一薄膜晶体管T1包括层叠设置的多晶硅半导体层210、第一栅极GE1、设置于第一栅极GE1远离多晶硅半导体层210一侧的第一源极S1和第一漏极D1，第二薄膜晶体管T2包括层叠设置的氧化物半导体层217、第二栅极GE2、以及设置于第二栅极GE2远离氧化物半导体层217一侧的第二源极S2和第二漏极D2，存储电容C包括设置于第一栅极GE1远离衬底基板20一侧的第一极板216，第一极板216和第一栅极GE1在衬底基板20上的正投影区域均与多晶硅半导体层210的沟道区在衬底基板20上的正投影区域重叠，第二栅极GE2在衬底基板20上的正投影区域与氧化物半导体层217在衬底基板20上的正投影区域重叠，第一极板216与第一薄膜晶体管T1的第一栅极GE1构成存储电容C，第一极板216与第二栅极GE2设置于同一膜层上。
在本申请实施例中，多晶硅半导体层210为低温多晶硅半导体层，氧化物半导体层217的材料优选为铟镓锌氧化物（indium gallium zinc oxide, IGZO）。当然，在其他一些实施例中，氧化物半导体层217的材料还可包括但不限于铟镓氧化物或者铟锌氧化物等氧化物半导体材料，具体材料可以根据实际需求进行选择，此处不做限制。
如图2所示，第二薄膜晶体管T2的氧化物半导体层217靠近衬底基板20一侧表面与衬底基板之间的距离大于第一薄膜晶体管T1的多晶硅半导体层210靠近衬底基板20一侧表面与衬底基板之间的距离。
具体的，参照图2，薄膜晶体管阵列层21包括依次层叠设置于多晶硅半导体层210上的第一栅极绝缘层211和第一层间绝缘层212，第一栅极绝缘层211覆盖多晶硅半导体层210，第一栅极GE1设置于第一栅极绝缘层211和第一层间绝缘层212之间，氧化物半导体层217则设置于第一层间绝缘层212远离第一栅极绝缘层211的一侧上。通过将氧化物半导体层217设置在多晶硅半导体层210远离衬底基板20的一侧，可以防止制备多晶硅半导体层210时的高温对氧化物半导体层217的结构以及性质造成破坏。
在本申请实施例中，第一栅极绝缘层211的材料为氧化硅，第一层间绝缘层212为氮化硅和氧化硅材料形成的叠层结构，氮化硅膜层设置于氧化硅膜层与第一栅极绝缘层211之间，且第一层间绝缘层212中硅-氢键含量的原子百分比取值为25%。通过提高第一层间绝缘层212中的氢含量，可提高多晶硅半导体层210的稳定性，同时还可以利用第一层间绝缘层212中氧化硅膜层防止氮化硅膜层中氢离子扩散至氧化物半导体层217中，保证氧化物半导体层217的稳定性不受影响。当然，第一层间绝缘层212中硅-氢键含量的原子百分比取值不仅限于本申请实施例所提供的设置，在其他一些实施例中，第一层间绝缘层212中硅-氢键含量的原子百分比取值也可以包括但不限于20%或者30%，其取值最好介于20%~30%之间，具体数值可以根据实际需求进行设定，此处不做限制。
进一步的，薄膜晶体管阵列层21还包括层叠设置于第一层间绝缘层212远离第一栅极绝缘层211一侧上的第二栅极绝缘层213和第二层间绝缘层214，第一极板216和第二栅极GE2均设置于第二栅极绝缘层213和第二层间绝缘层214之间。相较于图1所示的显示面板，本申请实施例所提供的显示面板将存储电容的第一极板216与第二薄膜晶体管T2的第二栅极GE2设置于同一层，利用第二栅极GE2下方的第二栅极绝缘层213将第二栅极GE2和第一极板216所在膜层与第一栅极GE1所在金属膜层分层隔开，以此可以取消原有用于将第一栅极GE1所在金属膜层与第一极板216所在金属膜层分层隔开的由无机绝缘材料所形成的栅极绝缘层，从而减少显示面板中的膜层数量以及膜层叠构的厚度，进而降低显示面板工艺流程的复杂程度，并提高显示面板的弯折能力。
优选的，在本申请实施例中，第一极板216与第二栅极GE2由同层金属制成，因此可以利用一张掩膜版同时制备形成第一极板216和第二栅极GE2，从而可以省略单独用于制备第一极板216所需要的掩膜版以及相关工艺制程，进而降低显示面板工艺流程的复杂程度以及生产成本。当然，在一些实施例中，第一极板216和第二栅极GE2虽然设置于同一层，但是可以使用不同材料，通过不同的工艺制备而成，此处不做限制。
具体的，如图2所示，第一源极S1、第一漏极D1、第二源极S2和第二漏极D2均设置于第二层间绝缘层214和钝化保护层215之间，第一源极S1和第一漏极D1通过多个贯穿第二层间绝缘层214、第二栅极绝缘层213、第一层间绝缘层212和第一栅极绝缘层211的第一过孔分别与多晶硅半导体210的第一源极区和第一漏极区连接，设置于平坦层22和像素定义层23之间的阳极25通过过孔与第一漏极D1连接。第二源极S2和第二漏极D2通过多个贯穿第二层间绝缘层214和第二栅极绝缘层213的第二过孔与氧化物半导体层217的第二源极区和第二漏极区连接。
本申请实施例的有益效果：本申请实施通过利用第一薄膜晶体管的第一栅极与第一极板构成存储电容，同时将第一极板与第二薄膜晶体管的第二栅极同层设置，可以省略用于将第一栅极与第一极板分层隔开的栅极绝缘层、以及用于制备形成第一极板所需要的掩膜版，以此减少显示面板中的膜层数量以及膜层叠构的厚度，从而降低显示面板工艺流程的复杂程度以及生产成本，并提高显示面板的弯折能力。
本申请实施例还提供一种显示面板，下面结合图3进行详细说明，图3为本申请实施例提供的显示面板的膜层结构示意图。本申请实施例所提供的显示面板与上述实施例所提供的显示面板的结构大致相同，此处不再赘述。本申请实施例所提供的显示面板与上述实施例所提供的显示面板的区别之处在于，本申请实施例中存储电容C包括并联的第一电容和第二电容，第一栅极GE1与第一极板216之间设有第二极板218，第二极板218在衬底基板20上的正投影区域分别与第一极板216和第一栅极GE1各自在衬底基板20上的正投影区域重叠。
第一栅极GE1与第二极板218构成第一电容，第一极板216与第二极板218构成第二电容，第一电容与第二电容通过设置于薄膜晶体管阵列层21中的信号走线并联，以此可以增加存储电容C的单位电容值，从而在保证存储电容C电容值不变的情况下可以压缩存储电容C的尺寸，进而减小像素电路所占据的面积，并提高显示面板的分辨率。当然，在其他的一些实施例中，同样也可以在存储电容C尺寸不变的情况下，通过本实施例的方式增加存储电容C的电容值，从而在存储电容C存储电位信号时，降低其受到漏电流的影响，进而提高显示面板在低刷新率或者低功耗的状态下，显示面板显示效果的稳定性。
进一步的，在本申请实施例中，第二极板218与第二薄膜晶体管T2的氧化物半导体层217同层设置，以此可以在增加第二极板218的情况下，保持显示面板原有的膜层数量以及膜层结构不变，进而不影响显示面板的弯折性能。
当然，第二极板218设置的位置不仅限于本申请实施例所提供的与氧化物半导体叠层217同层设置，在其他一些实施例中，第二极板218可以设置于第一栅极GE1与第一极板216之间除氧化物半导体层217所在膜层之外的其他膜层中，其同样可以实现与上述实施例相同的技术效果，具体设置的膜层位置可以根据实际情况进行选择，此处不做限制。
优选的，在本申请实施例中，第二极板218与氧化物半导体层217由同层氧化物材料制成，因此可以利用一张掩膜版同时制备形成氧化物半导体层217和第二极板218，从而可以省略单独用于制备第二极板218所需要的掩膜版以及相关工艺制程，进而降低显示面板工艺流程的复杂程度以及生产成本。当然，在一些实施例中，第二极板218和第二栅极GE2虽然设置于同一层，但是可以使用不同材料，通过不同的工艺制备而成，此处不做限制。
本申请实施例的有益效果：本申请实施例利用第一薄膜晶体管的第一栅极与第一极板构成存储电容，同时在第一栅极与第一极板之间设置第二极板，第二极板分别与第一栅极和第一极板分别形成存储电容的并联的第一电容和第二电容，同时将第一极板与第二薄膜晶体管的第二栅极同层设置，并将第二极板与氧化物半导体层同层设置，可以省略用于将第一栅极与第一极板分层隔开的栅极绝缘层以及分别用于制备第一极板和第二极板的掩膜版，以此减少显示面板中的膜层数量以及膜层叠构的厚度，从而降低显示面板工艺流程的复杂程度和生产成本，并提高显示面板的弯折能力和显示面板的显示效果。
本申请实施例还提供一种显示装置，下面结合图4进行详细说明，图4为本申请实施例提供的显示装置的结构示意图。如图4所示，显示装置3包括装置主体31和显示面板32，装置主体31包括框架总成以及设置于框架总成中的电源、处理器、摄像头等零部件（图中未示出），显示面板32设置于装置主体31上。本申请实施例所提供的显示面板32为上述实施例所提供任意一种的显示面板，且本申请实施例所提供的显示装置3同样可以实现与上述实施例所提供的显示面板相同的技术效果，此处不再赘述。
本申请实施例还提供一种显示面板的制作方法，下面结合图5A至图5I进行详细说明，图5A至图5I为本申请实施例提供的与显示面板的制作方法对应的显示面板的膜层结构示意图，本申请实施例提供的显示面板的制作方法包括：
步骤S1：如图5A所示，提供衬底基板40，在衬底基板40上形成多晶硅半导体层410；
步骤S2：如图5B所示，在衬底基板40上形成覆盖多晶硅半导体层410的第一栅极绝缘层411；
步骤S3：如图5C所示，在第一栅极绝缘层411远离衬底基板40的一侧上沉积金属材料，通过图案化工艺，形成图案化的第一栅极GE1，第一栅极GE1在衬底基板40上的正投影区域与多晶硅半导体层410的沟道区在衬底基板40上的正投影区域重叠；
步骤S4：如图5D所示，在第一栅极绝缘层411远离衬底基板40的一侧上形成覆盖第一栅极GE1的第一层间绝缘层412；
步骤S5：如图5E所示，在第一层间绝缘层412远离第一栅极绝缘层411的一侧上形成氧化物半导体层417；
步骤S6：如图5F所示，在第一层间绝缘层412远离栅极绝缘层的一侧上形成覆盖氧化物半导体层417的第二栅极绝缘层413；
步骤S7：如图5G所示，在第二栅极绝缘层413远离衬底基板40的一侧上沉积金属材料，通过图案化工艺形成多个间隔排布的第一极板416和第二栅极GE2，第一极板416在衬底基板20上的正投影区域与第一栅极GE1在衬底基板上的正投影区域重叠，第一极板416与第一栅极GE1构成存储电容C；
步骤S8：如图5H所示，在第二栅极GE2远离第二栅极绝缘层413的一侧形成覆盖第二栅极GE2和第一极板416的第二层间绝缘层414，刻蚀形成多个贯穿第二层间绝缘层414、第二栅极绝缘层413、第一层间绝缘层412和第一栅极绝缘层411的第一过孔以及贯穿第二层间绝缘层414和第二栅极绝缘层413的第二过孔，在第二层间绝缘层414上形成第一源极S1、第一漏极D1、第二源极S2和第二漏极D2，第一源极S1与第一漏极D1、第一栅极GE1和多晶硅半导体层410构成第一薄膜晶体管T1，第二源极S2与第二漏极D2、第二栅极GE2和氧化物半导体层417构成第二薄膜晶体管T2；
步骤S9：如图5I所示，在第二层间绝缘层414上形成覆盖第一源极S1、第一漏极D1、第二源极S2和第二漏极D2的钝化保护层415，并在钝化保护层415远离第二层间绝缘层414的一侧依次形成平坦层42、阳极45、像素定义层43、发光层46、阴极47、以及间隔排布于像素定义层43表面的多个隔垫物44。步骤S9中制作方法与现有技术中的制作方法相同，此处不做赘述。
在本申请实施例步骤S4中，所形成的第一层间绝缘层412为氮化硅和氧化硅材料的叠层结构，氮化硅膜层位于氧化硅膜层与第一栅极绝缘层411之间。氮化硅膜层需要在SiH4+NH3+N2的气体氛围中制成，通过SiH4在气体氛围中的比例，将第一层间绝缘层412中硅-氢键的原子百分比控制在20%~30%之间，从而提高多晶硅半导体层410的稳定性，同时还可以利用第一层间绝缘层412中氧化硅膜层防止氮化硅膜层中氢离子扩散至氧化物半导体层417中，保证氧化物半导体层417的稳定性不受影响。
在本申请实施例步骤S7中，沉积的金属材料可以为Cu、Al、Mo等金属材料中多种材料所形成的叠层结构。在其他实施例中，第二栅极GE2和第一极板416也可以为其他导电材料和结构，此处不做限制。步骤S7中，利用第二栅极GE2的图案化工艺同时形成存储电容C的第一极板416，可以省略单独用于制作形成第一极板416的掩膜版以及相关工艺制程，同时在结构上还可以省去用于将第一极板416所在金属膜层与第一栅极GE1所在金属膜层分层隔开的栅极绝缘层，从而不仅可以降低显示面板制作工艺的复杂程度，还可以减少显示面板内膜层的数量以及膜层叠构的厚度，从而提高显示面板的弯折能力。
本申请实施例的有益效果：本申请实施例提供的显示面板的制作方法利用制备第二栅极的工艺制程同时制作形成存储电容的第一极板，以此可以省略用于制作形成第一极板的掩膜版以及相关工艺制程，降低显示面板制作工艺的复杂程度，同时还可以减少显示板内膜层的数量以及膜层叠构的厚度，从而提高显示面板的弯折能力。
本申请实施例还提供一种显示面板的制作方法，其步骤与上述实施例所提的制作方法大致相同，此处不再赘述。本申请实施例所提供的显示面板的制作方法与上述实施例所提供的显示面板的制作方法的区别之处在于，如图6A和图6B所示，图6A和图6B是本申请实施例提供的与显示面板制作方法对应的显示面板的膜层结构示意图，形成氧化物半导体层的步骤S5包括：
步骤S501：如图6A所示，在第一层间绝缘层412远离第一栅极绝缘层411的一侧沉积一层氧化物半导体材料401；以及
步骤S502：如图6B所示，通过图案化工艺，形成多个间隔排布的氧化物半导体层417和第二极板418，第二极板418在衬底基板40上的正投影区域与第一栅极GE1在衬底基板40上的正投影区域重叠。
本申请实施例的后续步骤与上述实施例所提供的制作方法大致相同，其形成的显示面板的结构与上述实施例中图3的显示面板的结构相同，此处不再赘述。步骤S502所形成的第二极板418可分别与第一栅极GE1和第一极板416构成存储电容中相并联的第一电容和第二电容，以此可以增加存储电容C的单位电容值，从而在保证存储电容C电容值不变的情况下可以压缩存储电容C的尺寸，进而减小像素电路所占据的面积，并提高显示面板的分辨率，同样也可以在存储电容C尺寸不变的情况下，增加存储电容C的电容值，从而在存储电容C存储电位信号时，降低其受到漏电流的影响，进而提高显示面板在低刷新率或者低功耗的状态下，显示面板显示效果的稳定性。
在步骤S5中，氧化物半导体层417的材料优选为IGZO。当然，在其他一些实施例中，氧化物半导体层417的材料还可包括但不限于铟镓氧化物或者铟锌氧化物等氧化物半导体材料，具体材料可以根据实际需求进行选择，此处不做限制。步骤S501至步骤S502，利用制备氧化物半导体层417的制程同时制作形成第二极板418，以此在增加第二极板418的情况下，保持显示面板原有的膜层数量以及膜层厚度不变，进而保证显示面板的弯折性能，同时还可以省略单独用于制备第二极板418所需的掩膜版以及相关工艺流程，进而降低显示面板的工艺流程的复杂程度以及生产成本。
本申请实施例的有益效果：本申请实施例提供的显示面板的制作方法分别利用制备第二栅极和氧化物半导体层的工艺制程同时制作形成第一极板和第二极板，以此可以减少掩膜版数量以及相关工艺制程，同时还可以减少显示面板内膜层的数量以及膜层叠构的厚度，从而在降低显示面板工艺流程的复杂程度和生产成本的同时，提高显示面板的弯折能力和显示面板的显示效果。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种显示面板，包括：
    衬底基板；
    薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层内设有多个间隔排布的第一薄膜晶体管、第二薄膜晶体管和存储电容；
    其中，所述第一薄膜晶体管包括层叠设置的多晶硅半导体层和第一栅极，所述第二薄膜晶体管包括层叠设置的氧化物半导体层和第二栅极，所述存储电容包括设置于所述第一栅极远离所述衬底基板一侧上的第一极板，所述第一栅极与所述第一极板构成所述存储电容，所述第一极板与所述第二栅极同层设置。
  2. 如权利要求1所述的显示面板，其中，所述氧化物半导体层靠近所述衬底基板一侧表面与所述衬底基板之间的距离大于所述多晶硅半导体层靠近所述衬底基板一侧表面与所述衬底基板之间的距离。
  3. 如权利要求1所述的显示面板，其中，所述薄膜晶体管阵列层包括依次层叠设置于所述多晶硅半导体层上的第一栅极绝缘层和第一层间绝缘层，所述第一栅极设置于所述第一栅极绝缘层与所述第一层间绝缘层之间，所述氧化物半导体层设置于所述第一层间绝缘层远离所述第一栅极绝缘层的一侧上。
  4. 如权利要求3所述的显示面板，其中，所述第一层间绝缘层为氮化硅和氧化硅材料形成的叠层结构，且所述第一层间绝缘层中硅-氢键的原子百分比取值介于20%~30%。
  5. 如权利要求3所述的显示面板，其中，所述薄膜晶体管阵列层还包括层叠设置于所述第一层间绝缘层远离所述第一栅极绝缘层一侧上的第二栅极绝缘层和第二层间绝缘层，所述第一极板和所述第二栅极均设置于所述第二栅极绝缘层与所述第二层间绝缘层之间。
  6. 如权利要求5所述的显示面板，其中，所述第一极板与所述第二栅极由同层金属制成。
  7. 如权利要求5所述的显示面板，其中，所述存储电容包括并联的第一电容和第二电容，所述第一栅极与所述第一极板之间设有第二极板，所述第二极板分别与所述第一栅极和所述第一极板构成所述第一电容和所述第二电容。
  8. 如权利要求7所述的显示面板，其中，所述第二极板在所述衬底基板上的正投影区域与所述第一栅极或所述第一极板在所述衬底基板上的正投影区域重叠。
  9. 如权利要求7所述的显示面板，其中，所述第二极板与所述氧化物半导体层同层设置。
  10. 如权利要求9所述的显示面板，其中，所述第二极板与所述氧化物半导体层由同层氧化物材料制成。
  11. 如权利要求5所述的显示面板，其中，所述第一薄膜晶体管包括第一源极和第一漏极，所述第二薄膜晶体管包括第二源极和第二漏极，所述第一源极和所述第一漏极分别通过贯穿所述第二层间绝缘层、第二栅极绝缘层、第一层间绝缘层和第一栅极绝缘层的第一过孔与所述多晶硅半导体层连接，所述第二源极和所述第二漏极分别通过贯穿所述第二层间绝缘层和所述第二栅极绝缘层的第二过孔与所述氧化物半导体层连接。
  12. 一种显示装置，包括装置主体以及设置于所述装置主体上的显示面板，所述显示面板包括：
    衬底基板；
    薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层内设有多个间隔排布的第一薄膜晶体管、第二薄膜晶体管和存储电容；
    其中，所述第一薄膜晶体管包括层叠设置的多晶硅半导体层和第一栅极，所述第二薄膜晶体管包括层叠设置的氧化物半导体层和第二栅极，所述存储电容包括设置于所述第一栅极远离所述衬底基板一侧上的第一极板，所述第一栅极与所述第一极板构成所述存储电容，所述第一极板与所述第二栅极同层设置。
  13. 如权利要求12所述的显示装置，其中，所述氧化物半导体层靠近所述衬底基板一侧表面与所述衬底基板之间的距离大于所述多晶硅半导体层靠近所述衬底基板一侧表面与所述衬底基板之间的距离。
  14. 如权利要求12所述的显示装置，其中，所述薄膜晶体管阵列层包括依次层叠设置于所述多晶硅半导体层上的第一栅极绝缘层和第一层间绝缘层，所述第一栅极设置于所述第一栅极绝缘层与所述第一层间绝缘层之间，所述氧化物半导体层设置于所述第一层间绝缘层远离所述第一栅极绝缘层的一侧上。
  15. 如权利要求14所述的显示装置，其中，所述第一层间绝缘层为氮化硅和氧化硅材料形成的叠层结构，且所述第一层间绝缘层中硅-氢键的原子百分比取值介于20%~30%。
  16. 如权利要求14所述的显示装置，其中，所述薄膜晶体管阵列层还包括层叠设置于所述第一层间绝缘层远离所述第一栅极绝缘层一侧上的第二栅极绝缘层和第二层间绝缘层，所述第一极板和所述第二栅极均设置于所述第二栅极绝缘层与所述第二层间绝缘层之间。
  17. 如权利要求16所述的显示装置，其中，所述第一极板与所述第二栅极由同层金属制成。
  18. 如权利要求16所述的显示装置，其中，所述存储电容包括并联的第一电容和第二电容，所述第一栅极与所述第一极板之间设有第二极板，所述第二极板分别与所述第一栅极和所述第一极板构成所述第一电容和所述第二电容。
  19. 如权利要求18所述的显示装置，其中，所述第二极板在所述衬底基板上的正投影区域与所述第一栅极或所述第一极板在所述衬底基板上的正投影区域重叠。
  20. 一种显示装置，包括装置主体以及设置于所述装置主体上的显示面板，所述显示面板包括：
    衬底基板；
    薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层内设有多个间隔排布的第一薄膜晶体管、第二薄膜晶体管和存储电容；
    其中，所述第一薄膜晶体管包括层叠设置的多晶硅半导体层和第一栅极，所述第二薄膜晶体管包括层叠设置的氧化物半导体层和第二栅极，所述薄膜晶体管阵列层还包括依次层叠设置于所述多晶硅半导体层上的第一栅极绝缘层、第一层间绝缘层、第二栅极绝缘层和第二层间绝缘层，所述存储电容包括设置于所述第一栅极远离所述衬底基板一侧上的第一极板，所述第一栅极与所述第一极板构成所述存储电容，所述第一极板与所述第二栅极同层设置，且位于所述第二栅极绝缘层与所述第二层间绝缘层之间。
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