WO2022011779A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2022011779A1
WO2022011779A1 PCT/CN2020/110262 CN2020110262W WO2022011779A1 WO 2022011779 A1 WO2022011779 A1 WO 2022011779A1 CN 2020110262 W CN2020110262 W CN 2020110262W WO 2022011779 A1 WO2022011779 A1 WO 2022011779A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
gate
layer
gate insulating
semiconductor layer
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PCT/CN2020/110262
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English (en)
French (fr)
Inventor
赵慧慧
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/972,032 priority Critical patent/US11417689B2/en
Publication of WO2022011779A1 publication Critical patent/WO2022011779A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel.
  • LTPO Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide
  • LTPS TFT Low Temperature Poly-Silicon TFT, low temperature polycrystalline silicon thin film transistor
  • LTPO TFT Low Temperature Polycrystalline Oxide TFT, Low Temperature Polycrystalline Oxide Thin Film Transistors
  • the fabrication of the LTPO structure requires more layers.
  • the LTPS TFT needs to be fabricated, and then the oxide semiconductor thin film transistor needs to be fabricated.
  • a thick insulating film needs to be formed between the two as a barrier, thereby increasing the distance from the source and drain to the polysilicon layer in the LTPS TFT, increasing the distance between the source and drain holes and the polysilicon layer.
  • the pixel density is getting larger and larger, and the aperture requirement of the via hole is getting smaller and smaller. As a whole, the aperture diameter of the via hole is small and the hole depth is long, which is easy to cause etching.
  • the inorganic layer remains when the via hole is formed, which increases the contact resistance between the source and drain electrodes and the polysilicon layer. In severe cases, the source and drain traces are disconnected, resulting in the overlap between the source and drain electrodes and the polysilicon layer. Abnormal; in addition, due to the increase of the film layer caused by the LTPO structure, the thickness of the film layer in the binding area of the display panel also increases, which increases the difficulty of digging holes in the binding area, and also affects the PAD. Bending performance.
  • the existing LTPS structure sequentially includes a substrate 201, a polysilicon layer 202, an insulating layer 203, a gate 1 204, an insulating layer 205, an insulating layer 3 206, IGZO (indium gallium zinc oxide indium gallium zinc oxide) layer 207, insulating layer 4 208, gate 2 209, insulating layer 5 210, source and drain 211 and other film structures, obviously, the via 212 between the polysilicon layer 202 and the source and drain 211 It needs to pass through many film layers such as insulating layer 1 203, insulating layer 2 205, insulating layer 3 206, insulating layer 4 208 and insulating layer 5 210, and the aperture is small, which increases the difficulty of the process and easily causes source and drain 211 and polysilicon.
  • IGZO indium gallium zinc oxide indium gallium zinc oxide
  • the insulating layer 205 is usually made of materials such as SiNx with high hydrogen content and is arranged on the whole surface, so that the hydrogen in the insulating layer 205 The ions can easily invade into the IGZO layer 207 which is extremely sensitive to hydrogen, thereby causing the IGZO layer 207 to become conductive and fail.
  • the present application provides a display panel to solve the problem that there are many film layers in the existing LTPO structure and increase the LTPS
  • the length of the via hole between the source-drain and the polysilicon layer in the TFT also reduces the aperture of the via hole, which increases the difficulty of the process, and is likely to cause an increase in the contact resistance or abnormal overlap between the source-drain and the polysilicon layer.
  • the present application provides a display panel to solve the problem that there are many film layers in the existing LTPO structure and increase the LTPS
  • the length of the via hole between the source-drain and the polysilicon layer in the TFT also reduces the aperture of the via hole, which increases the difficulty of the process, and is likely to cause an increase in the contact resistance or abnormal overlap between the source-drain and the polysilicon layer.
  • the present application provides a display panel, comprising a substrate, and a first thin film transistor and a second thin film transistor disposed on the substrate at intervals;
  • the first thin film transistor includes a polysilicon semiconductor layer on the substrate, a first gate located above the polysilicon semiconductor layer, and a first source electrode and a first drain electrode respectively connected to the polysilicon semiconductor layer;
  • the second thin film transistor includes an oxide semiconductor layer over the substrate, a third gate over the oxide semiconductor layer, and a second source electrode and a second gate electrode respectively connected to the oxide semiconductor layer drain;
  • a third gate insulating layer corresponding to the position of the third gate is disposed between the oxide semiconductor layer and the third gate, and the third gate insulating layer covers part of the oxide material semiconductor layer;
  • a first metal layer is disposed on the side of the oxide semiconductor layer away from the third gate, a first interlayer insulating layer is disposed between the first metal layer and the oxide semiconductor layer, and the first interlayer insulating layer is disposed between the first metal layer and the oxide semiconductor layer.
  • a second gate insulating layer is provided on the side of the metal layer away from the oxide semiconductor layer, and the first metal layer includes a second gate electrode arranged opposite to the oxide semiconductor layer;
  • a first gate insulating layer is arranged on the polysilicon semiconductor layer and the substrate, the first gate is arranged on the first gate insulating layer, and the first metal layer further includes and the first gate insulating layer.
  • the electrode plate opposite to the grid.
  • the second gate insulating layer corresponds to the position of the first metal layer
  • the second gate insulating layer includes a gate corresponding to the position of the second gate.
  • a first insulator part, the orthographic projection of the first insulator part on the substrate covers the orthographic projection of the second gate on the substrate.
  • a first gate insulating layer is provided on the polysilicon semiconductor layer and the substrate, the first gate is arranged on the first gate insulating layer, and the first gate insulating layer is provided on the first gate insulating layer.
  • a metal layer further includes an electrode plate disposed opposite to the first gate, the second gate insulating layer further includes a second insulator portion corresponding to the position of the electrode plate, wherein the second insulator portion The polysilicon semiconductor layer is partially covered, and the orthographic projection of the second insulator portion on the substrate covers the orthographic projection of the electrode plate on the substrate.
  • a second interlayer insulating layer is provided on the third gate electrode, and a second metal layer is provided on the second interlayer insulating layer;
  • the display panel is provided with a first via hole and a second via hole passing through the first gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer, and the The third via hole and the fourth via hole of the two interlayer insulating layers, the second metal layer is connected to the polysilicon semiconductor layer through the first via hole and the second via hole to form the first source
  • the second source electrode and the second drain electrode are formed by connecting with the oxide semiconductor layer through the third via hole and the fourth via hole and the first drain electrode.
  • the display panel includes a display area and a binding area adjacent to the display area, and the first thin film transistor and the second thin film transistor are disposed in the display area ;
  • the first metal layer further includes a first metal trace located in the binding area
  • the second metal layer further includes a second metal trace located in the binding area
  • the first metal trace is located in the binding area.
  • a fifth via hole is arranged above the line through the first interlayer insulating layer and the second interlayer insulating layer in sequence, and the second metal trace passes through the fifth via hole and the first interlayer insulating layer. Metal trace connections.
  • the pattern of the second gate insulating layer is the same as that of the first metal layer, and the orthographic projection of the second gate insulating layer on the substrate covers the first metal layer.
  • the pattern of the third gate insulating layer and the third gate is the same, and the orthographic projection of the third gate insulating layer on the substrate covers the third gate insulating layer. Orthographic projection of the tri-grid on the substrate.
  • the oxide semiconductor layer includes an active segment corresponding to the position of the third gate, and two conductor segments respectively located at both ends of the active segment, the third
  • the orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the active segment on the substrate.
  • the second source electrode and the second drain electrode are respectively connected to the two conductor segments, the wiring resistance of the conductor segments is 500 ohms to 1200 ohms, and the conductors
  • the contact resistance between the segment and the second source electrode or the second drain electrode is 700 ohms to 1800 ohms.
  • the third gate insulating layer is located in the channel region between the second source electrode and the second drain electrode.
  • the width of the third gate insulating layer is 0.2 um ⁇ 1.2 um larger than the width of the third gate electrode.
  • the beneficial effects of the present application are: in the present application, by disposing the third gate insulating layer at a position corresponding to the position of the third gate electrode, and the third gate insulating layer covering part of the oxide semiconductor layer in the second thin film transistor, It is avoided that the third gate insulating layer is disposed in the display panel on the whole surface, the film thickness of other positions in the display panel except the area where the third gate is located is reduced, and it is convenient to reduce the thickness of the first source and the first source in the first thin film transistor.
  • the depth of the via hole between the first drain electrode and the polycrystalline silicon semiconductor layer reduces the contact resistance of the first source electrode and the first drain electrode and the polycrystalline silicon semiconductor layer overlapping; at the same time, it also reduces the film layer of the display panel in the bonding area Thickness, which reduces the technological difficulty of digging holes in the binding area, and also reduces the need for PAD in the binding area. Impact of Bending.
  • 1 is a schematic structural diagram of a conventional display panel
  • FIG. 2 is a schematic structural diagram of a display panel in an embodiment of the present application.
  • FIG. 3 is a schematic block diagram of a process flow of a method for fabricating a display panel according to an embodiment of the present application.
  • 4A-4F are schematic structural diagrams of the process flow of a method for fabricating a display panel according to an embodiment of the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • the present application provides a display panel, as shown in FIG. 2 , comprising a substrate 10, and a first thin film transistor 20 and a second thin film transistor 30 arranged on the substrate 10 at intervals;
  • the first thin film transistor 20 includes a polysilicon semiconductor layer 21 located on the substrate 10 , a first gate electrode 22 located above the polysilicon semiconductor layer 21 , and a first source electrode respectively connected to the polysilicon semiconductor layer 21 . 23 and the first drain 24;
  • the second thin film transistor 30 includes an oxide semiconductor layer 31 located above the substrate 10 , a third gate electrode 32 located above the oxide semiconductor layer 31 , and a third gate electrode 32 respectively connected to the oxide semiconductor layer 31 .
  • a third gate insulating layer 40 corresponding to the position of the third gate 32 is disposed between the oxide semiconductor layer 31 and the third gate 32 , and the third gate insulating layer 40 covering part of the oxide semiconductor layer 31;
  • a first metal layer 50 is provided on the side of the oxide semiconductor layer 31 away from the third gate 32 , and a first interlayer insulating layer is provided between the first metal layer 50 and the oxide semiconductor layer 31 60 , a second gate insulating layer 70 is provided on the side of the first metal layer 50 away from the oxide semiconductor layer 31 , and the first metal layer 50 includes a second gate insulating layer 70 disposed opposite to the oxide semiconductor layer 31 .
  • Two gates 51, the second gate insulating layer 70 may be arranged on the whole surface;
  • a first gate insulating layer 80 is disposed on the polysilicon semiconductor layer 21 and the substrate 10 , the first gate 22 is disposed on the first gate insulating layer 80 , and the first metal layer 50 is further It includes an electrode plate 52 arranged opposite to the first gate 22; the electrical properties of the first thin film transistor and the second thin film transistor can be significantly improved by the arrangement of the second gate 51 and the electrode plate 52 Moreover, the second grid electrode and the electrode plate are also located in the same film layer, which can be fabricated in the same process, which also minimizes the influence on the thickness of the display panel.
  • the fabrication of the LTPO structure requires more layers.
  • the LTPS TFT needs to be fabricated, and then the oxide semiconductor thin film transistor needs to be fabricated.
  • the oxide semiconductor thin film transistor needs to be fabricated.
  • Length and, with the increasing demand for high-resolution display, the pixel density is getting larger and larger, and the aperture requirement of the via hole is getting smaller and smaller.
  • the aperture diameter of the via hole is small and the hole depth is long, which is easy to cause etching.
  • the inorganic layer remains when the via hole is formed, which increases the contact resistance between the source and drain electrodes and the polysilicon layer. In severe cases, the source and drain traces are disconnected, resulting in the overlap between the source and drain electrodes and the polysilicon layer. Abnormal; in addition, due to the increase of the film layer caused by the LTPO structure, the thickness of the film layer in the binding area of the display panel also increases, which increases the difficulty of digging holes in the binding area, and also affects the PAD.
  • the third gate insulating layer 40 is arranged at a position corresponding to the position of the third gate 32 , and the third gate insulating layer 40 covers part of the oxide in the second thin film transistor 30
  • the material semiconductor layer 31 prevents the third gate insulating layer 40 from being disposed in the display panel on the whole surface, reduces the film thickness of the display panel except for the area where the third gate 32 is located, and facilitates the reduction of the first thin film.
  • the depth of the via hole between the first source electrode 23 and the first drain electrode 24 and the polysilicon semiconductor layer 21 in the transistor 20 reduces the contact resistance of the first source electrode 23 and the first drain electrode 24 and the polysilicon semiconductor layer 21 overlapping; At the same time, the film thickness of the display panel in the binding area is also reduced, the process difficulty of digging holes in the binding area is reduced, and the PAD in the binding area is also reduced.
  • the position of the second gate insulating layer 70 corresponds to the position of the first metal layer 50
  • the second gate insulating layer 70 includes and the second gate insulating layer 70 .
  • the first insulator portion 71 corresponding to the position of the pole 51, the orthographic projection of the first insulator portion 71 on the substrate 10 covers the orthographic projection of the second gate 51 on the substrate 10; obviously, this implementation
  • the second gate insulating layer 70 is not provided on the entire surface, but the first insulator portion 71 may be formed by patterning.
  • the second gate insulating layer 70 is provided At the position corresponding to the position of the first metal layer 50, the film thickness of the portion of the display panel located outside the region where the first metal layer 50 is located can be reduced; in addition, when the third gate insulating layer 40 is placed It is arranged at a position corresponding to the position of the third gate 32, and on the basis of reducing the thickness of the film layer of the display panel in the binding area, in this embodiment, the second gate insulating layer 70 is arranged at the same position as the first gate insulating layer 70.
  • the position corresponding to the position of the metal layer 50 further reduces the film thickness of the display panel in the binding area, further reduces the technological difficulty of digging holes in the binding area, and improves the PAD of each functional layer in the binding area. Bending performance.
  • the second gate insulating layer 70 includes a first insulator portion 71 corresponding to the position of the second gate 51 , the first insulator portion 71 and the second gate
  • the position of 51 corresponds to, and the orthographic projection of the first insulator portion 71 on the substrate 10 covers the orthographic projection of the second gate 51 on the substrate 10, so that the first insulator portion 71
  • the number of layers between the electrode 23 and the first drain electrode 24 and the polysilicon semiconductor layer 21 is reduced, that is, the number of layers between the first source electrode 23 and the first drain electrode 24 and the polysilicon semiconductor layer is reduced.
  • the insulating layer 205 is usually made of materials such as SiNx with high hydrogen content and arranged on the whole surface, the insulating layer 205 is Hydrogen ions can easily invade into the IGZO layer 207 that is extremely sensitive to hydrogen, thereby causing the IGZO layer 207 to become conductive and fail. Corresponding arrangement also avoids hydrogen ions from invading the oxide semiconductor layer 31 due to the entire surface of the second gate insulating layer 70 , thereby avoiding conductorization of the oxide semiconductor layer 31 .
  • An insulator part 71 is provided corresponding to the position of the second gate 51 , and the hydrogen ions in the first insulator part 71 can also be blocked by the second gate 51 to avoid the oxide semiconductor Layer 31 becomes conductive causing device failure.
  • the second gate insulating layer 70 further includes a second insulator part 72 corresponding to the position of the electrode plate 52 , wherein the second insulator part 72 partially covers The orthographic projection of the polycrystalline silicon semiconductor layer 21 and the second insulator portion 72 on the substrate 10 covers the orthographic projection of the electrode plate 52 on the substrate 10;
  • the first metal layer 50 may further include an electrode plate 52 disposed opposite to the first gate 22, correspondingly, the second gate insulating layer 70 further includes a second insulator portion 72 corresponding to the position of the electrode plate 52, so A capacitor is formed between the electrode plate 52 and the first grid 22, and the orthographic projection of the second insulator portion 72 on the substrate 10 covers the orthographic projection of the electrode plate 52 on the substrate 10, so that
  • the second insulator part 72 has a good support for the electrode plate 52 , and at the same time, the second insulator part 72 can also serve as a medium between the electrode plate 52 and the first gate 22 to form a capacitor layer, obviously
  • a second interlayer insulating layer 90 is formed on the third gate electrode 32 , and a second metal layer 110 is formed on the second interlayer insulating layer 90 ;
  • the display panel is provided with a first via hole 101 and a second via hole 102 passing through the first gate insulating layer 80 , the first interlayer insulating layer 60 and the second interlayer insulating layer 90 , and Passing through the third via hole 103 and the fourth via hole 104 of the second interlayer insulating layer 90, the second metal layer 110 passes through the first via hole 101 and the second via hole 102 and all the
  • the polysilicon semiconductor layer 21 is connected to form the first source electrode 23 and the first drain electrode 24 and is connected to the oxide semiconductor layer 31 through the third via hole 103 and the fourth via hole 104
  • the second source electrode 33 and the second drain electrode 34 it can be understood that the first via hole 101 and the second via hole 102 only need to pass through the first gate insulating layer 80, the first The three functional layers of the interlayer insulating layer 60 and the second interlayer insulating layer 90 do not need to pass through the third gate insulating layer 40 and the second gate insulating layer 70, which greatly reduces the The hole depth of the first
  • the pore diameters of the first via hole 101 and the second via hole 102 are reduced from 1.1 ⁇ m to 1.6 ⁇ m to 0.7 ⁇ m to 1.4 ⁇ m; similarly, the third via hole 103 and the fourth via hole 104 only need to pass through The second interlayer insulating layer 90 does not need to pass through the third gate insulating layer 40 , which also reduces the difficulty of the manufacturing process of the third via hole 103 and the fourth via hole 104 and reduces the The contact resistance of the second source electrode 33 and the second drain electrode 34 being overlapped with the oxide semiconductor layer 31 .
  • the display panel includes a display area 100 and a binding area 200 adjacent to the display area 100 , the first thin film transistor 20 and the second thin film transistor 30 . arranged in the display area 100;
  • the first metal layer 50 further includes a first metal trace 53 located in the bonding area 200
  • the second metal layer 110 further includes a second metal trace 111 located in the binding area 200
  • the first metal trace 53 is provided with a fifth via hole 105 which passes through the first interlayer insulating layer 60 and the second interlayer insulating layer 90 in sequence, and the second metal trace 111 passes through
  • the fifth via hole 105 is connected to the first metal trace 53; it can be understood that the fifth via hole 105 only needs to pass through the first interlayer insulating layer 60 and the second interlayer
  • the insulating layer 90 does not need to pass through the second gate insulating layer 70, thereby reducing the fabrication process of the fifth via hole 105 and reducing the distance between the second metal trace 111 and the first metal
  • the contact resistance of the wire 53 overlap.
  • the second gate is insulated
  • the layer 70 further includes a third insulator part 73 corresponding to the position of the first metal trace 53 , and the orthographic projection of the third insulator part 73 on the substrate 10 covers the position of the first metal trace 53 .
  • the orthographic projection on the substrate 10 obviously, the first metal trace 53 and the third insulator part 73 are both located in the binding area 200, and the first via 101 and the The film layer structure that the second via hole 102 needs to pass through; in addition, as shown in FIG.
  • the display panel further includes a deep hole 106 located in the binding region 200 , and the deep hole is filled with organic matter Filling layer 107
  • the base 10 includes a first substrate 11, a spacer layer 12, a second substrate 13, a buffer layer 14 and a cover layer 15 in sequence; specifically, the deep hole 106 only needs to pass through the buffer layer 14.
  • the capping layer 15, the first gate insulating layer 80, the first interlayer insulating layer 60 and the second interlayer insulating layer 90 do not need to additionally pass through the second gate insulating layer 70 and the first interlayer insulating layer 90.
  • the triple gate insulating layer 40 reduces the difficulty of the fabrication process of the deep hole 106 , and also improves the performance of the PAD Bending of each functional layer in the bonding region 200 .
  • the pattern of the second gate insulating layer 70 is the same as that of the first metal layer 50 , and the pattern of the second gate insulating layer 70 on the substrate 10 is the same.
  • the orthographic projection covers the orthographic projection of the first metal layer 50 on the substrate 10; it can be understood that the pattern of the second gate insulating layer 70 is the same as that of the first metal layer 50, so that the first The second gate insulating layer 70 and the first metal layer 50 are just aligned.
  • the second gate insulating layer 70 and the first metal layer 50 can be formed by patterning the same mask, so that the The orthographic projection of the second gate insulating layer 70 on the substrate 10 covers the orthographic projection of the first metal layer 50 on the substrate 10; it is avoided that the second gate insulating layer 70 is disposed at any In the region outside the location of the first metal layer 50, the film thickness of the region outside the location of the first metal layer 50 is reduced.
  • the pattern of the third gate insulating layer 40 and the third gate electrode 32 is the same, and the pattern of the third gate insulating layer 40 on the substrate 10 is the same.
  • the orthographic projection covers the orthographic projection of the third gate electrode 32 on the substrate 10; it can be understood that the pattern of the third gate insulating layer 40 and the third gate electrode 32 is the same, so that the third gate insulating layer 40 has the same pattern as the third gate electrode 32.
  • the triple gate insulating layer 40 and the third gate 32 are just aligned.
  • the third gate insulating layer 40 and the third gate 32 can be patterned using the same mask, so that the The orthographic projection of the third gate insulating layer 40 on the substrate 10 covers the orthographic projection of the third gate 32 on the substrate 10; it is avoided that the third gate insulating layer 40 is disposed at the The region outside the position of the third gate electrode 32 is reduced, and the film thickness of the region outside the position of the third gate electrode 32 is reduced.
  • the oxide semiconductor layer 31 includes an active segment 311 corresponding to the position of the third gate 32 , and two conductors located at two ends of the active segment 311 respectively.
  • segment 312 the orthographic projection of the third gate insulating layer 40 on the substrate 10 covers the orthographic projection of the active segment 311 on the substrate 10; it can be understood that the third gate insulating layer The layer 40 covers part of the oxide semiconductor layer 31 .
  • the orthographic projection of the third gate insulating layer 40 on the substrate 10 covers the positive projection of the active segment 311 on the substrate 10 .
  • the third gate insulating layer 31 is fabricated on the oxide semiconductor layer 31 .
  • a conductorization process can be performed directly on the oxide semiconductor layer 31, and the oxide semiconductor layer 31 can be directly subjected to a conductorization process using the third gate insulating layer 40 as a mask.
  • the portion of the semiconductor layer 31 that is not covered by the third gate insulating layer 40 is directly conductive, so that the oxide semiconductor layer 31 includes the active segment 311 , and two conductor segments 312 respectively located at both ends of the active segment 311.
  • the oxide semiconductor in the IGZO TFT is covered by the entire surface, and only the first via hole 101 and the After the second via hole 102 is formed, the oxide semiconductor layer 31 is conductive, and only the oxide semiconductor layer 31 corresponding to the first via hole 101 and the second via hole 102 can be conductive.
  • the second source electrode 33 and the second drain electrode 34 are respectively connected to The two conductor segments 312 are connected, the wiring resistance of the conductor segments 312 is 500 ohms to 1200 ohms, and the contact resistance between the conductor segments 312 and the second source electrode 33 or the second drain electrode 34 is 700 ohms to 1800 ohms; in addition, during specific use, the oxide semiconductor layer 31 may also include oxide semiconductor traces (not shown in the figure) connected to other functional layers if necessary. It is also possible to realize the complete conductorization of the oxide semiconductor wiring and reduce the contact resistance between the oxide semiconductor layer 31 and other functional layers.
  • the third gate insulating layer 40 is located in the channel region between the second source electrode 33 and the second drain electrode 34 under the view of the hierarchical structure. ; It can be understood that the third gate insulating layer 40 may be located in the channel region between the second source electrode 33 and the second drain electrode 34, that is, the third gate is avoided.
  • the electrode insulating layer 40 is located under the second source electrode 33 and the second drain electrode 34 , reducing the third via hole 103 and the third via hole 103 under the second source electrode 33 and the second drain electrode 34 .
  • the hole depth of the fourth via hole 104 is located in the channel region between the second source electrode 33 and the second drain electrode 34 under the view of the hierarchical structure. ; It can be understood that the third gate insulating layer 40 may be located in the channel region between the second source electrode 33 and the second drain electrode 34, that is, the third gate is avoided.
  • the electrode insulating layer 40 is located under the second source electrode 33 and the second drain electrode 34 , reducing the third via hole 103 and the third
  • the width of the third gate insulating layer 40 is larger than the width of the third gate 32 by 0.2 ⁇ m ⁇ 1.2 ⁇ m; it can be understood that the width of the third gate insulating layer 40 is The width is set to be larger than the width of the third gate electrode 32 to avoid that the width of the third gate electrode 32 is larger than the width of the third gate insulating layer 40 , which may cause the third gate electrode 32 and the
  • the third gate insulating layer 40 and the third gate 32 can be formed by patterning the same mask to make the third gate insulating
  • the orthographic projection of the layer 40 on the substrate 10 covers the orthographic projection of the third gate 32 on the substrate 10 , and the third gate insulating layer 40 and the third gate can be adjusted through a patterning process
  • the inclination angle of the side of the pole 32, specifically, the width of the third gate insulating layer 40 is 0.2um to 1.2um larger than the width of the third gate 32; on the same side, the third gate
  • the present application also provides a method for manufacturing a display panel, as shown in FIG. 3 , comprising the following steps:
  • Step S100 providing a substrate 10
  • Step S200 forming a first thin film transistor 20 and a second thin film transistor 30 on the substrate 10 at intervals, the first thin film transistor 20 includes a polysilicon semiconductor layer 21 formed on the The first gate electrode 22 above the polysilicon semiconductor layer 21 , and the first source electrode 23 and the first drain electrode 24 respectively connected to the polysilicon semiconductor layer 21 ; an oxide semiconductor layer 31, a third gate electrode 32 formed above the oxide semiconductor layer 31, and a second source electrode 33 and a second drain electrode 34 respectively connected to the oxide semiconductor layer 31; A third gate insulating layer 40 corresponding to the position of the third gate 32 is formed between the oxide semiconductor layer 31 and the third gate 32, and the third gate insulating layer 40 covers a part of the gate.
  • the oxide semiconductor layer 31 is described.
  • the third gate insulating layer 40 is patterned to prevent the thickness of the display panel from increasing due to the structure of the third gate insulating layer 40 covering the entire layer. Specifically, as shown in FIGS. 4C to 4D , the The third gate insulating layer 40 and the third gate 32 are patterned using the same mask. It should be noted that the third gate insulating layer 40 and the third gate 32 are patterned using the same mask.
  • the third gate insulating layer 40 and the third gate 32 may be formed by etching using the same mask, or it may be understood that the third gate insulating layer 40 is formed by etching the third gate insulating layer 40.
  • the three gates 32 are formed by mask etching, so that the pattern of the third gate insulating layer 40 is the same as that of the third gate 32 , and the third gate insulating layer 40 is formed on the substrate 10 .
  • the orthographic projection covers the orthographic projection of the third gate 32 on the substrate 10 ; the only difference is that, in the patterning process, the third gate insulating layer 40 is etched and the third gate 32 is etched.
  • Different etching gases are used, which not only changes the pattern structure of the third gate insulating layer 40 , but also reduces the via holes between the first source electrode 23 and the first drain electrode 24 in the first thin film transistor 20 and the polysilicon semiconductor layer 21 .
  • the depth of 113 reduces the contact resistance of the first source electrode 23 and the first drain electrode 24 and the polysilicon semiconductor layer 21 lapped together, and there is no additional process and production cost, which is suitable for large-scale production.
  • step S200 in step S200 , forming the first thin film transistor 20 and the second thin film transistor 30 on the substrate 10 at intervals includes:
  • a first gate insulating layer 80 is formed on the polycrystalline silicon semiconductor layer 21 and the substrate 10 , the first gate electrode 22 is formed on the first gate insulating layer 80 , and the first gate electrode 22 is formed on the first gate insulating layer 80 .
  • a second gate insulating layer 70 is formed thereon, a first metal layer 50 is formed on the second gate insulating layer 70 , and a first metal layer 50 is formed on the first metal layer 50 and the first gate insulating layer 80
  • the interlayer insulating layer 60 wherein the second gate insulating layer 70 corresponds to the position of the first metal layer 50 , and the first metal layer 50 includes a first metal layer opposite to the oxide semiconductor layer 31 .
  • the second gate insulating layer 70 includes a first insulator portion 71 corresponding to the position of the second gate 51 , and the orthographic projection of the first insulator portion 71 on the substrate 10 covers the orthographic projection of the second grid 51 on the substrate 10;
  • the oxide semiconductor layer 31 is formed on the first interlayer insulating layer 60 , the second interlayer insulating layer 90 is formed on the third gate electrode 32 , and the second interlayer insulating layer 90 is formed The second metal layer 110 .
  • the position where the second gate insulating layer 70 is formed corresponds to the position where the first metal layer 50 is formed, which is equivalent to performing a patterning step on the second gate insulating layer 70 , to prevent the second gate insulating layer 70 from increasing the thickness of the display panel due to the whole-layer covering structure.
  • the second gate insulating layer The layer 70 and the first metal layer 50 are patterned using the same mask; it should be noted that the second gate insulating layer 70 and the first metal layer 50 are patterned using the same mask.
  • the second gate insulating layer 70 and the first metal layer 50 may be formed by etching using the same mask, or it can be understood that the second gate insulating layer 70 is formed by etching the first metal layer 50 as The mask is etched and formed, so that the pattern of the second gate insulating layer 70 and the first metal layer 50 is the same, and the orthographic projection of the second gate insulating layer 70 on the substrate 10 covers the The orthographic projection of the first metal layer 50 on the substrate 10 ; the only difference is that in the patterning process, the etching gas used for etching the second gate insulating layer 70 is different from the etching gas used for etching the first metal layer 50 ; Not only the pattern structure of the second gate insulating layer 70 is changed, but also the depth of the via hole 113 between the first source electrode 23 and the first drain electrode 24 in the first thin film transistor 20 and the polysilicon semiconductor layer 21 is reduced, reducing the The contact resistance of the first source electrode 23 and the first drain electrode 24 and the polysilicon semiconductor layer 21 overlapped,
  • the first metal layer 50 includes a second gate electrode 51 disposed opposite to the oxide semiconductor layer 31
  • the second gate insulating layer 70 includes a first insulator portion 71 corresponding to the position of the second gate electrode 51
  • the second gate insulating layer 70 The orthographic projection of an insulator portion 71 on the substrate 10 covers the orthographic projection of the second gate 51 on the substrate 10 .
  • the method before forming the second metal layer 110 on the second interlayer insulating layer 90, the method further includes:
  • a first via hole 101 and a second via hole 102 are formed in the display panel through the first gate insulating layer 80 , the first interlayer insulating layer 60 and the second interlayer insulating layer 90 , and forming a third via hole 103 and a fourth via hole 104 passing through the second interlayer insulating layer 90;
  • the forming the second metal layer 110 on the second interlayer insulating layer 90 includes:
  • the first source electrode 23 and the first drain electrode connected to the polysilicon semiconductor layer 21 through the first via hole 101 and the second via hole 102 are formed on the second interlayer insulating layer 90 24 ; and the second source electrode 33 and the second drain electrode 34 connected to the oxide semiconductor layer 31 through the third via hole 103 and the fourth via hole 104 .
  • the display panel includes a display area 100 and a binding area 200 adjacent to the display area 100 , the first thin film transistor 20 and the second thin film
  • the transistor 30 is disposed in the display area 100, and the substrate 10 sequentially includes a first substrate 11, a spacer layer 12, a second substrate 13, a buffer layer 14 and a cover layer 15; wherein, the substrate 10 is formed in the display panel
  • the first via hole 101 , the second via hole 102 , the third via hole 103 and the fourth via hole 104 , a fifth via hole 105 and a deep hole in the binding area 200 are also formed in the display panel.
  • the fifth via hole 105 passes through the first interlayer insulating layer 60 and the second interlayer insulating layer 90, the deep hole 106 passes through the buffer layer 14, the cover layer 15, the first interlayer insulating layer 90 A gate insulating layer 80, the first interlayer insulating layer 60 and the second interlayer insulating layer 90; obviously, the fifth via hole 105 does not need to pass through the second gate insulating layer 70, the deep The hole 106 does not need to pass through the second gate insulating layer 70 and the third gate insulating layer 40 , thereby reducing the fabrication process of the fifth via hole 105 and the deep hole 106 and reducing the The contact resistance of the second metal trace 111 overlapping with the first metal trace 53 improves the performance of the PAD Bending of each functional layer in the binding area 200;
  • the manufacturing method of the display panel further includes forming a first flat layer 120 , a bridge layer 121 , a second flat layer 122 , an anode 123 , a first flat layer 120 , a bridge layer 121 , a second flat layer 122 , an anode 123 , The pixel definition layer 124 , the light emitting functional layer 125 and the support spacer pillars 126 .
  • the third gate insulating layer 40 is disposed at a position corresponding to the position of the third gate 32 , and the third gate insulating layer 40 covers part of the oxide semiconductor in the second thin film transistor 30
  • the layer 31 prevents the third gate insulating layer 40 from being disposed in the display panel on the whole surface, reduces the film thickness of other positions in the display panel except the area where the third gate 32 is located, and is convenient to reduce the first thin film transistor 20
  • the depth of the via hole between the first source electrode 23 and the first drain electrode 24 and the polysilicon semiconductor layer 21 reduces the contact resistance of the first source electrode 23 and the first drain electrode 24 and the polysilicon semiconductor layer 21 overlapping;
  • the film thickness of the display panel in the binding area 200 is also reduced, the technological difficulty of digging holes in the binding area 200 is reduced, and the PAD in the binding area 200 is also reduced. Impact of Bending.

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Abstract

本申请提出了一种显示面板，包括基底、以及间隔设置于基底上的第一薄膜晶体管和第二薄膜晶体管，在氧化物半导体层远离第三栅极一侧设置第一金属层，第一金属层与氧化物半导体层之间设置第一层间绝缘层，第一金属层远离所述氧化物半导体层的一侧设有第二栅极绝缘层，第一金属层包括与氧化物半导体层相对设置的第二栅极。

Description

显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
随着显示技术的发展，LTPO(Low Temperature Polycrystalline Oxide, 低温多晶氧化物)作为一种低功耗的显示技术受到越来越广泛的关注，相比于LTPS TFT（Low Temperature Poly-Silicon TFT，低温多晶硅薄膜晶体管），LTPO TFT(Low Temperature Polycrystalline Oxide TFT , 低温多晶氧化物薄膜晶体管)具有更低的驱动功率，并且LTPO TFT将部分晶体管转化成氧化物，漏电流更少。
 技术问题
目前，相比于LTPS 结构，制作LTPO结构需要更多的膜层，首先需要制作LTPS TFT，然后再制作氧化物半导体薄膜晶体管，为防止氧化物半导体薄膜晶体管与LTPS TFT之间相互干扰，需要在两者之间形成较厚的绝缘膜层作为阻隔，从而增加了LTPS TFT中源漏极到多晶硅层的距离，增加了源漏极与多晶硅层之间过孔的长度，并且，随着对高分辨率显示的需求越来越多，像素密度越来越大，对过孔的孔径要求越来越小，整体上使得过孔孔径小且孔深长，容易使得蚀刻过孔时造成无机层残留，导致源漏极与多晶硅层之间搭接的接触电阻增大，严重的更会使得源漏极走线发生断线，导致源漏极与多晶硅层之间搭接异常；此外，由于LTPO结构导致膜层的增加，也使得显示面板中绑定区部分的膜层厚度增加，增加了在绑定区内挖孔的工艺难度，并且，也影响了PAD Bending的性能。
具体的，如图1所示，现有的LTPS结构依次包括基板201、多晶硅层202、绝缘层一203、栅极一204、绝缘层二205、绝缘层三206、IGZO (indium gallium zinc oxide铟镓锌氧化物)层207、绝缘层四208、栅极二209、绝缘层五210和源漏极211等膜层结构，显然，所述多晶硅层202与源漏极211之间的过孔212需要穿过绝缘层一203、绝缘层二205、绝缘层三206、绝缘层四208和绝缘层五210等众多膜层，并且孔径较小，增加了工艺难度，容易造成源漏极211与多晶硅层202之间搭接的接触电阻增大或搭接异常的问题；此外，绝缘层二205通常采用诸如氢含量较高的SiNx等材料制作并呈整面设置，使得绝缘层二205中的氢离子很容易入侵到对氢极其敏感的IGZO层207，从而导致IGZO层207导体化而失效。
 技术解决方案
本申请提供一种显示面板，以解决现有LTPO结构中膜层较多，增加了LTPS TFT中源漏极与多晶硅层之间过孔的长度，也减小了过孔的孔径，增加了工艺难度，容易造成源漏极与多晶硅层之间搭接的接触电阻增大或搭接异常的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供了一种显示面板，以解决现有LTPO结构中膜层较多，增加了LTPS TFT中源漏极与多晶硅层之间过孔的长度，也减小了过孔的孔径，增加了工艺难度，容易造成源漏极与多晶硅层之间搭接的接触电阻增大或搭接异常的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供了一种显示面板，包括基底、以及间隔设置于所述基底上的第一薄膜晶体管和第二薄膜晶体管；
所述第一薄膜晶体管包括位于所述基底上的多晶硅半导体层、位于所述多晶硅半导体层上方的第一栅极、及分别与所述多晶硅半导体层连接的第一源极和第一漏极；
所述第二薄膜晶体管包括位于所述基底上方的氧化物半导体层、位于所述氧化物半导体层上方的第三栅极、及分别与所述氧化物半导体层连接的第二源极和第二漏极；
其中，所述氧化物半导体层与所述第三栅极之间设有与所述第三栅极位置相对应的第三栅极绝缘层，所述第三栅极绝缘层覆盖部分所述氧化物半导体层；
所述氧化物半导体层远离所述第三栅极一侧设有第一金属层，所述第一金属层与所述氧化物半导体层之间设有第一层间绝缘层，所述第一金属层远离所述氧化物半导体层的一侧设有第二栅极绝缘层，所述第一金属层包括与所述氧化物半导体层相对设置的第二栅极；
所述多晶硅半导体层和所述基底上设有第一栅极绝缘层，所述第一栅极设置于所述第一栅极绝缘层上，所述第一金属层还包括与所述第一栅极相对设置的电极板。
在本申请所提供的显示面板中，所述第二栅极绝缘层与所述第一金属层的位置相对应，所述第二栅极绝缘层包括与所述第二栅极位置相对应的第一绝缘子部，所述第一绝缘子部在所述基底上的正投影覆盖所述第二栅极在所述基底上的正投影。
在本申请所提供的显示面板中，所述多晶硅半导体层和所述基底上设有第一栅极绝缘层，所述第一栅极设置于所述第一栅极绝缘层上，所述第一金属层还包括与所述第一栅极相对设置的电极板，所述第二栅极绝缘层还包括与所述电极板位置相对应的第二绝缘子部，其中，所述第二绝缘子部部分覆盖所述多晶硅半导体层，所述第二绝缘子部在所述基底上的正投影覆盖所述电极板在所述基底上的正投影。
在本申请所提供的显示面板中，所述第三栅极上设有第二层间绝缘层，所述第二层间绝缘层上设有第二金属层；
所述显示面板内设置有穿过所述第一栅极绝缘层、第一层间绝缘层和所述第二层间绝缘层的第一过孔和第二过孔、以及穿过所述第二层间绝缘层的第三过孔和第四过孔，所述第二金属层穿过所述第一过孔和所述第二过孔与所述多晶硅半导体层连接形成所述第一源极和所述第一漏极且穿过所述第三过孔和所述第四过孔与所述氧化物半导体层连接形成所述第二源极和第二漏极。
在本申请所提供的显示面板中，所述显示面板包括显示区和与所述显示区相邻的绑定区，所述第一薄膜晶体管和所述第二薄膜晶体管设置于所述显示区内；
所述第一金属层还包括位于所述绑定区内的第一金属走线，所述第二金属层还包括位于所述绑定区内的第二金属走线，所述第一金属走线上方设有依次穿过所述第一层间绝缘层和所述第二层间绝缘层的第五过孔，所述第二金属走线穿过所述第五过孔与所述第一金属走线连接。
在本申请所提供的显示面板中，所述第二栅极绝缘层与所述第一金属层的图案相同，且所述第二栅极绝缘层在所述基底上的正投影覆盖所述第一金属层在所述基底上的正投影。
在本申请所提供的显示面板中，所述第三栅极绝缘层与所述第三栅极的图案相同，且所述第三栅极绝缘层在所述基底上的正投影覆盖所述第三栅极在所述基底上的正投影。
在本申请所提供的显示面板中，所述氧化物半导体层包括与所述第三栅极位置相对应的有源段、及分别位于所述有源段两端的两导体段，所述第三栅极绝缘层在所述基底上的正投影覆盖所述有源段在所述基底上的正投影。
在本申请所提供的显示面板中，所述第二源极和所述第二漏极分别与两所述导体段连接，所述导体段的走线电阻为500欧姆～1200欧姆，所述导体段与所述第二源极或与所述第二漏极的接触阻抗为700欧姆～1800欧姆。
在本申请所提供的显示面板中，在层级结构视角下，所述第三栅极绝缘层位于所述第二源极与所述第二漏极之间的沟道区内。
在本申请所提供的显示面板中，所述第三栅极绝缘层的宽度比所述第三栅极的宽度大0.2um～1.2um。
 有益效果
本申请的有益效果为：本申请通过将第三栅极绝缘层设置于与第三栅极位置相对应的位置，并且第三栅极绝缘层覆盖部分第二薄膜晶体管中的氧化物半导体层，避免了第三栅极绝缘层呈整面设置于显示面板中，减小了显示面板中除第三栅极所在区域后其它位置的膜层厚度，便于减少第一薄膜晶体管中第一源极和第一漏极到多晶硅半导体层之间过孔的深度，降低了第一源极和第一漏极与多晶硅半导体层搭接的接触电阻；同时，也降低了显示面板位于绑定区的膜层厚度，降低了绑定区内挖孔的工艺难度，也减少了对绑定区内PAD Bending的影响。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有显示面板的结构示意图；
图2为本申请实施例中显示面板的结构示意图；
图3为本申请实施例中显示面板的制作方法的流程示意框图；及
图4A-4F本申请实施例中显示面板的制作方法的流程结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
现结合具体实施例对本申请的技术方案进行描述。
本申请提供了一种显示面板，如图2所示，包括基底10、以及间隔设置于所述基底10上的第一薄膜晶体管20和第二薄膜晶体管30；
所述第一薄膜晶体管20包括位于所述基底10上的多晶硅半导体层21、位于所述多晶硅半导体层21上方的第一栅极22、及分别与所述多晶硅半导体层21连接的第一源极23和第一漏极24；
所述第二薄膜晶体管30包括位于所述基底10上方的氧化物半导体层31、位于所述氧化物半导体层31上方的第三栅极32、及分别与所述氧化物半导体层31连接的第二源极33和第二漏极34；
其中，所述氧化物半导体层31与所述第三栅极32之间设有与所述第三栅极32位置相对应的第三栅极绝缘层40，所述第三栅极绝缘层40覆盖部分所述氧化物半导体层31；
所述氧化物半导体层31远离所述第三栅极32一侧设有第一金属层50，所述第一金属层50与所述氧化物半导体层31之间设有第一层间绝缘层60，所述第一金属层50远离所述氧化物半导体层31的一侧设有第二栅极绝缘层70，所述第一金属层50包括与所述氧化物半导体层31相对设置的第二栅极51，所述第二栅极绝缘层70可以是呈整面设置；
所述多晶硅半导体层21和所述基底10上设有第一栅极绝缘层80，所述第一栅极22设置于所述第一栅极绝缘层80上，所述第一金属层50还包括与所述第一栅极22相对设置的电极板52；通过所述第二栅极51和所述电极板52的设置可以明显提升所述第一薄膜晶体管和所述第二薄膜晶体管的电学性能，并且，所述第二栅极和所述电极板还位于同一膜层，可以在同一工序中制作，也最大化的减少对显示面板厚度的影响。
可以理解的是，目前，相比于LTPS结构，制作LTPO结构需要更多的膜层，首先需要制作LTPS TFT，然后再制作氧化物半导体薄膜晶体管，为防止氧化物半导体薄膜晶体管与LTPS TFT之间相互干扰，需要在两者之间形成较厚的绝缘膜层作为阻隔，从而增加了LTPS TFT中源漏极到多晶硅层的距离，增加了源漏极与多晶硅层之间过孔的长度，并且，随着对高分辨率显示的需求越来越多，像素密度越来越大，对过孔的孔径要求越来越小，整体上使得过孔孔径小且孔深长，容易使得蚀刻过孔时造成无机层残留，导致源漏极与多晶硅层之间搭接的接触电阻增大，严重的更会使得源漏极走线发生断线，导致源漏极与多晶硅层之间搭接异常；此外，由于LTPO结构导致膜层的增加，也使得显示面板中绑定区部分的膜层厚度增加，增加了在绑定区内挖孔的工艺难度，并且，也影响了PAD Bending的性能；本实施例中，通过将第三栅极绝缘层40设置于与第三栅极32位置相对应的位置，并且第三栅极绝缘层40覆盖部分第二薄膜晶体管30中的氧化物半导体层31，避免了第三栅极绝缘层40呈整面设置于显示面板中，减小了显示面板中除第三栅极32所在区域后其它位置的膜层厚度，便于减少第一薄膜晶体管20中第一源极23和第一漏极24到多晶硅半导体层21之间过孔的深度，降低了第一源极23和第一漏极24与多晶硅半导体层21搭接的接触电阻；同时，也降低了显示面板位于绑定区的膜层厚度，降低了绑定区内挖孔的工艺难度，也减少了对绑定区内PAD Bending的影响；其中，所述氧化物半导体层31的材料为IGZO (indium gallium zinc oxide铟镓锌氧化物)。
在一实施例中，如图2所示，所述第二栅极绝缘层70与所述第一金属层50的位置相对应，所述第二栅极绝缘层70包括与所述第二栅极51位置相对应的第一绝缘子部71，所述第一绝缘子部71在所述基底10上的正投影覆盖所述第二栅极51在所述基底10上的正投影；显然，本实施例中，所述所述第二栅极绝缘层70不是呈整面设置，可以是通过图案化形成所述第一绝缘子部71，可以理解的是，将所述第二栅极绝缘层70设置于与所述第一金属层50位置相对应的位置，可以减少所述显示面板中位于所述第一金属层50所在区域以外部分的膜层厚度；此外，在将第三栅极绝缘层40设置于与第三栅极32位置相对应的位置，降低显示面板位于绑定区的膜层厚度的基础上，本实施例通过将所述第二栅极绝缘层70设置于与所述第一金属层50位置相对应的位置，也进一步降低了显示面板位于绑定区的膜层厚度，进一步降低了绑定区内挖孔的工艺难度，提高了绑定区内各功能层PAD Bending的性能。
承上，本实施例中，所述第二栅极绝缘层70包括与所述第二栅极51位置相对应的第一绝缘子部71，所述第一绝缘子部71与所述第二栅极51的位置相对应，并且，所述第一绝缘子部71在所述基底10上的正投影覆盖所述第二栅极51在所述基底10上的正投影，使得所述第一绝缘子部71对所述第二栅极51整体具备较好的支撑，同时，也减少了所述显示面板中位于所述第二栅极51所在区域以外部分的膜层厚度，例如，减少所述第一源极23和所述第一漏极24与所述多晶硅半导体层21之间的膜层数量，也即减小了所述第一源极23和所述第一漏极24与所述多晶硅半导体层21之间的间距；此外，如图1所示，现有LTPO结构中，由于绝缘层二205通常采用诸如氢含量较高的SiNx等材料制作并呈整面设置，使得绝缘层二205中的氢离子很容易入侵到对氢极其敏感的IGZO层207，从而导致IGZO层207导体化而失效；本实施例中，通过将所述第一绝缘子部71与所述第二栅极51的位置相对应设置，也避免了将所述第二栅极绝缘层70整面设置造成氢离子入侵所述氧化物半导体层31，从而避免了所述氧化物半导体层31的导体化，并且，所述第一绝缘子部71与所述第二栅极51的位置相对应设置，也可以通过所述第二栅极51对所述第一绝缘子部71中的氢离子进行阻挡，避免了所述氧化物半导体层31被导体化而造成器件失效。
在一实施例中，如图2所示，所述第二栅极绝缘层70还包括与所述电极板52位置相对应的第二绝缘子部72，其中，所述第二绝缘子部72部分覆盖所述多晶硅半导体层21，所述第二绝缘子部72在所述基底10上的正投影覆盖所述电极板52在所述基底10上的正投影；可以理解的是，所述第一金属层50还可以包括与所述第一栅极22相对设置的电极板52，对应的，所述第二栅极绝缘层70还包括与所述电极板52位置相对应的第二绝缘子部72，所述电极板52与所述第一栅极22之间形成电容，所述第二绝缘子部72在所述基底10上的正投影覆盖所述电极板52在所述基底10上的正投影，使得所述第二绝缘子部72对所述电极板52具备很好的支撑，同时，所述第二绝缘子部72也可以作为所述电极板52与所述第一栅极22形成电容之间的介质层，显然，所述电极板52和所述第二绝缘子部72位于所述第一源极23与所述第一漏极24之间的区域内，并不影响所述第一源极23和第一漏极24与所述多晶硅半导体层21之间的膜层厚度。
在一实施例中，如图2所示，所述第三栅极32上设有第二层间绝缘层90，所述第二层间绝缘层90上设有第二金属层110；
所述显示面板内设置有穿过所述第一栅极绝缘层80、第一层间绝缘层60和所述第二层间绝缘层90的第一过孔101和第二过孔102、以及穿过所述第二层间绝缘层90的第三过孔103和第四过孔104，所述第二金属层110穿过所述第一过孔101和所述第二过孔102与所述多晶硅半导体层21连接形成所述第一源极23和所述第一漏极24且穿过所述第三过孔103和所述第四过孔104与所述氧化物半导体层31连接形成所述第二源极33和第二漏极34；可以理解的是，所述第一过孔101和所述第二过孔102仅需穿过所述第一栅极绝缘层80、第一层间绝缘层60和所述第二层间绝缘层90三个功能层，而无需额外穿过所述第三栅极绝缘层40和所述第二栅极绝缘层70，极大的减少了所述第一过孔101和所述第二过孔102的孔深，降低了所述第一过孔101和所述第二过孔102的制作工艺难度，同时，也降低了第一源极23和第一漏极24与多晶硅半导体层21搭接的接触电阻，避免了所述第一源极23和第一漏极24与所述多晶硅半导体层21出现搭接异常的问题，具体的，所述第一过孔101和所述第二过孔102的孔径由1.1μm～1.6μm降至0.7μm～1.4μm；同理，所述第三过孔103和第四过孔104仅需穿过所述第二层间绝缘层90，而无需额外穿过所述第三栅极绝缘层40，也减小了所述第三过孔103和第四过孔104的制作工艺难度，降低了所述第二源极33和所述第二漏极34与所述氧化物半导体层31搭接的接触电阻。
在一实施例中，如图2所示，所述显示面板包括显示区100和与所述显示区100相邻的绑定区200，所述第一薄膜晶体管20和所述第二薄膜晶体管30设置于所述显示区100内；
所述第一金属层50还包括位于所述绑定区200内的第一金属走线53，所述第二金属层110还包括位于所述绑定区200内的第二金属走线111，所述第一金属走线53上方设有依次穿过所述第一层间绝缘层60和所述第二层间绝缘层90的第五过孔105，所述第二金属走线111穿过所述第五过孔105与所述第一金属走线53连接；可以理解的是，所述第五过孔105仅需穿过所述第一层间绝缘层60和所述第二层间绝缘层90，而无需穿过所述第二栅极绝缘层70，从而也降低了所述第五过孔105的制作工艺，降低了所述第二金属走线111与所述第一金属走线53搭接的接触电阻。
值得注意的是，如图2所示，本实施例中，当所述第一金属层50还包括位于所述绑定区200内的第一金属走线53时，所述第二栅极绝缘层70还包括与所述第一金属走线53位置相对应的第三绝缘子部73，所述第三绝缘子部73在所述基底10上的正投影覆盖所述第一金属走线53在所述基底10上的正投影；显然，所述第一金属走线53和所述第三绝缘子部73均位于所述绑定区200内，不会额外增加所述第一过孔101和所述第二过孔102所需穿过的膜层结构；此外，如图2所示，所述显示面板还包括一位于所述绑定区200内的深孔106，所述深孔内填充有有机物填充层107，所述基底10依次包括第一衬底11、间隔层12、第二衬底13、缓冲层14和覆盖层15；具体的，所述深孔106仅需穿过所述缓冲层14、覆盖层15、第一栅极绝缘层80、第一层间绝缘层60和所述第二层间绝缘层90，而无需额外穿过所述第二栅极绝缘层70和所述第三栅极绝缘层40，减少了所述深孔106的制作工艺难度，同时也提高了绑定区200内各功能层PAD Bending的性能。
在一实施例中，如图2所示，所述第二栅极绝缘层70与所述第一金属层50的图案相同，且所述第二栅极绝缘层70在所述基底10上的正投影覆盖所述第一金属层50在所述基底10上的正投影；可以理解的是，所述第二栅极绝缘层70与所述第一金属层50的图案相同，使得所述第二栅极绝缘层70与所述第一金属层50刚好对位，本实施例中，所述第二栅极绝缘层70与所述第一金属层50可以采用同一道光罩图案化形成，使得所述第二栅极绝缘层70在所述基底10上的正投影覆盖所述第一金属层50在所述基底10上的正投影；避免所述第二栅极绝缘层70设置在位于所述第一金属层50所在位置之外的区域，减少位于所述第一金属层50所在位置之外的区域的膜层厚度。
在一实施例中，如图2所示，所述第三栅极绝缘层40与所述第三栅极32的图案相同，且所述第三栅极绝缘层40在所述基底10上的正投影覆盖所述第三栅极32在所述基底10上的正投影；可以理解的是，所述第三栅极绝缘层40与所述第三栅极32的图案相同，使得所述第三栅极绝缘层40与所述第三栅极32刚好对位，本实施例中，所述第三栅极绝缘层40与所述第三栅极32可以采用同一道光罩图案化形成，使得所述第三栅极绝缘层40在所述基底10上的正投影覆盖所述第三栅极32在所述基底10上的正投影；避免所述第三栅极绝缘层40设置在位于所述第三栅极32所在位置之外的区域，减少位于所述第三栅极32所在位置之外的区域的膜层厚度。
在一实施例中，如图2所示，所述氧化物半导体层31包括与所述第三栅极32位置相对应的有源段311、及分别位于所述有源段311两端的两导体段312，所述第三栅极绝缘层40在所述基底10上的正投影覆盖所述有源段311在所述基底10上的正投影；可以理解的是，所述第三栅极绝缘层40覆盖部分所述氧化物半导体层31，本实施例中，所述第三栅极绝缘层40在所述基底10上的正投影覆盖所述有源段311在所述基底10上的正投影，使得所述有源段311与所述第三栅极绝缘层40的位置相对应，此种结构形式，使得在具体的制作过程中，在所述氧化物半导体层31上制作所述第三栅极绝缘层40和所述第三栅极32之后，可以对所述氧化物半导体层31直接进行一导体化制程，利用所述第三栅极绝缘层40作为掩膜对所述氧化物半导体层31上未被所述第三栅极绝缘层40覆盖的部分直接进行导体化，以使得所述氧化物半导体层31包括与所述第三栅极32位置相对应的有源段311、及分别位于所述有源段311两端的两导体段312，相比于现有IGZO结构中，IGZO TFT中的氧化物半导体被整面覆盖，只能在所述第一过孔101和所述第二过孔102制作好后对所述氧化物半导体层31进行导体化，且只能对所述氧化物半导体层31与所述第一过孔101和所述第二过孔102相对应的局部区域进行导体化，本实施例中，可以实现对所述氧化物半导体层31中除所述有源段311外的其它部分完全进行导体化，降低了所述导体段312的走线电阻，同时也降低了所述导体段312与所述第二源极33或与所述第二漏极34的接触阻抗，具体的，所述第二源极33和所述第二漏极34分别与两所述导体段312连接，所述导体段312的走线电阻为500欧姆～1200欧姆，所述导体段312与所述第二源极33或与所述第二漏极34的接触阻抗为700欧姆～1800欧姆；此外，在具体使用时，所述氧化物半导体层31如有必要还可以包括与其它功能层连接的氧化物半导体走线（图中未出示），采用本实施例中上述结构，也可以实现所述氧化物半导体走线的完全导体化，降低所述氧化物半导体层31与其它功能层连接的接触阻抗。
在一实施例中，如图2所示，在层级结构视角下，所述第三栅极绝缘层40位于所述第二源极33与所述第二漏极34之间的沟道区内；可以理解的是，所述第三栅极绝缘层40可以位于所述第二源极33与所述第二漏极34之间的沟道区内，也即是避免了所述第三栅极绝缘层40位于所述第二源极33与所述第二漏极34的下方，减少了所述第二源极33与所述第二漏极34下方的所述第三过孔103和第四过孔104的孔深。
在一实施例中，所述第三栅极绝缘层40的宽度比所述第三栅极32的宽度大0.2um～1.2um；可以理解的是，将所述第三栅极绝缘层40的宽度设置成比所述第三栅极32的宽度大，避免所述第三栅极32的宽度大于所述第三栅极绝缘层40的宽度后，容易造成所述第三栅极32与所述氧化物半导体层31短接的现象，本实施例中，所述第三栅极绝缘层40与所述第三栅极32可以采用同一道光罩图案化形成，使得所述第三栅极绝缘层40在所述基底10上的正投影覆盖所述第三栅极32在所述基底10上的正投影，可以通过图案化工艺调整所述第三栅极绝缘层40与所述第三栅极32侧边的倾斜角，具体的，所述第三栅极绝缘层40的宽度比所述第三栅极32的宽度大0.2um～1.2um；在同一侧边处，所述第三栅极绝缘层40单边的宽度比所述第三栅极32单边的宽度大0.1um～0.6um；此外，所述显示面板还可以包括位于所述第二层间绝缘层90上方的第一平坦层120、桥接层121、第二平坦层122、阳极123、像素定义层124、发光功能层125和支撑隔垫柱126。
本申请还提供一种显示面板的制作方法，如图3所示，包括如下步骤：
步骤S100：提供一基底10；
步骤S200：在所述基底10上形成间隔设置的第一薄膜晶体管20和第二薄膜晶体管30，所述第一薄膜晶体管20包括形成于所述基底10上的多晶硅半导体层21、形成于所述多晶硅半导体层21上方的第一栅极22、及分别与所述多晶硅半导体层21连接的第一源极23和第一漏极24；所述第二薄膜晶体管30包括形成于所述基底10上方的氧化物半导体层31、形成于所述氧化物半导体层31上方的第三栅极32、及分别与所述氧化物半导体层31连接第二源极33和第二漏极34；其中，所述氧化物半导体层31与所述第三栅极32之间形成有与所述第三栅极32位置相对应的第三栅极绝缘层40，所述第三栅极绝缘层40覆盖部分所述氧化物半导体层31。
可以理解的是，在制作所述第二薄膜晶体管30的过程中，通过将所述第三栅极绝缘层40形成在所述第三栅极32位置相对应的位置，相当于对所述第三栅极绝缘层40图案化，避免所述第三栅极绝缘层40为整层覆盖的结构造成所述显示面板各处的厚度增加，具体的，如图4C至图4D所示，所述第三栅极绝缘层40与所述第三栅极32采用同一道光罩图案化形成，需要说明的是，所述第三栅极绝缘层40与所述第三栅极32采用同一道光罩图案化形成，所述第三栅极绝缘层40与所述第三栅极32可以是采用同一光罩蚀刻成型，也可以理解为所述第三栅极绝缘层40以蚀刻成型后的所述第三栅极32为光罩蚀刻成型，从而使得所述第三栅极绝缘层40与所述第三栅极32的图案相同，且所述第三栅极绝缘层40在所述基底10上的正投影覆盖所述第三栅极32在所述基底10上的正投影；区别仅在于，在图案化过程中，蚀刻所述第三栅极绝缘层40与蚀刻所述第三栅极32所采用的蚀刻气体不同，不仅改变了所述第三栅极绝缘层40的图案结构，实现减少第一薄膜晶体管20中第一源极23和第一漏极24到多晶硅半导体层21之间过孔113的深度，降低了第一源极23和第一漏极24与多晶硅半导体层21搭接的接触电阻，而且没有额外增加工艺制程，不增加生产成本，适于规模化制作。
在一实施例中，如图4A至4E所示，在步骤S200中，所述在所述基底10上形成间隔设置的第一薄膜晶体管20和第二薄膜晶体管30包括：
在所述多晶硅半导体层21和所述基底10上形成第一栅极绝缘层80，在所述第一栅极绝缘层80上形成所述第一栅极22，在所述第一栅极22上形成第二栅极绝缘层70，在所述第二栅极绝缘层70上形成第一金属层50，在所述第一金属层50和所述第一栅极绝缘层80上形成第一层间绝缘层60，其中，所述第二栅极绝缘层70与所述第一金属层50的位置相对应，所述第一金属层50包括与所述氧化物半导体层31相对设置的第二栅极51，所述第二栅极绝缘层70包括与所述第二栅极51位置相对应的第一绝缘子部71，所述第一绝缘子部71在所述基底10上的正投影覆盖所述第二栅极51在所述基底10上的正投影；
在所述第一层间绝缘层60上形成所述氧化物半导体层31，在所述第三栅极32上形成第二层间绝缘层90，在所述第二层间绝缘层90上形成第二金属层110。
可以理解的是，将形成所述第二栅极绝缘层70的位置与形成所述第一金属层50的位置相对应，相当于对所述第二栅极绝缘层70进行了一图案化步骤，避免所述第二栅极绝缘层70为整层覆盖的结构造成所述显示面板各处的厚度增加，在一实施例中，如图4A至图4B所示，所述第二栅极绝缘层70与所述第一金属层50采用同一道光罩图案化形成；需要说明的是，所述第二栅极绝缘层70与所述第一金属层50采用同一道光罩图案化形成，所述第二栅极绝缘层70与所述第一金属层50可以是采用同一光罩蚀刻成型，也可以理解为所述第二栅极绝缘层70以蚀刻成型后的所述第一金属层50为光罩蚀刻成型，从而使得所述第二栅极绝缘层70与所述第一金属层50的图案相同，且所述第二栅极绝缘层70在所述基底10上的正投影覆盖所述第一金属层50在所述基底10上的正投影；区别仅在于，在图案化过程中，蚀刻所述第二栅极绝缘层70与蚀刻所述第一金属层50所采用的蚀刻气体不同；不仅改变了所述第二栅极绝缘层70的图案结构，实现减少第一薄膜晶体管20中第一源极23和第一漏极24到多晶硅半导体层21之间过孔113的深度，降低了第一源极23和第一漏极24与多晶硅半导体层21搭接的接触电阻，而且没有额外增加工艺制程，不增加生产成本，适于规模化制作；具体的，所述第一金属层50包括与所述氧化物半导体层31相对设置的第二栅极51，所述第二栅极绝缘层70包括与所述第二栅极51位置相对应的第一绝缘子部71，所述第一绝缘子部71在所述基底10上的正投影覆盖所述第二栅极51在所述基底10上的正投影。
在一实施例中，在所述第二层间绝缘层90上形成第二金属层110之前，还包括：
在所述显示面板内形成穿过所述第一栅极绝缘层80、第一层间绝缘层60和所述第二层间绝缘层90的第一过孔101和第二过孔102、以及形成穿过所述第二层间绝缘层90的第三过孔103和第四过孔104；
所述在所述第二层间绝缘层90上形成第二金属层110包括：
在所述第二层间绝缘层90上形成穿过所述第一过孔101和所述第二过孔102与所述多晶硅半导体层21连接的第一源极23和所述第一漏极24；及穿过所述第三过孔103和所述第四过孔104与所述氧化物半导体层31连接的第二源极33和第二漏极34。
可以理解的是，如图4E至图4F所示，所述显示面板包括显示区100和与所述显示区100相邻的绑定区200，所述第一薄膜晶体管20和所述第二薄膜晶体管30设置于所述显示区100内，所述基底10依次包括第一衬底11、间隔层12、第二衬底13、缓冲层14和覆盖层15；其中，在所述显示面板内形成第一过孔101、第二过孔102、第三过孔103和第四过孔104的同时，在所述显示面板内还形成位于所述绑定区200内的第五过孔105和深孔106，所述第五过孔105穿过所述第一层间绝缘层60和所述第二层间绝缘层90，所述深孔106穿过所述缓冲层14、覆盖层15、第一栅极绝缘层80、第一层间绝缘层60和所述第二层间绝缘层90；显然，所述第五过孔105无需穿过所述第二栅极绝缘层70，所述深孔106无需穿过所述第二栅极绝缘层70和所述第三栅极绝缘层40，从而也降低了所述第五过孔105和所述深孔106的制作工艺，降低了所述第二金属走线111与所述第一金属走线53搭接的接触电阻，提高了绑定区200内各功能层PAD Bending的性能；
此外，如图4F所示，所述显示面板的制作方法还包括，在所述第二层间绝缘层90上依次形成第一平坦层120、桥接层121、第二平坦层122、阳极123、像素定义层124、发光功能层125和支撑隔垫柱126。
综上所述，本申请通过将第三栅极绝缘层40设置于与第三栅极32位置相对应的位置，并且第三栅极绝缘层40覆盖部分第二薄膜晶体管30中的氧化物半导体层31，避免了第三栅极绝缘层40呈整面设置于显示面板中，减小了显示面板中除第三栅极32所在区域后其它位置的膜层厚度，便于减少第一薄膜晶体管20中第一源极23和第一漏极24到多晶硅半导体层21之间过孔的深度，降低了第一源极23和第一漏极24与多晶硅半导体层21搭接的接触电阻；同时，也降低了显示面板位于绑定区200的膜层厚度，降低了绑定区200内挖孔的工艺难度，也减少了对绑定区200内PAD Bending的影响。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，包括基底、以及间隔设置于所述基底上的第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管包括位于所述基底上的多晶硅半导体层、位于所述多晶硅半导体层上方的第一栅极、及分别与所述多晶硅半导体层连接的第一源极和第一漏极；
    所述第二薄膜晶体管包括位于所述基底上方的氧化物半导体层、位于所述氧化物半导体层上方的第三栅极、及分别与所述氧化物半导体层连接的第二源极和第二漏极；
    其中，所述氧化物半导体层与所述第三栅极之间设有与所述第三栅极位置相对应的第三栅极绝缘层，所述第三栅极绝缘层覆盖部分所述氧化物半导体层；
    所述氧化物半导体层远离所述第三栅极一侧设有第一金属层，所述第一金属层与所述氧化物半导体层之间设有第一层间绝缘层，所述第一金属层远离所述氧化物半导体层的一侧设有第二栅极绝缘层，所述第一金属层包括与所述氧化物半导体层相对设置的第二栅极；
    所述多晶硅半导体层和所述基底上设有第一栅极绝缘层，所述第一栅极设置于所述第一栅极绝缘层上，所述第一金属层还包括与所述第一栅极相对设置的电极板。
  2. 根据权利要求1所述的显示面板，其中，所述第二栅极绝缘层与所述第一金属层的位置相对应，所述第二栅极绝缘层包括与所述第二栅极位置相对应的第一绝缘子部，所述第一绝缘子部在所述基底上的正投影覆盖所述第二栅极在所述基底上的正投影。
  3. 根据权利要求2所述的显示面板，其中，所述第二栅极绝缘层还包括与所述电极板位置相对应的第二绝缘子部，其中，所述第二绝缘子部部分覆盖所述多晶硅半导体层，所述第二绝缘子部在所述基底上的正投影覆盖所述电极板在所述基底上的正投影。
  4. 根据权利要求3所述的显示面板，其中，所述第三栅极上设有第二层间绝缘层，所述第二层间绝缘层上设有第二金属层；
    所述显示面板内设置有穿过所述第一栅极绝缘层、第一层间绝缘层和所述第二层间绝缘层的第一过孔和第二过孔、以及穿过所述第二层间绝缘层的第三过孔和第四过孔，所述第二金属层穿过所述第一过孔和所述第二过孔与所述多晶硅半导体层连接形成所述第一源极和所述第一漏极且穿过所述第三过孔和所述第四过孔与所述氧化物半导体层连接形成所述第二源极和第二漏极。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板包括显示区和与所述显示区相邻的绑定区，所述第一薄膜晶体管和所述第二薄膜晶体管设置于所述显示区内；
    所述第一金属层还包括位于所述绑定区内的第一金属走线，所述第二金属层还包括位于所述绑定区内的第二金属走线，所述第一金属走线上方设有依次穿过所述第一层间绝缘层和所述第二层间绝缘层的第五过孔，所述第二金属走线穿过所述第五过孔与所述第一金属走线连接。
  6. 根据权利要求2所述的显示面板，其中，所述第二栅极绝缘层与所述第一金属层的图案相同，且所述第二栅极绝缘层在所述基底上的正投影覆盖所述第一金属层在所述基底上的正投影。
  7. 根据权利要求1所述的显示面板，其中，所述第三栅极绝缘层与所述第三栅极的图案相同，且所述第三栅极绝缘层在所述基底上的正投影覆盖所述第三栅极在所述基底上的正投影。
  8. 根据权利要求7所述的显示面板，其中，所述氧化物半导体层包括与所述第三栅极位置相对应的有源段、及分别位于所述有源段两端的两导体段，所述第三栅极绝缘层在所述基底上的正投影覆盖所述有源段在所述基底上的正投影。
  9. 根据权利要求8所述的显示面板，其中，所述第二源极和所述第二漏极分别与两所述导体段连接，所述导体段的走线电阻为500欧姆～1200欧姆，所述导体段与所述第二源极或与所述第二漏极的接触阻抗为700欧姆～1800欧姆。
  10. 根据权利要求7所述的显示面板，其中，在层级结构视角下，所述第三栅极绝缘层位于所述第二源极与所述第二漏极之间的沟道区内。
  11. 根据权利要求7所述的显示面板，其中，所述第三栅极绝缘层的宽度比所述第三栅极的宽度大0.2um～1.2um。
  12. 一种显示面板，包括基底、以及间隔设置于所述基底上的第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管包括位于所述基底上的多晶硅半导体层、位于所述多晶硅半导体层上方的第一栅极、及分别与所述多晶硅半导体层连接的第一源极和第一漏极；
    所述第二薄膜晶体管包括位于所述基底上方的氧化物半导体层、位于所述氧化物半导体层上方的第三栅极、及分别与所述氧化物半导体层连接的第二源极和第二漏极；
    其中，所述氧化物半导体层与所述第三栅极之间设有与所述第三栅极位置相对应的第三栅极绝缘层，所述第三栅极绝缘层覆盖部分所述氧化物半导体层；
    所述氧化物半导体层远离所述第三栅极一侧设有第一金属层，所述第一金属层与所述氧化物半导体层之间设有第一层间绝缘层，所述第一金属层远离所述氧化物半导体层的一侧设有第二栅极绝缘层，所述第一金属层包括与所述氧化物半导体层相对设置的第二栅极；
    所述多晶硅半导体层和所述基底上设有第一栅极绝缘层，所述第一栅极设置于所述第一栅极绝缘层上，所述第一金属层还包括与所述第一栅极相对设置的电极板；
    所述第二栅极绝缘层与所述第一金属层的位置相对应，所述第二栅极绝缘层包括与所述第二栅极位置相对应的第一绝缘子部，所述第一绝缘子部在所述基底上的正投影覆盖所述第二栅极在所述基底上的正投影；
    所述第三栅极绝缘层与所述第三栅极的图案相同，且所述第三栅极绝缘层在所述基底上的正投影覆盖所述第三栅极在所述基底上的正投影。
  13. 根据权利要求12所述的显示面板，其中，所述第二栅极绝缘层还包括与所述电极板位置相对应的第二绝缘子部，其中，所述第二绝缘子部部分覆盖所述多晶硅半导体层，所述第二绝缘子部在所述基底上的正投影覆盖所述电极板在所述基底上的正投影。
  14. 根据权利要求13所述的显示面板，其中，所述第三栅极上设有第二层间绝缘层，所述第二层间绝缘层上设有第二金属层；
    所述显示面板内设置有穿过所述第一栅极绝缘层、第一层间绝缘层和所述第二层间绝缘层的第一过孔和第二过孔、以及穿过所述第二层间绝缘层的第三过孔和第四过孔，所述第二金属层穿过所述第一过孔和所述第二过孔与所述多晶硅半导体层连接形成所述第一源极和所述第一漏极且穿过所述第三过孔和所述第四过孔与所述氧化物半导体层连接形成所述第二源极和第二漏极。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板包括显示区和与所述显示区相邻的绑定区，所述第一薄膜晶体管和所述第二薄膜晶体管设置于所述显示区内；
    所述第一金属层还包括位于所述绑定区内的第一金属走线，所述第二金属层还包括位于所述绑定区内的第二金属走线，所述第一金属走线上方设有依次穿过所述第一层间绝缘层和所述第二层间绝缘层的第五过孔，所述第二金属走线穿过所述第五过孔与所述第一金属走线连接。
  16. 根据权利要求12所述的显示面板，其中，所述第二栅极绝缘层与所述第一金属层的图案相同，且所述第二栅极绝缘层在所述基底上的正投影覆盖所述第一金属层在所述基底上的正投影。
  17. 根据权利要求12所述的显示面板，其中，所述氧化物半导体层包括与所述第三栅极位置相对应的有源段、及分别位于所述有源段两端的两导体段，所述第三栅极绝缘层在所述基底上的正投影覆盖所述有源段在所述基底上的正投影。
  18. 根据权利要求17所述的显示面板，其中，所述第二源极和所述第二漏极分别与两所述导体段连接，所述导体段的走线电阻为500欧姆～1200欧姆，所述导体段与所述第二源极或与所述第二漏极的接触阻抗为700欧姆～1800欧姆。
  19. 根据权利要求12所述的显示面板，其中，在层级结构视角下，所述第三栅极绝缘层位于所述第二源极与所述第二漏极之间的沟道区内。
  20. 根据权利要求12所述的显示面板，其中，所述第三栅极绝缘层的宽度比所述第三栅极的宽度大0.2um～1.2um。
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