WO2021248614A1 - Goa电路及显示面板 - Google Patents

Goa电路及显示面板 Download PDF

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Publication number
WO2021248614A1
WO2021248614A1 PCT/CN2020/101359 CN2020101359W WO2021248614A1 WO 2021248614 A1 WO2021248614 A1 WO 2021248614A1 CN 2020101359 W CN2020101359 W CN 2020101359W WO 2021248614 A1 WO2021248614 A1 WO 2021248614A1
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Prior art keywords
circuit unit
thin film
signal
film transistor
ckn
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PCT/CN2020/101359
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English (en)
French (fr)
Inventor
胡晓斌
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/055,345 priority Critical patent/US11521553B2/en
Publication of WO2021248614A1 publication Critical patent/WO2021248614A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the invention relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA Gate Driver On Array (array substrate row drive) technology is conducive to the design of the narrow frame of the display screen, and reduces the cost, and has been widely researched and applied.
  • Figure 1 shows a common single-stage GOA circuit.
  • Figure 2 shows the timing diagram of the GOA circuit.
  • the threshold voltage of the thin film transistor drifts after long-term operation, which causes the output signal ST(N), Q(N) and G(N) to attenuate; among them, the thin film transistor whose gate is controlled by the attenuation signal (Figure 1) T11, T31, T41, T25, T52, T54) in the on-state and off-state will further deteriorate, resulting in further attenuation of its output signal. This unstable state will form a vicious circle and cause the GOA circuit to fail.
  • an inverter composed of thin film transistors (T51, T52, T53, T54) in Figure 1 and node voltage maintaining thin film transistors (T42, T26, T32) will be added. But on the one hand, a lot of thin film transistors are added, which makes the area occupied by the GOA circuit larger, and the frame of the panel is widened; on the other hand, the gates of the inverters T52 and T54 are also controlled by the attenuated signal Q(N). There is still a vicious circle generated by the potential competition between the KN node and the Q(N) node in Fig. 1, which easily leads to failure.
  • the purpose of the present invention is to provide a GOA circuit for reducing the number of thin film transistors in the GOA circuit and improving the stability of the GOA circuit.
  • the present invention provides a GOA circuit, including a plurality of GOA circuit units cascaded, wherein the n-th GOA circuit unit includes: a pull-up control circuit unit (101), a pull-up circuit unit (102), and a downstream circuit unit (103) ), a pull-down circuit unit (104), and a capacitor (Cb); wherein, the pull-up control circuit unit (101), the pull-up circuit unit (102), the downstream circuit unit (103), the The pull-down circuit unit (104), the pull-down sustain circuit unit (105), and the capacitor (Cb) are all electrically connected to the first node Q(n); the pull-up circuit unit (101) is respectively connected to the n-1th stage The clock signal (CKN-1), the start trigger signal (STV) of the GOA circuit unit or the stage transmission signal (STN-1) of the n-1th GOA circuit unit are used to connect the first node Q( n) Charged to a high potential; the pull-up circuit unit (102) is connected to the clock signal (CKN
  • the pull-up control circuit unit (101) includes:
  • the first thin film transistor (T11), the gate of the first thin film transistor (T11) is connected to the clock signal (CKN-1) of the n-1th stage GOA circuit unit, and the drain of the first thin film transistor (T11) Connect the start trigger signal (STV) or the stage transfer signal (STN-1) of the n-1th stage GOA circuit unit, and the source of the first thin film transistor (T11) is connected to the first node (QN).
  • the pull-up circuit unit (102) includes:
  • the second thin film transistor (T21), the gate of the second thin film transistor (T21) is connected to the first node (QN), the drain of the two thin film transistors (T21) is connected to the clock signal (CKN), the The source of the second thin film transistor (T21) is connected to the output signal (GN) of the n-th stage GOA circuit unit.
  • the download circuit unit (103) includes:
  • the pull-down circuit unit (104) includes:
  • the fourth thin film transistor (T23), the gate of the fourth thin film transistor (T23) is connected to the clock signal (CKN+2) of the GOA circuit unit of the n+2 level, and the drain of the four thin film transistor (T23) is connected
  • the stage transfer signal (STN) of the nth stage GOA circuit unit, and the source of the fourth thin film transistor (T23) is connected to the first low-potential direct current signal (VSSQ);
  • the fifth thin film transistor (T31), the gate of the fifth thin film transistor (T31) is connected to the clock signal (CKN+2) of the n+2th GOA circuit unit, and the drain of the fifth thin film transistor (T31)
  • the electrode is connected to the output signal (GN) of the n-th GOA circuit unit, and the source of the fifth thin film transistor (T31) is connected to the second low-potential direct current signal (VSSG);
  • the sixth thin film transistor (T41), the gate of the sixth thin film transistor (T41) is connected to the clock signal (CKN+2) of the n+2th GOA circuit unit, and the sixth thin film transistor (T41)
  • the drain is connected to the first node (QN), and the source of the sixth thin film transistor (T41) is connected to the first low-potential direct current signal (VSSQ).
  • n is equal to 1, the drain of the first thin film transistor (T11) is connected to the start trigger signal (STV);
  • n is greater than 1, the drain of the first thin film transistor (T11) is connected to the stage transmission signal (STN-1) of the n-1th stage GOA circuit unit.
  • the clock signal (CKN-1), the clock signal (CKN), the clock signal (CKN+1) and the clock signal (CKN+2) have a signal high duty cycle of 25%, and the signals are delayed in time.
  • the adjacent signal delay time is 25% of the clock period; the high level of the clock signal is the same as the high level of the start trigger signal (STV); the low level of the clock signal is the same as the start trigger signal (STV). ) Has the same low potential.
  • the potential of the first low-potential direct current signal is the same as the low potential of the initial trigger signal (STV);
  • the potential of the second low-potential direct current signal (VSSG) is higher than the potential of the first low-potential direct current signal (VSSQ).
  • the GOA circuit includes phase 1 to phase 5 in one cycle
  • phase 1 the initial trigger signal (STV) is pulled high and the circuit starts;
  • phase 2 the clock signal (CKN-1) and the level transmission signal (STN-1) signal of the n-1th level GOA circuit unit are high at the same time, and CKN+2 is low at this time, T41, T31 , T23 is turned off, so the first node (QN) of this stage is charged to a high potential, thereby turning on the transistors T21 and T22;
  • phase 3 the low level of the clock signal (CKN-1) turns off T11, and the clock signal (CKN) changes to high level at the same time, charging the output signals STN and GN to a high level; the output signal (GN) is used to drive the panel Load (driving of the gate line); and the output signal (STN) stage is transmitted to the next stage (stage transmission signal) to charge the first node (QN+1) of the next stage to a high potential;
  • stage 4 the clock signal (CKN) becomes a low level, and the output signals STN and GN are pulled down to a low level;
  • phase 5 the high level of the clock signal (CKN+2) turns on T41 and pulls down the first node (QN) to a low level, so that the transistors T21 and T22 are turned off.
  • the present invention also provides a display panel including the GOA circuit.
  • the present invention provides a GOA circuit and a display panel.
  • the thin film transistors required by the inverter are reduced, and the number of transistors is reduced, which can effectively reduce the area occupied by the GOA area, which is beneficial to reduce the frame size of the panel;
  • the gates of the thin film transistors in the GOA circuit are all controlled by unattenuated clock signals, which can avoid failures caused by the attenuation of the stage transfer signal caused by the drift of the threshold voltage of the thin film transistors.
  • Fig. 1 is a circuit diagram of a GOA circuit provided by the prior art
  • Fig. 2 is a timing control and signal output waveform diagram of the GOA circuit provided by the prior art
  • FIG. 3 is a circuit diagram of the GOA circuit provided by the present invention.
  • Fig. 4 is a timing control and signal output waveform diagram of the GOA circuit provided by the present invention.
  • the present invention provides a GOA circuit including multiple GOA circuits cascaded.
  • the n-th GOA circuit unit includes: a pull-up control circuit unit (101), a pull-up circuit unit (102), a downstream circuit unit (103), a pull-down circuit unit (104), and a capacitor (Cb).
  • the pull-up control circuit unit (101), the pull-up circuit unit (102), the downstream circuit unit (103), the pull-down circuit unit (104), the pull-down sustain circuit unit (105), and The capacitors (Cb) are all electrically connected to the first node Q(n).
  • the pull-up circuit unit (101) is respectively connected to the clock signal (CKN-1), the start trigger signal (STV) of the n-1 level GOA circuit unit or the level transmission of the n-1 level GOA circuit unit.
  • the signal (STN-1) is used to charge the first node Q(n) in the circuit to a high potential.
  • the pull-up control circuit unit (101) includes: a first thin film transistor (T11), the gate of the first thin film transistor (T11) is connected to the clock signal (CKN-1) of the n-1th GOA circuit unit, The drain of the first thin film transistor (T11) is connected to the start trigger signal (STV) or the stage transfer signal (STN-1) of the n-1th stage GOA circuit unit, and the first thin film transistor (T11) The source is connected to the first node (QN).
  • the pull-up circuit unit (102) is connected to a clock signal (CKN) to pull the output signal (GN) of the n-th GOA circuit unit to the high potential of the clock signal (CKN).
  • the pull-up circuit unit (102) includes: a second thin film transistor (T21), the gate of the second thin film transistor (T21) is connected to the first node (QN), and the second thin film transistor (T21) The drain is connected to the clock signal (CKN), and the source of the second thin film transistor (T21) is connected to the output signal (GN) of the nth stage GOA circuit unit.
  • the download circuit unit (103) connects to the clock signal (CKN) and outputs the stage transfer signal (STN) of the n-th GOA circuit unit to control the pull-up control circuit of the n+1-th GOA unit The opening or closing of the unit.
  • the download circuit unit (103) includes:
  • the pull-down circuit unit (104) is respectively connected to the clock signal (CKN+2), the first low-potential direct current signal (VSSQ) and the second low-potential direct current signal (VSSG) of the n+2th GOA circuit unit, Used to pull down the first node Q(n) precharge, the level transfer signal (STN) of the nth level GOA circuit unit, and the nth level scan driving signal G(n) to a low level .
  • the pull-down circuit unit (104) includes:
  • the fourth thin film transistor (T23), the gate of the fourth thin film transistor (T23) is connected to the clock signal (CKN+2) of the GOA circuit unit of the n+2 level, and the drain of the four thin film transistor (T23) is connected
  • the stage transfer signal (STN) of the nth stage GOA circuit unit, and the source of the fourth thin film transistor (T23) is connected to the first low-potential direct current signal (VSSQ);
  • the fifth thin film transistor (T31), the gate of the fifth thin film transistor (T31) is connected to the clock signal (CKN+2) of the n+2th GOA circuit unit, and the drain of the fifth thin film transistor (T31)
  • the electrode is connected to the output signal (GN) of the n-th GOA circuit unit, and the source of the fifth thin film transistor (T31) is connected to the second low-potential direct current signal (VSSG);
  • the sixth thin film transistor (T41), the gate of the sixth thin film transistor (T41) is connected to the clock signal (CKN+2) of the n+2th GOA circuit unit, and the sixth thin film transistor (T41)
  • the drain is connected to the first node (QN), and the source of the sixth thin film transistor (T41) is connected to the first low-potential direct current signal (VSSQ).
  • the capacitor (Cb) is used to provide and maintain the precharged potential of the first node Q(n), and the capacitor is connected to the output signal (GN) of the nth-stage GOA circuit unit.
  • n is equal to 1, the drain of the first thin film transistor (T11) is connected to the start trigger signal (STV); if n is greater than 1, the drain of the first thin film transistor (T11) is connected to The stage transmission signal of the n-1th GOA circuit unit (STN-1).
  • FIG 4 it is the timing control diagram provided by the present invention, where the clock signal (CKN-1), the clock signal (CKN), the clock signal (CKN+1) and the clock signal (CKN+2) have high signal levels
  • the duty cycle is 25%, the signal is delayed in time, and the adjacent signal delay time is 25% of the clock period.
  • the high potential of the clock signal is the same as the high potential of the start trigger signal (STV); the low potential of the clock signal is the same as the low potential of the start trigger signal (STV).
  • the potential of the first low-potential direct current signal (VSSQ) is the same as the low potential of the start trigger signal (STV); the potential of the second low-potential direct current signal (VSSG) is higher than the first low-potential direct current signal Signal (VSSQ) potential.
  • phase 1 the start trigger signal (STV) is pulled high, and the circuit starts; in phase 2, the clock signal (CKN-1) and the n-1 level GOA circuit The level transmission signal (STN-1) signal of the unit is high at the same time, and at this time CKN+2 is low, T41, T31, and T23 are turned off, so the first node (QN) of this stage is charged to high potential, thereby turning the transistor T21 , T22 is turned on; in phase 3, the low level of the clock signal (CKN-1) turns off T11, and the clock signal (CKN) changes to high at the same time, charging the output signals STN and GN to a high level; the output signal (GN) is used for Drive the load of this line of the panel (driving of the gate line); and the output signal (STN) stage is transmitted to the next stage (stage transmission signal) to charge the first node (QN+1) of the next stage to a high potential; In phase 4, the clock signal (STN-1) and the n-1 level G
  • the clock signal (CKN+2) turns on T31, T41, and T23 once in each cycle, thereby maintaining GN, QN, and STN at the corresponding low potentials, playing the role of pull-down maintenance.
  • the present invention provides a GOA circuit.
  • the thin film transistors required by the inverter are reduced, and the number of transistors is reduced, which can effectively reduce the area occupied by the GOA area, which is beneficial to reduce the frame size of the panel; the GOA
  • the gates of the thin film transistors in the circuit are all controlled by unattenuated clock signals, which can avoid failures caused by the attenuation of the stage transfer signal caused by the threshold voltage drift of the thin film transistors.
  • the GOA circuit is a GOA circuit of an LTPS panel, or the GOA circuit is a GOA circuit of an OLED panel.
  • the first to twelfth thin film transistors are all P-type thin film transistors or N-type thin film transistors.
  • the present invention also provides a display panel including the GOA circuit as described above.
  • the display panel includes an OLED display panel or an LTPS display panel.
  • the thin film transistors required by the inverter are reduced, and the number of transistors is reduced, which can effectively reduce the area occupied by the GOA area, which is conducive to reducing the frame size of the panel, and is conducive to the display
  • the panel realizes a narrow frame design.
  • the gates of the thin film transistors in the GOA circuit are controlled by unattenuated clock signals, which can avoid failures caused by the attenuation of the stage transfer signal caused by the threshold voltage drift of the thin film transistors, which increases the reliability of the display panel. .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路及显示面板，在电路结构上，减少了反相器所需的薄膜晶体管，晶体管数量进行缩减，可以有效缩减GOA区域所占面积，有利于缩减面板的边框尺寸；GOA电路中薄膜晶体管的栅极都由未经衰减的时钟信号（CKN-1, CKN, CKN+1, CKN+2）控制，可以避免因薄膜晶体管阈值电压漂移引起的级传信号（STN, STN-1）衰减导致的失效。

Description

GOA电路及显示面板 技术领域
本发明涉及显示技术领域，特别是一种GOA电路及显示面板。
 背景技术
GOA(Gate Driver on Array，阵列基板行驱动)技术有利于显示屏窄边框的设计，并且降低成本，得到广泛的研究和应用。
 技术问题
图1所示是常见的单级GOA电路。图2为GOA电路时序图。在GOA电路中，长期工作后薄膜晶体管阈值电压漂移，导致输出信号ST(N)、Q(N)及G(N)产生衰减；其中，栅极被衰减信号所控制的薄膜晶体管（如图1中的T11、T31、T41、T25、T52、T54）的导通状态和关闭状态会进一步恶化，从而导致其输出信号进一步衰减。这种不稳定状态会形成恶性循环，导致GOA电路失效。为了提高电路可靠性，会增加由图1中薄膜晶体管（T51、T52、T53、T54）所构成的反相器及节点电压维持薄膜晶体管（T42、T26、T32）。但是这一方面增加了很多薄膜晶体管，使得GOA电路所占面积变大，面板的边框加宽；另一方面构成反相器的T52与T54的栅极也是由衰减信号Q(N)所控制，仍然存在图1中KN节点与Q(N)节点的电位竞争所产生的恶性循环，容易导致失效。
 技术解决方案
本发明的目的是，提供一种GOA电路，用以减少GOA电路的薄膜晶体管数量的同时提高GOA电路的稳定性。
本发明提供一种GOA电路，包括级联的多个GOA电路单元，其中第n级GOA电路单元包括：上拉控制电路单元（101）、上拉电路单元（102）、下传电路单元（103）、下拉电路单元（104）、以及电容（Cb）；其中，所述上拉控制电路单元（101）、所述上拉电路单元（102）、所述下传电路单元（103）、所述下拉电路单元（104）、所述下拉维持电路单元（105）以及电容（Cb）均电连接至第一节点Q（n）；所述上拉电路单元（101）分别接入第n-1级GOA 电路单元的时钟信号（CKN-1）、起始触发信号（STV）或所述第n-1级GOA 电路单元的级传信号（STN-1），用以将电路中第一节点Q（n）充电到高电位；所述上拉电路单元（102）接入时钟信号（CKN），用以将第n级GOA 电路单元的输出信号（GN）拉高到所述时钟信号（CKN）的高电位；所述下传电路单元（103）接入所述时钟信号（CKN）并输出第n级GOA 电路单元的级传信号（STN），用以控制第n+1级的GOA单元的上拉控制电路单元的打开或关闭；所述下拉电路单元（104）分别接入所述第n+2级GOA 电路单元的时钟信号（CKN+2）、第一低电位直流信号（VSSQ）以及第二低电位直流信号（VSSG），用以拉低所述第一节点Q（n）预充电、所述第n级GOA 电路单元的级传信号（STN）以及所述第n级的扫描驱动信号G（n）的电位至低电位；所述电容（Cb）用以提供并维持所述第一节点Q（n）预充电的电位，所述电容的连接所述第n级GOA 电路单元的输出信号（GN）。
进一步地，所述上拉控制电路单元（101）包括：
第一薄膜晶体管(T11)，所述第一薄膜晶体管(T11)的栅极连接第n-1级GOA 电路单元的时钟信号（CKN-1），所述第一薄膜晶体管(T11)的漏极连接起始触发信号（STV）或所述第n-1级GOA 电路单元的级传信号（STN-1），所述第一薄膜晶体管(T11)的源极连接第一节点（QN）。
进一步地，所述上拉电路单元（102）包括：
第二薄膜晶体管(T21)，所述第二薄膜晶体管(T21)的栅极连接所述第一节点（QN），所述二薄膜晶体管(T21)的漏极连接时钟信号（CKN），所述第二薄膜晶体管(T21)的源极连接所述第n级GOA 电路单元的输出信号（GN）。
进一步地，所述下传电路单元（103）包括：
第三薄膜晶体管(T22)，所述第三薄膜晶体管(T22)的栅极连接所述第一节点（QN），所述三薄膜晶体管(T22)的漏极连接所述时钟信号（CKN），所述第三薄膜晶体管(T22)的源极输出所述第n级GOA 电路单元的级传信号（STN）。
进一步地，所述下拉电路单元（104）包括：
第四薄膜晶体管(T23)，所述第四薄膜晶体管(T23)的栅极连接第n+2级GOA 电路单元的时钟信号（CKN+2），所述四薄膜晶体管(T23)的漏极连接所述第n级GOA 电路单元的级传信号（STN），所述第四薄膜晶体管(T23)的源极连接第一低电位直流信号（VSSQ）；
第五薄膜晶体管(T31)，所述第五薄膜晶体管(T31)的栅极连接所述第n+2级GOA 电路单元的时钟信号（CKN+2），所述五薄膜晶体管(T31)的漏极连接所述第n级GOA 电路单元的输出信号（GN），所述第五薄膜晶体管(T31)的源极连接第二低电位直流信号（VSSG）；
第六薄膜晶体管(T41)，所述第六薄膜晶体管(T41)的栅极连接所述第n+2级GOA 电路单元的时钟信号（CKN+2），所述第六薄膜晶体管(T41)的漏极连接所述第一节点（QN），所述第六薄膜晶体管(T41)的源极连接所述第一低电位直流信号（VSSQ）。
进一步地，若n等于1，则所述第一薄膜晶体管(T11)的漏极连接起始触发信号（STV）；
若n大于1，则所述第一薄膜晶体管(T11)的漏极连接起所述第n-1级GOA 电路单元的级传信号（STN-1）。
进一步地，时钟信号（CKN-1）、时钟信号（CKN）、时钟信号（CKN+1）以及时钟信号（CKN+2）的信号高电位占空比为25%，信号在时间上依次延迟，相邻信号延迟时间为25%的时钟周期；所述时钟信号的高电位与所述起始触发信号（STV）的高电位相同；所述时钟信号的低电位与所述起始触发信号（STV）的低电位相同。
进一步地，所述第一低电位直流信号（VSSQ）的电位与所述起始触发信号（STV）的低电位相同；
所述第二低电位直流信号（VSSG）的电位高于所述第一低电位直流信号（VSSQ）电位。
进一步地，所述GOA电路在一个周期内包括阶段1~阶段5；
在阶段1，起始触发信号（STV）拔高，电路启动；
在阶段2，所述时钟信号（CKN-1）与所述第n-1级GOA 电路单元的级传信号（STN-1）信号同时高电位，而此时CKN+2低电位，T41、T31、T23关断，因而本级的第一节点（QN）充电至高电位，从而将晶体管T21、T22打开；
在阶段3，时钟信号（CKN-1）低电位将T11关断，时钟信号（CKN）同时变为高电位，将输出信号STN以及GN充电至高电位；输出信号（GN）用以驱动面板本行负载（栅极线的驱动）；而输出信号（STN）级传至下一级（级传信号），用以将下一级的第一节点（QN+1）充电至高电位；
在阶段4，时钟信号（CKN）变成低电位，将输出信号STN以及GN下拉至低电位；
在阶段5，时钟信号（CKN+2）高电位将T41打开，将第一节点（QN）下拉至低电位，从而晶体管T21、T22关断。
本发明还提供一种显示面板，包括所述的GOA电路。
 有益效果
本发明提供一种GOA电路及显示面板，在电路结构上，减少了反相器所需的薄膜晶体管，晶体管数量进行缩减，可以有效缩减GOA区域所占面积，有利于缩减面板的边框尺寸；所述GOA电路中薄膜晶体管的栅极都由未经衰减的时钟信号控制，可以避免因薄膜晶体管阈值电压漂移引起的级传信号衰减导致的失效。
 附图说明
图1为现有技术提供的GOA电路的电路图；
图2为现有技术提供的GOA电路的时序控制及信号输出波形图；
图3为本发明提供的GOA电路的电路图；
图4为本发明提供的GOA电路的时序控制及信号输出波形图。
 本发明的实施方式
本申请提供一种实体键盘输入系统、键盘输入方法及存储介质，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图3所示，本发明提供一种GOA电路，包括级联的多个GOA电路。
其中第n级GOA电路单元包括：上拉控制电路单元（101）、上拉电路单元（102）、下传电路单元（103）、下拉电路单元（104）、以及电容（Cb）。
所述上拉控制电路单元（101）、所述上拉电路单元（102）、所述下传电路单元（103）、所述下拉电路单元（104）、所述下拉维持电路单元（105）以及电容（Cb）均电连接至第一节点Q（n）。
所述上拉电路单元（101）分别接入第n-1级GOA 电路单元的时钟信号（CKN-1）、起始触发信号（STV）或所述第n-1级GOA 电路单元的级传信号（STN-1），用以将电路中第一节点Q（n）充电到高电位。
所述上拉控制电路单元（101）包括：第一薄膜晶体管(T11)，所述第一薄膜晶体管(T11)的栅极连接第n-1级GOA 电路单元的时钟信号（CKN-1），所述第一薄膜晶体管(T11)的漏极连接起始触发信号（STV）或所述第n-1级GOA 电路单元的级传信号（STN-1），所述第一薄膜晶体管(T11)的源极连接第一节点（QN）。
所述上拉电路单元（102）接入时钟信号（CKN），用以将第n级GOA 电路单元的输出信号（GN）拉高到所述时钟信号（CKN）的高电位。
所述上拉电路单元（102）包括：第二薄膜晶体管(T21)，所述第二薄膜晶体管(T21)的栅极连接所述第一节点（QN），所述二薄膜晶体管(T21)的漏极连接时钟信号（CKN），所述第二薄膜晶体管(T21)的源极连接所述第n级GOA 电路单元的输出信号（GN）。
所述下传电路单元（103）接入所述时钟信号（CKN）并输出第n级GOA 电路单元的级传信号（STN），用以控制第n+1级的GOA单元的上拉控制电路单元的打开或关闭。
所述下传电路单元（103）包括：
第三薄膜晶体管(T22)，所述第三薄膜晶体管(T22)的栅极连接所述第一节点（QN），所述三薄膜晶体管(T22)的漏极连接所述时钟信号（CKN），所述第三薄膜晶体管(T22)的源极输出所述第n级GOA 电路单元的级传信号（STN）。
所述下拉电路单元（104）分别接入所述第n+2级GOA 电路单元的时钟信号（CKN+2）、第一低电位直流信号（VSSQ）以及第二低电位直流信号（VSSG），用以拉低所述第一节点Q（n）预充电、所述第n级GOA 电路单元的级传信号（STN）以及所述第n级的扫描驱动信号G（n）的电位至低电位。
所述下拉电路单元（104）包括：
第四薄膜晶体管(T23)，所述第四薄膜晶体管(T23)的栅极连接第n+2级GOA 电路单元的时钟信号（CKN+2），所述四薄膜晶体管(T23)的漏极连接所述第n级GOA 电路单元的级传信号（STN），所述第四薄膜晶体管(T23)的源极连接第一低电位直流信号（VSSQ）；
第五薄膜晶体管(T31)，所述第五薄膜晶体管(T31)的栅极连接所述第n+2级GOA 电路单元的时钟信号（CKN+2），所述五薄膜晶体管(T31)的漏极连接所述第n级GOA 电路单元的输出信号（GN），所述第五薄膜晶体管(T31)的源极连接第二低电位直流信号（VSSG）；
第六薄膜晶体管(T41)，所述第六薄膜晶体管(T41)的栅极连接所述第n+2级GOA 电路单元的时钟信号（CKN+2），所述第六薄膜晶体管(T41)的漏极连接所述第一节点（QN），所述第六薄膜晶体管(T41)的源极连接所述第一低电位直流信号（VSSQ）。
所述电容（Cb）用以提供并维持所述第一节点Q（n）预充电的电位，所述电容的连接所述第n级GOA 电路单元的输出信号（GN）。
进一步地，若n等于1，则所述第一薄膜晶体管(T11)的漏极连接起始触发信号（STV）；若n大于1，则所述第一薄膜晶体管(T11)的漏极连接起第n-1级GOA 电路单元的级传信号（STN-1）。
如图4所示，为本发明提供的时序控制图，其中，时钟信号（CKN-1）、时钟信号（CKN）、时钟信号（CKN+1）以及时钟信号（CKN+2）的信号高电位占空比为25%，信号在时间上依次延迟，相邻信号延迟时间为25%的时钟周期。
所述时钟信号的高电位与所述起始触发信号（STV）的高电位相同；所述时钟信号的低电位与所述起始触发信号（STV）的低电位相同。
所述第一低电位直流信号（VSSQ）的电位与所述起始触发信号（STV）的低电位相同；所述第二低电位直流信号（VSSG）的电位高于所述第一低电位直流信号（VSSQ）电位。
继续参照图2所示，一个周期内，在阶段1，起始触发信号（STV）拔高，电路启动；在阶段2，所述时钟信号（CKN-1）与所述第n-1级GOA 电路单元的级传信号（STN-1）信号同时高电位，而此时CKN+2低电位，T41、T31、T23关断，因而本级的第一节点（QN）充电至高电位，从而将晶体管T21、T22打开；在阶段3，时钟信号（CKN-1）低电位将T11关断，时钟信号（CKN）同时变为高电位，将输出信号STN以及GN充电至高电位；输出信号（GN）用以驱动面板本行负载（栅极线的驱动）；而输出信号（STN）级传至下一级（级传信号），用以将下一级的第一节点（QN+1）充电至高电位；在阶段4，时钟信号（CKN）变成低电位，将输出信号STN以及GN下拉至低电位；在阶段5，时钟信号（CKN+2）高电位将T41打开，将第一节点（QN）下拉至低电位，从而晶体管T21、T22关断。
在此后每个周期，时钟信号（CKN+2）每个周期将T31、T41、T23打开一次，从而将GN、QN、STN维持在对应的低电位，起到下拉维持的作用。
本发明提供一种GOA电路，在电路结构上，减少了的反相器所需的薄膜晶体管，晶体管数量进行缩减，可以有效缩减GOA区域所占面积，有利于缩减面板的边框尺寸；所述GOA电路中薄膜晶体管的栅极都由未经衰减的时钟信号控制，可以避免因薄膜晶体管阈值电压漂移引起的级传信号衰减导致的失效。
所述GOA电路为LTPS面板的GOA电路，或所述GOA电路为OLED面板的GOA电路。
所述第一至第十二薄膜晶体管皆为P型薄膜晶体管或N型薄膜晶体管。
本发明还提供一种显示面板，包括如上所述的GOA电路。所述显示面板包括OLED显示面板或LTPS显示面板。
一方面，所述GOA电路在电路结构上，减少了反相器所需的薄膜晶体管，晶体管数量进行缩减，可以有效缩减GOA区域所占面积，有利于缩减面板的边框尺寸，有利于所述显示面板实现窄边框设计。
另一方面，所述GOA电路中薄膜晶体管的栅极都由未经衰减的时钟信号控制，可以避免因薄膜晶体管阈值电压漂移引起的级传信号衰减导致的失效，这增加了显示面板的信赖性。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (10)

  1. 一种GOA电路，其中，包括级联的多个GOA电路单元，其中第n级GOA电路单元包括：上拉控制电路单元（101）、上拉电路单元（102）、下传电路单元（103）、下拉电路单元（104）、以及电容（Cb）；
    其中，所述上拉控制电路单元（101）、所述上拉电路单元（102）、所述下传电路单元（103）、所述下拉电路单元（104）、所述下拉维持电路单元（105）以及电容（Cb）均电连接至第一节点Q（n）；
    所述上拉电路单元（101）分别接入第n-1级GOA 电路单元的时钟信号（CKN-1）、起始触发信号（STV）或所述第n-1级GOA 电路单元的级传信号（STN-1），用以将电路中第一节点Q（n）充电到高电位；
    所述上拉电路单元（102）接入时钟信号（CKN），用以将第n级GOA 电路单元的输出信号（GN）拉高到所述时钟信号（CKN）的高电位；
    所述下传电路单元（103）接入所述时钟信号（CKN）并输出第n级GOA 电路单元的级传信号（STN），用以控制第n+1级的GOA单元的上拉控制电路单元的打开或关闭；
    所述下拉电路单元（104）分别接入所述第n+2级GOA 电路单元的时钟信号（CKN+2）、第一低电位直流信号（VSSQ）以及第二低电位直流信号（VSSG），用以拉低所述第一节点Q（n）预充电、所述第n级GOA 电路单元的级传信号（STN）以及所述第n级的扫描驱动信号G（n）的电位至低电位；
    所述电容（Cb）用以提供并维持所述第一节点Q（n）预充电的电位，所述电容的连接所述第n级GOA 电路单元的输出信号（GN）。
  2. 根据权利要求1所述的GOA电路，其中，
    所述上拉控制电路单元（101）包括：
    第一薄膜晶体管(T11)，所述第一薄膜晶体管(T11)的栅极连接第n-1级GOA 电路单元的时钟信号（CKN-1），所述第一薄膜晶体管(T11)的漏极连接起始触发信号（STV）或所述第n-1级GOA 电路单元的级传信号（STN-1），所述第一薄膜晶体管(T11)的源极连接第一节点（QN）。
  3. 根据权利要求1所述的GOA电路，其中，
    所述上拉电路单元（102）包括：
    第二薄膜晶体管(T21)，所述第二薄膜晶体管(T21)的栅极连接所述第一节点（QN），所述二薄膜晶体管(T21)的漏极连接时钟信号（CKN），所述第二薄膜晶体管(T21)的源极连接所述第n级GOA 电路单元的输出信号（GN）。
  4. 根据权利要求1所述的GOA电路，其中，
    所述下传电路单元（103）包括：
    第三薄膜晶体管(T22)，所述第三薄膜晶体管(T22)的栅极连接所述第一节点（QN），所述三薄膜晶体管(T22)的漏极连接所述时钟信号（CKN），所述第三薄膜晶体管(T22)的源极输出所述第n级GOA 电路单元的级传信号（STN）。
  5. 根据权利要求1所述的GOA电路，其中，
    所述下拉电路单元（104）包括：
    第四薄膜晶体管(T23)，所述第四薄膜晶体管(T23)的栅极连接第n+2级GOA 电路单元的时钟信号（CKN+2），所述四薄膜晶体管(T23)的漏极连接所述第n级GOA 电路单元的级传信号（STN），所述第四薄膜晶体管(T23)的源极连接第一低电位直流信号（VSSQ）；
    第五薄膜晶体管(T31)，所述第五薄膜晶体管(T31)的栅极连接所述第n+2级GOA 电路单元的时钟信号（CKN+2），所述五薄膜晶体管(T31)的漏极连接所述第n级GOA 电路单元的输出信号（GN），所述第五薄膜晶体管(T31)的源极连接第二低电位直流信号（VSSG）；
    第六薄膜晶体管(T41)，所述第六薄膜晶体管(T41)的栅极连接所述第n+2级GOA 电路单元的时钟信号（CKN+2），所述第六薄膜晶体管(T41)的漏极连接所述第一节点（QN），所述第六薄膜晶体管(T41)的源极连接所述第一低电位直流信号（VSSQ）。
  6. 根据权利要求2所述的GOA电路，其中，
    若n等于1，则所述第一薄膜晶体管(T11)的漏极连接起始触发信号（STV）；
    若n大于1，则所述第一薄膜晶体管(T11)的漏极连接起所述第n-1级GOA 电路单元的级传信号（STN-1）。
  7. 根据权利要求1所述的GOA电路，其中，
    时钟信号（CKN-1）、时钟信号（CKN）、时钟信号（CKN+1）以及时钟信号（CKN+2）的信号高电位占空比为25%，信号在时间上依次延迟，相邻信号延迟时间为25%的时钟周期；
    所述时钟信号的高电位与所述起始触发信号（STV）的高电位相同；
    所述时钟信号的低电位与所述起始触发信号（STV）的低电位相同。
  8. 根据权利要求1所述的GOA电路，其中，
    所述第一低电位直流信号（VSSQ）的电位与所述起始触发信号（STV）的低电位相同；
    所述第二低电位直流信号（VSSG）的电位高于所述第一低电位直流信号（VSSQ）电位。
  9. 如权利要求1所述的GOA电路，其中，
    所述GOA电路在一个周期内包括阶段1~阶段5；
    在阶段1，起始触发信号（STV）拔高，电路启动；
    在阶段2，所述时钟信号（CKN-1）与所述第n-1级GOA 电路单元的级传信号（STN-1）信号同时高电位，而此时CKN+2低电位，T41、T31、T23关断，因而本级的第一节点（QN）充电至高电位，从而将晶体管T21、T22打开；
    在阶段3，时钟信号（CKN-1）低电位将T11关断，时钟信号（CKN）同时变为高电位，将输出信号STN以及GN充电至高电位；输出信号（GN）用以驱动面板本行负载（栅极线的驱动）；而输出信号（STN）级传至下一级（级传信号），用以将下一级的第一节点（QN+1）充电至高电位；
    在阶段4，时钟信号（CKN）变成低电位，将输出信号STN以及GN下拉至低电位；
    在阶段5，时钟信号（CKN+2）高电位将T41打开，将第一节点（QN）下拉至低电位，从而晶体管T21、T22关断。
  10. 一种显示面板，其中，包括如权利要求1所述的GOA电路。
PCT/CN2020/101359 2020-06-09 2020-07-10 Goa电路及显示面板 WO2021248614A1 (zh)

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