WO2020233041A1 - 扫描驱动电路和显示面板 - Google Patents

扫描驱动电路和显示面板 Download PDF

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Publication number
WO2020233041A1
WO2020233041A1 PCT/CN2019/120336 CN2019120336W WO2020233041A1 WO 2020233041 A1 WO2020233041 A1 WO 2020233041A1 CN 2019120336 W CN2019120336 W CN 2019120336W WO 2020233041 A1 WO2020233041 A1 WO 2020233041A1
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Prior art keywords
transistor
terminal
electrically connected
potential
signal input
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PCT/CN2019/120336
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English (en)
French (fr)
Inventor
范龙飞
段培
何国冰
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合肥维信诺科技有限公司
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Publication of WO2020233041A1 publication Critical patent/WO2020233041A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a scan driving circuit and a display panel.
  • the display panels in the related art mostly adopt the array substrate row drive (Gate Driver on Array, GOA) technology to integrate the scan drive circuit in the non-display area of the display panel.
  • GOA Gate Driver on Array
  • the structure of the scan driving circuit in the related art is relatively complicated, which is not conducive to the realization of the narrow frame design of the display panel.
  • the embodiments of the present application provide a scan driving circuit and a display panel to simplify the structure of the scan driving circuit, and facilitate the realization of a narrow frame design of the display panel.
  • an embodiment of the present application provides a scan driving circuit, including: an input module, a first output module, a second output module, an output control module, a first node, a second node, a clock signal input terminal, a A potential signal input terminal, a second potential signal input terminal, a shift signal input terminal and a scanning signal output terminal;
  • the input module is electrically connected to the second node, the clock signal input terminal, and the shift signal input terminal, the input module is configured to control the potential of the second node, and the second node is configured to Controlling the conduction state of the second output module;
  • the output control module is electrically connected to the first node, the second node, the clock signal input terminal, the shift signal input terminal, and the first potential signal input terminal; the output control module is provided To control the potential of the first node, the first node is set to control the conduction state of the first output module;
  • the first output module is electrically connected to the first node, the first potential signal input terminal, and the scan signal output terminal; while the first output module is on, the first potential signal input terminal is input The first potential signal of is transmitted to the scanning signal output terminal;
  • the second output module is electrically connected to the second node, the second potential signal input terminal, and the scan signal output terminal; while the second output module is on, the second potential signal input terminal is input The second potential signal is transmitted to the scanning signal output terminal.
  • the embodiment of the present application further provides a display panel, including at least two scan driving circuits, clock signal lines, first potential signal lines, and second potential signal lines as described in any embodiment of the present application. , Start signal line and at least two scan lines;
  • the clock signal input terminal of the scan drive circuit is electrically connected to the clock signal line
  • the first potential signal input terminal of the scan drive circuit is electrically connected to the first potential signal line
  • the second potential signal input terminal of the scan drive circuit is electrically connected to the first potential signal line.
  • the potential signal input terminal is electrically connected to the second potential signal line;
  • the at least two scan lines are respectively electrically connected to the scan signal output terminals of the corresponding at least two scan driving circuits;
  • the at least two scan driving circuits are connected in cascade connection with each other, the shift signal input terminal of the scan driving circuit of the first stage is electrically connected to the start signal line; the scan signal output terminal of the scan driving circuit of the previous stage is connected to The shift signal input terminal of the scan driving circuit in the next stage is electrically connected.
  • FIG. 1 is a schematic structural diagram of a scan driving circuit provided by an embodiment of the application
  • FIG. 2 is a schematic timing diagram of a scan driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of another scan driving circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • FIG. 8 is a timing diagram of another scan driving circuit provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • FIG. 1 is a schematic structural diagram of a scan driving circuit provided by an embodiment of the application.
  • the scan driving circuit 10 includes: an input module (also called an input circuit) 110, a first output module (also called a first output circuit) 120, and a second output module (also called a second output circuit).
  • the input module 110 is electrically connected to the second node N2, the clock signal input terminal 101, and the shift signal input terminal 104.
  • the input module 110 is set to control the potential of the second node N2, and the second node N2 is set to control the second output module 130. Conduction state.
  • the output control module 140 is electrically connected to the first node N1, the second node N2, the clock signal input terminal 101, the shift signal input terminal 104, and the first potential signal input terminal 102; the output control module 140 is set to control the first node N1 Potential, the first node N1 is set to control the conduction state of the first output module 120.
  • the first output module 120 is electrically connected to the first node N1, the first potential signal input terminal 102, and the scan signal output terminal 105; during the on period of the first output module 120, the first potential signal input from the first potential signal input terminal 102 is transmitted To the scan signal output terminal 105.
  • the second output module 130 is electrically connected to the second node N2, the second potential signal input terminal 103, and the scan signal output terminal 105; during the on period of the second output module 130, the second potential signal input from the second potential signal input terminal 103 is transmitted To the scan signal output terminal 105.
  • the clock signal of the clock signal input terminal 101 is switched between a high potential and a low potential at a fixed clock frequency.
  • the shift signal of the shift signal input terminal 104 is a pulse signal with a certain pulse width.
  • the scan signal of the scan signal output terminal 105 is also a pulse signal with a certain pulse width, and the pulse width of the scan signal is equal to the pulse width of the shift signal, and is delayed by one clock period from the shift signal, thereby realizing the shift of the scan drive circuit Features.
  • the clock signal input terminal 101 of the scan driving circuit 10 is electrically connected to the clock signal line on the display panel
  • the shift signal input terminal 104 is electrically connected to the scan signal output terminal of the previous scan driving circuit
  • the scan signal The output terminal 105 is electrically connected to the scan line of the display panel.
  • the first potential signal is a low potential signal
  • the second potential signal is a high potential signal.
  • FIG. 2 is a timing diagram of a scan driving circuit provided by an embodiment of the application. Referring to FIG. 2, the driving method of the scan driving circuit 10 is as follows:
  • the shift signal IN of the shift signal input terminal 104 is at a high level; the input module 110 responds to the clock signal CLK and the shift signal to control the potential of the second node N2; the second output module 130 responds to the second node N2 Potential is turned on, and the second potential signal of the second potential signal input terminal 103 is transmitted to the scan signal output terminal 105; and the output control module 140 responds to the potential of the second node N2 to transmit the first potential signal of the first potential signal input terminal 102 A potential signal is transmitted to the first node N1; the first output module 120 is turned off in response to the potential of the first node N1.
  • the scan signal output terminal 105 outputs the second potential signal OUT.
  • stage T12 the shift signal IN at the shift signal input terminal 104 is at a low level, and the clock signal at the clock signal input terminal 101 is at a low level; the potential of the second node N2 maintains the level of stage T11; the second output module 130 responds to the first The potential of the two nodes N2 is turned on, and the second potential signal of the second potential signal input terminal 103 is transmitted to the scan signal output terminal 105; and the output control module 140 responds to the potential of the second node N2 to input the first potential signal The first potential signal of the terminal 102 is transmitted to the first node N1; the first output module 120 is turned off in response to the potential of the first node N1.
  • the scan signal output terminal 105 outputs the second potential signal.
  • the shift signal IN of the shift signal input terminal 104 is at a low level; the input module 110 responds to the clock signal and the shift signal to control the potential of the second node N2; the second output module 130 responds to the potential of the second node N2 And turn off; the output control module 140 controls the potential of the first node N1 in response to the potential of the second node N2, the clock signal, and the shift signal; the first output module 120 turns on in response to the potential of the first node N1 to turn the first
  • the first potential signal of the potential signal input terminal 102 is transmitted to the scan signal output terminal 105; the scan signal output terminal 105 outputs the first potential signal; therefore, the first potential signal output by the scan signal output terminal 105 is delayed by one compared with the shift signal Clock cycle output.
  • stage T14 the shift signal IN at the shift signal input terminal 104 is at a high potential, and the clock signal at the clock signal input terminal 101 is at a low potential; the potential of the second node N2 maintains the potential of the stage T13; the second output module 130 responds to the first The potential of the second node N2 is turned off; the output control module 140 controls the potential of the first node N1 in response to the potential of the second node N2, the clock signal and the shift signal; the first output module 120 conducts in response to the potential of the first node N1 On, the first potential signal of the first potential signal input terminal 102 is transmitted to the scan signal output terminal 105.
  • the shift signal IN of the shift signal input terminal 104 is at a high level; the input module 110 responds to the clock signal and the shift signal to control the potential of the second node N2; the second output module 130 responds to the potential of the second node N2 While on, the second potential signal of the second potential signal input terminal 103 is transmitted to the scan signal output terminal 105; and, in response to the potential of the second node N2, the output control module 140 transmits the first potential signal of the first potential signal input terminal 102 The potential signal is transmitted to the first node N1; the first output module 120 is turned off in response to the potential of the first node N1.
  • the scan signal output terminal 105 outputs the second potential signal.
  • the embodiment of the present application provides a brand new scan driving circuit 10, which includes an input module 110, a first output module 120, a second output module 130, an output control module 140, a first node N1, a second node N2, the clock signal input terminal 101, the first potential signal input terminal 102, the second potential signal input terminal 103, the shift signal input terminal 104 and the scan signal output terminal 105, realize the shift input to the shift signal input terminal 104 Signal shift function.
  • the architecture of the scan driving circuit 10 provided by the embodiment of the present application only includes an output control module 140, a clock signal input terminal 101 and a shift signal input terminal 104. Therefore, the structure of the scan driving circuit 10 Simple and simple control logic.
  • the scan driving circuit 10 provided by the embodiment of the present application is applied to a display panel, only one clock signal line and one shift signal line are provided for the scan driving circuit 10 on the display panel, which is beneficial to realize a narrow frame of the display panel.
  • FIG. 3 is a schematic structural diagram of another scan driving circuit provided by an embodiment of the application.
  • the input module includes a first transistor M1, the control terminal of the first transistor M1 is electrically connected to the clock signal input terminal 101, and the first terminal of the first transistor M1 It is electrically connected to the shift signal input terminal 104, and the second terminal of the first transistor M1 is electrically connected to the second node N2.
  • the first transistor M1 is an N-type transistor
  • the control process for the input module to control the potential of the second node N2 to be high is as follows: if the clock signal CLK of the clock signal input terminal 101 is high, the shift signal input terminal The shift signal IN of 104 is at a high potential, the first transistor M1 is turned on, and the high potential reaches the second node N2 along the first transistor M1; the control process of the input module controlling the potential of the second node N2 to a low potential is as follows: The clock signal CLK at the signal input terminal 101 is at a high level, and the shift signal IN at the shift signal input terminal 104 is at a low level, the first transistor M1 is turned on, and the low level reaches the second node N2 along the first transistor M1.
  • the input module only includes the first transistor M1, which is beneficial to reduce the number of devices in the scan driving circuit 10.
  • FIG. 4 is a schematic structural diagram of another scan driving circuit provided by an embodiment of the application.
  • the output control module 140 includes a first capacitor C1, a second transistor M2, a third transistor M3, and a fourth transistor M4;
  • the second end of the first capacitor C1 is electrically connected to the control end of the second transistor M2;
  • the control end of the second transistor M2 is electrically connected to the second end of the third transistor M3, and the second end of the second transistor M2 is electrically connected to the second end of the third transistor M3.
  • the first end of the transistor M2 is electrically connected to the first end of the first capacitor C1, the second end of the second transistor M2 is electrically connected to the first node N1; the control end of the third transistor M3 is electrically connected to the shift signal input terminal 104 , The first terminal of the third transistor M3 is electrically connected to the first potential signal input terminal 102; the control terminal of the fourth transistor M4 is electrically connected to the second node N2, and the first terminal of the fourth transistor M4 is electrically connected to the first potential signal input terminal 102 is electrically connected, and the second end of the fourth transistor M4 is electrically connected to the first node N1.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 are all N-type transistors, the first potential signal is a low potential, and the second potential signal is a high potential.
  • the control process of the output control module 140 controlling the potential of the first node N1 to be high is as follows: if the clock signal CLK of the clock signal input terminal 101 is high, the shift signal IN of the shift signal input 104 is low, The second node N2 is at a low potential; the third transistor M3 and the fourth transistor M4 are turned off; due to the floating control terminal of the second transistor M2 and the coupling effect of the first capacitor C1, the control terminal potential of the second transistor M2 When pulled high, the second transistor M2 is turned on; the clock signal CLK signal reaches the first node N1 along the second transistor M2.
  • the control process of the output control module 140 controlling the potential of the first node N1 to be low is as follows: if the shift signal IN of the shift signal input terminal 104 is high, the second node N2 is high; the third transistor M3 is turned on The first potential signal VGL reaches the control terminal of the second transistor M2 along the third transistor M3, so that the second transistor M2 is turned off; the high potential of the second node N2 controls the fourth transistor M4 to turn on; the first potential signal VGL is along the first The four transistor M4 reaches the first node N1.
  • the output control module 140 is set to include a first capacitor C1, a second transistor M2, a third transistor M3, and a fourth transistor M4, which not only uses a small number of components, but can also be used when the second output module is turned on. Maintaining the reliable shutdown of the first output module helps to improve the reliability of the scan signal output terminal.
  • FIG. 5 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • the second output module 130 includes a fifth transistor M5 and a second capacitor C2; the control terminal of the fifth transistor M5 and the second terminal of the second capacitor C2
  • the first terminal of the fifth transistor M5 is electrically connected to the second potential signal input terminal 103
  • the second terminal of the fifth transistor M5 is electrically connected to the scan signal output terminal 105 and the second node N2
  • the first terminal of the second capacitor C2 One end is electrically connected to the scan signal output terminal 105, the second node, and the second end of the fifth transistor M5, and the second end of the second capacitor C2 is electrically connected to the control end of the fifth transistor M5.
  • the fifth transistor M5 is an N-type transistor.
  • the control process of the second output module 130 to output the second potential signal is as follows: if the second node N2 is at a high potential, the fifth transistor M5 is turned on and the second potential signal is The fifth transistor M5 reaches the scan signal output terminal 105.
  • the second capacitor C2 has a function of storing potential, and is configured to maintain the potential of the second node N2 in the previous stage when the input module 110 is turned off.
  • the second output module only includes the fifth transistor M5 and the second capacitor C2, which is beneficial to reduce the number of devices in the scan driving circuit 10.
  • FIG. 6 is a schematic structural diagram of another scan driving circuit provided by an embodiment of the application.
  • the first output module 120 includes a sixth transistor M6 and a third capacitor C3; the control terminal of the sixth transistor M6 is electrically connected to the first node N1, The first terminal of the six transistor M6 is electrically connected to the first potential signal input terminal 102, the second terminal of the sixth transistor M6 is electrically connected to the scan signal output terminal 105; the first terminal of the third capacitor C3 is electrically connected to the first potential signal input terminal 102 is electrically connected, and the second end of the third capacitor C3 is electrically connected to the control end of the sixth transistor M6.
  • the sixth transistor M6 is an N-type transistor.
  • the control process of the first output module 120 to output the first potential signal is as follows: if the first node N1 is at a high potential, the sixth transistor M6 is turned on, and the first potential signal is The sixth transistor M6 reaches the scan signal output terminal 105.
  • the third capacitor C3 has a function of storing potential, and is configured to maintain the potential of the first node N1 in the previous stage when the output control module 140 is turned off.
  • the first output module only includes the sixth transistor M6 and the third capacitor C3, which is beneficial to reduce the number of devices in the scan driving circuit 10.
  • FIG. 7 is a schematic structural diagram of another scan driving circuit provided by an embodiment of the application
  • FIG. 8 is a schematic timing diagram of another scan driving circuit provided by an embodiment of the application. Referring to FIG. 7 and FIG. 8, the driving method of the scan driving circuit 10 is:
  • stage T22 the shift signal IN is at a high potential and the clock signal CLK is at a low potential; the third transistor M3 is turned on, the first potential signal VGL reaches the control terminal of the second transistor M2 through the third transistor M3, and the second transistor M2 is turned off Off; due to the high potential stored in the second capacitor C2 in stage T21, the fifth transistor M5 is turned on, and the fourth transistor M4 is turned on; the first potential signal VGL along the fourth transistor M4 reaches the control terminal of the sixth transistor M6, The six transistor M6 is turned off (in the case where the scan driving circuit 10 includes the eighth transistor M8, please refer to FIG.
  • the first potential signal VGL reaches the control terminal of the sixth transistor M6 along the fourth transistor M4 and the control terminal of the eighth transistor M8
  • the control terminal turns off the sixth transistor M6 and the eighth transistor M8);
  • the second potential signal VGH is output to the scan signal output terminal 105 along the fifth transistor M5.
  • stage T26 the shift signal IN is at a low level and the clock signal CLK is at a low level; the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off; because the second capacitor C2 is stored in the stage T25 When the voltage is low, the fourth transistor M4 and the fifth transistor M5 are turned off; because the third capacitor C3 stores a high potential in the stage T25, the sixth transistor M6 is turned on; the first potential signal VGL is output to the scan signal along the sixth transistor M6
  • the output terminal 105, the scanning signal OUT of the scanning signal output terminal 105 VGL.
  • stage T28 the shift signal IN is at a high potential and the clock signal CLK is at a low potential; the first transistor M1 is turned off; since the second capacitor C2 stores a low potential in the stage T27, the fifth transistor M5 and the fourth transistor M4 are turned off.
  • stage T2A the shift signal IN is at a high potential and the clock signal CLK is at a low potential; the third transistor M3 is turned on, the first potential signal VGL reaches the control terminal of the second transistor M2 through the third transistor M3, and the second transistor M2 is turned off Off; due to the high potential stored in the second capacitor C2 in stage T29, the fifth transistor M5 is turned on, and the fourth transistor M4 is turned on; the first potential signal VGL along the fourth transistor M4 reaches the control terminal of the sixth transistor M6, The six transistor M6 is turned off (in the case where the scan driving circuit 10 includes the eighth transistor M8, please refer to FIG.
  • the first potential signal VGL reaches the control terminal of the sixth transistor M6 along the fourth transistor M4 and the control terminal of the eighth transistor M8
  • the control terminal turns off the sixth transistor M6 and the eighth transistor M8);
  • the second potential signal VGH is output to the scan signal output terminal 105 along the fifth transistor M5.
  • the scan drive circuit 10 provided by the embodiment of the present application only includes six transistors and three capacitors, and the number of devices is small. When the scan drive circuit 10 is applied to a display panel, it occupies a small area of the display panel, which is beneficial to implementation The narrow border of the display panel.
  • the fifth transistor M5 and/or the sixth transistor M6 are double-gate transistors. Since the double-gate transistor has the property of reducing leakage current, the fifth transistor M5 and/or The sixth transistor M6 is a double-gate transistor which can reduce the leakage current of the scan signal output terminal 105.
  • FIG. 9 is a schematic structural diagram of another scan driving circuit provided by an embodiment of the application.
  • the scan driving circuit 10 further includes a seventh transistor M7.
  • the control terminal of the transistor M7 is electrically connected to the second potential signal input terminal 103
  • the first terminal of the seventh transistor M7 is electrically connected to the second node N2
  • the second terminal of the seventh transistor M7 is electrically connected to the second output module 130.
  • the seventh transistor M7 is arranged between the second node N2 and the second output module 130 to function as a voltage divider to reduce the leakage current from the second node N2 to the second output module 130.
  • FIG. 10 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • the scan driving circuit 10 further includes an eighth transistor M8 and a ninth transistor M8.
  • Transistor M9; the control terminal and the first terminal of the eighth transistor M8 are electrically connected to the first output module 120, the second terminal of the eighth transistor M8 is electrically connected to the scan signal output terminal 105; the control terminal of the ninth transistor M9 is electrically connected to the scan
  • the signal output terminal 105 is electrically connected, the first terminal of the ninth transistor M9 is electrically connected to the second potential signal input terminal, and the second terminal of the ninth transistor M9 is electrically connected to the first terminal of the eighth transistor M8.
  • the eighth transistor M8 and the ninth transistor M9 play a role in preventing leakage current from being transmitted to the scanning signal output terminal 105 through the first output module 120.
  • the principle is that when the second output module 130 is turned on, the second output module 130 outputs the second potential signal to the scan signal output terminal 105.
  • the first node N1 controls the eighth transistor M8 to turn off, and the scan signal output terminal 105 controls the ninth transistor M9 to turn on. If there is leakage at the output terminal of the first output module 120, the leakage current will be transferred to the second potential through the ninth transistor M9
  • the signal input terminal 103 and the potential of the first terminal of the eighth transistor M8 are equal to the potential of the first potential signal input terminal 102.
  • the potential of the scan signal output terminal 105 is equal to the potential of the first potential signal input terminal 102, the potentials of the first terminal and the second terminal of the eighth transistor M8 are equal, thereby preventing leakage current from being transmitted to the scan signal through the eighth transistor M8 The output terminal.
  • FIG. 11 is a schematic structural diagram of yet another scan driving circuit provided by an embodiment of the application.
  • optionally further includes a tenth transistor M10 and an eleventh transistor M11;
  • the control terminal and the first terminal of the tenth transistor M10 are electrically connected to the second output module 130, the second terminal of the tenth transistor M10 is electrically connected to the scan signal output terminal 105; the control terminal of the eleventh transistor M11 is electrically connected to the scan signal output
  • the terminal 105 is electrically connected, the first terminal of the eleventh transistor M11 is electrically connected to the first potential signal input terminal 102, and the second terminal of the eleventh transistor M11 is electrically connected to the first terminal of the tenth transistor M10.
  • the tenth transistor M10 and the eleventh transistor M11 play a role in preventing leakage current from being transmitted to the scanning signal output terminal 105 through the second output module 130.
  • the principle is that when the first output module 120 is turned on, the first output module 120 outputs the first potential signal to the scan signal output terminal 105.
  • the second node N2 controls the tenth transistor M10 to turn off, and the scan signal output terminal 105 controls the eleventh transistor M11 to turn on. If there is leakage at the output terminal of the second output module 130, the leakage current will be transmitted to the first transistor through the eleventh transistor M11.
  • a potential signal input terminal 102, and the potential of the first terminal of the tenth transistor M10 is equal to the potential of the first potential signal input terminal 102.
  • the potential of the scan signal output terminal 105 is equal to the potential of the first potential signal input terminal 102, the potentials of the first terminal and the second terminal of the tenth transistor M10 are equal, thereby preventing leakage current from being transmitted to the scan signal through the tenth transistor M10 The output terminal.
  • the multiple transistors are all N-type transistors, which is not a limitation of the application.
  • multiple transistors may be set as P-type transistors, or some transistors may be N-type transistors, and some transistors may be P-type transistors, which can be set according to requirements in practical applications.
  • the plurality of transistors are set as P-type transistors, the first potential signal is a high potential signal, the second potential signal is a low potential signal, and the high potential signal output by the scan signal output terminal 105 is higher than that of the shift signal. Delay output by one clock cycle.
  • FIG. 12 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes at least two scan driving circuits 10, a clock signal line 20, a first potential signal line, a second potential signal line, a start signal line 30, and at least two scan driving circuits as provided in any embodiment of the present application.
  • Scan line 40 The clock signal input terminal of the scan drive circuit 10 is electrically connected to the clock signal line 20, the first potential signal input terminal of the scan drive circuit is electrically connected to the first potential signal line, and the second potential signal input terminal of the scan drive circuit is electrically connected to the second potential.
  • the signal lines are electrically connected; at least two scan lines 40 are respectively electrically connected to the scan signal output ends of the corresponding at least two scan drive circuits 10. At least two scan drive circuits 10 are connected in cascade connection with each other.
  • the shift signal input end of the first scan drive circuit 10 is electrically connected to the start signal line 30; the scan signal output end of the previous scan drive circuit 10 is connected to the next scan
  • the shift signal input terminal of the driving circuit 10 is electrically connected.
  • the display panel provided by the embodiment of the application includes a brand new scan driving circuit 10, which includes an input module, a first output module, a second output module, an output control module, a first node, a second node,
  • the clock signal input terminal, the first potential signal input terminal, the second potential signal input terminal, the shift signal input terminal and the scan signal output terminal realize the function of shifting the shift signal input from the shift signal input terminal.
  • the architecture of the scan driving circuit 10 provided by the embodiment of the present application only includes an output control module, a clock signal input terminal, and a shift signal input terminal. Therefore, only one clock signal line 20 and a clock signal line 20 are provided on the scan driving circuit 10 on the display panel. A shift signal line is beneficial to realize the narrow frame of the display panel.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种扫描驱动电路（10）和显示面板，扫描驱动电路（10）包括：输入模块（110）、第一输出模块（120）、第二输出模块（130）、输出控制模块（140）、第一节点（N1）、第二节点（N2）、时钟信号输入端（101）、第一电位信号输入端（102）、第二电位信号输入端（103）、移位信号输入端（104）和扫描信号输出端（105）；输入模块（110）与第二节点（N2）、时钟信号输入端（101）和移位信号输入端（104）电连接，输入模块（101）设置为控制第二节点（N2）的电位，第二节点（N2）设置为控制第二输出模块（130）的导通状态；输出控制模块（140）与第一节点（N1）、第二节点（N2）、时钟信号输入端（101）、移位信号输入端（104）和第一电位信号输入端（102）电连接；输出控制模块（140）设置为控制第一节点（N1）的电位，第一节点（N1）设置为控制第一输出模块（120）的导通状态。

Description

扫描驱动电路和显示面板
本申请要求在2019年05月21日提交中国专利局、申请号为201910425299.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种扫描驱动电路和显示面板。
背景技术
随着显示技术的不断发展，消费者对显示面板的要求也越来越高。其中，当前显示面板的一个发展趋势是全面屏。在相关技术中，为了驱动显示面板显示，需要在显示面板上设置扫描驱动电路等驱动电路。相关技术中的显示面板多采用阵列基板行驱动(Gate Driver on Array，GOA)技术将扫描驱动电路集成在显示面板的非显示区。然而，相关技术中的扫描驱动电路的结构较为复杂，不利于实现显示面板的窄边框设计。
发明内容
本申请实施例提供一种扫描驱动电路和显示面板，以简化扫描驱动电路的结构，有利于实现显示面板的窄边框设计。
在一实施例中，本申请实施例提供一种扫描驱动电路，包括：输入模块、第一输出模块、第二输出模块、输出控制模块、第一节点、第二节点、时钟信号输入端、第一电位信号输入端、第二电位信号输入端、移位信号输入端和扫描信号输出端；
所述输入模块与所述第二节点、所述时钟信号输入端和所述移位信号输入端电连接，所述输入模块设置为控制所述第二节点的电位，所述第二节点设置为控制所述第二输出模块的导通状态；
所述输出控制模块与所述第一节点、所述第二节点、所述时钟信号输入端、所述移位信号输入端和所述第一电位信号输入端电连接；所述输出控制模块设置为控制所述第一节点的电位，所述第一节点设置为控制所述第一输出模块的导通状态；
所述第一输出模块与所述第一节点、所述第一电位信号输入端和所述扫描信号输出端电连接；所述第一输出模块导通期间，所述第一电位信号输入端输入的第一电位信号传输至所述扫描信号输出端；
所述第二输出模块与所述第二节点、所述第二电位信号输入端和所述扫描 信号输出端电连接；所述第二输出模块导通期间，所述第二电位信号输入端输入的第二电位信号传输至所述扫描信号输出端。
在一实施例中，本申请实施例还提供了一种显示面板，包括至少两个如本申请任意实施例所述的扫描驱动电路、时钟信号线、第一电位信号线、第二电位信号线、启动信号线和至少两条扫描线；
所述扫描驱动电路的时钟信号输入端与所述时钟信号线电连接，所述扫描驱动电路的第一电位信号输入端与所述第一电位信号线电连接，所述扫描驱动电路的第二电位信号输入端与所述第二电位信号线电连接；所述至少两条扫描线分别与对应的所述至少两个扫描驱动电路的扫描信号输出端电连接；
所述至少两个扫描驱动电路彼此级联连接，第一级所述扫描驱动电路的移位信号输入端与所述启动信号线电连接；上一级所述扫描驱动电路的扫描信号输出端与下一级所述扫描驱动电路的移位信号输入端电连接。
附图说明
图1为本申请实施例提供的一种扫描驱动电路的结构示意图；
图2为本申请实施例提供的一种扫描驱动电路的时序示意图；
图3为本申请实施例提供的另一种扫描驱动电路的结构示意图；
图4为本申请实施例提供的又一种扫描驱动电路的结构示意图；
图5为本申请实施例提供的又一种扫描驱动电路的结构示意图；
图6为本申请实施例提供的又一种扫描驱动电路的结构示意图；
图7为本申请实施例提供的又一种扫描驱动电路的结构示意图；
图8为本申请实施例提供的另一种扫描驱动电路的时序示意图；
图9为本申请实施例提供的又一种扫描驱动电路的结构示意图；
图10为本申请实施例提供的又一种扫描驱动电路的结构示意图；
图11为本申请实施例提供的又一种扫描驱动电路的结构示意图；
图12为本申请实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
本申请实施例提供了一种扫描驱动电路。图1为本申请实施例提供的一种扫描驱动电路的结构示意图。参见图1，该扫描驱动电路10包括：输入模块(也可称为输入电路)110、第一输出模块(也可称为第一输出电路)120、第二输出模块(也可称为第二输出电路)130、输出控制模块(也可称为输出控制电路)140、第一节点N1、第二节点N2、时钟信号输入端101、第一电位信号输入端102、第二电位信号输入端103、移位信号输入端104和扫描信号输出端105。
输入模块110与第二节点N2、时钟信号输入端101和移位信号输入端104电连接，输入模块110设置为控制第二节点N2的电位，第二节点N2设置为控制第二输出模块130的导通状态。
输出控制模块140与第一节点N1、第二节点N2、时钟信号输入端101、移位信号输入端104和第一电位信号输入端102电连接；输出控制模块140设置为控制第一节点N1的电位，第一节点N1设置为控制第一输出模块120的导通状态。
第一输出模块120与第一节点N1、第一电位信号输入端102和扫描信号输出端105电连接；第一输出模块120导通期间，第一电位信号输入端102输入的第一电位信号传输至扫描信号输出端105。
第二输出模块130与第二节点N2、第二电位信号输入端103和扫描信号输出端105电连接；第二输出模块130导通期间，第二电位信号输入端103输入的第二电位信号传输至扫描信号输出端105。
其中，时钟信号输入端101的时钟信号以固定的时钟频率，在高电位和低电位之间切换。移位信号输入端104的移位信号为具有一定脉冲宽度的脉冲信号。扫描信号输出端105的扫描信号也为具有一定脉冲宽度的脉冲信号，且扫描信号的脉冲宽度与移位信号的脉冲宽度相等，比移位信号延迟一个时钟周期，从而实现扫描驱动电路的移位功能。
示例性地，该扫描驱动电路10的时钟信号输入端101与显示面板上的时钟信号线电连接，移位信号输入端104与上一级扫描驱动的电路的扫描信号输出端电连接，扫描信号输出端105与显示面板的扫描线电连接。第一电位信号为低电位信号，第二电位信号为高电位信号。图2为本申请实施例提供的一种扫描驱动电路的时序示意图。参见图2，该扫描驱动电路10的驱动方法如下：
在阶段T11，移位信号输入端104的移位信号IN为高电位；输入模块110响应时钟信号CLK和移位信号，控制第二节点N2的电位；第二输出模块130响应第二节点N2的电位而导通，将第二电位信号输入端103的第二电位信号传输至扫描信号输出端105；以及，输出控制模块140响应第二节点N2的电位， 将第一电位信号输入端102的第一电位信号传输至第一节点N1；第一输出模块120响应第一节点N1的电位而关断。扫描信号输出端105输出第二电位信号OUT。
在阶段T12，移位信号输入端104的移位信号IN为低电位，时钟信号输入端101的时钟信号为低电位；第二节点N2的电位保持阶段T11的电位；第二输出模块130响应第二节点N2的电位而导通，将第二电位信号输入端103的第二电位信号传输至扫描信号输出端105；以及，输出控制模块140响应第二节点N2的电位，将第一电位信号输入端102的第一电位信号传输至第一节点N1；第一输出模块120响应第一节点N1的电位而关断。扫描信号输出端105输出第二电位信号。
在阶段T13，移位信号输入端104的移位信号IN为低电位；输入模块110响应时钟信号和移位信号，控制第二节点N2的电位；第二输出模块130响应第二节点N2的电位而关断；输出控制模块140响应第二节点N2的电位、时钟信号和移位信号，控制第一节点N1的电位；第一输出模块120响应第一节点N1的电位而导通，将第一电位信号输入端102的第一电位信号传输至扫描信号输出端105；扫描信号输出端105输出第一电位信号；因此，扫描信号输出端105输出的第一电位信号相比于移位信号延迟一个时钟周期输出。
在阶段T14，移位信号输入端104的移位信号IN为高电位，时钟信号输入端101的时钟信号为低电位；第二节点N2的电位保持阶段T13的电位；第二输出模块130响应第二节点N2的电位而关断；输出控制模块140响应第二节点N2的电位、时钟信号和移位信号，控制第一节点N1的电位；第一输出模块120响应第一节点N1的电位而导通，将第一电位信号输入端102的第一电位信号传输至扫描信号输出端105。
在阶段T15，移位信号输入端104的移位信号IN为高电位；输入模块110响应时钟信号和移位信号，控制第二节点N2的电位；第二输出模块130响应第二节点N2的电位而导通，将第二电位信号输入端103的第二电位信号传输至扫描信号输出端105；以及，输出控制模块140响应第二节点N2的电位，将第一电位信号输入端102的第一电位信号传输至第一节点N1；第一输出模块120响应第一节点N1的电位而关断。扫描信号输出端105输出第二电位信号。
本申请实施例提供了一种全新的扫描驱动电路10，该扫描驱动电路10包括输入模块110、第一输出模块120、第二输出模块130、输出控制模块140、第一节点N1、第二节点N2、时钟信号输入端101、第一电位信号输入端102、第二电位信号输入端103、移位信号输入端104和扫描信号输出端105，实现了对移位信号输入端104输入的移位信号的移位功能。与相关技术相比，本申请实 施例提供的扫描驱动电路10的架构仅包括一个输出控制模块140、一个时钟信号输入端101和一个移位信号输入端104，因此，该扫描驱动电路10的结构简单以及控制逻辑简单。且本申请实施例提供的扫描驱动电路10应用于显示面板时，仅在显示面板上为扫描驱动电路10设置一条时钟信号线和一条移位信号线，有利于实现显示面板的窄边框。
图3为本申请实施例提供的另一种扫描驱动电路的结构示意图。参见图3，在上述多个实施例的基础上，可选地，输入模块包括第一晶体管M1，第一晶体管M1的控制端与时钟信号输入端101电连接，第一晶体管M1的第一端与移位信号输入端104电连接，第一晶体管M1的第二端与第二节点N2电连接。
示例性地，第一晶体管M1为N型晶体管，该输入模块控制第二节点N2的电位为高电位的控制过程为，若时钟信号输入端101的时钟信号CLK为高电位，移位信号输入端104的移位信号IN为高电位，第一晶体管M1导通，高电位沿第一晶体管M1到达第二节点N2；该输入模块控制第二节点N2的电位为低电位的控制过程为，若时钟信号输入端101的时钟信号CLK为高电位，移位信号输入端104的移位信号IN为低电位，第一晶体管M1导通，低电位沿第一晶体管M1到达第二节点N2。
本申请实施例设置输入模块仅包括第一晶体管M1，有利于减少扫描驱动电路10中器件的数量。
图4为本申请实施例提供的又一种扫描驱动电路的结构示意图。参见图4，在上述多个实施例的基础上，可选地，输出控制模块140包括第一电容C1、第二晶体管M2、第三晶体管M3和第四晶体管M4；第一电容C1的第一端与时钟信号输入端101电连接，第一电容C1的第二端与第二晶体管M2的控制端电连接；第二晶体管M2的控制端与第三晶体管M3的第二端电连接，第二晶体管M2的第一端与第一电容C1的第一端电连接，第二晶体管M2的第二端与第一节点N1电连接；第三晶体管M3的控制端与移位信号输入端104电连接，第三晶体管M3的第一端与第一电位信号输入端102电连接；第四晶体管M4的控制端与第二节点N2电连接，第四晶体管M4的第一端与第一电位信号输入端102电连接，第四晶体管M4的第二端与第一节点N1电连接。
示例性地，第二晶体管M2、第三晶体管M3和第四晶体管M4均为N型晶体管，第一电位信号为低电位，第二电位信号为高电位。
该输出控制模块140控制第一节点N1的电位为高电位的控制过程为，若时钟信号输入端101的时钟信号CLK为高电位，移位信号输入端104的移位信号IN为低电位，第二节点N2为低电位；第三晶体管M3和第四晶体管M4关断；由于第二晶体管M2的控制端浮置(floating)，以及第一电容C1的耦合作用， 第二晶体管M2的控制端电位被拉高，第二晶体管M2导通；时钟信号CLK信号沿第二晶体管M2到达第一节点N1。
该输出控制模块140控制第一节点N1的电位为低电位的控制过程为，若移位信号输入端104的移位信号IN为高电位，第二节点N2为高电位；第三晶体管M3导通；第一电位信号VGL沿第三晶体管M3到达第二晶体管M2的控制端，使第二晶体管M2关断；第二节点N2的高电位控制第四晶体管M4导通；第一电位信号VGL沿第四晶体管M4到达第一节点N1。
本申请实施例设置输出控制模块140包括第一电容C1、第二晶体管M2、第三晶体管M3和第四晶体管M4，不仅采用了较少的器件数量，还可以在第二输出模块导通时，维持第一输出模块可靠关断，有利于提升扫描信号输出端的可靠性。
图5为本申请实施例提供的又一种扫描驱动电路的结构示意图。参见图5，在上述多个实施例的基础上，可选地，第二输出模块130包括第五晶体管M5和第二电容C2；第五晶体管M5的控制端与第二电容C2的第二端电连接，第五晶体管M5的第一端与第二电位信号输入端103电连接，第五晶体管M5的第二端与扫描信号输出端105和第二节点N2电连接；第二电容C2的第一端与扫描信号输出端105、第二节点以及第五晶体管M5的第二端电连接，第二电容C2的第二端与第五晶体管M5的控制端电连接。
示例性地，第五晶体管M5为N型晶体管，该第二输出模块130输出第二电位信号的控制过程为，若第二节点N2为高电位，第五晶体管M5导通，第二电位信号沿第五晶体管M5到达扫描信号输出端105。以及，第二电容C2具有存储电位的作用，设置为在输入模块110关断时，维持上一阶段第二节点N2的电位。
本申请实施例设置第二输出模块仅包括第五晶体管M5和第二电容C2，有利于减少扫描驱动电路10中器件的数量。
图6为本申请实施例提供的又一种扫描驱动电路的结构示意图。参见图6，在上述多个实施例的基础上，可选地，第一输出模块120包括第六晶体管M6和第三电容C3；第六晶体管M6的控制端与第一节点N1电连接，第六晶体管M6的第一端与第一电位信号输入端102电连接，第六晶体管M6的第二端与扫描信号输出端105电连接；第三电容C3的第一端与第一电位信号输入端102电连接，第三电容C3的第二端与第六晶体管M6的控制端电连接。
示例性地，第六晶体管M6为N型晶体管，该第一输出模块120输出第一电位信号的控制过程为，若第一节点N1为高电位，第六晶体管M6导通，第一 电位信号沿第六晶体管M6到达扫描信号输出端105。以及，第三电容C3具有存储电位的作用，设置为在输出控制模块140关断时，维持上一阶段第一节点N1的电位。
本申请实施例设置第一输出模块仅包括第六晶体管M6和第三电容C3，有利于减少扫描驱动电路10中器件的数量。
在上述多个实施例的基础上，本申请实施例还提供了一种扫描驱动电路。图7为本申请实施例提供的又一种扫描驱动电路的结构示意图，图8为本申请实施例提供的另一种扫描驱动电路的时序示意图。参见图7和图8，该扫描驱动电路10的驱动方法为：
在阶段T21：移位信号IN为高电位、时钟信号CLK为高电位；第一晶体管M1、第三晶体管M3导通；第一电位信号VGL沿第三晶体管M3到达第二晶体管M2的控制端，使第二晶体管M2关断；移位信号IN沿第一晶体管M1到达第四晶体管M4的控制端，第四晶体管M4导通；第一电位信号VGL沿第四晶体管M4到达第六晶体管M6的控制端，使第六晶体管M6关断；移位信号IN沿第一晶体管M1到达第五晶体管M5的控制端，使第五晶体管M5导通；第二电位信号VGH写入第二电容C2，第二电位信号VGH沿第五晶体管M5输出至扫描信号输出端105，扫描信号输出端105的扫描信号OUT＝VGH。
在阶段T22：移位信号IN为高电位、时钟信号CLK为低电位；第三晶体管M3导通，第一电位信号VGL通过第三晶体管M3到达第二晶体管M2的控制端，第二晶体管M2关断；由于阶段T21第二电容C2存入高电位，第五晶体管M5导通，且第四晶体管M4导通；第一电位信号VGL沿第四晶体管M4到达第六晶体管M6的控制端，将第六晶体管M6关断(在该扫描驱动电路10包括第八晶体管M8的情况下，请参见图10，第一电位信号VGL沿第四晶体管M4到达第六晶体管M6的控制端和第八晶体管M8的控制端，将第六晶体管M6和第八晶体管M8关断)；第二电位信号VGH沿第五晶体管M5输出至扫描信号输出端105。VGH可以通过第五晶体管M5输出，扫描信号输出端105的扫描信号OUT＝VGH。
在阶段T23：移位信号IN为高电位、时钟信号CLK为高电位；第一晶体管M1、第三晶体管M3导通；第一电位信号VGL沿第三晶体管M3到达第二晶体管M2的控制端，使第二晶体管M2关断；移位信号IN沿第一晶体管M1到达第四晶体管M4的控制端，第四晶体管M4导通；第一电位信号VGL沿第四晶体管M4到达第六晶体管M6的控制端，使第六晶体管M6关断；移位信号IN沿第一晶体管M1到达第五晶体管M5的控制端，使第五晶体管M5导通；第二 电位信号VGH写入第二电容C2，第二电位信号VGH沿第五晶体管M5输出至扫描信号输出端105，扫描信号输出端105的扫描信号OUT＝VGH。
在阶段T24：移位信号IN为低电位、时钟信号CLK为低电位；第一晶体管M1、第二晶体管M2和第三晶体管M3均关断；由于第二电容C2在阶段T23被写入高电位，因此第五晶体管M5和第四晶体管M4导通；第一电位信号VGL通过第四晶体管M4到达第六晶体管M6的控制端，使第六晶体管M6关断；第二电位信号VGH沿第五晶体管M5输出至扫描信号输出端105，扫描信号输出端105的扫描信号OUT＝VGH。
在阶段T25：移位信号IN为低电位、时钟信号CLK为高电位；第一晶体管M1导通；第三晶体管M3和第四晶体管M4关断；由于第二晶体管M2的控制端浮置(floating)，以及第一电容C1的耦合作用，第二晶体管M2的控制端电位被拉高，第二晶体管M2导通；移位信号IN沿第一晶体管M1到达第五晶体管M5的控制端，第五晶体管M5关断；时钟信号CLK信号沿第二晶体管M2到达第六晶体管M6的控制端，第六晶体管M6导通；第一电位信号VGL沿第六晶体管M6输出至扫描信号输出端105，扫描信号输出端105的扫描信号OUT＝VGL；因此，扫描信号输出端105输出的低电位信号相比于移位信号的低电位延迟一个时钟周期输出。
在阶段T26：移位信号IN为低电位、时钟信号CLK为低电位；第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4关断；由于第二电容C2在阶段T25存储了低电位，第四晶体管M4和第五晶体管M5关断；由于第三电容C3在阶段T25存储了高电位，第六晶体管M6导通；第一电位信号VGL沿第六晶体管M6输出至扫描信号输出端105，扫描信号输出端105的扫描信号OUT＝VGL。
在阶段T27：移位信号IN为低电位、时钟信号CLK为高电位；第一晶体管M1导通，第三晶体管M3和第四晶体管M4关断；由于第二晶体管M2的控制端浮置(floating)，以及第一电容C1的耦合作用，第二晶体管M2的控制端电位被拉高，第二晶体管M2导通；移位信号IN沿第一晶体管M1到达第五晶体管M5的控制端，第五晶体管M5关断；时钟信号CLK信号沿第二晶体管M2到达第六晶体管M6的控制端，第六晶体管M6导通；第一电位信号VGL沿第六晶体管M6输出至扫描信号输出端105，扫描信号输出端105的扫描信号OUT＝VGL。
在阶段T28：移位信号IN为高电位、时钟信号CLK为低电位；第一晶体管M1关断；由于第二电容C2在阶段T27存储了低电位，第五晶体管M5和第四晶体管M4关断；第三晶体管M3导通，第一电位信号VGL沿第三晶体管M3 到达第二晶体管M2的控制端，第二晶体管M2关断；由于第三电容C3在阶段T27存储了高电位，第六晶体管M6导通；第一电位信号VGL沿第六晶体管M6输出至扫描信号输出端105，扫描信号输出端105的扫描信号OUT＝VGL。
在阶段T29，移位信号IN为高电位、时钟信号CLK为高电位；第一晶体管M1、第三晶体管M3导通；第一电位信号VGL沿第三晶体管M3到达第二晶体管M2的控制端，使第二晶体管M2关断；移位信号IN沿第一晶体管M1到达第四晶体管M4的控制端，第四晶体管M4导通；第一电位信号VGL沿第四晶体管M4到达第六晶体管M6的控制端，使第六晶体管M6关断；移位信号IN沿第一晶体管M1到达第五晶体管M5的控制端，使第五晶体管M5导通；第二电位信号VGH写入第二电容C2，第二电位信号VGH沿第五晶体管M5输出至扫描信号输出端105，扫描信号输出端105的扫描信号OUT＝VGH。
在阶段T2A：移位信号IN为高电位、时钟信号CLK为低电位；第三晶体管M3导通，第一电位信号VGL通过第三晶体管M3到达第二晶体管M2的控制端，第二晶体管M2关断；由于阶段T29第二电容C2存入高电位，第五晶体管M5导通，且第四晶体管M4导通；第一电位信号VGL沿第四晶体管M4到达第六晶体管M6的控制端，将第六晶体管M6关断(在该扫描驱动电路10包括第八晶体管M8的情况下，请参见图10，第一电位信号VGL沿第四晶体管M4到达第六晶体管M6的控制端和第八晶体管M8的控制端，将第六晶体管M6和第八晶体管M8关断)；第二电位信号VGH沿第五晶体管M5输出至扫描信号输出端105。VGH可以通过第五晶体管M5输出，扫描信号输出端105的扫描信号OUT＝VGH。
本申请实施例提供的扫描驱动电路10仅包括六个晶体管和三个电容，器件的数量较少，当该扫描驱动电路10应用于显示面板时，所占用显示面板的面积较小，有利于实现显示面板的窄边框。
在上述多个实施例的基础上，可选地，第五晶体管M5和/或第六晶体管M6为双栅晶体管，由于双栅晶体管具有降低漏电流的性质，因此，第五晶体管M5和/或第六晶体管M6为双栅晶体管可以减小扫描信号输出端105的漏电流。
图9为本申请实施例提供的又一种扫描驱动电路的结构示意图，参见图9，在上述多个实施例的基础上，可选地，扫描驱动电路10还包括第七晶体管M7，第七晶体管M7的控制端与第二电位信号输入端103电连接，第七晶体管M7的第一端与第二节点N2电连接，第七晶体管M7的第二端与第二输出模块130电连接。其中，第七晶体管M7设置于第二节点N2和第二输出模块130之间，起到分压作用，以减小第二节点N2向第二输出模块130的漏电流。
图10为本申请实施例提供的又一种扫描驱动电路的结构示意图，参见图10，在上述多个实施例的基础上，可选地，扫描驱动电路10还包括第八晶体管M8和第九晶体管M9；第八晶体管M8的控制端和第一端均与第一输出模块120电连接，第八晶体管M8的第二端与扫描信号输出端105电连接；第九晶体管M9的控制端与扫描信号输出端105电连接，第九晶体管M9的第一端与第二电位信号输入端电连接，第九晶体管M9的第二端与第八晶体管M8的第一端电连接。
其中，第八晶体管M8和第九晶体管M9起到了避免漏电流通过第一输出模块120传输至扫描信号输出端105的作用。原理为，当第二输出模块130导通时，第二输出模块130向扫描信号输出端105输出第二电位信号。第一节点N1控制第八晶体管M8关断，扫描信号输出端105控制第九晶体管M9导通，若第一输出模块120的输出端存在漏电，漏电流会通过第九晶体管M9传输至第二电位信号输入端103，并且第八晶体管M8的第一端的电位与第一电位信号输入端102的电位相等。由于扫描信号输出端105的电位与第一电位信号输入端102的电位相等，使得第八晶体管M8的第一端和第二端的电位相等，从而避免了漏电流通过第八晶体管M8传输至扫描信号输出端。
图11为本申请实施例提供的又一种扫描驱动电路的结构示意图，参见图11，在上述多个实施例的基础上，可选地，还包括第十晶体管M10和第十一晶体管M11；第十晶体管M10的控制端和第一端均与第二输出模块130电连接，第十晶体管M10的第二端与扫描信号输出端105电连接；第十一晶体管M11的控制端与扫描信号输出端105电连接，第十一晶体管M11的第一端与第一电位信号输入端102电连接，第十一晶体管M11的第二端与第十晶体管M10的第一端电连接。
其中，第十晶体管M10和第十一晶体管M11起到了避免漏电流通过第二输出模块130传输至扫描信号输出端105的作用。原理为，当第一输出模块120导通时，第一输出模块120向扫描信号输出端105输出第一电位信号。第二节点N2控制第十晶体管M10关断，扫描信号输出端105控制第十一晶体管M11导通，若第二输出模块130的输出端存在漏电，漏电流会通过第十一晶体管M11传输至第一电位信号输入端102，并且第十晶体管M10的第一端的电位与第一电位信号输入端102的电位相等。由于扫描信号输出端105的电位与第一电位信号输入端102的电位相等，使得第十晶体管M10的第一端和第二端的电位相等，从而避免了漏电流通过第十晶体管M10传输至扫描信号输出端。
在一实施例中，在上述多个实施例中以多个晶体管均为N型晶体管进行说明，并非对本申请的限定。在其他实施例中，还可以将多个晶体管设置为P型晶体管，或部分晶体管采用N型晶体管，部分晶体管采用P型晶体管，在实际 应用中可以根据需求进行设定。示例性地，多个晶体管设置为P型晶体管，第一电位信号为高电位信号，第二电位信号为低电位信号，扫描信号输出端105输出的高电位信号相比于移位信号的高电位延迟一个时钟周期输出。
本申请实施例还提供了一种显示面板。图12为本申请实施例提供的一种显示面板的结构示意图。参见图12，该显示面板包括至少两个如本申请任意实施例所提供的扫描驱动电路10、时钟信号线20、第一电位信号线、第二电位信号线、启动信号线30和至少两条扫描线40。扫描驱动电路10的时钟信号输入端与时钟信号线20电连接，扫描驱动电路的第一电位信号输入端与第一电位信号线电连接，扫描驱动电路的第二电位信号输入端与第二电位信号线电连接；至少两条扫描线40分别与对应的至少两个扫描驱动电路10的扫描信号输出端电连接。至少两个扫描驱动电路10彼此级联连接，第一级扫描驱动电路10的移位信号输入端与启动信号线30电连接；上一级扫描驱动电路10的扫描信号输出端与下一级扫描驱动电路10的移位信号输入端电连接。
本申请实施例提供的显示面板包括了一种全新的扫描驱动电路10，该扫描驱动电路10包括输入模块、第一输出模块、第二输出模块、输出控制模块、第一节点、第二节点、时钟信号输入端、第一电位信号输入端、第二电位信号输入端、移位信号输入端和扫描信号输出端，实现了对移位信号输入端输入的移位信号的移位功能。本申请实施例提供的扫描驱动电路10的架构仅包括一个输出控制模块、一个时钟信号输入端和一个移位信号输入端，因此，显示面板上仅为扫描驱动电路10设置一条时钟信号线20和一条移位信号线，有利于实现显示面板的窄边框。

Claims (11)

  1. 一种扫描驱动电路，包括：输入模块、第一输出模块、第二输出模块、输出控制模块、第一节点、第二节点、时钟信号输入端、第一电位信号输入端、第二电位信号输入端、移位信号输入端和扫描信号输出端；
    所述输入模块与所述第二节点、所述时钟信号输入端和所述移位信号输入端电连接，所述输入模块设置为控制所述第二节点的电位，所述第二节点设置为控制所述第二输出模块的导通状态；
    所述输出控制模块与所述第一节点、所述第二节点、所述时钟信号输入端、所述移位信号输入端和所述第一电位信号输入端电连接；所述输出控制模块设置为控制所述第一节点的电位，所述第一节点设置为控制所述第一输出模块的导通状态；
    所述第一输出模块与所述第一节点、所述第一电位信号输入端和所述扫描信号输出端电连接；所述第一输出模块导通期间，所述第一电位信号输入端输入的第一电位信号传输至所述扫描信号输出端；
    所述第二输出模块与所述第二节点、所述第二电位信号输入端和所述扫描信号输出端电连接；所述第二输出模块导通期间，所述第二电位信号输入端输入的第二电位信号传输至所述扫描信号输出端。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述输入模块包括第一晶体管，所述第一晶体管的控制端与所述时钟信号输入端电连接，所述第一晶体管的第一端与所述移位信号输入端电连接，所述第一晶体管的第二端与所述第二节点电连接。
  3. 根据权利要求1所述的扫描驱动电路，其中，所述输出控制模块包括第一电容、第二晶体管、第三晶体管和第四晶体管；
    所述第一电容的第一端与所述时钟信号输入端电连接，所述第一电容的第二端与所述第二晶体管的控制端电连接；
    所述第二晶体管的控制端与所述第三晶体管的第二端电连接，所述第二晶体管的第一端与所述第一电容的第一端电连接，所述第二晶体管的第二端与所述第一节点电连接；
    所述第三晶体管的控制端与所述移位信号输入端电连接，所述第三晶体管的第一端与所述第一电位信号输入端电连接；
    所述第四晶体管的控制端与所述第二节点电连接，所述第四晶体管的第一端与所述第一电位信号输入端电连接，所述第四晶体管的第二端与所述第一节点电连接。
  4. 根据权利要求1所述的扫描驱动电路，其中，所述第二输出模块包括第五晶体管和第二电容；
    所述第五晶体管的控制端与所述第二电容的第二端电连接，所述第五晶体管的第一端与所述第二电位信号输入端电连接，所述第五晶体管的第二端与所述扫描信号输出端电连接；
    所述第二电容的第一端与所述扫描信号输出端、所述第二节点以及所述第五晶体管的第二端电连接，所述第二电容的第二端与所述第五晶体管的控制端电连接。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述第五晶体管为双栅晶体管。
  6. 根据权利要求1所述的扫描驱动电路，其中，所述第一输出模块包括第六晶体管和第三电容；
    所述第六晶体管的控制端与所述第一节点电连接，所述第六晶体管的第一端与所述第一电位信号输入端电连接，所述第六晶体管的第二端与所述扫描信号输出端电连接；
    所述第三电容的第一端与所述第一电位信号输入端电连接，所述第三电容的第二端与所述第六晶体管的控制端电连接。
  7. 根据权利要求6所述的扫描驱动电路，其中，所述第六晶体管为双栅晶体管。
  8. 根据权利要求1所述的扫描驱动电路，还包括第七晶体管，所述第七晶体管的控制端与所述第二电位信号输入端电连接，所述第七晶体管的第一端与所述第二节点电连接，所述第七晶体管的第二端与所述第二输出模块电连接。
  9. 根据权利要求1所述的扫描驱动电路，还包括第八晶体管和第九晶体管；
    所述第八晶体管的控制端和第一端均与所述第一输出模块电连接，所述第八晶体管的第二端与所述扫描信号输出端电连接；
    所述第九晶体管的控制端与所述扫描信号输出端电连接，所述第九晶体管的第一端与所述第二电位信号输入端电连接，所述第九晶体管的第二端与所述第八晶体管的第一端电连接。
  10. 根据权利要求1所述的扫描驱动电路，还包括第十晶体管和第十一晶体管；
    所述第十晶体管的控制端和第一端均与所述第二输出模块电连接，所述第十晶体管的第二端与所述扫描信号输出端电连接；
    所述第十一晶体管的控制端与所述扫描信号输出端电连接，所述第十一晶体管的第一端与所述第一电位信号输入端电连接，所述第十一晶体管的第二端与所述第十晶体管的第一端电连接。
  11. 一种显示面板，包括至少两个如权利要求1-10任一项所述的扫描驱动电路、时钟信号线、第一电位信号线、第二电位信号线、启动信号线和至少两条扫描线；
    所述扫描驱动电路的时钟信号输入端与所述时钟信号线电连接，所述扫描驱动电路的第一电位信号输入端与所述第一电位信号线电连接，所述扫描驱动电路的第二电位信号输入端与所述第二电位信号线电连接；所述至少两条扫描线分别与对应的所述至少两个扫描驱动电路的扫描信号输出端电连接；
    所述至少两个扫描驱动电路彼此级联连接，第一级所述扫描驱动电路的移位信号输入端与所述启动信号线电连接；上一级所述扫描驱动电路的扫描信号输出端与下一级所述扫描驱动电路的移位信号输入端电连接。
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