WO2021246204A1 - 半導体装置、半導体モジュールおよび半導体装置の製造方法 - Google Patents

半導体装置、半導体モジュールおよび半導体装置の製造方法 Download PDF

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Publication number
WO2021246204A1
WO2021246204A1 PCT/JP2021/019433 JP2021019433W WO2021246204A1 WO 2021246204 A1 WO2021246204 A1 WO 2021246204A1 JP 2021019433 W JP2021019433 W JP 2021019433W WO 2021246204 A1 WO2021246204 A1 WO 2021246204A1
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Prior art keywords
semiconductor device
semiconductor
semiconductor element
electrode pad
sealing material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/019433
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English (en)
French (fr)
Japanese (ja)
Inventor
青吾 大澤
康嗣 大倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
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Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to CN202180040056.8A priority Critical patent/CN115699296B/zh
Publication of WO2021246204A1 publication Critical patent/WO2021246204A1/ja
Priority to US18/059,748 priority patent/US12482714B2/en
Anticipated expiration legal-status Critical
Priority to US19/285,712 priority patent/US20250357230A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/041—Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H10W70/6528—Cross-sectional shapes of the portions that connect to chips, wafers or package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires

Definitions

  • the present disclosure relates to a semiconductor device having a fan-out package structure, a semiconductor module using the semiconductor device, and a method for manufacturing the semiconductor device.
  • Examples of a semiconductor device having a power semiconductor element and a semiconductor module having a double-sided heat dissipation structure using the same include those described in Patent Document 1.
  • the semiconductor module described in Patent Document 1 includes a semiconductor device as a power semiconductor element, two heat sinks arranged on both sides of the semiconductor device, a lead terminal, and a wire connecting the semiconductor device and the lead terminal. To prepare for. Further, in order to prevent a short circuit due to contact between the wire and the heat sink, this semiconductor module is made of a material having high thermal conductivity between the surface of the semiconductor device on which the wire is connected and the heat sink facing this surface. A heat sink is placed.
  • the above-mentioned semiconductor module has a structure in which the gap between the semiconductor device and the heat sink is made larger than a predetermined value by the heat dissipation block to prevent the contact between the wire and the heat sink, the heat dissipation block becomes an obstacle to thinning. There is. Further, since the heat dissipation block is arranged between the semiconductor device and the heat sink, the thermal resistance increases by the amount of the heat dissipation block, and the heat dissipation property of the semiconductor module decreases.
  • the present inventors have diligently studied the structures of semiconductor devices and semiconductor modules in order to make this type of semiconductor module thinner and to increase heat dissipation.
  • the semiconductor device has a fan-out package structure in which a rewiring layer is formed, and a heat sink is bonded to both sides of the semiconductor device without a heat dissipation block, and a lead terminal is connected to the rewiring layer without a wire.
  • a semiconductor module with the above structure. This results in a semiconductor module having a double-sided heat dissipation structure that does not have a heat dissipation block and wires, and is thin and has high heat dissipation.
  • the insulating property in the semiconductor device is insufficient due to the step between the side surface of the semiconductor element and the sealing material covering the semiconductor device. It turned out that it could be done.
  • this semiconductor device when a step is generated between the side surface of the semiconductor element and the sealing material covering the step, the step is formed in the region of the insulating film constituting the rewiring layer that covers the step. The resulting crack may occur. When such a crack in the insulating film occurs, it becomes impossible to secure the insulating property between the wiring formed on the stepped portion and the end portion of the semiconductor element.
  • the present disclosure relates to suppressing a short circuit between an extended wiring arranged on a semiconductor element and a semiconductor element in a semiconductor device having a fan-out package structure, and improving insulation. Further, the present invention relates to a semiconductor module having a double-sided heat dissipation structure, which uses a semiconductor device with improved insulation, has high reliability, is thinned, and has high heat dissipation.
  • a semiconductor device is composed of a semiconductor element having a first electrode pad and a plurality of second electrode pads on the front surface and generating a current in a direction connecting the front surface and the back surface, and an insulating resin material. And an encapsulant that covers part of the surface and sides of the semiconductor device, and is placed on the semiconductor element and inside or over the encapsulant and electrically connected to the second electrode pad. At the same time, it is provided with an extended wiring extending from the inside to the outside of the outer shell of the semiconductor element.
  • the side surface and a part of the surface of the semiconductor element are covered with a sealing material made of an insulating resin material, so that a step between the side surface of the semiconductor element and the sealing material covering the semiconductor element does not occur.
  • the extended wiring formed on the boundary between the side surface of the semiconductor element and the encapsulant is not affected by the step difference between the side surface of the semiconductor element and the encapsulant. Therefore, the insulation defect caused by the step is suppressed, the short circuit between the extended wiring and the semiconductor element is suppressed, and the insulation property is improved.
  • a semiconductor module is a semiconductor element having at least one or more first electrode pads and at least one second electrode pads on the front surface and generating a current in a direction connecting the front surface and the back surface.
  • the first encapsulant which is made of an insulating resin material and covers the periphery of the semiconductor element including a part of the surface, and the inside of the first encapsulant or the first encapsulant on the semiconductor element.
  • a semiconductor device and a semiconductor device, which are arranged on a sealing material, are electrically connected to a second electrode pad, and have an extended wiring extending from the inside to the outside of the outer shell of the semiconductor element.
  • the first heat radiating member connected to the back surface exposed from the first sealing material via the bonding material, and the second heat radiating member electrically connected to the first electrode pad of the semiconductor device via the bonding material.
  • a lead frame that is electrically connected to the extended wiring of the semiconductor device via a bonding material, a semiconductor device, a part of the first heat dissipation member, a part of the second heat dissipation member, and a part of the lead frame. It comprises a second encapsulant to cover.
  • the first heat radiating member and the second heat radiating member are arranged to face each other with the semiconductor device according to one aspect of the present disclosure interposed therebetween, and the lead frame is connected to the extended wiring of the semiconductor device via the bonding material. It becomes a semiconductor module.
  • the semiconductor device and the lead frame are joined via a joining material, and there is no heat dissipation block for securing a gap between the second heat dissipation member and the semiconductor device, and the structure is made thinner and has higher heat dissipation. Further, since the short circuit between the extended wiring and the semiconductor element in the semiconductor device is suppressed, the reliability is further improved.
  • the extending wiring and the lead frame may be connected via a joining material. Even in this case, the semiconductor module has a simpler configuration, is thinner, and has higher heat dissipation.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a fan-out package structure, in which at least one or more first electrode pads and at least one or more second electrode pads are provided on the surface.
  • a semiconductor element to be provided is prepared, and a thick portion, a first thin portion extending outward from the upper end of the thick portion and having a thickness smaller than that of the thick portion, and a first thin portion provided at the tip of the first thin portion.
  • the medium-walled portion which is thinner than the thick-walled portion and thicker than the first thin-walled portion, and the medium-walled portion are extended from the medium-walled portion toward the lower end side of the thick-walled portion, and are thicker than the thick-walled portion.
  • a conductive member having a small second thin wall portion is prepared, the back surface of the semiconductor element is attached to a support substrate, and the lower end surface of the thick wall portion of the conductive member is attached to the first electrode pad of the semiconductor element. Is connected, and the tip of the second thin-walled portion of the conductive member is connected to the second electrode pad of the semiconductor element, and the conductive member is connected to cover the semiconductor element attached to the support substrate together with the conductive member. It includes forming a material and removing the encapsulant from the surface of the encapsulant that covers the conductive member to expose the thick and medium thickness parts of the conductive member from the encapsulant.
  • an insulating resin material is used, and in removing the encapsulant, the first thin-walled portion of the conductive member is removed, and the thick-walled portion, the medium-walled portion, and the first 2 Separate from the thin part.
  • a sealing material is formed, and the sealing material and the first thin wall portion are removed to remove the thickness of the conductive member.
  • the meat portion and the medium meat portion and the second thin meat portion are separated.
  • a portion connected to the first electrode pad from one conductive member and an extended wiring connected to the second electrode pad are formed, and a semiconductor device having a fan-out package structure is manufactured. Therefore, before the forming of the sealing material, the conductive member including the extended wiring is connected to the second electrode pad in advance, and the sealing material covering the surface and the side surface of the semiconductor element is formed together with the conductive member.
  • FIG. 3A It is sectional drawing which shows the manufacturing process following FIG. 3B. It is sectional drawing which shows the manufacturing process following FIG. 3C. It is sectional drawing which shows the manufacturing process following FIG. 3D. It is sectional drawing which shows the manufacturing process following FIG. 3E. It is sectional drawing which shows the manufacturing process following FIG. 3F. It is sectional drawing which shows the manufacturing process following FIG. 3G.
  • FIG. 3 is a cross-sectional view showing a manufacturing process following FIG. 3I. It is a figure which shows an example of the other manufacturing method about the rewiring layer of the semiconductor device of 1st Embodiment, and is the sectional view which shows the manufacturing process following FIG. 3D.
  • FIG. 4A shows a modification of the manufacturing process of FIG. 4A, and is a diagram showing a manufacturing process following FIG. 3D.
  • FIG. 5 is an enlarged cross-sectional view showing a VI region in FIG. It is sectional drawing which shows an example of the semiconductor module using the semiconductor device of 1st Embodiment.
  • FIG. 10A It is sectional drawing which shows the manufacturing process following FIG. 10B. It is sectional drawing which shows the manufacturing process following FIG. 10C. It is sectional drawing which shows the manufacturing process following FIG. 10D. It is sectional drawing which shows the manufacturing process which follows FIG. 10E. It is sectional drawing which shows the manufacturing process following FIG. 10F.
  • FIG. 10G It is sectional drawing which shows the manufacturing process following FIG. 10G. It is sectional drawing which shows the manufacturing process following FIG. 10H. It is sectional drawing which shows the manufacturing process following FIG. 10I. It is sectional drawing which shows the manufacturing process following FIG. 10J. It is explanatory drawing for demonstrating the step break of the insulating layer in the case where the cross-sectional shape of the upper end of the inner wall surface of a sealing material is a right angle shape.
  • 11 is an enlarged cross-sectional view showing an XII region in FIG. 11. It is an enlarged cross-sectional view which shows an example in which the inner wall surface of a sealing material has another cross-sectional shape. It is sectional drawing which shows the structure of the semiconductor device of 3rd Embodiment.
  • FIG. 15A It is a top view of the conductive member bonded to a semiconductor substrate as seen from the top surface. It is an arrow view seen from the XVB direction in FIG. 15A. It is sectional drawing which shows the temporary fixing process of the semiconductor substrate to which the conductive member was bonded in the manufacturing process of the semiconductor device of 3rd Embodiment. It is sectional drawing which shows the manufacturing process following FIG. 16A. It is sectional drawing which shows an example of the semiconductor module which concerns on other embodiment.
  • FIG. 1 is a cross-sectional view showing a configuration between II in FIG.
  • the semiconductor device 1 of the present embodiment is, for example, as shown in FIG. 1, on a semiconductor element 11, a sealing material 12, a first conductor portion 13, a second conductor portion 14, and a semiconductor element 11.
  • a rewiring layer 15 having an extended wiring 152 extending from the inside to the outside of the outer shell of the semiconductor element 11 is provided.
  • the semiconductor element 11 includes a first electrode pad 111, a plurality of second electrode pads 112, an electric field relaxation layer 113, and an insulating film 114 on the element on the surface 11a, and the first conductor portion 13 is connected to the first electrode pad 111.
  • the second conductor portion 14 is connected to the second electrode pad 112.
  • the extended wiring 152 extends from the second conductor portion 14 to the outside of the outer shell of the semiconductor element 11, and a part of the region near the tip thereof is exposed from the sealing material 12.
  • the semiconductor device 1 is a fan-out package in which a part of the surface 11a of the semiconductor element 11 is covered with a sealing material 12 and a rewiring layer 15 including an extended wiring 152 is formed on one surface 12a of the sealing material 12. It is a structure (hereinafter referred to as "FOP structure").
  • the semiconductor element 11 includes, for example, a first electrode pad 111 made of a metal material such as Cu (copper) on the surface 11a, a plurality of second electrode pads 112, an electric field relaxation layer 113, an electric field relaxation layer 113, and a surface 11a. It has an insulating film 114 on the element that covers a part of the element.
  • the semiconductor element 11 is, for example, a power semiconductor element such as an IGBT, and is manufactured by a normal semiconductor process.
  • the semiconductor element 11 has, for example, a third electrode pad (not shown) formed on the back surface 11b, and the third electrode pad can be connected to another member.
  • the first electrode pad 111 and the third electrode pad are, for example, a pair of electrodes constituting an emitter electrode and a collector electrode, and serve as a current path in a direction connecting the front surface 11a and the back surface 11b of the semiconductor element 11.
  • At least one of the plurality of second electrode pads 112 is a gate electrode, and is used to control the on / off of the current between the first electrode pad 111 and the third electrode pad.
  • the first conductor portion 13 is connected to the first electrode pad 111.
  • a second conductor portion 14 is connected to each of the plurality of second electrode pads 112.
  • the portion of the semiconductor element 11 other than the back surface 11b is covered with the sealing material 12.
  • the electric field relaxation layer 113 is, for example, a guard ring or the like, but is not limited thereto.
  • the sealing material 12 is a member that covers a portion other than the back surface 11b of the semiconductor element 11, and is made of an insulating resin material, for example, an arbitrary resin material such as an epoxy resin. Specifically, the sealing material 12 covers a part of the surface 11a of the semiconductor element 11 including the insulating film 114 on the element, and the side surface 11c between the front surface 11a and the back surface 11b, that is, the periphery thereof.
  • the encapsulant 12 straddles the side surface 11c of the semiconductor element 11 and covers a part of the surface 11a when viewed from the normal direction with respect to the surface 11a of the semiconductor element 11, and its outer shell is outside the outer shell of the semiconductor element 11. Is located in.
  • the outer shape of the sealing material 12 is larger than the outer shape of the semiconductor element 11.
  • One surface 12a of the encapsulant 12 on the side covering the surface 11a of the semiconductor element 11 is located at a position higher than the surface 11a.
  • the other surface 12b of the sealing material 12, which is opposite to the one surface 12a, constitutes the back surface 1b of the semiconductor device 1 together with the back surface 11b of the semiconductor element 11.
  • the first conductor portion 13 and the second conductor portion 14 are made of a conductive material such as Cu, and are formed by electrolytic plating or the like. As shown in FIG. 1, the first conductor portion 13 and the second conductor portion 14 are extended toward the upper portion (for example, directly above) of the semiconductor element 11, that is, in the normal direction with respect to the surface 11a, and in the present embodiment, the first conductor portion 13 and the second conductor portion 14 are extended.
  • the thickness is set to a height of 12a or more on one side of the sealing material 12. A part of the first conductor portion 13 and the second conductor portion 14 is arranged inside the rewiring layer 15.
  • One end of the first conductor portion 13 is connected to the first electrode pad 111, and the other end opposite to one end is exposed from the sealing material 12.
  • the other end surface of the first conductor portion 13 is covered with, for example, a covering portion 161 made of Cu or the like and a metal thin film 153 made of Ni (nickel), Au (gold) or the like.
  • One end of the second conductor portion 14 is connected to the second electrode pad 112, and the other end opposite to one end is exposed from the sealing material 12. As shown in FIG. 1, an extended wiring 152 extending from the inside to the outside of the outer shell of the semiconductor element 11 is connected to the other end of the second conductor portion 14.
  • the second conductor portion 14 is formed in the same number as the plurality of second electrode pads 112.
  • the rewiring layer 15 includes an insulating layer 151, an extended wiring 152, and a covering portion 161 and is formed so as to cover one surface 12a of the sealing material 12.
  • the rewiring layer 15 is formed by, for example, a known rewiring forming technique.
  • the rewiring layer 15 is not limited to the wiring example shown in FIG. 1, and may have a configuration in which a plurality of insulating films and internal wiring are laminated.
  • the insulating layer 151 is made of an insulating material such as polyimide, and is formed by an arbitrary coating process or the like.
  • the insulating layer 151 is formed through a plurality of film forming steps and a patterning step by a photolithographic etching method, and is a part of the extended wiring 152 extending from the first conductor portion 13 and the second conductor portion 14. It has a predetermined pattern shape to expose.
  • the insulating layer 151 is formed on one surface 12a of the sealing material 12 which covers the insulating film 114 on the element and has a flat surface, and the interface between the side surface 11c of the semiconductor element 11 and the sealing material 12 ( It has a shape without steps due to (hereinafter referred to as "side interface").
  • the insulating layer 151 has a shape that does not cause cracks due to the side interface and can secure the insulating property between the semiconductor element 11 and the extended wiring 152. The details will be described later.
  • the portion of the insulating layer 151 on the one side 12a side of the extended wiring 152 (the first layer 1511 described later) is thicker than the extended wiring 152 (described later) from the viewpoint of ensuring insulation. It is preferable that the size is larger than that of the second layer 1512).
  • the extension wiring 152 includes, for example, Cu, Au, Ni, Al (aluminum), Ti (titanium), Ag (silver), Pd (palladium), W (tungsten), Zn (zinc), Pb (lead) and the like. It is made of a conductive metal material as a main component.
  • the extended wiring 152 extends from the second conductor portion 14, and is formed by electrolytic plating, electroless plating, or the like.
  • the extended wiring 152 is placed on the semiconductor element 11 on one surface 12a of the sealing material 12 via a part of the insulating layer 151, and has a wiring length straddling the inside and outside of the outer shell of the semiconductor element 11. It has become.
  • the extension wiring 152 is formed in the same number as the second conductor portion 14, and all of them extend from the second conductor portion 14 located inside the outer shell of the semiconductor element 11 to the outside of the outer shell.
  • Each of the plurality of extended wirings 152 is a partial region near the tip on the opposite side of the second conductor portion 14, and a predetermined region located outside the outer shell of the semiconductor element 11 is exposed from the insulating layer 151. At the same time, it is covered with a metal thin film 154 made of Au or the like.
  • the extension wiring 152 is preferably thicker than the second electrode pad 112 from the viewpoint of impedance reduction.
  • the metal thin films 153 and 154 are exposed from the insulating layer 151 and function as external electrodes that can be connected to the first electrode pad 111 and the second electrode pad 112 from the outside.
  • the metal thin films 153 and 154 are electrode portions exposed to the outside on the side opposite to the first electrode pad 111 or the second electrode pad 112, and may be referred to as a "first external electrode” and a "second external electrode", respectively. ..
  • the metal thin film 153 is arranged at a distance from the metal thin film 154, and its outer shape and plane size are larger than those of the metal thin film 154. In the example of FIG.
  • the plurality of metal thin films 154 have the same outer shape and plane size and are evenly arranged, but are not limited to this, and may have different outer shapes and plane sizes or are non-uniform. It may be arranged.
  • the metal thin films 153 and 154 may be a plating layer made of Ni, Au, or the like as long as they are exposed to the outside of the rewiring layer 15 and can be used for connection with the outside. , May be a bump made of solder or the like.
  • the above is the basic configuration of the semiconductor device 1 of the present embodiment.
  • the semiconductor device 1 has a FOP structure in which a rewiring layer 15 is formed via a sealing material 12 that covers the surface 11a of the semiconductor element 11, and is caused by the boundary between the side surface 11c of the semiconductor element 11 and the sealing material 12.
  • the structure is such that the step to be formed does not occur in the rewiring layer 15.
  • a short circuit between the semiconductor element 11 and the extended wiring 152 is suppressed, so that the semiconductor device 1 has improved insulation between the semiconductor element 11 and the extended wiring 152 as compared with the conventional semiconductor device having a FOP structure.
  • the reliability is high.
  • a semiconductor substrate 10 having an element-on-element insulating film 114 covering the first electrode pad 111, the second electrode pad 112, the electric field relaxation layer 113, the electric field relaxation layer 113, and the like is prepared on the surface 11a of the semiconductor element 11.
  • the first conductor portion 13 is formed on the first electrode pad 111 of the semiconductor substrate 10 and the second conductor portion 14 is formed on the second electrode pad 112 by electrolytic plating or the like.
  • the back surface 11b of the semiconductor element 11 among the semiconductor substrates 10 on which the conductor portions 13 and 14 are formed is attached to the support substrate 200 for temporary fixing.
  • the support substrate 200 for example, any one having an adhesive sheet (not shown) having high adhesion to Si (silicon) on its surface is used.
  • a mold (not shown) is prepared, the semiconductor substrate 10 held on the support substrate 200 is covered with a resin material such as epoxy resin by compression molding or the like, and cured by heating or the like, as shown in FIG. 3B. , The sealing material 12 is molded. As a result, a sealing material 12 that covers the surface 11a and the side surface of the semiconductor element 11 together with the conductor portions 13 and 14 is formed. After that, the semiconductor substrate 10 covered with the sealing material 12 is peeled off from the support substrate 200 by, for example, heat treatment.
  • the sealing material 12 is removed from the surface covering the surface 11a side of the semiconductor element 11, and the first conductor portion 13 and the second conductor portion 14 are exposed from the sealing material 12.
  • the sealing material 12 has a flat one-sided surface 12a that covers the insulating film 114 on the element and a part of the surface 11a, and has a shape without steps due to the insulating film 114 on the element.
  • the sealing material 12 may be removed by, for example, a method of grinding using a grinding tool such as a grinder (not shown), or by any other method such as cutting, etching or polishing. , Not particularly limited.
  • a solution containing a resin material such as polyimide is applied by a spin coating method or the like and dried to form a first layer 1511 constituting a part of the insulating layer 151 as shown in FIG. 3D.
  • the first layer 1511 exposes at least a part of the first conductor portion 13 and the second conductor portion 14 of the semiconductor substrate 10 by patterning, for example, by a photolithography etching method, and one surface 12a of the sealing material 12 is exposed. It has a predetermined pattern shape that covers the.
  • the first layer 1511 formed on the flat one surface 12a has a shape without an interface step straddling the side surface of the semiconductor element 11 and the sealing material 12, even if the portion is located on the insulating film 114 on the element. Therefore, the extension wiring 152 formed on the extension wiring 152 will not be adversely affected.
  • the seed layer 16 covering the exposed portion of the first layer 1511 and the semiconductor substrate 10 is formed by vacuum film formation such as by a sputtering method.
  • the seed layer 16 is made of a conductive material such as Cu.
  • an insulating resist layer 16r having a predetermined pattern shape covering a part thereof is formed by the same process as that of the first layer 1511.
  • a covering portion 161 that covers at least a part of the first conductor portion 13 and a part of the first layer 1511 are covered, and at least a part of the second conductor portion 14 is covered. It forms a connected extension wiring 152.
  • the covering portion 161 and the extended wiring 152 are made of a conductive metal material such as Cu.
  • the resist layer 16r is removed with a stripping solution or the like to expose the seed layer 16 from the resist layer 16r.
  • an etching solution or the like is used to remove the portion of the seed layer 16 that is covered with the resist layer 16r.
  • the second layer 1512 which is the remainder of the insulating layer 151, is formed by the spin coating method.
  • the second layer 1512 is patterned by the photolithography etching method, and as shown in FIG. 3J, an unnecessary part of the second layer 1512 is removed to obtain a predetermined pattern shape. Specifically, it covers a predetermined region of the covering portion 161 located above the first conductor portion 13, and a part of the extended wiring 152 near the tip on the opposite side of the second conductor portion 14. A part of the second layer 1512 is removed, and a part of the covering portion 161 and the extended wiring 152 is exposed to the outside. As a result, the insulating layer 151 constituting the rewiring layer 15 is formed.
  • the metal thin films 153 and 154 that cover the portion exposed from the second layer 1512 of the covering portion 161 and the extended wiring 152 are formed.
  • the semiconductor device 1 of the present embodiment can be manufactured by the above steps.
  • [Modification example of manufacturing method] The above manufacturing method is merely an example, and the present invention is not limited thereto.
  • the covering portion 161 and the extended wiring 152 may be formed by a screen printing method instead of electrolytic plating.
  • the print layer 171 is formed by screen printing using a screen mask and a conductive paste material (not shown), and the printed layer 171 is formed and fired to form the covering portion 161 and the covering portion 161.
  • the extension wiring 152 may be formed.
  • the conductive paste material for example, sintered Ag, Cu paste material, Ag paste material and the like can be used.
  • the covering portion 161 and the extended wiring 152 may be made of different materials.
  • the first printing layer 171 covering the first conductor portion 13 is formed by screen printing
  • the second conductor portion 14 is covered and extended to the outside of the outer shell of the semiconductor element 11.
  • the second printed layer 172 is formed into a film. After that, by performing a firing process, it is possible to form the covering portion 161 and the extended wiring 152 made of different conductive materials.
  • the covering portion 161 connected to the first electrode pad 111 which is an emitter electrode
  • the extended wiring 152 connected to the gate electrode and the second electrode pad 112 which is another signal terminal and has a long wiring length can be configured by using a conductive paste material having a lower stress than the covering portion 161.
  • the covering portion 161 and the extended wiring 152 are formed by screen printing, the number of steps is reduced as compared with the rewiring forming technique, and the covering portion 161 and the extended wiring 152 are thickened (limited) as compared with the electrolytic plating. Although it is not a thing, it can also be (for example, 20 ⁇ m or more). Further, in the case of screen printing, it becomes easy to form a plurality of wirings having different wiring characteristics required depending on the wiring forming portion, the wiring length, and the like.
  • the semiconductor device 1 of the present embodiment may be manufactured by forming the covering portion 161 and the extended wiring 152 according to the above modification.
  • the reason why the short circuit between the extended wiring 152 and the semiconductor element 11 is suppressed is that the surface of the semiconductor device 300 is not covered with the sealing material 302 (hereinafter, simply “semiconductor”).
  • a device 300 will be described with reference to FIGS. 5 and 6.
  • the semiconductor device 300 covers the semiconductor element 301 having the first electrode 303, the second electrode 304, the electric field relaxation layer 305, and the insulating film 306 on the element covering the first electrode 303, the second electrode 304, and the side surface thereof.
  • a sealing material 302 is provided.
  • the semiconductor device 300 extends from an insulating layer 309 covering a part of the surface 301a of the semiconductor element 301 and one surface 302a of the encapsulant 302, a covering portion 311 covering the first electrode 303, and a second electrode 304.
  • the extension wiring 310 and a metal thin film 312 covering a part thereof are provided.
  • the semiconductor device 300 has a FOP structure and can transmit an electric signal to the second electrode 304 via a metal thin film 312 exposed to the outside outside the outer shell of the semiconductor element 301.
  • the portion of the insulating layer 309 located closer to the semiconductor element 301 or the sealing material 302 than the extended wiring 310 is the first layer 307, the rest is the second layer 308, and the first layer 307 is a semiconductor.
  • the structure is such that a step may occur at the interface between the element 301 and the sealing material 302.
  • the thickness of the portion of the first layer 307 that covers the step becomes thinner than the other portion due to the interface step between the semiconductor element 301 and the sealing material 302. It ends up.
  • the interface step between the semiconductor element 301 and the sealing material 302 is thinner than the sealing material 302 and the insulating film 306 on the element, resulting in a short circuit between the extending wiring 310 and the semiconductor element 301. May occur.
  • the portion of the first layer 307 that covers the side surface 301c of the semiconductor element 301 and the sealing material 302 across the step is partially thinner than the other portions. It becomes.
  • the locally thinned portion of the first layer 307 may have cracks on the interface between the side surface 301c of the semiconductor element 301 and the sealing material 12 due to factors such as thermal stress.
  • step break cracks caused by a step between the side surface of the semiconductor element and the sealing material covering the insulating layer, which is the base of the extended wiring.
  • the front surface 301a is attached to a support substrate (not shown) and temporarily fixed to form the back surface 301b and the sealing material 302 covering the side surface, and then the back surface 301b is exposed by the step of removing the sealing material 302. It will be in the state of.
  • the semiconductor device 300 is obtained by forming a rewiring layer having an insulating layer 309 and an extended wiring 310 on the surface 301a by a known rewiring forming technique.
  • the sealing material 302 is made of an insulating resin material containing fine particles such as heat dissipation filler
  • the surface 301a has a rewiring layer. Fine particles may be present at the time of formation. Then, instead of the step at the side interface between the side surface 301c of the semiconductor element 301 and the sealing material 302, a step due to fine particles such as the heat radiating filler is generated, and the step caused by the step of the heat radiating filler is generated in the first layer 307. Cuts can occur.
  • the sealing material 12 covers the insulating film 114 on the element and has a flat one surface 12a located higher than the surface 11a of the semiconductor element 11, and one surface 12a. It has a structure in which an insulating layer 151 and an extended wiring 152 are formed on the insulating layer 151. Therefore, the first layer 1511 which is the base of the extended wiring 152 does not have a locally thin portion due to the step at the side interface between the side surface 11c of the semiconductor element 11 and the sealing material 12, and the step breakage occurs. Since it is suppressed, insulation is ensured.
  • the back surface 11b side of the semiconductor element 11 on which the conductor portions 13 and 14 are formed is temporarily fixed to the support substrate 200, the sealing material 12 covering the front surface 11a and the side surface is molded, and then the sealing material 12 is formed.
  • One side 12a of the sealing material 12 is formed by grinding. Therefore, even when an insulating resin material containing fine particles such as a heat radiating filler is used as the sealing material 12, no step due to the fine particles is generated on one surface 12a, which is caused by the fine particles in the sealing material 12. There is no step break.
  • the semiconductor device 1 has a structure in which the insulating property is ensured in a part of the insulating layer 151 which is the base of the extended wiring 152, the short circuit between the extended wiring 152 and the semiconductor element 11 is suppressed, and the reliability is improved.
  • a semiconductor module configuration example Next, an example of a semiconductor module using the semiconductor device 1 of the present embodiment will be described with reference to FIG. 7.
  • a wiring portion connected to the outside in another cross section of the second heat sink 3 described later is shown by a broken line.
  • the semiconductor device 1 When the semiconductor device 1 is applied to a semiconductor module having a double-sided heat dissipation structure, for example, as shown in FIG. 7, the semiconductor module can be made thinner and has higher heat dissipation, which is suitable.
  • the case where the semiconductor device 1 is applied to a semiconductor module having a double-sided heat dissipation structure will be described as a typical example, but the present invention is not limited to this application example.
  • the semiconductor module includes a semiconductor device 1, a first heat sink 2, a second heat sink 3, a lead frame 4, a joining material 5, and a sealing material 6.
  • the semiconductor module has a double-sided heat dissipation structure in which two heat sinks 2 and 3 are arranged facing each other with the semiconductor device 1 interposed therebetween, and heat generated by the semiconductor device 1 is discharged to the outside from both sides via these heat sinks 2 and 3. be.
  • the back surface 1b side is connected to the first heat sink 2, and the metal thin film 153 covering the first conductor portion 13 of the front surface 1a side is connected to the second heat sink 3 via a bonding material 5. Is connected.
  • the semiconductor device 1 is arranged so that, for example, the entire area of the back surface 1b fits inside the outer shell of the upper surface 2a of the first heat sink 2.
  • the surface exposed to the outside is set as one surface 3a, and the surface facing the semiconductor device 1 is set as the other surface 3b. It is arranged outside the outer shell of the other surface 3b of the second heat sink 3.
  • the extended wiring 152 of the semiconductor device 1 is electrically connected to the lead frame 4 via the joining material 5 in a region outside the outer shell of the second heat sink 3.
  • the first heat sink 2 has a plate shape having an upper surface 2a and a lower surface 2b that are in a front-to-back relationship, and is made of, for example, a metal material such as Cu or Fe (iron).
  • the semiconductor device 1 is mounted on the upper surface 2a via a bonding material 5 made of solder, and the lower surface 2b is exposed from the sealing material 6.
  • the first heat sink 2 is, for example, a current path for energization of the semiconductor device 1, and a part of the upper surface 2a side extends to the outside of the sealing material 6. That is, in the present embodiment, the first heat sink 2 plays two roles of a heat radiating member and wiring.
  • the first heat sink 2 may be referred to as a "first heat dissipation member".
  • the second heat sink 3 has a plate shape having one side surface 3a and another side surface 3b which are in a front-to-back relationship, and is made of the same material as the first heat sink 2.
  • the other surface 3b of the second heat sink 3 is arranged so as to face a part of the upper surface 2a of the semiconductor device 1, and one surface 3a is exposed from the sealing material 6.
  • the second heat sink 3 is electrically connected to the first conductor portion 13 via the bonding material 5, and is a current path of the semiconductor element 11 like the first heat sink 2.
  • a part of the other surface 3b side of the second heat sink 3 extends to the outside of the sealing material 6, and serves two roles of a heat radiating member and electrical wiring.
  • the second heat sink 3 may be referred to as a "second heat dissipation member".
  • the lead frame 4 is made of, for example, a metal material such as Cu or Fe, and as shown in FIG. 7, one of the extended wirings 152 in an exposed region located outside the outer shell of the second heat sink 3 in the semiconductor device 1. It is electrically connected to the metal thin film 154 that covers the portion via the bonding material 5.
  • the lead frame 4 includes, for example, a plurality of leads having the same number as the second electrode pad 112, and each of the plurality of leads is electrically connected to the extension wiring 152.
  • a plurality of adjacent leads are connected by a tie bar (not shown) until the encapsulant 6 is formed, but the tie bar is removed by press punching or the like after the encapsulant 6 is formed. It becomes a separated state.
  • the lead frame 4 may be configured as the same member as the first heat sink 2 or the second heat sink 3, and may be connected by a tie bar (not shown) until the formation of the sealing material 6. Even in this case, the lead frame 4 is separated from the first heat sink 2 or the second heat sink 3 by removing the tie bar by press punching or the like after the sealing material 6 is formed.
  • the joining material 5 is a joining material that joins the components of the semiconductor module to each other, and a conductive material such as solder is used for electrically connecting.
  • the joining material 5 is not limited to solder, but at least a material different from the wire is used.
  • the encapsulant 6 is made of, for example, a thermosetting resin such as an epoxy resin, and as shown in FIG. 7, covers the semiconductor device 1, a part of the heat sinks 2 and 3, a part of the lead frame 4, and the bonding material 5. ing.
  • the encapsulant 6 can be said to be a "second encapsulant" that covers the semiconductor device 1 when the encapsulant 12 constituting a part of the semiconductor device 1 is used as the "first encapsulant".
  • This semiconductor module has a structure in which the extended wiring 152 of the semiconductor device 1 and the lead frame 4 are joined by a joining material 5 in a region outside the outer shell of the second heat sink 3. Therefore, unlike the conventional semiconductor module described in Japanese Patent Application Laid-Open No. 2001-156225, the wire connection between the semiconductor device 1 and the lead frame 4 becomes unnecessary. Further, by not using the wire, it is not necessary to arrange the heat dissipation block for preventing the contact between the wire and the second heat sink 3 between the semiconductor device 1 and the second heat sink 3. As a result, the thickness of the semiconductor module can be reduced by the amount of the heat dissipation block, and the thermal resistance of the heat dissipation block is eliminated, so that the thermal resistance from the semiconductor device 1 to the second heat sink 3 becomes small.
  • the semiconductor module using the semiconductor device 1 does not require the heat dissipation block and the wire connection between the members, and has a structure that is thinner and has lower thermal resistance than the conventional one. Further, since the short circuit between the extended wiring 152 of the semiconductor device 1 and the semiconductor element 11 is suppressed, the reliability of the semiconductor module is also improved.
  • both the first and second heat radiating members are composed of a heat sink, but the present invention is not limited to this.
  • the first and second heat radiating members may be composed of the heat transfer insulating substrate 7 and the heat transfer insulating substrates 2 and 3, and the heat transfer insulating substrate 7 may be bonded to the semiconductor device 1.
  • the heat transfer insulating substrate 7 includes an electric conductive portion 71, an insulating portion 72, and a heat conductive portion 73, which are laminated in this order, and the electric conductive portion 71 and the heat conductive portion 73 are formed in the insulating portion 72. It is an electrically independent configuration by being separated.
  • the conductive portion 73 is mainly made of a metal material such as Cu, and each is composed of a metal material.
  • the heat conductive portion 73 is joined to the first heat sink 2 or the second heat sink 3 via a joining material such as solder (not shown).
  • a joining material such as solder (not shown).
  • a DBC (abbreviation of Direct Bonded Copper) substrate can be used as the heat transfer insulating substrate 7, for example.
  • the electrical conduction portion 71 of the heat transfer insulating substrate 7 is, for example, partially connected to an external power source or the like, or is connected to another wiring such as a lead frame 4, and is connected to the semiconductor element 11. Electrical exchange is possible.
  • the semiconductor device 1 and the heat sinks 2 and 3 are insulated by the heat transfer insulating substrate 7, and when the heat sinks 2 and 3 are connected to an external cooler or the like, the cooler or the like and the semiconductor module are used.
  • the structure does not require a separate insulating layer to be interposed between the two. Therefore, the semiconductor module shown in FIG. 8 also has an effect of improving reliability when connected to an external cooler or the like.
  • the first and second heat dissipation members may be partially composed of the heat transfer insulating substrate 7 as described above, or may be entirely composed of the heat transfer insulating substrate 7. good.
  • the semiconductor device 1 has a structure in which a rewiring layer 15 including an extended wiring 152 is formed on a flat one surface 12a of a sealing material 12 that covers the insulating film 114 on the element of the semiconductor element 11. ..
  • a rewiring layer 15 including an extended wiring 152 is formed on a flat one surface 12a of a sealing material 12 that covers the insulating film 114 on the element of the semiconductor element 11. ..
  • the rewiring layer 15 after the first layer 1511 which is a part of the insulating layer 151 is formed on the flat one surface 12a, there is no step on the boundary between the side surface 11c of the semiconductor element 11 and the sealing material 12. It is obtained by forming an extension wiring 152 on the first layer 1511 as a base.
  • the first layer 1511 can secure the insulating property without causing a step break due to a step at the boundary between the side surface 11c of the semiconductor element 11 and the sealing material 12.
  • the insulating property in the rewiring layer 15 is ensured, the short circuit between the semiconductor element 11 and the extended wiring 152 is suppressed, and the semiconductor device 1 having an FOP structure with improved reliability is obtained.
  • this semiconductor device 1 while connecting a heat radiating member such as a heat sink and the first electrode pad 111, the extending wiring 152 electrically connected to the second electrode pad 112 on the outer outside of the heat radiating member. It is a FOP structure that can join the exposed part and other members such as a lead frame. Therefore, by using the semiconductor device 1 in the semiconductor module, it becomes unnecessary to connect the heat dissipation block and the wires between the members, and it can be said that the semiconductor device 1 has a structure suitable for thinning and high heat dissipation of the semiconductor module.
  • the inner wall surface 12c is located on the surface 11a of the semiconductor element 11 of the encapsulant 12, and the surface connected to the one surface 12a is defined as the “inner wall surface 12c”.
  • the first conductor portion is different from the first embodiment in that it has a curved curved shape in a cross-sectional view. In this embodiment, this difference will be mainly described.
  • the inner wall surface 12c has a curved curved surface shape in which the boundary portion between the one surface 12a and the inner wall surface 12c does not form a corner in a cross-sectional view, for example, as shown in FIG.
  • the sealing material 12 has an opening that exposes the surface 11a side of the semiconductor element 11, and the inner wall surface 12c constituting the opening has a cross-sectional shape having a curvature.
  • the portion of the insulating layer 151 that covers the stepped portion between the one surface 12a of the sealing material 12 and the surface 11a of the semiconductor element 11 is designated as a "stepped covering portion" to prevent cracks from occurring in the stepped covering portion and to insulate. This is to ensure sex. Details of this will be described later in the method for manufacturing the semiconductor device 1 of the present embodiment.
  • a semiconductor substrate 10 having a first electrode pad 111, a second electrode pad 112, an electric field relaxation layer 113, an insulating film 114 on the element covering the electric field relaxation layer 113, etc. is prepared on the surface 11a of the semiconductor element 11.
  • a temporary protective material 210 that covers the first electrode pad 111 and the second electrode pad 112 of the semiconductor element 11 is formed.
  • the temporary protective material 210 for example, an adhesive material, a photosensitive resin material, or the like can be used.
  • the back surface 11b of the semiconductor element 11 of the semiconductor substrate 10 on which the temporary protective material 210 is formed is attached to the support substrate 200 for temporary fixing.
  • a sealing material 12 that covers the semiconductor substrate 10 together with the temporary protective material 210 is formed by the same method as in the first embodiment. After that, the semiconductor substrate 10 covered with the sealing material 12 is peeled off from the support substrate 200 by, for example, heat treatment.
  • the surface of the encapsulant 12 covering the surface 11a side of the semiconductor element 11 is ground using a grinding tool such as a grinder (not shown).
  • the temporary protective material 210 is exposed from the sealing material 12.
  • the sealing material 12 is formed with a flat one-sided surface 12a that covers the insulating film 114 on the element and a part of the surface 11a. Grinding is mentioned as an example of removing the sealing material 12 for exposing the temporary protective material 210, but the present invention is not limited to this, and other arbitrary methods such as cutting, etching, and polishing are adopted. Can be done.
  • the inner wall surface 12c of the sealing material 12 has a shape in which the boundary portion between the one surface 12a and the inner wall surface 12c has a corner portion in a cross-sectional view.
  • the sealing material 12 has a curved surface shape in which the inner wall surface 12c is curved in a cross-sectional view, and has a shape without corners at the boundary portion between the one surface 12a and the inner wall surface 12c.
  • the first layer 1511 has a predetermined pattern shape that exposes the first conductor portion 13 and the second conductor portion 14 of the semiconductor substrate 10 and covers one surface 12a and the inner wall surface 12c of the sealing material 12. Will be done.
  • the portion of the first layer 1511 that covers the inner wall surface 12c and the one surface 12a is caused by the boundary portion between the inner wall surface 12c and the one surface 12a. It is suppressed that it becomes thin locally. Specifically, since the region of the sealing material 12 extending from one surface 12a to the inner wall surface 12c is gently inclined, the first layer is compared with the case where the region has a corner portion such as a right angle. The shape of the portion of 1511 that covers the region is stable.
  • the first layer 1511 has the corner portion at the step portion of the sealing material 12. It will be covered.
  • the height of the stepped portion between the one surface 12a of the sealing material 12 and the exposed portion of the semiconductor element 11 changes abruptly, and the first layer 1511 covering the stepped portion may be locally thinned. ..
  • the first layer 1511 and the extension wiring 152 formed on the first layer 1511 may be cut off. If the first layer 1511 has a step break, a short circuit may occur between the extension wiring 152 and the semiconductor element 11, and if the extension wiring 152 has a step break, the energization failure occurs. It causes. This step breakage of the extended wiring 152 can also occur when the first layer 1511 cannot follow the corner portion of the sealing material 12 and cannot cover the corner portion.
  • the occurrence of cracks in the surface is called "step break”.
  • the first layer 1511 suppresses the occurrence of locally thin spots. Therefore, the first layer 1511 has a shape in which step breakage is suppressed and its insulating property is ensured. Further, in the extended wiring 152 formed on the extended wiring 152, the step breakage in the first layer 1511 is suppressed, so that the generation of cracks due to the step breakage is suppressed.
  • the seed layer 16 covering the first layer 1511 and the electrode pads 111 and 112 is formed by the same method as in the first embodiment.
  • an insulating resist layer 16r having a predetermined pattern shape covering a part of the seed layer 16 is formed by the same step as that of the first layer 1511.
  • FIG. 10I for example, by performing electrolytic plating, a covering portion 161 that covers the first electrode pad 111, and an extended wiring 152 that covers a part of the first layer 1511 and the second electrode pad 112 are provided.
  • the covering portion 161 that covers the first electrode pad 111 and the extended wiring 152 that covers the second electrode pad 112 and extends to the outside of the outer shell of the semiconductor element 11 are provided. Can be formed.
  • the metal thin films 153 and 154 covering the portion of the covering portion 161 and the extending wiring 152 exposed from the second layer 1512 are formed.
  • the semiconductor device 1 of the present embodiment can be manufactured by the above process.
  • the inner wall surface 12c has a curved cross-sectional shape, the step breakage in the first layer 1511 which is the base of the extension wiring 152 is suppressed, and the extension wiring 152 and the semiconductor element 11 are short-circuited.
  • the semiconductor device 1 has a structure in which the above is suppressed. Further, in the semiconductor device 1, the first layer 1511 and the extended wiring 152 are provided on the flat one surface 12a of the sealing material 12 that covers a part of the side surface 11c and the surface 11a of the semiconductor element 11 as in the first embodiment. It is a structure in which a part of is formed.
  • a short circuit between the extended wiring 152 and the semiconductor element 11 is made as compared with the case where the rewiring layer 15 is directly formed on the boundary step between the side surface 11c of the semiconductor element 11 and the sealing material 12. Is suppressed and reliability is improved.
  • the inner wall surface 12c may have a shape in which the step formed by the one surface 12a and the exposed portion of the semiconductor element 11 changes gently.
  • the intersection angle ⁇ between the one surface 12a and the inner wall surface 12c is It may have a tapered shape with an obtuse angle.
  • the step breakage of the insulating layer 151 can be suppressed.
  • the first layer 1511 of the insulating layer 151 can follow the corners of the encapsulant 12, and the corners of the encapsulant 12 are locally thinned or the corners are formed from the first layer 1511. Exposure is suppressed, and step breakage of the extended wiring 152 can also be suppressed.
  • the semiconductor device can obtain the same effect as that of the second embodiment.
  • the semiconductor device 1 of the present embodiment does not have the rewiring layer 15, the first conductive portion 181 is connected to the first electrode pad 111, and the second electrode pad 112 is connected to the first conductive portion 181. It differs from the first embodiment in that the two conductive portions 182 are connected to each other. In this embodiment, this difference will be mainly described.
  • the sealing material 12 covers the surface 11a and the side surface of the semiconductor element 11, and the one surface 12a covering the surface 11a side is exposed to the outside.
  • a part of the sealing material 12 covers the first conductive portion 181 and the second conductive portion 182 in the present embodiment, and plays a role corresponding to the insulating layer 151 of the rewiring layer 15.
  • the first conductive portion 181 is connected to the first electrode pad 111, and the end face on the side opposite to the first electrode pad 111 is sealed in a region inside the outer shell of the semiconductor element 11. It is exposed from the material 12.
  • the first conducting portion 181 is a member corresponding to the first conductor portion 13 in the first embodiment.
  • the second conduction portion 182 is connected to the second electrode pad 112, and the end surface opposite to the second electrode pad 112 is sealed in a region outside the outer shell of the semiconductor element 11. It is exposed from the material 12.
  • the second conducting portion 182 is a member corresponding to the second conductor portion 14 and the extended wiring 152 in the first embodiment.
  • the second conductive portion 182 constitutes one member together with the first conductive portion 181 during the manufacturing of the semiconductor device 1 of the present embodiment, and is separated from the first conductive portion 181 in the step of removing the sealing material 12. By doing so, it is a separate body from the first conduction portion 181. Therefore, the second conductive portion 182 is composed of a single member made of the same material as the first conductive portion 181 from the portion connected to the second electrode pad 112 to the exposed portion from the sealing material 12. There is.
  • the first conductive portion 181 and the second conductive portion 182 are members that constitute the conductive member 19 shown in FIGS. 15A and 15B, for example, and the portion connecting them is the manufacturing process of the semiconductor device 1. It became a separate body by being removed in the middle of.
  • the conductive member 19 has a thick-walled portion 191, a plurality of first thin-walled portions 192, a plurality of medium-walled portions 193, and a plurality of second thin-walled portions 194. It becomes.
  • the conductive member 19 includes a plurality of first thin-walled portions 192 extending outward from the upper end side surface of the thick-walled portion 191, that is, the upper end surface 19a, and as shown in FIG. 15A, the conductive member 19 includes a plurality of first thin-walled portions 192.
  • a plurality of first thin-walled portions 192 are arranged in parallel with their extension directions aligned and separated from each other.
  • the thick portion 191 has the largest thickness
  • the medium wall portion 193 has the largest thickness next to the thick portion 191.
  • the conductive member 19 includes a first thin-walled portion 192 and a second thin-walled portion 194, which are smaller in thickness than the medium-walled portion 193, and the second thin-walled portion 194 from each of the medium-walled portions 193 is a thick-walled portion 191. It extends toward the lower end surface.
  • a metal plate such as Cu is prepared and partially thinned by etching to form portions corresponding to the first thin-walled portion 192, the medium-walled portion 193, and the second thin-walled portion 194, and then pressed. It can be manufactured by a method such as punching and bending. In this case, for example, by punching with a press, a gap is formed between the extension portions composed of the first thin wall portion 192, the middle wall portion 193, and the second thin wall portion 194, and the extension portions are separated into a plurality of extension portions. .. Then, by bending the second thin portion 194 toward the lower end side surface of the thick portion 191 by bending processing by a press, the conductive member 19 shown in FIG. 15A or FIG. 15B can be obtained.
  • the bending direction of the plurality of second thin-walled portions 194 is appropriately determined according to the arrangement of the second electrode pads 112 of the semiconductor element 11.
  • the tip portions of the plurality of second thin-walled portions 194 opposite to the middle-walled portions 193 are in a state of facing different directions, for example, as shown in FIG. 15A.
  • FIGS. 16A and 16B an example of the manufacturing method of the semiconductor device 1 of the present embodiment will be described with reference to FIGS. 16A and 16B. Here, a manufacturing process different from that of the first embodiment will be mainly described.
  • a semiconductor substrate 10 and a conductive member 19 having an insulating film 114 on the element covering the first electrode pad 111, the second electrode pad 112, the electric field relaxation layer 113, the electric field relaxation layer 113, and the like are prepared on the surface 11a of the semiconductor element 11. do.
  • the thick portion 191 is connected to the first electrode pad 111 of the semiconductor element 11, and the tip portion of the second thin portion 194 is connected to the second electrode pad 112 by a joining material such as solder (not shown).
  • the back surface 11b of the semiconductor element 11 of the semiconductor substrate 10 to which the conductive member 19 is connected is attached to the support substrate 200 for temporary fixing.
  • the encapsulant 12 that covers the semiconductor substrate 10 together with the conductive member 19 is formed by compression molding or the like using a mold (not shown).
  • the sealing material 12 is ground from the surface of the sealing material 12 on the side covering the conductive member 19 with a grinding tool such as a grinder (not shown), and the conductive member 19 is exposed from the sealing material 12.
  • a grinding tool such as a grinder (not shown)
  • the first thin-walled portion 192 is completely removed, and a part of the medium-walled portion 193 is left.
  • the thick portion 191 and the medium-walled portion 193 and the second thin-walled portion 194 are separated, and the first conductive portion 181 and the second conductive portion 182 are formed.
  • grinding using a grinding tool such as a grinder (not shown) is given as an example, but the present invention is not limited to this, and for example, It may be done by any other method such as cutting, etching or polishing.
  • the semiconductor device 1 of the present embodiment can be manufactured by the above manufacturing method.
  • the conductive member 19 having the second conductive portion 182 that functions as the extended wiring 152 is formed before the sealing material 12. Therefore, the second conductive portion 182 is a manufacturing method that is not affected by the boundary between the side surface 11c of the semiconductor element 11 and the sealing material 12, insulation defects are suppressed, and a short circuit between the second conductive portion 182 and the semiconductor element 11 is performed. Does not occur. Further, the formation of the rewiring layer 15 becomes unnecessary, and the number of manufacturing steps can be reduced as compared with the first embodiment, so that the manufacturing cost is reduced.
  • the second external electrode of the semiconductor device 1 is an exposed region arranged outside the outer shell of the second heat sink 3, and the lead frame 4 is connected to the second external electrode in the exposed region.
  • the structure is shown as an example of a semiconductor module, but the structure is not limited to this.
  • the second heat radiating member has the heat transfer insulating substrate 7, for example, as shown in FIG. 17, the second external electrode of the semiconductor device 1 and the lead frame 4 are connected via the heat transfer insulating substrate 7. It may be a semiconductor module.
  • the electric conduction portion 71 of the heat transfer insulating substrate 7 has an arbitrary pattern in which the portion connected to the first external electrode of the semiconductor device 1 and the portion connected to the second external electrode are electrically independent.
  • the lead frame 4 is arranged inside the outer shell of the second heat radiating member, and is connected to the portion of the electrical conduction portion 71 connected to the second external electrode via the bonding material 5. It is electrically connected to the second external electrode.
  • the configuration of the semiconductor module using the semiconductor device 1 may be appropriately changed depending on the heat radiating member. This is the same not only when the semiconductor device 1 of the first embodiment is used, but also when the semiconductor device 1 of each of the other embodiments is used.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2021/019433 2020-06-05 2021-05-21 半導体装置、半導体モジュールおよび半導体装置の製造方法 Ceased WO2021246204A1 (ja)

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CN202180040056.8A CN115699296B (zh) 2020-06-05 2021-05-21 半导体装置、半导体模组及半导体装置的制造方法
US18/059,748 US12482714B2 (en) 2020-06-05 2022-11-29 Semiconductor device, semiconductor module, and method for manufacturing semiconductor device
US19/285,712 US20250357230A1 (en) 2020-06-05 2025-07-30 Semiconductor device, semiconductor module, and method for manufacturing semiconductor device

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JP2021190670A (ja) 2021-12-13
CN115699296A (zh) 2023-02-03
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CN115699296B (zh) 2026-04-21
US20230093554A1 (en) 2023-03-23
US12482714B2 (en) 2025-11-25

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