WO2021233087A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2021233087A1
WO2021233087A1 PCT/CN2021/090098 CN2021090098W WO2021233087A1 WO 2021233087 A1 WO2021233087 A1 WO 2021233087A1 CN 2021090098 W CN2021090098 W CN 2021090098W WO 2021233087 A1 WO2021233087 A1 WO 2021233087A1
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word line
trench
width
semiconductor structure
layer
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PCT/CN2021/090098
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English (en)
French (fr)
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雒曲
谢文浩
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长鑫存储技术有限公司
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Priority to EP21798541.5A priority Critical patent/EP3955296A4/en
Priority to US17/386,485 priority patent/US11871555B2/en
Publication of WO2021233087A1 publication Critical patent/WO2021233087A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • This application relates to the field of semiconductor technology, in particular to a semiconductor structure and a method of forming the same.
  • Semiconductor devices are more and more widely used in integrated circuits.
  • dynamic random access memory is a type of semiconductor memory widely used in integrated circuits.
  • semiconductor devices continue to develop toward high integration. Therefore, more severe challenges are presented to semiconductor manufacturing technology.
  • semiconductor devices may generate leakage current, which may affect the storage performance of the semiconductor devices.
  • the technical problem to be solved by this application is to provide a semiconductor structure and a method of forming the same, which can reduce the leakage current of the semiconductor structure and improve the storage performance of the semiconductor device.
  • the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, the semiconductor substrate has a plurality of independent active regions, the active regions pass through shallow trench isolation regions Isolation; etch the active region and the shallow trench isolation region to form a trench, the trench includes a first trench and a second trench, the first trench is located in the active region , The second trench is located in the shallow trench isolation region, the width of the first trench is greater than the width of the second trench; a word line is formed in the trench, and the word line includes The first word line and the second word line, the first word line is located in the first trench, the second word line is located in the second trench, and the width of the first word line is greater than the width of the first word line. Describe the width of the second word line.
  • the etching rate of the etching substance to the shallow trench isolation region is lower than that of the active region.
  • the etch rate is such that the width of the first trench is greater than the width of the second trench.
  • the depth of the first trench is less than the depth of the second trench, and the distance from the bottom of the first word line to the surface of the semiconductor substrate is less than that from the bottom of the second word line to the semiconductor substrate. The distance from the substrate surface.
  • the method further includes: forming a sacrificial layer on the surface of the semiconductor substrate, the sacrificial layer covering the Source region and the shallow trench isolation region; in the step of etching the active region and the shallow trench isolation region to form the trench, etching the sacrificial layer, the active region, and The shallow trench isolation region forms the trench.
  • the step of forming a word line in the trench further includes: sequentially forming a dielectric layer, an adhesion layer, and a conductive layer in the trench, the dielectric layer at least covers the inner surface of the trench, and the adhesion layer At least cover the dielectric layer, and the conductive layer at least fills the trench; remove part of the adhesion layer and the conductive layer to form a word line, the upper surface of the word line is lower than the surface of the substrate.
  • a protective layer is filled, and the protective layer at least covers the word line.
  • the present application also provides a semiconductor structure, which is formed by using the above semiconductor structure forming method.
  • the semiconductor structure includes a semiconductor substrate having a plurality of independent active regions.
  • the active area is isolated by a shallow trench isolation area;
  • the word line includes a first word line and a second word line, the first word line is located in the active area, and the second word line is located in the shallow trench In the trench isolation region, the width of the first word line is greater than the width of the second word line.
  • the difference between the width of the first word line and the width of the second word line is 4-10 nm.
  • the width of the first word line is 20-30 nm, and the width of the second word line is 17-25 nm.
  • the distance from the bottom of the first word line to the surface of the semiconductor substrate is smaller than the distance from the bottom of the second word line to the surface of the semiconductor substrate.
  • the distance from the bottom of the first word line to the surface of the semiconductor substrate is 140 to 165 nm, and the distance from the bottom of the second word line to the surface of the semiconductor substrate is 175 to 190 nm.
  • the surface of the word line is lower than the surface of the semiconductor substrate.
  • the distance from the surface of the word line to the surface of the semiconductor substrate is 60-75 nm.
  • the word line includes a dielectric layer, an adhesion layer and a conductive layer arranged in sequence.
  • the upper surface of the adhesion layer is lower than the upper surface of the conductive layer.
  • the semiconductor structure further includes a protective layer, and the protective layer covers at least the word line.
  • the depth of the first word line is 65-105 nm
  • the depth of the second word line is 100-130 nm
  • the width of the first word line is 20-30 nm
  • the width of the second word line is 17-25nm.
  • the advantage of the present application is that the thickness of the shallow trench isolation region between the second word line and its adjacent active region of the semiconductor structure formed by the semiconductor structure forming method of the present application is large enough, then the thickness of the shallow trench isolation region between the second word line and the adjacent active region When the line is energized, the thickness of the inversion layer induced by the second word line in the active area is very small or not, which is not enough to form a parasitic transistor structure, and thus no leakage current is formed, which greatly improves the storage of the semiconductor device. performance.
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for forming a semiconductor structure according to the present application
  • FIGS. 2A to 2N are process flow diagrams of an embodiment of a method for forming a semiconductor structure of the present application
  • 3A and 3B are schematic structural diagrams of an embodiment of the semiconductor structure of this application.
  • FIG. 4 is a schematic structural diagram of another embodiment of the semiconductor structure of the present application.
  • semiconductor devices may generate leakage currents.
  • the buried word line (WL) will pass through the active area (AA) and the shallow trench isolation area (STI) at the same time, while the buried word line in the shallow trench isolation area
  • the wire When the wire is working, an inversion layer is induced in the active area adjacent to it, forming a parasitic transistor structure, which causes leakage current.
  • the present application provides a method for forming a semiconductor structure and a semiconductor structure, which can avoid forming a parasitic transistor structure, thereby avoiding leakage current in the semiconductor structure.
  • FIG. 1 is a schematic diagram of the steps of an embodiment of the method for forming a semiconductor structure of the present application.
  • the active region is isolated by a shallow trench isolation region; step S11, etching the active region and the shallow trench isolation region to form a trench, the trench including a first trench and Second trench; the first trench is located in the active region, the second trench is located in the shallow trench isolation region, the width of the first trench is greater than the second trench
  • Step S12 forming a word line in the trench, the word line includes a first word line and a second word line, the first word line is located in the first trench, the second The word line is located in the second trench, and the width of the first word line is greater than the width of the second word line.
  • FIGS. 2A to 2N are process flow diagrams of an embodiment of a method for forming a semiconductor structure of the present application.
  • FIG. 2A is a top view
  • FIG. 2B is a schematic cross-sectional structure along line AA in FIG. 2A, providing a semiconductor substrate having a plurality of independent active regions 201, the active region 201 is isolated by a shallow trench isolation region 202.
  • the material of the semiconductor substrate may be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it may also be silicon on insulator (SOI) or germanium on insulator (GOI); or It can also be other materials, such as group III-V compounds such as gallium arsenide.
  • the semiconductor substrate material is silicon.
  • the semiconductor substrate is doped with certain impurity ions as required, and the impurity ions may be N-shaped impurity ions or P-shaped impurity ions.
  • the doping includes well region doping and source and drain region doping.
  • the present application provides a method for forming the active region 201.
  • the forming method includes the following steps: using a photolithography and etching method to form a plurality of shallow trenches in a semiconductor substrate; filling the shallow trenches
  • An isolation material forms the shallow trench isolation region 202, and the isolation material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable isolation materials. In this embodiment, the isolation material is silicon oxide.
  • the semiconductor substrate isolated by the shallow trench isolation region 202 is the active region 201. In this embodiment, as shown in FIG. 2A, the active region 201 extends along the B1 direction, and the position of the active region 201 in adjacent rows may have a certain misalignment.
  • the isolation material when the shallow trench is filled with isolation material, the isolation material also covers the upper surface of the semiconductor substrate, that is, the upper surface of the active region 201 is also covered with isolation material .
  • the isolation material on the upper surface of the semiconductor substrate is removed, leaving only the isolation material located in the shallow trench; or When the shallow trench is filled with isolation material, only the isolation material is filled in the shallow trench, and the upper surface of the semiconductor substrate is not covered with the isolation material.
  • a sacrificial layer 210 is formed on the surface of the semiconductor substrate, and the sacrificial layer 210 covers the active region 201 and the shallow trench Isolated area 202.
  • the material of the sacrificial layer 210 includes one or more of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, single crystal silicon, and carbon.
  • the active region 201 and the shallow trench isolation region 202 are etched to form a trench 203.
  • the trench 203 includes a first trench 203A and a second trench 203B, the first trench 203A is located in the active region 201, the second trench 203B is located in the shallow trench isolation region 202, and the width of the first trench 203A is greater than that of the second trench 203A. The width of the trench 203B.
  • the sacrificial layer 210 since there is a sacrificial layer 210 on the surface of the semiconductor substrate, when step S11 is performed, the sacrificial layer 210 is also correspondingly etched to form the trench 203.
  • the trench 203 can be formed by photolithography and etching processes.
  • the width of the first trench 203A and the second trench 203B is controlled by changing the etching rate of the etching material to the shallow trench isolation region 202 and the active region 201, that is, the width of the first trench 203A and the second trench 203B are controlled.
  • the etching selection ratio of the etching material to the shallow trench isolation region 202 and the active region 201 controls the width of the first trench 203A and the second trench 203B.
  • the etching rate of the shallow trench isolation region 202 by the etching material is lower than the etching rate of the active region 201, so that the width of the first trench 203A is greater than that of the second trench.
  • the width of the groove 203B is lower than the etching rate of the active region 201.
  • the shallow trench isolation region 202 is a silicon dioxide isolation region
  • the active region 201 is a silicon active region.
  • the method for forming the trench includes the following steps:
  • a mask layer 220 and a photoresist layer 230 are formed on the sacrificial layer 210.
  • the mask layer 220 may be a single layer or multiple layers.
  • the mask layer 220 includes The carbon layer 221 and the SION layer 222.
  • the photoresist layer 230 is patterned to form a window 231. Specifically, in this step, the photoresist layer 230 is patterned by an ashing method.
  • the mask layer 220 is etched along the window 231 to expose the sacrificial layer 210.
  • HBr and CF 4 can be used as an etching gas to remove the SION layer 222; O 2 , SO 2 and Ar gas can be used as an etching gas to remove the carbon layer 221.
  • CF 4 , CH 2 F 2 and He gas can be used as etching gases to remove the sacrificial layer 210 to expose the active region and the shallow trench isolation region.
  • Cl 2 , HBr, CF 4 and CHF 3 are used as gas sources, and the active region 201 and the shallow trench isolation region 202 are etched for the first time by a plasma process for a certain period of time.
  • the etching rate of Cl 2 , HBr, CF 4 and CHF 3 to silicon is greater than that of silicon dioxide. Therefore, in this step, the etching parameters, such as etching time, can be controlled.
  • the first trench 203A with a set width is preliminarily formed. It is understandable that in this step, the shallow trench isolation region will also be etched, but the etching amount is much less than that of silicon.
  • the photoresist layer 230 and the mask layer 220 will be gradually etched and removed during the etching process. If the photoresist layer 230 and the mask layer 220 are not formed before the step of forming the first trench 203A shown in FIG. 2H If it is completely removed, the photoresist layer 230 and the mask layer 220 are removed by ashing and etching processes.
  • Figure 2I and Figure 2J are schematic cross-sectional views along the line AA in Figure 2I, using CF 4 and CHF 3 as gas sources, using a plasma process to etch the active Region 201 and the shallow trench isolation region 202 for a period of time.
  • the etching rate of CF 4 and CHF 3 on silicon dioxide is greater than the etching rate on silicon. Therefore, in this step, the etching parameters, such as the etching time, can be controlled to form a The second groove 203B. It is understandable that in this step, the active region 201 will also be etched continuously, but the etching amount is much smaller than that of silicon dioxide.
  • a by-product cleaning step is also included.
  • O 2 is used to act on the first groove 203A and the second groove 203B for a certain period of time to clean the by-products.
  • the width W1 of the first trench 203A formed by the above method is greater than the width W2 of the second trench 203B. It can be understood that those skilled in the art can also use other methods to form the trench. Since the width W1 of the first trench 203A is greater than the width W2 of the second trench 203B, the widths of the first word line and the second word line formed subsequently are also different.
  • the width W1 of the first trench 203A is 20-30 nm
  • the width W2 of the second trench 203B is 17-25 nm
  • the width W1 of the first trench 203A is similar to that of the second trench 203B.
  • the difference in width W2 is 4-10nm. If the size of the second trench 203B is too small, the width of the second word line 270B (shown in FIG. 2L) subsequently formed in the second trench 203B will be too small, resulting in a word line resistance. Larger and slower turn-on of the transistor.
  • the depth D1 of the first trench 203A is smaller than the depth D2 of the second trench 203B, and the depths of the first word line and the second word line formed subsequently are also different.
  • a word line is formed in the trench 203.
  • the word line includes a first word line and a second word line.
  • the first word line is located in the first trench
  • the second word line is located in the second trench
  • the first word line is located in the second trench.
  • the width of the line is greater than the width of the second word line.
  • a dielectric layer 240, an adhesion layer 250, and a conductive layer 260 are sequentially formed in the trench 203.
  • the dielectric layer 240 covers at least the inner surface of the trench 203
  • the adhesion layer 250 covers at least the The dielectric layer 240 and the conductive layer 260 at least fill the trench 203.
  • the dielectric layer 240 and the adhesion layer 250 are formed only in the trench 203.
  • the upper surface of the sacrificial layer 210 is also formed in sequence.
  • the dielectric layer 240 and the adhesion layer 250 are formed; before the conductive layer 260 is formed, the dielectric layer 240 and the adhesion layer 250 on the surface of the sacrificial layer 210 are removed.
  • the conductive layer 260 also covers the upper surface of the sacrificial layer 210.
  • the dielectric layer 240 can be an oxide layer, which can be used as a gate oxide layer.
  • the dielectric layer 240 may be formed using an in-situ steam generation (ISSG) process. It is understandable that if the dielectric layer 240 is formed by an in-situ water vapor generation process, since the material of the shallow trench isolation region 202 cannot be oxidized, only in the first trench of the active region 201 The dielectric layer 240 is formed in 203A, and the dielectric layer 240 is not formed in the second trench 203B of the shallow trench isolation region 202; if the dielectric layer 240 is formed by deposition or the like, then the dielectric layer 240 is formed in the The dielectric layer 240 can be formed in both the first trench 203A and the second trench 203B.
  • ISSG in-situ steam generation
  • the adhesion layer 250 may be a titanium nitride layer, and the conductive layer 260 may be a metal tungsten layer.
  • FIG. 2L and FIG. 2M where FIG. 2L is a top view, and FIG. 2M is a schematic cross-sectional view taken along line AA in FIG.
  • the upper surface is lower than the surface of the semiconductor substrate.
  • the conductive layer 260 is etched to a set height, and then a part of the adhesion layer 250 not covered by the conductive layer 260 is removed to form a word line 270, wherein the first trench 203A is formed in the first trench 203A.
  • a word line 270A, a second word line 270B is formed in the second trench 203B.
  • the dielectric layer 240 and the adhesion layer 250 are not shown in FIG. 2K. It can be understood that in this step, the dielectric layer 240 will also be partially removed or thinned as the etching process progresses.
  • the upper surface of the adhesion layer 250 is lower than the upper surface of the conductive layer 260 to reduce the GIDL (Gate Induce Drain Leakage) effect.
  • the width W1 of the first trench 203A is greater than the width W2 of the second trench 203B
  • the width C1 of the first word line 270A is greater than the width C2 of the second word line 270B .
  • the thickness H of the shallow trench isolation region 202 between the second word line 270B and its adjacent active region 201 is sufficiently large, so when the second word line 270B is powered on, the second word line 270B
  • the thickness of the inversion layer induced in the active region 201 is small or not, which is not enough to form a parasitic transistor structure, and thus no leakage current is formed, which greatly improves the storage performance of the semiconductor device.
  • the first word line and the second word line have the same width. When the second word line is energized, the thickness of the inversion layer induced by the second word line in the adjacent active area is very large. Large, can form a parasitic transistor structure, which will cause leakage current.
  • the distance H1 from the bottom of the first word line 270A to the surface of the semiconductor substrate is smaller than that of the second trench 203B.
  • the distance H2 from the bottom of the word line 270B to the surface of the semiconductor substrate is used to form a fin structure, increase the channel width, and improve the performance of the transistor of the semiconductor device to be formed subsequently.
  • the distance H1 from the bottom of the first word line 270A to the surface of the semiconductor substrate is 140 to 165 nm
  • the distance H2 from the bottom of the second word line 270B to the surface of the semiconductor substrate is 175 to 190 nm.
  • the method further includes the following steps: referring to FIG. 2N, a protective layer 280 is filled, and the protective layer 280 covers at least the word line 270 to prevent the conductive layer 260 from being oxidized.
  • the protective layer 280 may be a SiN layer. Wherein, in this embodiment, the protective layer 280 also covers the surface of the sacrificial layer 210.
  • the application also provides a semiconductor structure formed by the above-mentioned manufacturing method.
  • 3A and 3B are structural schematic diagrams of an embodiment of the semiconductor structure of this application, in which FIG. 3A is a top view, and FIG. 3B is a schematic cross-sectional view taken along line AA in FIG. 3A.
  • the semiconductor structure It includes a semiconductor substrate and a word line 370.
  • the semiconductor substrate has a plurality of independent active regions 301, and the active regions 301 are isolated by shallow trench isolation regions 302.
  • the word line 370 includes a first word line 370A and a second word line 370B.
  • the first word line 370A is located in the active region 301, and the second word line 370B is located in the shallow trench isolation region 302. middle.
  • the width C1 of the first word line 370A is greater than the width C2 of the second word line 370B. Further, the width C1 of the first word line 370A is 20-30 nm, the width C2 of the second word line 370B is 17-25 nm, and the width of the first word line 370A is equal to that of the second word line 370B.
  • the difference in width is 4-10nm. Wherein, if the width of the second word line 370B is too small, the resistance of the word line will be too large and the turn-on of the transistor will slow down.
  • the distance H1 from the bottom of the first word line 370A to the surface of the semiconductor substrate is smaller than the distance H2 from the bottom of the second word line 370B to the surface of the semiconductor substrate, so as to form a fin-like structure and increase The channel width improves the performance of the transistor of the subsequently formed semiconductor device.
  • the distance H1 from the bottom of the first word line 370A to the surface of the semiconductor substrate is 140 to 165 nm
  • the distance H2 from the bottom of the second word line 370B to the surface of the semiconductor substrate is 175 to 190 nm.
  • the distance H3 is 60 ⁇ 75nm.
  • the semiconductor structure further includes a protective layer 380 that covers at least the word line 370.
  • the thickness H of the shallow trench isolation region 302 between the second word line 370B and its adjacent active region 301 is sufficiently large, so when the second word line 370B is powered on, the The thickness of the inversion layer induced by the second word line 370B in the active region 301 is small or not, which is not enough to form a parasitic transistor structure, and thus no leakage current is formed, which greatly improves the storage performance of the semiconductor device.

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Abstract

本申请提供一种半导体结构及其形成方法。方法包括：提供半导体衬底，半导体衬底具有多个独立的有源区，有源区通过浅沟槽隔离区隔离；刻蚀有源区及浅沟槽隔离区以形成沟槽，沟槽包括第一沟槽和第二沟槽，第一沟槽位于有源区中，第二沟槽位于浅沟槽隔离区中，第一沟槽的宽度大于第二沟槽的宽度；在沟槽中形成字线，字线包括第一字线和第二字线，第一字线位于第一沟槽中，第二字线位于第二沟槽中，第一字线的宽度大于第二字线的宽度。第二字线与其相邻的有源区之间的浅沟槽隔离区的厚度足够大，在第二字线通电工作时，第二字线在有源区感应的反型层的厚度很小或者没有，不足以形成寄生晶体管结构，不会形成漏电流，大大提高了半导体器件的存储性能。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2020年05月18日递交的中国专利申请号202010419476.4，申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体技术领域，具体涉及一种半导体结构及其形成方法。
背景技术
半导体器件越来越广泛地应用在集成电路中，例如，动态随机存储器是一种广泛地应用在集成电路中的半导体存储器。随着半导体集成电路器件特征尺寸的不断缩小，半导体器件也不断的向高集成度发展，因此，给半导体制造技术提出了更加严峻的挑战。
随着半导体器件的集成度的不断增加，半导体器件可能会产生漏电流，其会影响半导体器件的存储性能。
因此，如何有效地降低漏电流，提高半导体器件的存储性能是目前亟待解决的技术问题。
发明内容
本申请所要解决的技术问题是，提供一种半导体结构及其形成方法，其能够降低半导体结构的漏电流，提升半导体器件的存储性能。
为解决上述技术问题，本申请中提供了一种半导体结构形成方法，包括：提供半导体衬底，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离区隔离；刻蚀所述有源区及所述浅沟槽隔离区以形成沟槽，所述沟槽包括第一沟槽和第二沟槽，所述第一沟槽位于所述有源区中，所述第二沟槽位于所述浅沟槽隔离区中，所述第一沟槽的宽度大于所述第二沟槽的宽度；在所述沟槽中形成字线，所述字线包括第一字线和第二字线，所述第一字线位于所述第一沟槽中，所述第二字线位于所述第二沟槽中，所述第一字线的宽度大于所述第二字线的宽度。
进一步，在刻蚀所述有源区及所述浅沟槽隔离区以形成沟槽的步骤中，刻蚀物质对所述浅沟槽隔离区的刻蚀速率小于对所述有源区的刻蚀速率，以使所述第一沟槽的宽度大于所述第二沟槽的宽度。
进一步，所述第一沟槽的深度小于所述第二沟槽的深度，所述第一字线的底部至所述半导体衬底表面的距离小于所述第二字线的底部至所述半导体衬底表面的距离。
进一步，在刻蚀所述有源区及所述浅沟槽隔离区以形成所述沟槽的步骤之前，还包括：在所述半导体衬底表面形成牺牲层，所述牺牲层覆盖所述有源区及所述浅沟槽隔离区；在刻蚀所述有源区及所述浅沟槽隔离区以形成所述沟槽的步骤中，刻蚀所述牺牲层、所述有源区及所述浅沟槽隔离区以形成所述沟槽。
进一步，在所述沟槽中形成字线的步骤进一步包括：在所述沟槽中依次形成介质层、黏附层和导电层，所述介质层至少覆盖所述沟槽内表面，所述黏附层至少覆盖所述介质层，所述导电层至少填满所述沟槽；去除部分所述黏附层及导电层，形成字线，所述字线的上表面低于所述衬底的表面。
进一步，在所述沟槽中形成字线的步骤之后，填充保护层，所述保护层至少覆盖所述字线。
为了解决上述技术问题，本申请还提供一种半导体结构，采用上述的半导体结构形成方法形成，所述半导体结构包括：半导体衬底，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离区隔离；字线，包括第一字线和第二字线，所述第一字线位于所述有源区中，所述第二字线位于所述浅沟槽隔离区中，所述第一字线的宽度大于所述第二字线的宽度。
进一步，所述第一字线的宽度与所述第二字线的宽度之差为4～10nm。
进一步，所述第一字线的宽度为20～30nm，所述第二字线的宽度为17～25nm。
进一步，所述第一字线的底部至所述半导体衬底表面的距离小于所述第二字线的底部至所述半导体衬底表面的距离。
进一步，所述第一字线的底部至所述半导体衬底表面的距离为140～165nm，所述第二字线的底部至所述半导体衬底表面的距离为175～190nm。
进一步，所述字线上表面低于所述半导体衬底的表面。
进一步，所述字线上表面至所述半导体衬底的表面的距离为60～75nm。
进一步，所述字线包括依次设置的介质层、黏附层及导电层。
进一步，所述黏附层的上表面低于所述导电层的上表面。
进一步，所述半导体结构还包括保护层，所述保护层至少覆盖所述字线。
进一步，所述第一字线的深度为65-105nm，所述第二字线的深度为100-130nm；所述第一字线的宽度为20-30nm，所述第二字线的宽度为17-25nm。
本申请的优点在于，采用本申请半导体结构形成方法形成的半导体结构，其第二字线 与其相邻的有源区之间的浅沟槽隔离区的厚度足够大，则在所述第二字线通电工作时，所述第二字线在所述有源区感应的反型层的厚度很小或者没有，不足以形成寄生晶体管结构，进而不会形成漏电流，大大提高了半导体器件的存储性能。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请半导体结构形成方法的一实施例的步骤示意图；
图2A～图2N是本申请半导体结构形成方法的一实施例的工艺流程图；
图3A及图3B为本申请半导体结构的一实施例的结构示意图；
图4是本申请半导体结构的另一实施例的结构示意图。
具体实施方式
为了使本申请的目的、技术手段及其效果更加清楚明确，以下将结合附图对本申请作进一步地阐述。应当理解，此处所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例，并不用于限定本申请。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
随着半导体器件的集成度的不断增加，半导体器件可能会产生漏电流。申请人研究发现，产生漏电流的原因是，在半导体结构中形成了寄生晶体管结构。该寄生晶体管结构会在半导体器件中形成漏电流。
申请人进一步研究发现，在半导体结构中，埋入式字线(WL)会同时穿过有源区(AA)和浅沟槽隔离区(STI)，而浅沟槽隔离区的埋入式字线在工作时会在与其相邻的有源区感应出反型层，形成寄生晶体管结构，从而产生漏电流。
因此，本申请提供一种半导体结构形成方法及半导体结构，其能够避免形成寄生晶体管结构，从而避免在半导体结构中产生漏电流。
图1为本申请半导体结构形成方法的一实施例的步骤示意图，请参阅图1，本申请半导体结构形成方法包括如下步骤：步骤S10，提供半导体衬底，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离区隔离；步骤S11，刻蚀所述有源区及所述浅沟槽隔离区以形成沟槽，所述沟槽包括第一沟槽和第二沟槽；所述第一沟槽位于所述有源区中， 所述第二沟槽位于所述浅沟槽隔离区中，所述第一沟槽的宽度大于所述第二沟槽的宽度；步骤S12，在所述沟槽中形成字线，所述字线包括第一字线和第二字线，所述第一字线位于所述第一沟槽中，所述第二字线位于所述第二沟槽中，所述第一字线的宽度大于所述第二字线的宽度。
图2A～图2N是本申请半导体结构形成方法的一实施例的工艺流程图。
请参阅步骤S10、图2A及图2B，其中，图2A为俯视图，图2B为沿图2A中A-A线的剖面结构示意图，提供半导体衬底，所述半导体衬底具有多个独立的有源区201，所述有源区201通过浅沟槽隔离区202隔离。
所述半导体衬底的材料可以为硅(Si)、锗(Ge)、硅锗(GeSi)、或碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中所述半导体衬底材料为硅。所述半导体衬底中根据需要掺杂一定的杂质离子，所述杂质离子可以为N形杂质离子或P形杂质离子。在一实施例中，所述掺杂包括阱区掺杂和源漏区掺杂。
本发申请提供一种所述有源区201的形成方法，所述形成方法包括如下步骤：采用光刻刻蚀的方法在半导体衬底中多个浅沟槽；在所述浅沟槽内填充隔离材料形成所述浅沟槽隔离区202，所述隔离材料包括但不限于氧化硅、氮化硅、氮氧化硅或其他合适的隔离材料。本实施例中，所述隔离材料为氧化硅。被所述浅沟槽隔离区202隔离的半导体衬底即为所述有源区201。本实施例中，如图2A所示，所述有源区201沿B1方向延伸，相邻行中有源区201位置可以具有一定的错位。
其中，在本实施例中，在所述浅沟槽内填充隔离材料时，所述隔离材料还覆盖所述半导体衬底的上表面，即在所述有源区201的上表面也覆盖隔离材料。在图2A中，由于有源区201被隔离材料遮挡，所以采用虚线绘示。在本申请其他实施例中，在所述浅沟槽内填充隔离材料后，所述半导体衬底的上表面的隔离材料被去除，仅保留位于所述浅沟槽内的隔离材料；或者在所述浅沟槽内填充隔离材料时，仅在所述浅沟槽内填充隔离材料，在所述半导体衬底上表面并未覆盖隔离材料。
可选地，在步骤S10之后包括如下步骤：请参阅步骤S100及图2C，在所述半导体衬底表面形成牺牲层210，所述牺牲层210覆盖所述有源区201及所述浅沟槽隔离区202。所述牺牲层210的材料包括二氧化硅、氮化硅、氮氧化硅、多晶硅、单晶硅、碳中的一种或多种。
请参阅步骤S11、图2D～图2I，刻蚀所述有源区201及所述浅沟槽隔离区202以形成沟槽203，所述沟槽203包括第一沟槽203A和第二沟槽203B，所述第一沟槽203A位于所述有源区201中，所述第二沟槽203B位于所述浅沟槽隔离区202中，所述第一沟槽203A的宽度大于所述第二沟槽203B的宽度。
在本实施例中，由于在所述半导体衬底表面还具有牺牲层210，则在执行步骤S11时，牺牲层210也被对应刻蚀，以形成所述沟槽203。
在本步骤中，可通过光刻及刻蚀工艺形成所述沟槽203。在刻蚀时，通过改变刻蚀物质对所述浅沟槽隔离区202及有源区201的刻蚀速率来控制所述第一沟槽203A及第二沟槽203B的宽度，即控制所述刻蚀物质对所述浅沟槽隔离区202及有源区201的刻蚀选择比而控制所述第一沟槽203A及第二沟槽203B的宽度。具体地说，刻蚀物质对所述浅沟槽隔离区202的刻蚀速率小于对所述有源区201的刻蚀速率，以使所述第一沟槽203A的宽度大于所述第二沟槽203B的宽度。
下面列举一所述沟槽的形成方法的实施例。在该实施例中，所述浅沟槽隔离区202为二氧化硅隔离区，所述有源区201为硅有源区。所述沟槽的形成方法包括如下步骤：
请参阅图2D，在牺牲层210上形成掩膜层220及光阻层230，所述掩膜层220可为单层或者多层，在该实施例中，所述掩膜层220包括依次设置的碳层221及SION层222。
请参阅图2E，图形化所述光阻层230，形成窗口231。具体地说，在该步骤中，采用灰化的方法图形化所述光阻层230。
请参阅图2F，沿所述窗口231刻蚀所述掩膜层220，暴露出所述牺牲层210。在该步骤中，可采用HBr与CF 4作为刻蚀气体去除SION层222；O 2、SO 2及Ar气作为刻蚀气体去除碳层221。
请参阅图2G，继续刻蚀所述牺牲层210，暴露出所述有源区及所述浅沟槽隔离区。在该步骤中，可采用CF 4、CH 2F 2及He气作为刻蚀气体去除牺牲层210，以暴露出所述有源区及所述浅沟槽隔离区。
请参阅图2H，采用Cl 2、HBr、CF 4及CHF3作为气源，采用等离子体工艺第一次刻蚀所述有源区201及所述浅沟槽隔离区202若干时间。在该步骤中，所述Cl 2、HBr、CF 4及CHF 3对硅的刻蚀速率大于对二氧化硅的刻蚀速率，因此，在该步骤中，可控制刻蚀参数，例如刻蚀时间，初步形成具有设定宽度的所述第一沟槽203A。可以理解的是，在该步骤中，浅沟槽隔离区也会被刻蚀，只是刻蚀量与硅相比要少很多。
其中，光阻层230及掩膜层220在刻蚀的过程中会被逐渐刻蚀去除，若是在图2H所示形成第一沟槽203A的步骤之前，光阻层230及掩膜层220未被完全去除，则采用灰化及刻蚀等工艺去除所述光阻层230及掩膜层220。
请参阅图2I及图2J，其中图2I为俯视图，图2J为沿图2I中A-A线的剖面示意图，采用CF 4及CHF 3作为气源，采用等离子体工艺第二次刻蚀所述有源区201及所述浅沟槽隔离区202若干时间。在该步骤中，CF 4及CHF 3对二氧化硅的刻蚀速率大于对硅的刻蚀速率，因此，在该步骤中，可控制刻蚀参数，例如刻蚀时间，形成具有设定宽度的所述第二沟槽203B。可以理解的是，在该步骤中，所述有源区201也会被继续刻蚀，只是刻蚀量与二氧化硅相比要少很多。
进一步，在刻蚀后，还包括副产物清理步骤。例如，采用O 2作用于第一沟槽203A及第二沟槽203B若干时间，以清理副产物。
采用上述方法形成的第一沟槽203A的宽度W1大于第二沟槽203B的宽度W2。可以理解的是，本领域技术人员也可采用其他方法形成所述沟槽。由于第一沟槽203A的宽度W1大于第二沟槽203B的宽度W2，则后续形成的第一字线与第二字线的宽度也不同。
进一步，所述第一沟槽203A的宽度W1为20～30nm，所述第二沟槽203B的宽度W2为17～25nm，所述第一沟槽203A的宽度W1与所述第二沟槽203B的宽度W2之差为4～10nm。若所述第二沟槽203B的尺寸太小，则会导致后续形成在第二沟槽203B中的第二字线270B(绘示于图2L中)的宽度太小，进而导致字线阻值偏大及晶体管的开启变慢。
进一步，在本实施例中，所述第一沟槽203A的深度D1小于所述第二沟槽203B的深度D2，则后续形成的第一字线与第二字线的深度也不同。
请参阅步骤S12，在所述沟槽203中形成字线。所述字线包括第一字线和第二字线，所述第一字线位于所述第一沟槽中，所述第二字线位于所述第二沟槽中，所述第一字线的宽度大于所述第二字线的宽度。
下面列举一字线的形成方法的实施例。
请参阅图2K，在所述沟槽203中依次形成介质层240、黏附层250和导电层260，所述介质层240至少覆盖所述沟槽203内表面，所述黏附层250至少覆盖所述介质层240，所述导电层260至少填满所述沟槽203。在本实施例中，仅在所述沟槽203中形成所述介质层240、黏附层250，在本申请其他实施例中，由于制备工艺的影响，在所述牺牲层210的上表面也依次形成所述介质层240及黏附层250；在形成导电层260之前，去除所述牺牲层 210表面的所述介质层240及黏附层250。在本实施例中，所述导电层260也覆盖所述牺牲层210的上表面。
其中，所述介质层240可为氧化层，其可作为栅极氧化层使用。可采用原位水汽生成(In-Situ Steam Generation，ISSG)工艺形成所述介质层240。可以理解的是，若采用原位水汽生成工艺形成所述介质层240，由于所述浅沟槽隔离区202的材料不能被氧化，因此，仅在所述有源区201的第一沟槽中203A中形成所述介质层240，在所述浅沟槽隔离区202的第二沟槽203B中并未形成所述介质层240；若是采用沉积等方式形成所述介质层240，则在所述第一沟槽203A及所述第二沟槽203B中均能够形成所述介质层240。
所述黏附层250可为氮化钛层，所述导电层260可为金属钨层。
请参阅图2L及图2M，其中图2L为俯视图，图2M为沿图2L中A-A线的剖面示意图，去除部分所述黏附层250及导电层260，形成字线270，所述字线270的上表面低于所述半导体衬底的表面。在该步骤中，刻蚀所述导电层260至设定高度，再去除未被导电层260覆盖的部分黏附层250，以形成字线270，其中，在所述第一沟槽203A中形成第一字线270A，在第二沟槽203B中形成第二字线270B。由于所述介质层240及黏附层250厚度较小，为了避免附图中线条重叠，在图2K中并未绘示介质层240及黏附层250。可以理解的是，在该步骤中，介质层240也会随着刻蚀工艺的进行而被部分去除或者减薄。
进一步，在形成的字线结构中，所述黏附层250的上表面低于所述导电层260的上表面，以降低GIDL(Gate Induce Drain Leakage)效应。
请参阅图2M，由于所述第一沟槽203A的宽度W1大于所述第二沟槽203B的宽度W2，则所述第一字线270A的宽度C1大于所述第二字线270B的宽度C2。所述第二字线270B与其相邻的有源区201之间的浅沟槽隔离区202的厚度H足够大，则在所述第二字线270B通电工作时，所述第二字线270B在所述有源区201感应的反型层的厚度很小或者没有，不足以形成寄生晶体管结构，进而不会形成漏电流，大大提高了半导体器件的存储性能。而在一些技术方案中，第一字线与第二字线等宽，则第二字线通电工作时，所述第二字线在与其相邻的有源区感应的反型层的厚度很大，能够形成寄生晶体管结构，从而会形成漏电流。
进一步，由于所述第一沟槽203A的深度D1小于所述第二沟槽203B的深度D2，则所述第一字线270A的底部至所述半导体衬底表面的距离H1小于所述第二字线270B的底部至所述半导体衬底表面的距离H2，以形成鳍状结构，增大沟道宽度，提高后续形成的半导 体器件的晶体管的性能。进一步，所述第一字线270A的底部至所述半导体衬底表面的距离H1为140～165nm，所述第二字线270B的底部至所述半导体衬底表面的距离H2为175～190nm。
进一步，所述第一字线270A与所述第二字线270B的上表面平齐，所述第一字线270A与所述第二字线270B的上表面至所述半导体衬底的表面的距离H3为60～75nm。进一步，在步骤S12后，还包括如下步骤：请参阅图2N，填充保护层280，所述保护层280至少覆盖所述字线270，以避免所述导电层260被氧化。所述保护层280可以为SiN层。其中，在本实施例中，所述保护层280也覆盖所述牺牲层210的表面。
本申请还提供一种采用上述制备方法形成的半导体结构。图3A及图3B为本申请半导体结构的一实施例的结构示意图，其中，图3A为俯视图，图3B为沿图3A中A-A线的剖面示意图，请参阅图3A及图3B，所述半导体结构包括半导体衬底及字线370。
所述半导体衬底具有多个独立的有源区301，所述有源区301通过浅沟槽隔离区302隔离。
所述字线370包括第一字线370A和第二字线370B，所述第一字线370A位于所述有源区301中，所述第二字线370B位于所述浅沟槽隔离区302中。所述第一字线370A的宽度C1大于所述第二字线370B的宽度C2。进一步，所述第一字线370A的宽度C1为20～30nm，所述第二字线370B的宽度C2为17～25nm，所述第一字线370A的宽度与所述第二字线370B的宽度之差为4～10nm。其中，若第二字线370B的宽度太小，进而导致字线阻值偏大及晶体管的开启变慢。
进一步，所述第一字线370A的底部至所述半导体衬底表面的距离H1小于所述第二字线370B的底部至所述半导体衬底表面的距离H2，以形成鳍状结构，增大沟道宽度，提高后续形成的半导体器件的晶体管的性能。进一步，所述第一字线370A的底部至所述半导体衬底表面的距离H1为140～165nm，所述第二字线370B的底部至所述半导体衬底表面的距离H2为175～190nm。
进一步，所述第一字线370A与所述第二字线370B的上表面平齐，所述第一字线370A与所述第二字线370B的上表面至所述半导体衬底的表面的距离H3为60～75nm。
图4是本申请半导体结构的另一实施例的结构示意图，请参阅图4，在该实施例中，所述半导体结构还包括保护层380，所述保护层380至少覆盖所述字线370。
在本申请中，所述第二字线370B与其相邻的有源区301之间的浅沟槽隔离区302的厚 度H足够大，则在所述第二字线370B通电工作时，所述第二字线370B在所述有源区301感应的反型层的厚度很小或者没有，不足以形成寄生晶体管结构，进而不会形成漏电流，大大提高了半导体器件的存储性能。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (18)

  1. 一种半导体结构形成方法，其中，包括：
    提供半导体衬底，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离区隔离；
    刻蚀所述有源区及所述浅沟槽隔离区以形成沟槽，所述沟槽包括第一沟槽和第二沟槽，所述第一沟槽位于所述有源区中，所述第二沟槽位于所述浅沟槽隔离区中，所述第一沟槽的宽度大于所述第二沟槽的宽度；
    在所述沟槽中形成字线，所述字线包括第一字线和第二字线，所述第一字线位于所述第一沟槽中，所述第二字线位于所述第二沟槽中，所述第一字线的宽度大于所述第二字线的宽度。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，在刻蚀所述有源区及所述浅沟槽隔离区以形成沟槽的步骤中，刻蚀物质对所述浅沟槽隔离区的刻蚀速率小于对所述有源区的刻蚀速率，以使所述第一沟槽的宽度大于所述第二沟槽的宽度。
  3. 根据权利要求2所述的半导体结构形成方法，其中，所述浅沟槽隔离区为二氧化硅隔离区，所述有源区为硅有源区，刻蚀所述有源区及所述浅沟槽隔离区以形成沟槽的方法包括：
    在所述半导体衬底上形成掩膜层及光阻层；
    图形化所述光阻层，形成窗口；
    沿所述窗口刻蚀所述掩膜层，暴露出所述硅有源区及所述二氧化硅隔离区；
    采用Cl 2、HBr、CF 4及CHF 3作为气源，采用等离子体工艺第一次刻蚀所述有源区及所述二氧化硅隔离区若干时间；
    采用CF 4及CHF 3作为气源，采用等离子体工艺第二次刻蚀所述有源区及所述浅沟槽隔离区若干时间，形成所述第一沟槽及所述第二沟槽。
  4. 根据权利要求1所述的半导体结构形成方法，其中，所述第一沟槽的深度小于所述第二沟槽的深度，所述第一字线的底部至所述半导体衬底表面的距离小于所述第二字线的底部至所述半导体衬底表面的距离。
  5. 根据权利要求1所述的半导体结构形成方法，其中，在刻蚀所述有源区及所述浅沟槽隔离区以形成所述沟槽的步骤之前，还包括：在所述半导体衬底表面形成牺牲层，所述牺牲层覆盖所述有源区及所述浅沟槽隔离区；在刻蚀所述有源区及所述浅沟槽隔离区以形成所述沟槽的步骤中，刻蚀所述牺牲层、所述有源区及所述浅沟槽隔离区以形成所述沟 槽。
  6. 根据权利要求1所述的半导体结构形成方法，其中，在所述沟槽中形成字线的步骤进一步包括：
    在所述沟槽中依次形成介质层、黏附层和导电层，所述介质层至少覆盖所述沟槽内表面，所述黏附层至少覆盖所述介质层，所述导电层至少填满所述沟槽；
    去除部分所述黏附层及导电层，形成字线，所述字线的上表面低于所述衬底的表面。
  7. 根据权利要求6所述的半导体结构形成方法，其中，在所述沟槽中形成字线的步骤之后，填充保护层，所述保护层至少覆盖所述字线。
  8. 一种半导体结构，采用如权利要求1所述的半导体结构形成方法形成，其中，所述半导体结构包括：
    半导体衬底，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离区隔离；
    字线，包括第一字线和第二字线，所述第一字线位于所述有源区中，所述第二字线位于所述浅沟槽隔离区中，所述第一字线的宽度大于所述第二字线的宽度。
  9. 根据权利要求8所述的半导体结构，其中，所述第一字线的宽度与所述第二字线的宽度之差为4～10nm。
  10. 根据权利要求8所述的半导体结构，其中，所述第一字线的宽度为20～30nm，所述第二字线的宽度为17～25nm。
  11. 根据权利要求8所述的半导体结构，其中，所述第一字线的底部至所述半导体衬底表面的距离小于所述第二字线的底部至所述半导体衬底表面的距离。
  12. 根据权利要求11所述的半导体结构，其中，所述第一字线的底部至所述半导体衬底表面的距离为140～165nm，所述第二字线的底部至所述半导体衬底表面的距离为175～190nm。
  13. 根据权利要求11所述的半导体结构，其中，所述字线上表面低于所述半导体衬底的表面。
  14. 根据权利要求13所述的半导体结构，其中，所述字线上表面至所述半导体衬底的表面的距离为60～75nm。
  15. 根据权利要求8所述的半导体结构，其中，所述字线包括依次设置的介质层、黏附层及导电层。
  16. 根据权利要求15所述的半导体结构，其中，所述黏附层的上表面低于所述导电层的上表面。
  17. 根据权利要求8所述的半导体结构，其中，所述半导体结构还包括保护层，所述保护层至少覆盖所述字线。
  18. 根据权利要求8所述的半导体结构，其中，所述第一字线的深度为65-105nm，所述第二字线的深度为100-130nm；所述第一字线的宽度为20-30nm，所述第二字线的宽度为17-25nm。
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