WO2021229734A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

Info

Publication number
WO2021229734A1
WO2021229734A1 PCT/JP2020/019180 JP2020019180W WO2021229734A1 WO 2021229734 A1 WO2021229734 A1 WO 2021229734A1 JP 2020019180 W JP2020019180 W JP 2020019180W WO 2021229734 A1 WO2021229734 A1 WO 2021229734A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
bonding
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2020/019180
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
慎也 西村
秀一 檜座
邦彦 西村
栄治 柳生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to US17/915,104 priority Critical patent/US12512648B2/en
Priority to JP2022522420A priority patent/JP7325624B2/ja
Priority to GB2215350.6A priority patent/GB2609786B/en
Priority to PCT/JP2020/019180 priority patent/WO2021229734A1/ja
Publication of WO2021229734A1 publication Critical patent/WO2021229734A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
    • H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/021—Silicon based substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0217—Removal of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/11—Separation of active layers from substrates

Definitions

  • This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • Patent Document 1 discloses a technique in which a laser is incident on a gallium nitride (GaN) layer grown on a sapphire substrate to separate the GaN layer from the sapphire substrate. Such a separation process is also called a laser lift-off process.
  • a laser As the laser, a laser having a wavelength absorbed by GaN is adopted.
  • the GaN When the laser passes through the sapphire substrate and is incident on the GaN layer, the GaN is separated into gallium (Ga: liquid or solid) and nitrogen (N 2 ) gas at the boundary portion of the GaN layer on the sapphire substrate side. This makes it possible to separate the GaN layer from the sapphire substrate.
  • Patent Document 1 after the separation surface of the separated GaN layer is polished, the GaN layer is bonded to a substrate different from the sapphire substrate.
  • Patent Document 2 also describes a laser lift-off process. Also in Patent Document 2, the semi-insulating GaN layer is separated from the sapphire substrate by the laser lift-off process. After that, the GaN layer is bonded to the heat conductive substrate by a bonding layer composed of Au and Sn.
  • Patent Document 3 also describes a laser lift-off process.
  • a GaN-based semiconductor layer is laminated on a growth substrate to form a semiconductor laminate, and then the semiconductor laminate is separated from the growth substrate by a laser lift-off step. Then, the separately prepared substrate is bonded to the semiconductor laminate with, for example, an adhesive or the like.
  • Patent Documents 1 to 3 irregularities are formed on the GaN surface after the laser lift-off process. In order to remove this unevenness, there is a problem that a polishing step is required and the productivity is low. Further, when the substrates are bonded after the laser lift-off process, a material different from the semiconductor layer such as an adhesive is used as the bonding layer for bonding these. This point can also lead to a decrease in productivity.
  • the present disclosure has been made in view of the above-mentioned problems, and an object thereof is to provide a technique capable of realizing a highly productive semiconductor device.
  • the semiconductor device according to the present disclosure is joined to the first substrate and the semiconductor layer between the first substrate, the semiconductor layer made of a nitride compound semiconductor, and the first substrate and the semiconductor layer, and described above.
  • a bonding layer containing at least one of the constituent elements of a nitride-based compound semiconductor is provided.
  • the method for manufacturing a semiconductor device is provided between a first substrate, a semiconductor layer made of a nitride-based compound semiconductor, and the first substrate and the semiconductor layer, and the first substrate and the semiconductor layer are provided.
  • a method for manufacturing a semiconductor device including a bonding layer for bonding a semiconductor, wherein a laser is incident on the semiconductor layer formed on the second substrate, and the second substrate is separated from the semiconductor layer. And the second step of superimposing the first substrate and the semiconductor layer, and the product formed on the bonding surface of the semiconductor layer by the irradiation of the laser are reacted to form the first substrate and the semiconductor layer.
  • a third step of forming the bonding layer to be bonded is provided.
  • FIG. It is sectional drawing which shows typically an example of the structure of the semiconductor device which concerns on Embodiment 1.
  • FIG. It is a flowchart which shows an example of the manufacturing method of the semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device.
  • FIG. It is a flowchart which shows another example of the manufacturing method of the semiconductor device which concerns on Embodiment 1.
  • FIG. It is a flowchart which shows another example of the manufacturing method of the semiconductor device which concerns on Embodiment 1.
  • FIG. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically an example of the structure of the semiconductor device which concerns on Embodiment 2.
  • FIG. It is a flowchart which shows an example of the manufacturing method of the semiconductor device which concerns on Embodiment 2.
  • It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device.
  • FIG. 1 It is sectional drawing which shows typically an example of the state which a part of the low melting point layer of a liquid has entered the inside of a seed layer. It is sectional drawing which shows typically an example of the structure of the semiconductor device which concerns on Embodiment 3.
  • FIG. It is a flowchart which shows an example of the manufacturing method of the semiconductor device which concerns on Embodiment 3. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically an example of the structure in the process of manufacturing a semiconductor device. It is sectional drawing which shows typically another example of the structure of the semiconductor device which concerns on Embodiment 3.
  • FIG. 1 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device 100 according to the first embodiment.
  • the semiconductor device 100 includes a first substrate 1, a semiconductor layer 2, and a bonding layer 3.
  • the semiconductor device 100 exemplified in FIG. 1 is, for example, a field effect transistor (FET), and further includes a plurality of electrodes 4.
  • FET field effect transistor
  • the first substrate (hereinafter referred to as a bonding substrate) 1 has an upper surface 1a and a lower surface 1b.
  • the bonding substrate 1 is, for example, a semi-insulating substrate, and as a more specific example, it is a silicon (Si) substrate or a silicon carbide (SiC) substrate.
  • the semiconductor layer 2 has an upper surface 2a and a lower surface 2b.
  • the lower surface 2b of the semiconductor layer 2 faces the upper surface 1a of the bonding substrate 1, and the bonding layer 3 is provided between the lower surface 2b of the semiconductor layer 2 and the upper surface 1a of the bonding substrate 1.
  • the bonding layer 3 is bonded to the upper surface 1a and the lower surface 2b. That is, the bonding layer 3 fixes the semiconductor layer 2 and the bonding substrate 1 to each other.
  • the upper surface 1a is also referred to as a joint surface 1a
  • the lower surface 2b is also referred to as a joint surface 2b.
  • the semiconductor layer 2 includes, for example, a nitride compound semiconductor.
  • the nitride-based compound semiconductor is, for example, a compound containing nitrogen and a Group 3 element, and as a more specific example, at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN). Including one.
  • the semiconductor layer 2 may be a laminate in which a plurality of functional layers made of semiconductors are laminated. Alternatively, the semiconductor layer 2 may be composed of a single semiconductor layer.
  • the buffer layer, the barrier layer, the channel layer, and the cap layer are laminated in this order from the bonding substrate 1 side to form the semiconductor layer 2.
  • Each of the buffer layer, the barrier layer, the channel layer and the cap layer contains a nitride compound semiconductor, and is composed of, for example, GaN, AlGaN or AlN.
  • each functional layer may be composed of a single semiconductor layer, or may be composed of a plurality of types of semiconductor layers.
  • the electrode 4 is partially formed on the upper surface 2a of the semiconductor layer 2.
  • three electrodes 4a to 4c are formed on the upper surface 2a of the semiconductor layer 2 as a plurality of electrodes 4.
  • the electrode 4b is, for example, a gate electrode.
  • the electrodes 4a and 4c are provided on opposite sides of the electrode 4b.
  • the electrode 4a is, for example, a source electrode, and the electrode 4c is, for example, a drain electrode.
  • the electrode 4 is formed of a conductor such as metal.
  • An insulating protective film (not shown) may be formed on the upper surface 2a of the semiconductor layer 2 and the plurality of electrodes 4.
  • the insulating protective film contains, for example, at least one of silicon nitride (SiN) and aluminum oxide (Al 2 O 3).
  • the insulating protective film is formed so as to cover the upper surface 2a of the semiconductor layer 2 and the electrode 4.
  • a part of the electrode 4 is not covered with the insulating protective film, and the electrode 4 is connected to the external wiring in the part. That is, a via hole is formed in the insulating protective film, and the electrode 4 is connected to the external wiring through the via hole.
  • the electrodes 4b and 4c may be connected to external wiring, respectively.
  • the semiconductor device 100 further includes, for example, a lead-out electrode 5 and an electrode 6. Further, in the example of FIG. 1, the semiconductor device 100 has a via hole 51 penetrating the bonding substrate 1, the bonding layer 3, and the semiconductor layer 2.
  • the electrode 4a is exposed on the bottom surface of the via hole 51.
  • the lead-out electrode 5 covers the inner wall of the via hole 51 and the exposed surface of the electrode 4a.
  • the electrode 6 is formed on the lower surface 1b of the bonding substrate 1 and the lead-out electrode 5. This electrode 6 is also called a back surface electrode.
  • the electrode 6 is electrically connected to the electrode 4a via the extraction electrode 5.
  • the lead-out electrode 5 and the electrode 6 are also made of a conductor such as metal.
  • the lead-out electrode 5 and the electrode 6 are not always necessary, and may be connected to an external wiring with the same structure as the electrode 4b and the electrode 4c.
  • the semiconductor device 100 does not necessarily have to be a field effect transistor, and may be, for example, various semiconductor devices such as a semiconductor diode or a semiconductor laser.
  • the bonding layer 3 contains at least one of the constituent elements of the semiconductor layer 2.
  • the bonding layer 3 contains gallium (Ga), which is one of the constituent elements of the semiconductor layer 2.
  • the bonding layer 3 contains the constituent element (for example, gallium) and a compound (for example, gallium compound) of a substance different from the constituent element.
  • the bonding layer 3 contains an oxide or a halide formed by reacting a constituent element of the semiconductor layer 2 with an oxygen or a halogen substance.
  • the bonding layer 3 contains gallium oxide as an oxide produced by the reaction of the constituent element with oxygen.
  • the junction surface 2b of the semiconductor layer 2 has, for example, an uneven shape (not shown) which is a laser irradiation mark, as will be described in detail later. This laser irradiation is performed in the manufacturing process (described later) of the semiconductor device 100.
  • the uneven shape is two-dimensionally formed on the entire surface of the joint surface 2b.
  • the joint layer 3 fills the unevenness of the joint surface 2b and adheres to the joint surface 2b.
  • FIG. 2 is a flowchart showing an example of a manufacturing method of the semiconductor device 100
  • FIGS. 3 to 7 are cross-sectional views schematically showing an example of a configuration in the middle of manufacturing the semiconductor device 100.
  • the semiconductor layer 2 is formed on the second substrate 10.
  • the second substrate 10 is a substrate for crystal growth of the semiconductor layer 2, and includes, for example, a sapphire substrate.
  • the semiconductor layer 2 is formed on the upper surface 10a of the second substrate 10 by, for example, a growth method such as a metalorganic vapor phase growth method.
  • a buffer layer, a barrier layer, a channel layer, and a cap layer are formed on the upper surface 10a of the second substrate 10 in this order to form the semiconductor layer 2.
  • the semiconductor layer 2 is composed of GaN, AlGaN, AlN, or the like, and none of the functional layers need to be single-phase, and may be composed of a plurality of layers. Further, some layers may be omitted. Further, impurities such as iron (Fe) or C (carbon) may be added to each functional layer, if necessary.
  • the epitaxial growth of the semiconductor layer 2 on the second substrate 10 produces a laminated structure in which the second substrate 10 and the semiconductor layer 2 are integrated.
  • step S2 the active region and the inactive region of the semiconductor layer 2 are separately formed and the electrode 4 is formed by various steps such as a photolithography step, a film forming step, an ion injection step, a metal vapor deposition and a plating step. At the same time, an insulating protective film is formed. As a result, a transistor structure including the semiconductor layer 2 and the electrode 4 is formed on the second substrate 10 (see FIG. 3).
  • the semiconductor device 100 since the semiconductor device 100 is a field effect transistor, the transistor structure was formed on the second substrate 10 in steps S1 and S2. However, if the semiconductor device 100 is another semiconductor device, a structure corresponding to the semiconductor device is formed on the second substrate 10.
  • step S3 the semiconductor layer 2 and the second substrate 10 are separated from each other by using laser irradiation (laser lift-off step).
  • the laser beam is irradiated from the lower surface 10b side of the second substrate 10.
  • a laser light having a wavelength having a low absorption rate and a high transmittance in the second substrate 10 is adopted.
  • a laser beam having a wavelength of 4 ⁇ m or less is adopted.
  • the laser light passes through the second substrate 10 and is incident on the semiconductor layer 2.
  • this laser light a laser light having a high absorption rate in the semiconductor layer 2 is adopted.
  • laser light having a wavelength of 370 nm or less is desirable, and more preferably, a wavelength of 360 nm or less.
  • a laser beam having a wavelength of 266 nm, which is a fourth harmonic of a YAG (Yttrium Aluminum Garnet) laser is adopted.
  • the nitride compound semiconductor absorbs the energy of the laser beam at the boundary portion of the semiconductor layer 2 on the second substrate 10 side.
  • Nitride-based compound semiconductors are separated into a single substance of each constituent element by the energy.
  • the laser beam is irradiated with an amount of light to the extent that this separation is performed.
  • gallium nitride separates into gallium and nitrogen. Nitrogen is a gas at room temperature. The formula for this chemical reaction is as follows.
  • gallium nitride is separated into gallium and nitrogen, which is a gas, at the boundary portion of the semiconductor layer 2 on the second substrate 10 side.
  • the melting point of this gallium is lower than the melting point of gallium nitride, which is about 30 degrees.
  • the semiconductor layer 2 is separated into a single substance (gallium) having a melting point lower than its own melting point and a single substance (nitrogen) which is a gas at the boundary portion.
  • the laser light is irradiated so as to draw a continuous line from the outer periphery of the second substrate 10.
  • the nitrogen gas can move outward from between the second substrate 10 and the semiconductor layer 2.
  • the gallium is solidified by cooling.
  • a low melting point layer 30 made of gallium is formed between the semiconductor layer 2 and the second substrate 10 (see FIG. 4).
  • the melting point of the low melting point layer 30 is lower than the melting points of the other layers, specifically, the melting points of the insulating protective film, the electrode 4, the semiconductor layer 2 and the second substrate 10.
  • the boundary surface between the semiconductor layer 2 and the low melting point layer 30 becomes the bonding surface 2b, and the bonding surface 2b has irregularities (not shown) due to laser irradiation.
  • the shape of this unevenness has a shape that reflects laser irradiation. Therefore, it can be said that this unevenness is a laser irradiation mark.
  • the laminated structure 100a including the insulating protective film, the electrode 4, the semiconductor layer 2, the low melting point layer 30, and the second substrate 10 is heated.
  • the laminated structure 100a is heated by a heater such as a hot plate (not shown).
  • the heater raises the temperature of the laminated structure 100a to a temperature higher than the melting point of the low melting point layer 30 and lower than the melting point of the other layers. As a result, the low melting point layer 30 is melted.
  • the semiconductor layer 2 and the second substrate 10 are separated from each other by separating the semiconductor layer 2 and the second substrate 10 from each other (see FIG. 5).
  • the laminated structure in which the second substrate 10 is separated from the laminated structure 100a is referred to as a laminated structure 100b.
  • a part of the low melting point layer 30 solidifies and becomes one of the constituent elements of the laminated structure 100b.
  • the low melting point layer 30 constitutes the lowest layer of the laminated structure 100b.
  • step S3 Since the temperature of the laminated structure 100a can be raised by laser irradiation, the semiconductor layer 2 may be separated from the second substrate 10 during laser irradiation.
  • step S4 the bonding substrate 1 and the semiconductor layer 2 are overlapped (see FIG. 6). Specifically, the laminated structure 100b is placed on the bonding surface 1a of the bonding substrate 1 so that the low melting point layer 30 of the laminated structure 100b comes into contact with the bonding surface 1a of the bonding substrate 1. As a result, the bonding surface 2b of the semiconductor layer 2 faces the bonding surface 1a of the bonding substrate 1 via the low melting point layer 30.
  • step S5 the melting point of the low melting point layer 30 is formed by reacting the product (that is, the low melting point layer 30) formed on the bonding surface 2b of the semiconductor layer 2 by the laser irradiation of step S3 with another substance.
  • the substance is bonded to the bonding substrate 1 and the semiconductor layer 2 while changing to a higher substance.
  • the substance functions as the bonding layer 3 (see FIG. 7).
  • a predetermined space in which the bonding substrate 1 and the laminated structure 100b are placed is set as an oxygen atmosphere, and the bonding substrate 1 and the laminated structure 100b are heated.
  • a heater such as a hot plate is used to heat the bonded substrate 1 and the laminated structure 100b to a temperature higher than the melting point of the low melting point layer 30 and lower than the melting point of the other layers.
  • the gallium of the low melting point layer 30 is liquefied and adheres to the entire surface of the bonding surface 1a of the bonding substrate 1. Further, since the low melting point layer 30 becomes a liquid, the low melting point layer 30 can fill the unevenness of the bonding surface 2b of the semiconductor layer 2 and adhere to the low melting point layer 30. Then, the gallium is oxidized by the surrounding oxygen and changed to gallium oxide (that is, the bonding layer 3) in a state of being bonded to the bonding surface 1a of the bonding substrate 1 and the bonding surface 2b of the semiconductor layer 2 (see FIG. 7). ). The melting point of the bonding layer 3 is higher than the melting point of the low melting point layer 30. In short, the low melting point layer 30 made of gallium is transformed into the high melting point bonding layer 3 containing gallium oxide. Further, this gallium oxide has an insulating property.
  • a via hole 51 that penetrates the bonding substrate 1, the bonding layer 3 and the semiconductor layer 2 and leads to the electrode 4a is formed by a processing method such as a reactive ion etching method, a wet etching method, or a laser processing method.
  • a processing method such as a reactive ion etching method, a wet etching method, or a laser processing method.
  • the via hole 51 may be formed by combining the above processing methods.
  • step S7 the extraction electrode 5 and the electrode 6 are formed.
  • the lead-out electrode 5 and the electrode 6 are formed by a method such as a vapor deposition or a sputtering method.
  • the electrode 6 is electrically connected to the electrode 4a via the extraction electrode 5.
  • the semiconductor device 100 can be manufactured by the above manufacturing method (see FIG. 1). Moreover, according to this manufacturing method, the junction layer 3 is formed by using the reactant (low melting point layer 30: gallium) of the semiconductor layer 2 generated by laser irradiation.
  • the conventional manufacturing method For comparison, consider the conventional manufacturing method.
  • all the low melting point layer 30 (gallium) is removed, and the bonding surface 2b of the semiconductor layer 2 is flattened by polishing or the like.
  • the bonding substrate 1 is bonded to the semiconductor layer 2 with an adhesive or the like.
  • the number of steps is increased because the step of removing the low melting point layer 30 and the step of flattening the joint surface 2b are required.
  • a material different from the semiconductor layer 2 such as an adhesive is used as the bonding layer for bonding the bonding substrate 1 and the semiconductor layer 2, the manufacturing cost is high.
  • the bonding layer 3 is formed by using the low melting point layer 30. Therefore, the step of removing the low melting point layer 30 and the step of flattening the joint surface 2b can be eliminated. Further, since the bonding layer 3 is formed by using the low melting point layer 30 generated from the semiconductor layer 2, the bonding layer 3 is configured to contain a constituent element (for example, gallium) of the semiconductor layer 2. According to this, the material cost of the bonding layer 3 can be reduced as compared with the case where the bonding layer 3 is made of a material completely different from the semiconductor layer 2 such as an adhesive.
  • the semiconductor device 100 can be manufactured with a smaller number of steps.
  • the material cost of the bonding layer 3 can be reduced. That is, productivity can be improved.
  • the bonding layer 3 fills the unevenness of the bonding surface 2b of the semiconductor layer 2 and adheres to the bonding surface 2b, the bonding area between the bonding layer 3 and the semiconductor layer 2 can be increased. According to this, it is possible to realize the semiconductor device 100 having high bonding strength.
  • step S5 the bonding substrate 1 and the laminated structure 100b were heated in an atmosphere of a gas such as oxygen that reacts with the low melting point layer 30.
  • a gas such as oxygen that reacts with the low melting point layer 30
  • the low melting point layer 30 can be reacted with the gas to change into the bonding layer 3.
  • a halogen gas for example, chlorine gas
  • the gallium in the low melting point layer 30 can be changed to a halide, and more specifically to gallium chloride (Ga 2 Cl 6) as a more specific example.
  • the melting point of gallium chloride is higher than the melting point of gallium.
  • FIG. 8 is a flowchart showing another example of the manufacturing method of the semiconductor device 100.
  • Steps S11 to S13 are the same as steps S1 to S3, respectively.
  • step S14 a thinning process for reducing the thickness of the low melting point layer 30 is performed.
  • a chemical solution for example, an etching solution
  • the laminated structure 100b is immersed in the chemical solution.
  • the chemical solution for example, hydrochloric acid can be adopted.
  • the low melting point layer 30 is gradually removed from its surface by the chemical solution.
  • the laminated structure 100b is taken out from the chemical solution and the chemical solution is washed away. Thereby, the low melting point layer 30 can be made thin.
  • steps S15 to S18 are executed in this order. Steps S15 to S18 are the same as steps S4 to S7, respectively.
  • the thickness of the low melting point layer 30 is reduced before the joining step (step S16) (step S14). Therefore, the bonding layer 3 can be thinned. As a result, the semiconductor device 100 can be made thinner.
  • the semiconductor device 100 illustrated in FIG. 1 has a via hole 51.
  • the via hole 51 penetrates the bonding substrate 1, the bonding layer 3, and the semiconductor layer 2, and the electrode 4 and the electrode 6 are electrically connected to each other by a lead-out electrode 5 in the via hole 51. Since the extraction electrode 5 contacts the inner wall of the via hole 51, a part of the extraction electrode 5 contacts the bonding layer 3 in the via hole 51.
  • the bonding layer 3 is formed by changing the low melting point layer 30 made of a conductive metal (gallium) into an insulating compound.
  • a conductive metal gallium
  • the conductive metal in the bonding layer 3 hereinafter referred to as a residual conductor
  • an insulation treatment may be performed to insulate the residual conductor contained in the bonding layer 3 exposed in the via hole 51.
  • FIG. 9 is a flowchart showing an example of the above-mentioned manufacturing method of the semiconductor device 100.
  • Steps S21 to S26 are the same as steps S1 to S6, respectively.
  • FIG. 10 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device 100 in the middle of manufacturing, and more specifically, shows the laminated structure 100c obtained by step S26.
  • a via hole 51 is formed in the laminated structure 100c.
  • step S27 following step S26 the residual conductor of the bonding layer 3 exposed in the via hole 51 is insulated.
  • the laminated structure 100c may be heated in an atmosphere of a gas such as oxygen gas or chlorine gas that reacts with the residual conductor.
  • the residual conductor (gallium) on the surface of the bonding layer 3 reacts with a gas such as oxygen or chlorine gas to form an insulating compound.
  • step S28 the extraction electrode 5 and the electrode 6 are formed in the same manner as in step S7.
  • step S27 the residual conductor of the bonding layer 3 exposed in the via hole 51 is insulated, so that the extraction electrode 5 and the electrode 6 are more reliably connected to the bonding layer 3. Can be avoided.
  • FIG. 11 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device 100A according to the second embodiment.
  • the semiconductor device 100A has the same configuration as the semiconductor device 100 except for the presence / absence of the via hole 51, the extraction electrode 5, and the electrode 6.
  • an example of a specific configuration of the bonding layer 3 in the semiconductor device 100A is also different from that of the semiconductor device 100.
  • the bonding layer 3 has an alloy containing at least one of the constituent elements (for example, gallium) of the semiconductor layer 2.
  • the substance other than gallium constituting the alloy contains, for example, at least one of magnesium (Mg), cobalt (Co), nickel (Ni), copper (Cu) and silver (Au).
  • an iron-gallium alloy produced by an alloying reaction of iron and gallium can be suitably used as the bonding layer 3.
  • FIG. 12 is a flowchart showing an example of a manufacturing method of the semiconductor device 100A.
  • Steps S31 to S33 are the same as steps S1 to S3, respectively.
  • the laminated structure 100b (see FIG. 5) is produced as in the first embodiment.
  • the boundary surface that is, the bonding surface 2b
  • the boundary surface that is, the bonding surface 2b
  • this unevenness has a shape characteristic of laser irradiation, it is a laser irradiation mark.
  • step S34 a seed layer 31 that contributes to the reaction with the low melting point layer 30 is formed on the bonding surface 1a of the bonding substrate 1.
  • FIG. 13 is a cross-sectional view schematically showing an example of the configuration of the bonding substrate 1 and the seed layer 31.
  • the seed layer 31 contains, for example, at least one of magnesium (Mg), cobalt (Co), nickel (Ni), copper (Cu) and silver (Au).
  • the seed layer 31 is formed on the bonding surface 1a of the bonding substrate 1 by various film forming methods such as a vapor deposition method or a sputtering method.
  • the execution timing of step S34 is not limited to this. Step S34 may be performed before step S35 described later, and may be performed before step S31, for example.
  • step S35 the bonding substrate 1 and the semiconductor layer 2 are superposed. Specifically, the laminated structure 100b is placed on the bonding substrate 1 so that the low melting point layer 30 is in contact with the seed layer 31.
  • FIG. 14 is a cross-sectional view schematically showing an example of a configuration of the semiconductor device 100A in the middle of manufacturing, and shows a state in which the laminated structure 100b is placed on the bonding substrate 1.
  • step S36 the low melting point layer 30 and the seed layer 31 are reacted to form a bonding layer 3, and the semiconductor layer 2 and the bonding substrate 1 are bonded by the bonding layer 3.
  • a heater such as a hot plate is used to heat the laminated structure 100b, the seed layer 31, and the bonded substrate 1.
  • the metal of the low melting point layer 30 diffuses into the seed layer 31 to form an alloy as the bonding layer 3.
  • the melting point of this alloy is higher than the melting point of gallium.
  • the processing time may be appropriately set according to the thickness of the bonding layer 3.
  • the reaction is carried out with a thickness of about 0.8 ⁇ m when the temperature is raised to 200 ° C. and the treatment time is 30 minutes. Progressed, and the bonding layer 3 was formed.
  • the joining layer 3 is formed by using the low melting point layer 30 in the joining step (step S36). Therefore, as in the first embodiment, the removal step of the low melting point layer 30 and the flattening treatment for the joint surface 2b can be eliminated. Further, since the constituent elements of the semiconductor layer 2 are used for a part of the bonding layer 3, the material cost can be reduced as compared with the case of using an alloy made of a material completely different from that of the semiconductor layer 2. That is, productivity can be improved.
  • the bonding layer 3 can be bonded to the semiconductor layer 2 with high bonding strength.
  • the characteristics of the alloy can be adjusted by the type and ratio of its constituent elements, it is easy to design the characteristics of the bonding layer 3.
  • the seed layer 31 may be porous.
  • the low melting point layer 30 for example, gallium
  • the heat treatment in the joining step (step S36) permeates the inside of the seed layer 31.
  • FIG. 15 is a cross-sectional view schematically showing an example of a state in which a part of the liquid low melting point layer 30 is contained inside the seed layer 31. Since the liquid low melting point layer 30 permeates the inside of the seed layer 31, the liquid low melting point layer 30 diffuses from the inside of the seed layer 31 and alloys to form the bonding layer 3.
  • the bonding layer 3 contains an alloy of a metal (for example, copper) constituting the seed layer 31 and a metal (for example, gallium) which is a constituent element of the semiconductor layer 2. Further, the pores of the porous metal (copper) may contain a metal (gallium) which is a constituent element of the semiconductor layer 2.
  • step S36 a part of the liquid low melting point layer 30 permeates the inside of the seed layer 31, and the alloying reaction also occurs inside the seed layer 31.
  • the reaction area can be increased and the reaction time can be shortened. Therefore, the bonding layer 3 can be formed in a shorter processing time.
  • the thickness of the bonding layer 3 can be reduced. Therefore, the distance (thickness) between the bonding substrate 1 and the semiconductor layer 2 can be shortened, and the thermal conductivity from the semiconductor layer 2 to the bonding substrate 1 can be enhanced.
  • ⁇ Material of seed layer> although metal is used as the seed layer 31, it is not always limited to this. In short, it suffices if the bonding layer 3 having a higher melting point than the low melting point layer 30 can be formed by reacting with the low melting point layer 30.
  • a material capable of reacting with the low melting point layer 30 to form a compound as the bonding layer 3 may be adopted as the material of the seed layer 31.
  • FIG. 16 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device 100B according to the third embodiment. Similar to the semiconductor device 100, the semiconductor device 100B includes a bonding substrate 1, a semiconductor layer 2, and a bonding layer 3. Although not shown in FIG. 16, the semiconductor device 100B may further include a lead-out electrode 5 and an electrode 6 as in the first embodiment. As illustrated in FIG. 16, in the third embodiment, the bonding surface 1a of the bonding substrate 1 has irregularities. The unevenness is arranged two-dimensionally in a plan view. For example, a plurality of line-shaped or dot-shaped protrusions or recesses may be arranged two-dimensionally. The bonding layer 3 fills the unevenness of the bonding surface 1a of the bonding substrate 1 and adheres to the bonding layer 3.
  • the bonding area between the bonding layer 3 and the bonding surface 1a of the bonding substrate 1 can be increased, and the bonding strength between the bonding substrate 1 and the bonding layer 3 can be improved.
  • the height of the unevenness of the bonding surface 1a of the bonding substrate 1 is, for example, 1 um or more and 500 um or less.
  • the height of the unevenness is less than the lower limit of the above range, the effect of increasing the surface area due to the uneven shape cannot be obtained.
  • the uneven height exceeds the upper limit of the above range, it becomes difficult for the joint layer 3 to fill the unevenness, which makes it difficult to form a joint.
  • the period of the unevenness of the joint surface 1a is less than 10 times the maximum height of the unevenness of the joint surface 1a. When the period of the unevenness is larger than the upper limit of the above range, the effect of increasing the surface area due to the uneven shape cannot be obtained.
  • FIG. 17 is a flowchart showing an example of a manufacturing method of the semiconductor device 100B according to the third embodiment.
  • Steps S41 to S43 are the same as steps S1 to S3, respectively.
  • the laminated structure 100b (see FIG. 5) is produced as in the first embodiment.
  • the boundary surface that is, the bonding surface 2b
  • the boundary surface that is, the bonding surface 2b
  • this unevenness has a shape characteristic of laser irradiation, it is a laser irradiation mark.
  • step S44 unevenness is formed on the bonding surface 1a of the bonding substrate 1.
  • unevenness is formed on the bonding surface 1a of the bonding substrate 1.
  • a resist process such as photolithography and nanoimprint
  • an etching process such as a wet etching method and a reactive ion etching method
  • unevenness is formed at an arbitrary portion of the joint surface 1a.
  • unevenness may be formed on the joint surface 1a of the joint substrate 1 by machining or the like.
  • step S45 the bonding substrate 1 and the semiconductor layer 2 are overlapped. Specifically, the laminated structure 100b is placed on the bonding surface 1a of the bonding substrate 1 so that the low melting point layer 30 is in contact with the bonding surface 1a.
  • FIG. 18 is a cross-sectional view showing an example of a configuration in the middle of manufacturing the semiconductor device 100B, in which the laminated structure 100b is placed on the bonding surface 1a of the bonding substrate 1.
  • step S46 the low melting point layer 30 is reacted to form the bonding layer 3.
  • the laminated structure 100b and the bonded substrate 1 are heated by using a heater such as a hot plate in an atmosphere of a gas such as oxygen gas or chlorine gas that can react with the low melting point layer 30.
  • a gas such as oxygen gas or chlorine gas that can react with the low melting point layer 30.
  • the low melting point layer 30 is liquefied to fill the unevenness of the bonding surface 2b of the semiconductor layer 2 and the unevenness of the bonding surface 1a of the bonding substrate 1, and react with a gas such as oxygen gas or chlorine gas to form the bonding layer 3.
  • a gas such as oxygen gas or chlorine gas
  • the joining layer 3 is formed by using the low melting point layer 30 in the joining step (step S46). Therefore, the step of removing the low melting point layer 30 and the flattening treatment of the joint surface 2b of the semiconductor layer 2 can be eliminated. Further, since the areas of the bonding surface 2b and the bonding surface 1a having irregularities are larger than those of the flat surface, the bonding layer 3 can be bonded to each of the semiconductor layer 2 and the bonding substrate 1 with high bonding strength.
  • the uneven structure of the bonding substrate 1 does not have to be the periodic structure illustrated in FIG. 16, and may have any shape.
  • the protrusions or recesses may be dispersed and formed at random positions in a plan view.
  • the shape of the unevenness may be appropriately set.
  • the convex or concave portion may have a dot-like shape, or may have a line-like shape.
  • the joint surface 1a may have an uneven shape due to a plurality of gently inclined structures. In short, if unevenness is formed on the bonding surface 1a, the area of the bonding surface 1a of the bonding substrate 1 can be made larger than that of the flat surface regardless of the shape, and the bonding strength can be improved.
  • FIG. 19 is a cross-sectional view schematically showing an example of a configuration in the middle of manufacturing a semiconductor device, and is a diagram schematically showing an example of the configuration of the semiconductor device 100B immediately before the via hole 51 is formed.
  • the region where the via hole 51 is formed in the bonding surface 1a of the bonding substrate 1 corresponds to a recess. Therefore, the thickness of the bonding substrate 1 becomes thin in the region where the via hole 51 is formed.
  • the etching amount of the bonding substrate 1 when forming the via hole 51 can be reduced.
  • the thickness of the bonding layer 3 becomes thicker in the region where the via hole 51 is formed. Therefore, for example, when the etching rate of the bonding substrate 1 is lower than the etching rate of the bonding layer 3, the uneven shape of the bonding surface 1a may be determined so that the bonding substrate 1 becomes thin in the region where the via hole 51 is formed.
  • the etching amount of the bonding substrate 1 having a low etching rate can be reduced, so that the manufacturing throughput of the semiconductor device 100B can be improved.
  • FIG. 20 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device 100C.
  • the semiconductor device 100C has the same configuration as the semiconductor device 100B except for the uneven shape of the bonding surface 1a of the bonding substrate 1.
  • the bonding surface 1a of the bonding substrate 1 has a convex portion.
  • the electrode 4a functions as a source electrode and the electrode 4c functions as a drain electrode, a current flows in the semiconductor layer 2 between the electrodes 4a and 4c. Therefore, the portion of the semiconductor layer 2 between the electrodes 4a and 4c functions as a heat generating source.
  • the bonding surface 1a of the bonding substrate 1 has a convex portion immediately below the heat generating portion. As a result, the distance between the heat generating portion and the bonding substrate 1 can be shortened, and the heat from the heat generating portion can be easily transferred to the bonding substrate 1.
  • the convex portion is formed only directly under the heat generating portion, the unevenness may be formed in other regions as well.
  • the width of the convex portion immediately below the heat generating portion (the width in the arrangement direction in which the electrodes 4a and 4c are arranged) may be wider than the width of the convex portion in the other region.
  • 1 1st substrate (bonding substrate), 10 2nd substrate, 1a, 2a bonding surface, 2 semiconductor layer, 3 bonding layer, 31 seed layer, 4 electrodes, 51 via holes.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Led Devices (AREA)
  • Semiconductor Lasers (AREA)
PCT/JP2020/019180 2020-05-14 2020-05-14 半導体装置および半導体装置の製造方法 Ceased WO2021229734A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US17/915,104 US12512648B2 (en) 2020-05-14 2020-05-14 Semiconductor device and method of manufacturing semiconductor device
JP2022522420A JP7325624B2 (ja) 2020-05-14 2020-05-14 半導体装置および半導体装置の製造方法
GB2215350.6A GB2609786B (en) 2020-05-14 2020-05-14 Semiconductor device and method of manufacturing semiconductor device
PCT/JP2020/019180 WO2021229734A1 (ja) 2020-05-14 2020-05-14 半導体装置および半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/019180 WO2021229734A1 (ja) 2020-05-14 2020-05-14 半導体装置および半導体装置の製造方法

Publications (1)

Publication Number Publication Date
WO2021229734A1 true WO2021229734A1 (ja) 2021-11-18

Family

ID=78525514

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/019180 Ceased WO2021229734A1 (ja) 2020-05-14 2020-05-14 半導体装置および半導体装置の製造方法

Country Status (4)

Country Link
US (1) US12512648B2 (https=)
JP (1) JP7325624B2 (https=)
GB (1) GB2609786B (https=)
WO (1) WO2021229734A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023223868A1 (ja) * 2022-05-19 2023-11-23 浜松ホトニクス株式会社 接合方法、半導体デバイスの製造方法及び半導体デバイス
WO2025017863A1 (ja) * 2023-07-19 2025-01-23 三菱電機株式会社 半導体装置および半導体装置の製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2025084380A (ja) * 2023-11-22 2025-06-03 住友金属鉱山株式会社 接合半導体基板および接合半導体基板の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0963912A (ja) * 1995-08-18 1997-03-07 Hoya Corp 貼り合わせ基板製造方法
JP2012099710A (ja) * 2010-11-04 2012-05-24 Ushio Inc 基板と結晶層の接着方法および接着されたワーク
JP2017139322A (ja) * 2016-02-03 2017-08-10 旭硝子株式会社 デバイス基板の製造方法、及び積層体

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7799675B2 (en) * 2003-06-24 2010-09-21 Sang-Yun Lee Bonded semiconductor structure and method of fabricating the same
JP2008022866A (ja) 2004-10-28 2008-02-07 Stream Co Ltd 彫刻真珠及びその加飾方法
JP4650224B2 (ja) 2004-11-19 2011-03-16 日亜化学工業株式会社 電界効果トランジスタ
US20080026248A1 (en) * 2006-01-27 2008-01-31 Shekar Balagopal Environmental and Thermal Barrier Coating to Provide Protection in Various Environments
JP6245791B2 (ja) * 2012-03-27 2017-12-13 日亜化学工業株式会社 縦型窒化物半導体素子およびその製造方法
KR20140012445A (ko) 2012-07-20 2014-02-03 삼성전자주식회사 질화물계 반도체 소자 및 이의 제조방법
FR3040108B1 (fr) * 2015-08-12 2017-08-11 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse
JP6431013B2 (ja) * 2016-09-21 2018-11-28 シャープ株式会社 窒化アルミニウム系半導体深紫外発光素子
US10074567B2 (en) * 2016-10-21 2018-09-11 QROMIS, Inc. Method and system for vertical integration of elemental and compound semiconductors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0963912A (ja) * 1995-08-18 1997-03-07 Hoya Corp 貼り合わせ基板製造方法
JP2012099710A (ja) * 2010-11-04 2012-05-24 Ushio Inc 基板と結晶層の接着方法および接着されたワーク
JP2017139322A (ja) * 2016-02-03 2017-08-10 旭硝子株式会社 デバイス基板の製造方法、及び積層体

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023223868A1 (ja) * 2022-05-19 2023-11-23 浜松ホトニクス株式会社 接合方法、半導体デバイスの製造方法及び半導体デバイス
WO2025017863A1 (ja) * 2023-07-19 2025-01-23 三菱電機株式会社 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
GB202215350D0 (en) 2022-11-30
GB2609786A (en) 2023-02-15
JPWO2021229734A1 (https=) 2021-11-18
US12512648B2 (en) 2025-12-30
US20230155351A1 (en) 2023-05-18
JP7325624B2 (ja) 2023-08-14
GB2609786B (en) 2025-05-14

Similar Documents

Publication Publication Date Title
JP5604855B2 (ja) 半導体装置及びその製造方法
JP5985337B2 (ja) 半導体装置およびその製造方法
JP7325624B2 (ja) 半導体装置および半導体装置の製造方法
US8294183B2 (en) Semiconductor substrate, method of fabricating the same, semiconductor device, and method of fabricating the same
JP7070848B2 (ja) 半導体装置の製造方法
JP5423390B2 (ja) Ｉｉｉ族窒化物系化合物半導体素子及びその製造方法
WO2011021710A1 (ja) 半導体素子およびその製造方法
JP2013187546A (ja) 高電子移動度トランジスタ及びその製造方法
TW201145585A (en) Light-emitting device and method of manufacturing the same
US11515208B2 (en) Semiconductor device and semiconductor apparatus
JP2011066398A (ja) 半導体素子およびその製造方法
CN104488086A (zh) 含有焊料的半导体器件、安装的含有焊料的半导体器件、含有焊料的半导体器件的制造方法和安装方法
CN104798185B (zh) Au系钎料模片接合半导体装置及其制造方法
JP4973046B2 (ja) 半導体装置の製造方法
JP5564799B2 (ja) 窒化ガリウム系半導体電子デバイスを作製する方法
JP5401802B2 (ja) 窒化物半導体装置のオーム性電極
CN102668040B (zh) 半导体装置以及半导体装置的制造方法
TWI284419B (en) Schottky barrier diode and process
JP2022144564A (ja) 半導体装置の製造方法
TW201314742A (zh) 半導體裝置及其製造方法
JP5022396B2 (ja) 半導体複合装置の製造方法
JPH0245976A (ja) 炭化ケイ素の電極形成方法
JP2026010268A (ja) 半導体装置、半導体装置の製造方法及び電子装置
JPS5950090B2 (ja) 半導体装置の製造方法
JP2026007387A (ja) 窒化物半導体デバイス及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20935463

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022522420

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 202215350

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20200514

WWE Wipo information: entry into national phase

Ref document number: 2215350.6

Country of ref document: GB

NENP Non-entry into the national phase

Ref country code: DE

WWP Wipo information: published in national office

Ref document number: 2215350.6

Country of ref document: GB

122 Ep: pct application non-entry in european phase

Ref document number: 20935463

Country of ref document: EP

Kind code of ref document: A1

WWG Wipo information: grant in national office

Ref document number: 2215350.6

Country of ref document: GB

WWG Wipo information: grant in national office

Ref document number: 17915104

Country of ref document: US