CN104488086A - 含有焊料的半导体器件、安装的含有焊料的半导体器件、含有焊料的半导体器件的制造方法和安装方法 - Google Patents

含有焊料的半导体器件、安装的含有焊料的半导体器件、含有焊料的半导体器件的制造方法和安装方法 Download PDF

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CN104488086A
CN104488086A CN201480001915.2A CN201480001915A CN104488086A CN 104488086 A CN104488086 A CN 104488086A CN 201480001915 A CN201480001915 A CN 201480001915A CN 104488086 A CN104488086 A CN 104488086A
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Prior art keywords
semiconductor device
solder
containing solder
layer
group iii
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CN201480001915.2A
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熊野哲弥
吉本晋
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Publication of CN104488086A publication Critical patent/CN104488086A/zh
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Abstract

一种含有焊料的半导体器件(1)包括半导体器件(1D)。该半导体器件(1D)包括衬底(10)，布置在该衬底(10)上的至少一层III族氮化物半导体层(20)，布置在该III族氮化物半导体层(20)上的肖特基电极(40)和布置在该肖特基电极(40)上的焊垫电极(50)。该焊垫电极(50)具有包括至少Pt层的多层结构。该含有焊料的半导体器件(1)还包括具有200至230℃的熔点且布置在半导体器件(1D)的焊垫电极(50)上的焊料(60)。因此，能够安装包括肖特基栅极、布置在肖特基栅极上的焊垫电极和布置在焊垫电极上的焊料的含有焊料的半导体器件，以提供不使半导体器件的性能劣化的安装的含有焊料的半导体器件。

Description

含有焊料的半导体器件、安装的含有焊料的半导体器件、含有焊料的半导体器件的制造方法和安装方法
技术领域
本发明涉及含有焊料的半导体器件、安装的含有焊料的半导体器件及含有焊料的半导体器件的制造方法和安装方法。
背景技术
近年来，由于III族氮化物半导体的优良的半导体性能，因此已经提出了包括衬底、III族氮化物半导体层和肖特基电极(与半导体层肖特基接触的电极，在下文中保持相同的意思)的半导体器件，诸如肖特基势垒二极管(在下文中简称为SBD)和高电子迁移率晶体管(在下文中简称为HEMT)。
例如，日本专利特开No.2008-177537(PTD 1)公开了一种SBD，其中将形成在III族氮化物半导体层上的肖特基金属层用介于其间的金属接合层接合到导电衬底。在这种SBD中，利用Au-Sn焊料通过Au-Sn共晶结合工艺接合金属接合层和导电衬底。
引用列表
专利文献
PTD 1：日本专利特开No.2008-177537
发明内容
技术问题
在日本专利特开No.2008-177537(PTD 1)中公开的SBD的安装通过将SBD的导电衬底的一侧或者与该侧相对的形成III族氮化物半导体层的肖特基金属层的另一侧接合到封装来执行。在SBD的该安装方法中，存在III族氮化物半导体层中产生的热难以散发的缺点。
为了应对这种缺点，需要开发具有使得能够将形成III族氮化物半导体层的肖特基金属层的一侧接合到封装的结构这样的SBD，换句话说，能够经由接合肖特基电极的一侧执行该安装。
为了能够实现经由接合肖特基电极的一侧的安装，将焊垫电极形成在已形成在III族氮化物半导体层上的肖特基电极上，且需要使用Au-Sn焊料将焊垫电极接合到封装。
然而，如果通过使用Au-Sn焊料在不小于其共熔温度(约280℃)的温度下、优选在用于稳定用途的约340℃的温度下接合形成在SBD的肖特基电极上的焊垫电极，将SBD安装到封装，则会产生与未安装的SBD相比安装的SBD的耐受电压显著减小的问题。
在研究上述问题的原因之后，发现为了防止Sn的扩散，将Pt包括在由焊料接合的焊垫电极中，因此如果将约280至340℃的高温施加到具有形成在肖特基电极上的焊垫电极的SBD，则由于焊垫电极中的Pt是硬的，所以应力将被集中到焊垫电极和与其接合的肖特基电极的电极边缘。另外，由于肖特基电极的电极边缘是电场集中的地方，因此集中的应力和集中的电场将会使漏电流增加。因此，显著减小了SBD的耐受电压。
基于以上发现和在进一步研究之后，本发明的发明人发现，在包括肖特基电极和布置在肖特基电极上的且包含Pt的焊垫电极的SBD的安装中，优选通过使用具有200至230℃熔点的焊料执行安装。
如上所述，本发明的一个目的在于提供含有焊料的半导体器件、安装的含有焊料的半导体器件、含有焊料的半导体器件的制造方法和安装方法，含有焊料的半导体器件包括布置在III族氮化物半导体层上的肖特基电极、布置在肖特基电极上的焊垫电极和布置在焊垫电极上的焊料，且在不使半导体器件的性能劣化的情况下能够经由焊料安装。
问题的解决方案
根据本发明的一个方面，提供一种包括半导体器件的含有焊料的半导体器件。该半导体器件提供有衬底、布置在该衬底上的至少一层III族氮化物半导体层、布置在该III族氮化物半导体层上的肖特基电极和布置在该肖特基电极上的焊垫电极。该焊垫电极具有包括至少Pt层的多层结构。该含有焊料的半导体器件还包括具有200至230℃熔点且布置在该半导体器件的焊垫电极上的焊料。
可接受的是，根据本发明一方面的含有焊料的半导体器件还包括具有开口且布置在III族氮化物半导体层上的介电层，且肖特基电极布置在位于介电层的开口内的III族氮化物半导体层的部分上。可接受的是，衬底是III族氮化物衬底。可接受的是，衬底是包括底层衬底和直接或间接地接合到底层衬底的III族氮化物膜的复合衬底。可接受的是，含有焊料的半导体器件包括从复合衬底移除底层衬底之后留下的III族氮化物膜作为衬底。可接受的是，焊料包括从由Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-In-Bi、Sn-Ag-Cu-Bi和Sn-Ag-Bi-In组成的组中选择的至少一种合金。可接受的是，Pt层具有30nm或更大的厚度。可接受的是，介电层包括从由Si3N4和SiO2组成的组中选择的至少一种硅化合物。
根据本发明的另一方面，提供一种安装的含有焊料的半导体器件，其中通过将含有焊料的半导体器件的焊料接合到封装将根据上述一个方面的含有焊料的半导体器件安装到封装。
根据本发明的另一方面，提供一种制造含有焊料的半导体器件的方法。该制造方法包括形成半导体器件的步骤。该形成半导体器件的步骤包括在衬底上形成至少一层III族氮化物半导体层的子步骤，在III族氮化物半导体层上形成肖特基电极的子步骤，和在肖特基电极上形成焊垫电极的子步骤。该焊垫电极具有包括至少Pt层的多层结构。该制造方法还包括在半导体器件的焊垫电极上布置具有200至230℃熔点的焊料的步骤。
在根据本发明一方面的制造含有焊料的半导体器件的方法中，可接受的是，形成半导体器件的步骤还包括在形成III族氮化物半导体层的子步骤之后且在形成肖特基电极的子步骤之前执行的，在III族氮化物半导体层上形成具有开口的介电层的子步骤，并且在形成肖特基电极的子步骤中，将肖特基电极形成在位于介电层的开口内的III族氮化物半导体层的部分上。
根据本发明的另一方面，提供一种安装含有焊料的半导体器件的方法。该安装方法包括如下步骤：制备根据本发明一方面的含有焊料的半导体器件；和将含有焊料的半导体器件的焊料在200至230℃的温度下接合到封装以安装该含有焊料的半导体器件。
可接受的是，根据本发明一方面的安装含有焊料的半导体器件的方法包括如下步骤：制备根据本发明一方面的含有焊料的半导体器件；将含有焊料的半导体器件的焊料在200至230℃的温度下接合到封装以安装该含有焊料的半导体器件；和从含有焊料的半导体器件的复合衬底移除底层衬底。
发明的有利效果
根据本发明，能够提供含有焊料的半导体器件、安装的含有焊料的半导体器件、含有焊料的半导体器件的制造方法和安装方法，该含有焊料的半导体器件包括布置在III族氮化物半导体层上的肖特基电极、布置在肖特基电极上的焊垫电极和布置在焊垫电极上的焊料，且在不使半导体器件的性能劣化的情况下能够经由焊料安装。
附图说明
图1是示意性描述根据本发明的含有焊料的半导体器件的一个示例的截图面；
图2是示意性描述根据本发明的含有焊料的半导体器件的另一个示例的截图面；
图3是示意性描述根据本发明的含有焊料的半导体器件的又一个示例的截图面；
图4是示意性描述根据本发明的安装的含有焊料的半导体器件的一个示例的截图面；
图5是示意性描述根据本发明的安装的含有焊料的半导体器件的另一个示例的截图面；
图6是示意性描述根据本发明的安装的含有焊料的半导体器件的又一个示例的截图面；
图7提供了示意性描述根据本发明的含有焊料的半导体器件的制造方法和安装方法的一个示例的截图面；
图8提供了示意性描述根据本发明的含有焊料的半导体器件的制造方法和安装方法的另一个示例的截图面；和
图9是描述根据本发明的未安装的含有焊料的半导体器件的耐受电压和安装的含有焊料的半导体器件的耐受电压之间的关系的图。
具体实施方式
[第一实施例：含有焊料的半导体器件]
参考图1至图3，根据本发明的某些实施例的含有焊料的半导体器件1、2A和3分别包括半导体器件1D、2AD和3D。半导体器件1、2A和3每个都包括衬底10、布置在衬底10上的至少一层III族氮化物半导体层20、布置在III族氮化物半导体层20上的肖特基电极40和布置在肖特基电极40上的焊垫电极50。焊垫电极50具有包括至少Pt层的多层结构。半导体器件1D、2AD和3D每个还包括具有200至230℃熔点的且布置在半导体器件的焊垫电极50上的焊料60。
在本实施例的含有焊料的半导体器件1、2A和3的每个中，由于焊垫电极50具有包括Pt层的多层结构且布置在肖特基电极40上，具有200至230℃熔点的焊料60布置在每个半导体器件1D、2AD和3D的焊垫电极50上，所以能使含有焊料的半导体器件在200至230℃的温度下接合到封装，从而抑制了由接合在焊垫电极50中包括的Pt层产生的并在肖特基电极40的电极边缘集中的应力引起的肖特基电极40的劣化。因此，能够抑制每个含有焊料的半导体器件1、2A和3的半导体器件性能的劣化。
从减轻集中于肖特基电极40的电极边缘的电场考虑，优选本实施例的每个含有焊料的半导体器件1、2A和3还包括提供有开口30w或者80w的且布置在III族氮化物半导体层20上的介电层30或者80，并且优选使肖特基电极40布置在位于介电层30或者80的开口30w或者80w内的III族氮化物半导体层20的部分上。
另外，从防止电流泄漏到芯片端面考虑，还优选使肖特基电极40布置在位于介电层30的开口30w内的III族氮化物半导体层20的部分上和位于开口30w附近(例如，离开口边缘100μm距离内)的介电层30的部分上。
如图2所示，含有焊料的半导体器件2A包括作为衬底10的包括底层衬底11和直接或者间接接合到底层衬底11的III族氮化物膜13的复合衬底。如图8所示，在通过接合焊料60将包括这种复合衬底的含有焊料的半导体器件2A安装到封装之后，从复合衬底移除底层衬底11，留下作为衬底的III族氮化物膜13。因此，提供包括III族氮化物膜13作为衬底的含有焊料的半导体器件2B。
(衬底)
参考图1至图3，没有特别限制衬底10，只要它能支撑布置在它上面的至少一层III族氮化物半导体层20，因此，可以是具有单层结构的单衬底或者具有多层结构的复合衬底。
参考图1和图3，从至少一层III族氮化物半导体层20能够经由生长布置在其上来考虑，优选衬底10是III族氮化物衬底。
参考图2，从通过减少昂贵的III族氮化物的量节省衬底的总成本考虑，优选衬底10是包括底层衬底11和直接或者间接地接合到底层衬底11的III族氮化物膜13的复合衬底。虽然底层衬底11没有特别限制只要它能直接或者间接地接合到III族氮化物膜13，但从节省衬底的总成本考虑，优选底层衬底11是Si衬底、SiC衬底、蓝宝石衬底、复合氧化物衬底(例如，Al2O3-SiO2基衬底，诸如莫来石(3Al2O3·2SiO2-2Al2O3·SiO)衬底，ZrO2-Y2O3-Al2O3-SiO2基衬底，诸如YSZ(使氧化钇稳定的氧化锆)-莫来石衬底等)，或者多晶衬底。另外，由于通过调整其化学成分可控制其热膨胀系数的原因，优选底层衬底11是复合氧化物衬底。
从改善底层衬底11和III族氮化物膜13之间的结合性考虑，在如上所述的复合衬底中，优选利用插入其间的结合膜12将底层衬底11和III族氮化物膜13彼此间接地接合。虽然接合膜12没有特别限制，但从改善底层衬底11和Ⅲ族氮化物膜13之间的结合性考虑，优选接合膜12是SiO2膜、Si3N4膜等。
(III族氮化物半导体层)
参考图1至图3，III族氮化物半导体层20没有特别限制，只要它是能使每个含有焊料的半导体器件1、2A或者3表现出半导体器件功能的至少一层III族氮化物半导体层20且根据含有焊料的半导体器件的类型其成分可以改变。参考图1和2，在每个含有焊料的半导体器件1或者2A是含有焊料的SBD(肖特基势垒二极管)的情况下，III族氮化物半导体层20可以包括例如n+-GaN层21和n--GaN层22。参考图3，在含有焊料的半导体器件3是含有焊料的HEMT(高电子迁移率晶体管)的情况下，III族氮化物半导体层20可以包括GaN层26、n-Al1-xGaxN层27(0<x<1)和n-GaN层28。
(具有开口的介电层)
参考图1至图3，虽然具有开口30w或者80w的介电层30或者80没有特别限制，只要它能改善每个含有焊料的半导体器件1、2A或者3的半导体器件功能，但从增强可靠性考虑，优选该介电层包括从由Si3N4和SiO2组成的组中选择的至少一种硅化合物，并优选该介电层是Si3N4层和SiO2层中的至少一层。
(肖特基电极)
参考图1至图3，虽然肖特基电极40没有特别限制，只要它是与III族氮化物半导体层20肖特基接触的电极，但从肖特基电极和III族氮化物半导体层之间的功函数差考虑，优选肖特基电极10例如是Ni/Au电极(具有从III族氮化物半导体层20一侧顺序布置的Ni层和Au层的多层结构的电极)或者Ni/Pd/Pt/Au电极(具有从III族氮化物半导体层20一侧顺序布置的Ni层、Pd层、Pt层和Au层的多层结构的电极)。
(焊垫电极)
参考图1至图3，虽然焊垫电极50没有特别限制，只要它是具有包括Pt层的多层结构且与肖特基电极40和焊料60有高结合性的电极，但从使用对焊料60具有良好润湿性的Au考虑，优选焊垫电极50例如是Ti/Pt/Au电极(具有从肖特基电极40一侧顺序布置的Ti层、Pt层和Au层的多层结构的电极)或者Ni/Pt/Au电极(具有从肖特基电极40一侧顺序布置的Ni层、Pt层和Au层的多层结构的电极)。
从有效地防止焊料60中包含的Sn的扩散考虑，焊垫电极50中提供的Pt层的厚度优选为30nm或更大，且更优选为50nm或更大。
(焊料)
参考图1至6，虽然焊料60没有特别限制，只要它具有200至230℃的熔点并且与焊垫电极50和封装100有高结合性，但从减小施加给半导体器件的应力考虑，优选焊料60包括从由Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-In-Bi、Sn-Ag-Cu-Bi和Sn-Ag-Bi-In构成的组中选择的至少一种合金。具体地，作为适当焊料的示例，可以给出Sn-Ag焊料、Sn-Cu焊料、Sn-Ag-Cu焊料、Sn-In-Bi焊料、Sn-Ag-Cu-Bi焊料、Sn-Ag-Bi-In焊料等。
(含有焊料的SBD)
参考图1，含有焊料的半导体器件1是含有焊料的SBD的示例，且包括衬底10、由在衬底10的一个主表面上顺序布置的n+-GaN层21和n--GaN层22组成的III族氮化物半导体层20、提供有开口30w且布置在III族氮化物半导体层20上的介电层30、布置在位于介电层30的开口30w内的III族氮化物半导体层20的部分上和位于开口30w附近的介电层30的部分上的肖特基电极40、布置在肖特基电极40上的焊垫电极50、布置在焊垫电极50上的焊料60和布置在衬底10的另一主表面上的衬底电极70。
参考图2，含有焊料的半导体器件2A是含有焊料的SBD的另一个示例，并且包括：衬底10，其为包括底层衬底11和直接或者间接接合到底层衬底11的III族氮化物膜13的复合衬底；由在衬底10的一个主表面上顺序布置的n+-GaN层21和n--GaN层22组成的III族氮化物半导体层20；提供有开口30w且布置在III族氮化物半导体层20上的介电层30；布置在位于介电层30的开口30w内的III族氮化物半导体层20的部分上和位于开口30w附近的介电层30的部分上的肖特基电极40；布置在肖特基电极40上的焊垫电极50以及布置在焊垫电极50上的焊料60。
参考图8，在通过接合焊料60将以上描述的含有焊料的半导体器件2A安装到封装100之后，从充当衬底10的复合衬底移除底层衬底11，留下作为衬底的III族氮化物膜13。因此，提供包括III族氮化物膜13作为衬底的含有焊料的半导体器件2B。
(含有焊料的HEMT)
参考图3，含有焊料的半导体器件3是含有焊料的HEMT的一个示例，且包括：衬底10；由在衬底10的一个主表面上顺序布置的GaN层26、n-Al1-xGaxN层27(0<x<1)和n-GaN层28组成的III族氮化物半导体层20；提供有开口80w且布置在III族氮化物半导体层20上的介电层80；肖特基电极40，其为布置在位于介电层80的开口80w内的III族氮化物半导体层20的部分上的栅电极；布置在肖特基电极40上的焊垫电极50以及布置在焊垫电极50上的焊料60。含有焊料的半导体器件3还包括：源电极42和漏电极44，它们被相互隔开并且分别提供在III族氮化物半导体层20的n-Al1-xGaxN层27上，n-Al1-xGaxN层27是通过移除位于III族氮化物半导体层20的n-GaN层28的部分上的介电层80的部分以及随后的n-GaN层28的部分而暴露的；布置在源电极42和漏电极44每个上的焊垫电极50；和布置在每个焊垫电极50上的焊料60。
[第二实施例：安装的含有焊料的半导体器件]
参考图4至图6，通过经由每个含有焊料的半导体器件1、2B和3中的接合焊料60将根据第一实施例的含有焊料的半导体器件1、2B和3的每个安装到封装100，得到了根据本发明另一实施例的安装的含有焊料的半导体器件6、7B和8的每个。在根据本实施例的安装的含有焊料的半导体器件6或者7B中，含有焊料的半导体器件1或者2B的衬底电极70经由布线90连接至封装100。
在本实施例的安装的含有焊料的半导体器件6、7B和8的每个中，由于含有焊料的半导体器件1、2B和3的每个在200至230℃的温度接合到封装100，所以抑制了由接合在焊垫电极50中包括的Pt层产生的并且集中在肖特基电极40的电极边缘上的应力引起的肖特基电极40的劣化，因此抑制了含有焊料的半导体器件1、2B或者3的半导体器件性能的劣化，结果，含有焊料的半导体器件1、2B或者3具有高的半导体器件性能。
(封装)
封装100是安装半导体器件的衬底。封装100没有特别限制，但优选包括由Cu、CuW等制成的具有高散热性能的导电部分和由环氧树脂、SiO2等制成的绝缘部分。
[第三实施例：制造含有焊料的半导体器件的方法]
参考图7和图8，根据该发明的另一实施例的制造含有焊料的半导体器件1或2A的方法包括形成半导体器件1D或者2AD的步骤。形成半导体器件1D或者2AD的步骤包括在衬底10上形成至少一层III族氮化物半导体层20的子步骤，在III族氮化物半导体层20上形成肖特基电极40的子步骤，和在肖特基电极40上形成焊垫电极50的子步骤。焊垫电极50具有包括至少Pt层的多层结构。根据该发明的另一实施例的制造含有焊料的半导体器件1或2A的方法还包括在半导体器件1D或者2AD的焊垫电极50上布置具有200至230℃熔点的焊料60的步骤。
根据本实施例的制造含有焊料的半导体器件1或2A的方法，在将其安装到封装时含有焊料的半导体器件1或者2A的半导体器件性能劣化被抑制，因此能够有效地制造含有焊料的半导体器件1或者2A，从其能够得到具有高半导体器件性能的安装的含有焊料的半导体器件。
从介电层30减轻集中到肖特基电极40的电极边缘上的电场考虑，优选本实施例的制造含有焊料的半导体器件1或2A的方法还包括在形成III族氮化物半导体层20的子步骤之后且在形成肖特基电极40的子步骤之前执行的，在III族氮化物半导体层20上形成具有开口30w的介电层30的子步骤，并且在形成肖特基电极40的子步骤中，将肖特基电极40形成在位于介电层30的开口30w内的III族氮化物半导体层20的部分上。
另外，从防止电流泄漏到芯片端面考虑，还优选在形成肖特基电极40的步骤中，将肖特基电极40形成在位于介电层30的开口30w内的III族氮化物半导体层20的部分上和位于开口30w附近(例如，离开口边缘100μm的距离内)的介电层30的部分上。
(形成半导体器件的步骤)
参考图7和图8，根据本实施例的制造含有焊料的半导体器件1或2A的方法包括形成半导体器件1D、2AD或者3D的步骤。形成半导体器件1D、2AD或者3D的步骤包括在衬底10上形成至少一层III族氮化物半导体层20的子步骤(参见图7(A)和8(A))，在III族氮化物半导体层20上形成肖特基电极40的子步骤(参见图7(C)和8(C))，和在肖特基电极40上形成焊垫电极50的子步骤(参见图7(D)和8(D))。优选地，形成半导体器件1D、2AD或者3D的步骤还包括在形成III族氮化物半导体层20的子步骤(参见图7(A)和8(A))之后且在形成肖特基电极40的子步骤(参见图7(C)和8(C))之前执行的，在III族氮化物半导体层20上形成具有开口30w的介电层30的子步骤(参见图7(B)和8(B))。
参考图7(A)和图8(A)，虽然在衬底10的一个主表面上形成至少一层III族氮化物半导体层20的子步骤中没有特别限制形成III族氮化物半导体层20的方法，但从生长高晶体质量的III族氮化物半导体层20考虑，作为气相生长法，优选HVPE(氢化物气相外延)法、MOCVD(金属有机化学气相沉积)法、MBE(分子束外延)法、升华法等，并且作为液相生长法，优选高压液氮法、助熔剂法等。
从生长高晶体质量的III族氮化物半导体层20考虑，优选衬底10是III族氮化物衬底。此外，从通过减小昂贵的III族氮化物的量节省衬底的总成本考虑，优选衬底10是包括底层衬底11和直接或者间接地接合到底层衬底11的III族氮化物膜13的复合衬底。
参考图7(B)和图8(B)，虽然在III族氮化物半导体层20上形成具有开口30w的介电层30的子步骤没有特别限制，但从有效形成具有开口30w的介电层30考虑，优选在III族氮化物半导体层20上形成介电层30之后，通过移除介电层30的部分形成开口30w。形成介电层30的方法没有特别限制只要它是适合于介电层30的材料的生长法，例如，优选磁控溅射法、ECR(电子回旋共振)溅射法、EB(电子束)气相沉积法等。在介电层30中形成开口30w的方法没有特别限制只要它适合于介电层30的材料，例如，优选湿蚀刻法等。
参考图7(C)和图8(C)，在III族氮化物半导体层20上，或者在位于介电层30的开口30w内的III族氮化物半导体层20的部分上，或者在位于介电层30的开口30w内的III族氮化物半导体层20的部分上和位于开口30w附近(例如，离开口边缘100μm的距离内)的介电层30的部分上形成肖特基电极40的子步骤中，形成肖特基电极40的方法没有特别限制只要它适合于肖特基电极40的材料，例如，优选EB气相沉积法等。
参考图7(D)和8(D)，在肖特基电极40上形成焊垫电极50的子步骤中，形成焊垫电极50的方法没有特别限制只要它适合于焊垫电极50的材料，例如，优选EB气相沉积法和随后的剥离工艺等。从有效地防止焊料60中包含的Sn的扩散考虑，焊垫电极50具有包括Pt层的多层结构。
另外，参考图7(E)，含有焊料的半导体器件1的制造方法可以包括在形成焊垫电极50的子步骤之后在衬底10的另一主表面上形成衬底电极70的子步骤。形成衬底电极70的方法没有特别限制只要它适合于衬底电极70的材料，例如，优选EB气相沉积法等。因此，能够有效地得到半导体器件1D和2AD。
(布置焊料的步骤)
参考图7(F)和图8(E)，虽然在每个半导体器件1D、2AD和3D的焊垫电极50上布置具有200至230℃熔点的焊料60的步骤中焊料60没有特别限制，但从减小施加到半导体器件的应力考虑，优选焊料60包括从由Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-In-Bi、Sn-Ag-Cu-Bi和Sn-Ag-Bi-In构成的组中选择的至少一种合金。因此，能够有效地得到含有焊料的半导体器件1和2A。
[第四实施例：含有焊料的半导体器件的安装方法]
参见图7和图8，根据本发明另一实施例的含有焊料的半导体器件1或2A的安装方法包括：提供第一实施例的含有焊料的半导体器件1或2A的步骤(参见图7(A)至图7(E)和图8(A)至图8(E))和在200至230℃的温度下将含有焊料的半导体器件1或2A的焊料60接合到封装100以安装含有焊料的半导体器件1、2A或3的步骤(参见图7(G)至图7(H)和图8(F)至图8(H))。
根据本实施例的用于安装含有焊料的半导体器件1或2A的方法，由于在将它安装到封装时的含有焊料的半导体器件1或2A的半导体器件性能的劣化被抑制，所以能够得到具有高半导体器件性能的安装的含有焊料的半导体器件6、7A或7B。
参见图8，从提高半导体器件的散热性能同时降低其成本考虑，优选根据本实施例的用于安装含有焊料的半导体器件2A的方法包括：提供含有焊料的半导体器件2A的步骤(参见图8(A)至图8(E))，将含有焊料的半导体器件2A的焊料60接合到封装100以安装含有焊料的半导体器件2A的步骤(参见图8(F))，以及从用作含有焊料的半导体器件2A的衬底10的复合衬底去除底层衬底11的步骤(参见图8(F)和图8(G))。根据该安装方法，能够将包括III族氮化物膜13作为衬底的含有焊料的半导体器件2B安装到封装100以提供安装的含有焊料的半导体器件7B，其具有高的半导体器件性能和高温操作性能。
(制备含有焊料的半导体器件)
参见图7(A)至图7(F)和图8(A)至图8(E)，由于制备含有焊料的半导体器件1或2A的步骤与根据第三实施例的制造含有焊料的半导体器件1或2A的方法相同，所以将不再重复其描述。
(安装含有焊料的半导体器件)
参见图7(G)和图8(F)，安装含有焊料的半导体器件1或2A的步骤是通过在200至230℃的温度下将含有焊料的半导体器件1或2A的焊料60接合到封装100来执行的。
参见图7(H)，在含有焊料的半导体器件1的情况下，通过布线90将含有焊料的半导体器件1的衬底电极70连接到封装100以提供安装的含有焊料的半导体器件6。
(从含有焊料的半导体器件的复合衬底去除底层衬底)
参见图8(F)和图8(G)，在通过将含有焊料的半导体器件2A接合到封装100所获得的安装的含有焊料的半导体器件7A的情况下，能够包括从用作含有焊料的半导体器件2A的衬底10的复合衬底去除底层衬底11的步骤。如果用作衬底10的复合衬底包括接合膜12，则还能够去除接合膜12。没有特别地限制用于去除底层衬底11和接合膜12的方法，因此可以使用诸如切割、机械加工、研磨或蚀刻的任何方法。该蚀刻可以是其中使用蚀刻剂的湿法蚀刻或者诸如RIE(反应离子蚀刻)的干法蚀刻。
参见图8(G)和图8(H)，在安装含有焊料的半导体器件7A的情况下，如上所述，从用作含有焊料的半导体器件2A的衬底10的复合衬底去除底层衬底11和接合膜12以暴露出III族氮化物膜13，并且通过在暴露出的III族氮化物膜13上形成衬底电极70获得含有焊料的半导体器件2B。用于形成衬底电极70的方法没有特别地限制，只要它适合于衬底电极70的材料，例如，优选EB气相沉积法等。
然后，参见图8(H)，可以通过布线90将含有焊料的半导体器件2B的衬底电极70连接到封装100来获得安装的含有焊料的半导体器件7B。
示例
(示例1)
1.制备含有焊料的半导体器件
参见图7(A)，根据MOCVD(金属有机化学气相沉积)法在GaN衬底的一个主表面上按顺序生长了3μm厚的n+-GaN层21(载流子浓度：2×1018cm-3)和5μm厚的n--GaN层22(载流子浓度：5×1015cm-3)作为III族氮化物半导体层20，其中GaN衬底用作直径为2英寸(5.08cm)且厚度为400μm的衬底10。
接下来，参见图7(B)，在III族氮化物半导体层20的n--GaN层22上根据溅射法形成1μm厚的Si3N4层作为介电层30之后，根据蚀刻法形成直径为1000μm的开口30w。
接下来，参见图7(C)，在位于介电层30的开口30w内的III族氮化物半导体层20的部分上和位于开口30w附近(离开口的边缘100μm的距离内)的介电层30的部分上，通过根据EB气相沉积法顺序沉积100nm厚的Ni层和500nm厚的Au层形成Ni/Au电极作为肖特基电极40。
接下来，参考图7(D)，通过根据EB气相沉积法在肖特基电极40上顺序地沉积50nm厚的Ti层、100nm厚的Pt层和2μm厚的Au层形成作为焊垫电极50的Ti/Pt/Au电极。
接下来，参考图7(E)，通过根据EB气相沉积法在衬底10的另一主表面上顺序地沉积200nm厚的Al层、50nm厚的Ti层和500nm厚的Au层形成作为衬底电极70的Al/Ti/Au电极，并通过划片和断裂将其制成具有尺寸为2mm×2mm的芯片。然后，具有210℃熔点的Sn-Ag焊料(焊料中Sn含量是97wt％且Ag含量是3wt％)作为焊料60布置在焊垫电极50上。
在上述的方法中，得到了含有焊料的半导体器件1的芯片。测量含有焊料的半导体器件1每个的耐受电压。将每个安装的含有焊料的半导体器件的耐受电压看作为肖特基电极40中漏电流为1×10-3A/cm2的反向电压。
2.含有焊料的半导体器件的安装
接下来，参考图7(G)，在230℃温度下将含有焊料的半导体器件1的焊料60接合到封装100。
接下来，参考图7(H)，经由由Au制成的布线90将含有焊料的半导体器件1的衬底电极70连接到封装100。
在如上所述的方法中，通过将含有焊料的半导体器件1的芯片安装到封装100来得到安装的含有焊料的半导体器件焊接芯片6。测量每个安装的含有焊料的半导体器件的耐受电压。用与未安装的含有焊料的半导体器件的耐受电压一样的标准，来测量安装的含有焊料的半导体器件的耐受电压。
在图9的图表中绘制了含有焊料的半导体器件1在安装之前和之后的耐受电压。
(比较示例1)
除了使用具有280℃熔点的Au-Sn焊料(焊料中Au含量是80wt％且Sn含量是20wt％)作为焊料，且在340℃的温度下将该焊料接合到封装以外，以与示例1相同的方法制备含有焊料的半导体器件并将其安装到封装，并测量了安装的含有焊料的半导体器件和未安装的含有焊料的半导体器件的耐受电压，且绘制在图9的图表中。
(比较示例2)
除了通过顺序沉积50nm厚的Ti层和2μm厚的Au层来形成没有Pt层的Ti/Au电极作为焊垫电极，使用具有280℃熔点的Au-Sn焊料(焊料中Au含量是80wt％且Sn含量是20wt％)作为焊料，且在340℃的温度下将该焊料接合到封装以外，以与示例1相同的方法制备含有焊料的半导体器件并将其安装到封装，测量安装的含有焊料的半导体器件和未安装的含有焊料的半导体器件的耐受电压，并绘制在图9的图表中。
参考图9，如由比较示例2所示，即使经由在焊垫电极上布置的焊料将焊垫电极中不包括Pt层的含有焊料的半导体器件在340℃的温度下接合到封装，与未安装的含有焊料的半导体器件的耐受电压相比，安装的含有焊料的半导体器件的耐受电压也不会减小。然而，由于Sn与n-型GaN欧姆接触，所以会产生由焊料中的Sn扩散使肖特基性能劣化的问题。因此，在焊垫电极中必须包括Pt层。
如由比较示例1所示，在经由在焊垫电极上布置的焊料将焊垫电极中包括Pt层的含有焊料的半导体器件在340℃的温度下接合到封装的情况下，与未安装的含有焊料的半导体器件的耐受电压相比，安装的含有焊料的半导体器件的耐受电压会显著减小。
相比之下，如由示例1所示，在经由在焊垫电极上布置的焊料将焊垫电极中包括Pt层的含有焊料的半导体器件在230℃的温度下接合到封装的情况下，与未安装的含有焊料的半导体器件的耐受电压相比，安装的含有焊料的半导体器件的耐受电压不会减小，并保持高耐压性能。
应该理解，为了在所有方面示例和描述而不是限制的目的，提出了本文公开的实施例。意指本发明的范围不限制于以上描述而是用权利要求的范围来限定，并包括意思和范围等效于权利要求的所有变更。
参考标记列表
1、2A、2B、3：含有焊料的半导体器件；1D、2AD、2BD、3D：半导体器件；6、7A、7B、8：安装的含有焊料的半导体器件；10：衬底；11：底层衬底；12：接合膜：13：III族氮化物膜；20：III族氮化物半导体层；21：n+-GaN层；22：n--GaN层；26：GaN层；27：n-Al1-xGaxN层；28：n-GaN层；30、80：介电层；30w、80w：开口；40：肖特基电极；42：源电极；44：漏电极；50：焊垫电极；60：焊料70：衬底电极；90：布线；100：封装

Claims (13)

1.一种含有焊料的半导体器件，包括半导体器件，
所述半导体器件包括：
衬底；
布置在所述衬底上的至少一层III族氮化物半导体层；
布置在所述III族氮化物半导体层上的肖特基电极；和
布置在所述肖特基电极上的焊垫电极，
所述焊垫电极具有包括至少Pt层的多层结构，
所述含有焊料的半导体器件还包括具有200至230℃的熔点并且布置在所述半导体器件的所述焊垫电极上的焊料。
2.根据权利要求1所述的含有焊料的半导体器件，其中
所述含有焊料的半导体器件还包括具有开口并且布置在所述III族氮化物半导体层上的介电层，并且
所述肖特基电极布置在所述III族氮化物半导体层的位于所述介电层的所述开口内的部分上。
3.根据权利要求1或2所述的含有焊料的半导体器件，其中
所述衬底是III族氮化物衬底。
4.根据权利要求1至3中的任一项所述的含有焊料的半导体器件，其中
所述衬底是复合衬底，所述复合衬底包括底层衬底和直接或间接地接合到所述底层衬底的III族氮化物膜。
5.根据权利要求4所述的含有焊料的半导体器件，其中
所述含有焊料的半导体器件包括从所述复合衬底移除所述底层衬底之后留下作为所述衬底的所述III族氮化物膜。
6.根据权利要求1至5中的任一项所述的含有焊料的半导体器件，其中
所述焊料包括从由Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-In-Bi、Sn-Ag-Cu-Bi和Sn-Ag-Bi-In组成的组中选择的至少一种合金。
7.根据权利要求1至6中的任一项所述的含有焊料的半导体器件，其中
所述Pt层具有30nm或更大的厚度。
8.根据权利要求2所述的含有焊料的半导体器件，其中
所述介电层包括从由Si3N4和SiO2组成的组中选择的至少一种硅化合物。
9.一种安装的含有焊料的半导体器件，包括根据权利要求1至8中的任一项所述的含有焊料的半导体器件，其中
通过将所述含有焊料的半导体器件的所述焊料接合到封装，来将所述含有焊料的半导体器件安装到所述封装。
10.一种制造含有焊料的半导体器件的方法，包括形成半导体器件的步骤，
形成半导体器件的步骤包括：
在衬底上形成至少一层III族氮化物半导体层的子步骤；
在所述III族氮化物半导体层上形成肖特基电极的子步骤；和
在所述肖特基电极上形成焊垫电极的子步骤，
所述焊垫电极具有包括至少Pt层的多层结构，
所述方法还包括在所述半导体器件的所述焊垫电极上布置具有200至230℃的熔点的焊料的步骤。
11.根据权利要求10所述的制造含有焊料的半导体器件的方法，其中
形成半导体器件的步骤还包括在形成所述III族氮化物半导体层的子步骤之后并且在形成所述肖特基电极的子步骤之前执行的在所述III族氮化物半导体层上形成具有开口的介电层的子步骤，和
在形成所述肖特基电极的子步骤中，将所述肖特基电极形成在所述III族氮化物半导体层的位于所述介电层的所述开口内的部分上。
12.一种安装含有焊料的半导体器件的方法，包括以下步骤：
制备根据权利要求1至4中的任一项所述的含有焊料的半导体器件；和
在200至230℃的温度下将所述含有焊料的半导体器件的所述焊料接合到封装以安装所述含有焊料的半导体器件。
13.一种安装含有焊料的半导体器件的方法，包括以下步骤：
制备根据权利要求4所述的含有焊料的半导体器件；
在200至230℃的温度下将所述含有焊料的半导体器件的所述焊料接合到封装以安装所述含有焊料的半导体器件；和
从所述含有焊料的半导体器件的所述复合衬底移除所述底层衬底。
CN201480001915.2A 2013-04-16 2014-04-15 含有焊料的半导体器件、安装的含有焊料的半导体器件、含有焊料的半导体器件的制造方法和安装方法 Pending CN104488086A (zh)

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