WO2021223302A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2021223302A1
WO2021223302A1 PCT/CN2020/097684 CN2020097684W WO2021223302A1 WO 2021223302 A1 WO2021223302 A1 WO 2021223302A1 CN 2020097684 W CN2020097684 W CN 2020097684W WO 2021223302 A1 WO2021223302 A1 WO 2021223302A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductive layer
binding
bonding
display panel
Prior art date
Application number
PCT/CN2020/097684
Other languages
English (en)
French (fr)
Inventor
周菁
张毅先
鲜于文旭
Original Assignee
武汉华星光电半导体显示技术有限公司
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Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/057,712 priority Critical patent/US11793042B2/en
Publication of WO2021223302A1 publication Critical patent/WO2021223302A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • This application relates to the field of display technology, in particular to a display panel and a manufacturing method thereof.
  • the proportion of screens used in electronic products is getting larger and larger, and full screens have become a trend that people are chasing.
  • the binding area of the display panel is usually bent to the back of the display panel, but due to the existence of the bending radius, the lower frame of the display panel still cannot be further narrowed.
  • the embodiments of the present application provide a display panel and a manufacturing method thereof to solve the technical problem of insufficient frame narrowing of the existing display panel.
  • An embodiment of the present application provides a display panel, the display panel includes a display area and an extension area provided outside the display area, and the display panel includes:
  • a binding module covers the display area and the extension area, the binding module includes a binding conductive layer, and the binding conductive layer is electrically connected to an external driving chip;
  • a display module covers the display area and the epitaxial area, the display module is disposed on the binding module, the display module includes a thin film transistor array structure, the thin film transistor array structure Including source and drain conductive layers;
  • the portion of the source-drain conductive layer located in the epitaxial region is electrically connected to the bonding conductive layer through a via hole.
  • the bonding conductive layer includes a plurality of fan-out traces and a plurality of bonding terminals, and the plurality of fan-out traces are electrically connected to the source-drain conductive layer, so
  • the binding terminals are connected to the fan-out wiring in a one-to-one correspondence, and the binding terminals are electrically connected to the external driving chip.
  • the bonding module further includes a first substrate structure, and the first substrate structure is disposed on a side of the bonding conductive layer facing away from the display module. On the side, an opening is opened on the first substrate structure, the opening is arranged corresponding to the plurality of binding terminals, and the plurality of binding terminals are exposed.
  • the first substrate structure includes a supporting layer and a first flexible substrate, and the first flexible substrate is disposed between the supporting layer and the binding conductive layer. between.
  • the display module further includes a second substrate structure, and the second substrate structure is disposed between the bonding module and the thin film transistor array structure;
  • the thin film transistor array structure further includes an active layer, a first insulating layer, a first gate conductive layer, a second insulating layer, a second gate conductive layer, and a dielectric layer sequentially arranged on the second substrate structure.
  • Layer and a flat layer, the source-drain conductive layer is disposed between the dielectric layer and the flat layer;
  • the via hole is located in the epitaxial region, and the via hole penetrates the dielectric layer, the second insulating layer, the first insulating layer, and the second substrate structure, and is connected to the fan-out wiring.
  • the second substrate structure includes a first barrier layer, a second flexible substrate, a second barrier layer, and a buffer layer sequentially disposed on the binding conductive layer.
  • the embodiment of the present application also relates to a method for manufacturing a display panel, which includes the following steps:
  • the substrate including a display area and an epitaxial area arranged outside the display area;
  • a display module on the bonding conductive layer the display module covering the display area and the epitaxial area, the display module including a thin film transistor array structure, the thin film transistor array structure including a source-drain conductive layer; The portion of the source-drain conductive layer located in the epitaxial region is electrically connected to the bonding conductive layer through a via hole.
  • the bonding conductive layer includes a plurality of fan-out wires and a plurality of bonding terminals, and the plurality of fan-out wires are electrically connected to the source and drain conductive layers.
  • Layer, the binding terminals are connected to the fan-out wiring in a one-to-one correspondence, and the binding terminals are electrically connected to the external driving chip.
  • the forming the display module on the bonding conductive layer includes the following steps:
  • the source-drain conductive layer and a flat layer are sequentially formed on the dielectric layer, and a part of the source-drain conductive layer fills the via hole and is connected to the fan-out trace.
  • the forming a binding conductive layer on the substrate further includes the following step: forming a first flexible substrate on the substrate;
  • the method further includes the following steps:
  • a support layer is attached to the side of the first flexible substrate facing away from the display module, and the first flexible substrate and the support layer form a first substrate structure;
  • a hole processing is performed in the region of the first substrate structure corresponding to the plurality of binding terminals to expose the plurality of binding terminals.
  • the binding module for binding the external drive chip is arranged on the back of the display module, and the source and drain conductive layers in the display module are conductively connected to the binding module of the binding module through via holes.
  • the layers are electrically connected, thereby saving the plane space for setting the binding module and achieving the effect of narrowing the frame.
  • FIG. 1 is a schematic diagram of a front view structure of a display panel according to an embodiment of the application
  • FIG. 2 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of a rear view structure of a display panel according to an embodiment of the application.
  • FIG. 4 is a flowchart of a method for manufacturing a display panel according to an embodiment of the application.
  • FIG. 5 is a flowchart of step S4 of the manufacturing method of the display panel according to the embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • the "on" or “under” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • FIG. 1 is a schematic diagram of a front view of a display panel according to an embodiment of the application
  • FIG. 2 is a schematic diagram of a cross-sectional structure of a display panel according to an embodiment of the application
  • Schematic diagram of rear view structure
  • An embodiment of the present application provides a display panel 100.
  • the display panel 100 includes a display area AA and an extension area NA disposed outside the display area AA.
  • the display panel 100 includes a binding module 10 and a display module 20.
  • the binding module 10 covers the display area AA and the extension area NA.
  • the bonding module 10 includes a bonding conductive layer 11, and the bonding conductive layer 11 is electrically connected to an external driving chip (not shown in the figure).
  • the external driving chip is a component other than the display panel 100 of this embodiment.
  • the display module 20 covers the display area AA and the extension area NA.
  • the display module 20 is arranged on the binding module 10.
  • the display module 20 includes a thin film transistor array structure 21, and the thin film transistor array structure 21 includes a source-drain conductive layer 211.
  • the portion of the source-drain conductive layer 211 located in the epitaxial region NA is electrically connected to the bonding conductive layer 11 through the via 21 a.
  • a bonding module 10 for bonding an external drive chip is arranged on the back of the display module 20, and the source and drain conductive layers 211 in the display module 20 are connected to each other through the via 21a.
  • the bonding conductive layer 11 of the fixed module 10 is electrically connected, so that the display panel 100 saves the plane space for arranging the bonding module 10 and achieves the effect of narrowing the frame.
  • the bonding conductive layer 11 includes a plurality of fan-out wires 111 and a plurality of bonding terminals 112.
  • a plurality of fan-out wires 111 are electrically connected to the source-drain conductive layer 211.
  • the binding terminals 112 are connected to the fan-out wiring 111 in a one-to-one correspondence, and the binding terminals 112 are electrically connected to an external driving chip.
  • the material of the binding conductive layer 11 may be pure metal, metal alloy, semiconductor material, or other conductive materials.
  • the binding conductive layer 11 is formed by stacking multiple layers of metal.
  • the fan-out wires 111 and the binding terminals 112 are both arranged on the back of the display module 20, which reduces the width of the lower frame compared to the prior art.
  • the source-drain conductive layer 211 in the display module 20 and the fan-out wiring 111 are connected by the via 21a. Compared with bending the bonding area to the display panel on the back of the display module, the bending radius is saved. Width, further reducing the width of the lower border. In addition, the use of the via 21a connection method improves the stability of the electrical connection between the display module 20 and the binding module 10; Bending stress causes damage to or even breakage of fan-out traces.
  • the source-drain conductive layer 211 includes a source electrode, a drain electrode, a data line and a driving lead, and the source electrode and the drain electrode are used to form a thin film transistor.
  • One end of the driving lead is connected to the data line, and the other end is connected to the fan-out wiring 111.
  • the bonding module 10 further includes a first substrate structure 12.
  • the first substrate structure 12 is disposed on the side of the bonding conductive layer 11 facing away from the display module 10.
  • An opening 12a is defined in the first substrate structure 12, and the opening 12a is provided corresponding to the plurality of binding terminals 112, and the plurality of binding terminals 112 are exposed.
  • the opening 12 a is arranged to expose the binding terminal 112 so as to facilitate the electrical connection of the external driving chip and the binding terminal 112.
  • the binding terminal 112 is directly bonded and connected with the external driving chip; in some embodiments, the binding terminal 112 may also be bonded and connected with the terminal of the circuit board with the external driving chip.
  • the first substrate structure 12 includes a supporting layer 121 and a first flexible substrate 122.
  • the first flexible substrate 122 is disposed between the support layer 121 and the bonding conductive layer 11.
  • the bonding module 10 includes a supporting layer 121, a first flexible substrate 122, and a bonding conductive layer 11 that are sequentially arranged.
  • both the first flexible substrate 122 and the supporting layer 121 are provided with sub-openings, and the two sub-openings are overlapped and communicated with each other to form an opening 12a.
  • the display module 20 further includes a second substrate structure 22, and the second substrate structure 22 is disposed between the bonding module 10 and the thin film transistor array structure 21.
  • the thin film transistor array structure 21 further includes an active layer 212, a first insulating layer 213, a first gate conductive layer 214, a second insulating layer 215, and a second gate conductive layer 216 sequentially disposed on the second substrate structure 22. , A dielectric layer 217, a flat layer 218, an anode layer 219, and a pixel definition layer 210.
  • the source-drain conductive layer 211 is provided between the dielectric layer 217 and the flat layer 218.
  • the display panel 100 of this embodiment further includes an organic light-emitting structure and an encapsulation layer. Since the organic light-emitting structure and the encapsulation layer are in the prior art, they will not be repeated here.
  • the via 21a is located in the epitaxial region NA.
  • the via 21 a penetrates the dielectric layer 217, the second insulating layer 215, the first insulating layer 213, and the second substrate structure 22, and is connected to the fan-out wiring 111.
  • the second substrate structure 22 includes a first barrier layer 221, a second flexible substrate 222, a second barrier layer 223, and a buffer layer 224 sequentially disposed on the bonding conductive layer 11.
  • the second substrate structure 22 may also include a barrier layer and a buffer layer disposed on the bonding conductive layer 11.
  • the second substrate structure 22 may also have other structures.
  • the display module 20 includes a first barrier layer 221, a second flexible substrate 222, a second barrier layer 223, a buffer layer 224, and an active Layer 212, first insulating layer 213, first gate conductive layer 214, second insulating layer 215, second gate conductive layer 216, dielectric layer 217, source-drain conductive layer 211, flat layer 218, anode layer 219 and Pixel definition layer 210.
  • the materials of the first gate conductive layer 214 and the second gate conductive layer 216 may be pure metals, metal alloys, semiconductor materials or other conductive materials, respectively.
  • the first gate conductive layer 214 and the second gate conductive layer 216 are respectively formed by a multilayer metal stack.
  • an embodiment of the present application also relates to a method for manufacturing a display panel.
  • the display panel is the display panel 100 of the above-mentioned embodiment.
  • the preparation method of the display panel includes the following steps:
  • Step S1 providing a substrate, the substrate including a display area and an epitaxial area arranged outside the display area;
  • Step S2 forming a first flexible substrate on the substrate, the first flexible substrate covering the display area and the epitaxial area;
  • Step S3 forming a bonding conductive layer on the substrate, the bonding conductive layer covering the display area and the epitaxial region, and the bonding conductive layer is electrically connected to an external driving chip;
  • Step S4 forming a display module on the bonding conductive layer, the display module covering the display area and the epitaxial area, the display module including a thin film transistor array structure, the thin film transistor array structure including source and drain Conductive layer; the portion of the source-drain conductive layer located in the epitaxial region is electrically connected to the binding conductive layer through via holes;
  • Step S5 Peel off the substrate
  • Step S6 attach a support layer to the side of the first flexible substrate facing away from the display module, and the first flexible substrate and the support layer form a first substrate structure;
  • Step S7 Perform an opening process in the region of the first substrate structure corresponding to the plurality of binding terminals to expose the plurality of binding terminals.
  • a bonding conductive layer for bonding an external drive chip is formed on the back of the display module, and the source and drain conductive layers in the display module are connected to the bonding conductive layer through the via holes It is electrically connected, so that the display panel saves the plane space for arranging the bonding conductive layer, and achieves the effect of narrowing the frame.
  • a substrate is provided.
  • the substrate includes a display area AA and an epitaxial area NA arranged outside the display area AA.
  • the substrate is a rigid substrate, such as a glass substrate.
  • the substrate is a carrier forming the display panel 100. Then go to step S2.
  • a first flexible substrate 122 is formed on the substrate.
  • the first flexible substrate 122 covers the display area AA and the epitaxial area NA.
  • the material of the first flexible substrate 122 may be polyimide.
  • the function of the first flexible substrate 122 is to isolate the substrate and the subsequently formed film layer, so as to avoid damaging the subsequently formed film layer when the substrate is peeled off, on the other hand, It is to increase the performance of water vapor intrusion. Then go to step S3.
  • a bonding conductive layer 11 is formed on the substrate.
  • the bonding conductive layer 11 covers the display area AA and the epitaxial area NA.
  • the bonding conductive layer 11 is electrically connected to an external driving chip. It should be noted that the external driving chip is a component other than the display panel of this embodiment.
  • the bonding conductive layer 11 includes a plurality of fan-out wires 111 and a plurality of bonding terminals 112.
  • a plurality of fan-out traces 111 are electrically connected to the source-drain conductive layer 211 formed later.
  • the binding terminals 112 are connected to the fan-out wiring 111 in a one-to-one correspondence.
  • the binding terminal 112 is electrically connected to an external driving chip.
  • the material of the binding conductive layer 11 may be pure metal, metal alloy, semiconductor material, or other conductive materials.
  • the binding conductive layer 11 is formed by stacking multiple layers of metal.
  • Both the fan-out wiring 111 and the binding terminal 112 are arranged on the back of the display module 20 to be formed later, which reduces the width of the lower frame compared with the prior art. Then go to step S4.
  • a display module 20 is formed on the bonding conductive layer 11.
  • the display module 20 covers the display area AA and the extension area NA.
  • the display module 20 includes a thin film transistor array structure 21.
  • the thin film transistor array structure 21 includes a source and drain conductive layer 211. The portion of the source-drain conductive layer 211 located in the epitaxial region NA is electrically connected to the bonding conductive layer 11 through the via 21 a.
  • Step S4 further includes the following steps:
  • S42 An active layer 212, a first insulating layer 213, a first gate conductive layer 214, a second insulating layer 215, a second gate conductive layer 216, and a dielectric layer are sequentially formed on the second substrate structure 22 217;
  • S43 Perform a patterning process on the portion of the dielectric layer 217 located in the epitaxial region NA to form a via 21a.
  • the via 21a penetrates the dielectric layer 217, the second insulating layer 215, and the first insulating layer.
  • S44 forming the source-drain conductive layer 211, the flat layer 218, the anode layer 219, and the pixel definition layer 210 on the dielectric layer 217 in sequence. A portion of the source-drain conductive layer 211 fills the via hole 21 a and is connected to the fan-out wiring 111.
  • step S41 a second substrate structure 22 is formed on the bonding conductive layer 11.
  • step S41 is to sequentially form a first barrier layer 221, a second flexible substrate 222, a second barrier layer 223, and a buffer layer 224 on the bonding conductive layer 11.
  • the first barrier layer 221 has a certain leveling property and provides a flat film base surface for subsequent film layers.
  • the first barrier layer 221 and the second barrier layer 223 both have the performance of blocking water vapor from entering the thin film transistor array structure 21. Then go to step S42.
  • step S42 an active layer 212, a first insulating layer 213, a first gate conductive layer 214, a second insulating layer 215, a second gate conductive layer 216 and Dielectric layer 217.
  • the materials of the first gate conductive layer 214 and the second gate conductive layer 216 may be pure metals, metal alloys, semiconductor materials or other conductive materials, respectively.
  • the first gate conductive layer 214 and the second gate conductive layer 216 are respectively formed by a multilayer metal stack. Then go to step S43.
  • step S43 patterning is performed on the portion of the dielectric layer 217 located in the epitaxial region NA to form a via 21a.
  • the via 21a penetrates the dielectric layer 217, the second insulating layer 215, The first insulating layer 213 and the second substrate structure 22.
  • a photolithography process is used to expose and develop the dielectric layer 217, and a plurality of via holes 21a are formed in the epitaxial region NA at a position corresponding to the fan-out wiring 111.
  • the through hole 21a is etched through, and dry etching, wet etching, or laser etching may be used.
  • the via 21a penetrates the dielectric layer 217, the second insulating layer 215, the first insulating layer 213 and the second substrate structure 22, and exposes the fan-out wiring 111. Then go to step S44.
  • step S44 the source-drain conductive layer 211, the flat layer 218, the anode layer 219, and the pixel definition layer 210 are sequentially formed on the dielectric layer 217. A portion of the source-drain conductive layer 211 fills the via hole 21 a and is connected to the fan-out wiring 111.
  • step S44 other film layers and module manufacturing processes such as an organic light emitting structure and an encapsulation layer are formed on the pixel definition layer 210. Since other film layers and module manufacturing processes are in the prior art, they will not be repeated here.
  • the material of the source-drain conductive layer is deposited in the via 21a, so that the leads of the source-drain conductive layer 211 of the epitaxial region NA are connected to the fan-out wiring 111.
  • the display module 20 includes a second substrate structure 22 and a thin film transistor array mechanism 21.
  • the source-drain conductive layer 211 in the display module 20 and the fan-out wiring 111 are connected by the via 21a.
  • the bending radius is saved.
  • the width of the lower frame is further reduced, and the stability of the electrical connection between the display module 20 and the binding module 10 is improved; compared with the existing display panel, it avoids bending and bending of the fan-out wiring
  • the effect of stress leads to damage or even breakage of fan-out traces.
  • step S5 the substrate is peeled off. Specifically, a laser is used to peel off the substrate. Then go to step S6.
  • step S6 a support layer 121 is attached to the side of the first flexible substrate 122 facing away from the display module 20, and the first flexible substrate 122 and the support layer 121 form a first substrate structure 12 .
  • the first substrate structure 12 and the bonding conductive layer 11 form a bonding module 10. Then, go to step S7.
  • step S7 an opening process is performed in the region of the first substrate structure 12 corresponding to the plurality of bonding terminals 112 to form openings 12a to expose the plurality of bonding terminals 112. Exposing the binding terminal 112 facilitates the electrical connection of an external driving chip and the binding terminal 112.
  • the binding module for binding the external drive chip is arranged on the back of the display module, and the source and drain conductive layers in the display module are conductively connected to the binding module of the binding module through via holes.
  • the layers are electrically connected, thereby saving the plane space for setting the binding module and achieving the effect of narrowing the frame.

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本申请提供一种显示面板及其制备方法，在显示面板中，绑定模组覆盖显示区和外延区，绑定模组的绑定导电层电性连接于外置的驱动芯片；显示模组覆盖显示区和外延区，显示模组设置在绑定模组上，显示模组包括薄膜晶体管阵列结构，薄膜晶体管阵列结构包括源漏导电层；源漏导电层位于外延区的部分通过过孔电性连接于绑定导电层。

Description

显示面板及其制备方法 技术领域
本申请涉及一种显示技术领域，特别涉及一种显示面板及其制备方法。
 背景技术
目前用于电子产品的屏幕屏占比愈来愈大，全面屏已成为人们追逐的趋势。但是，现有的电子产品的显示面板中，通常将显示面板的绑定区弯折至显示面板的背面，但是由于弯折半径的存在，显示面板的下边框依然不能进一步的窄边框化。
 技术问题
本申请实施例提供一种显示面板及其制备方法，以解决现有的显示面板窄边框化不足的技术问题。
 技术解决方案
本申请实施例提供一种显示面板，所述显示面板包括显示区和设置在所述显示区外侧的外延区，所述显示面板包括：
绑定模组，所述绑定模组覆盖所述显示区和外延区，所述绑定模组包括绑定导电层，所述绑定导电层电性连接于外置的驱动芯片；
显示模组，所述显示模组覆盖所述显示区和外延区，所述显示模组设置在所述绑定模组上，所述显示模组包括薄膜晶体管阵列结构，所述薄膜晶体管阵列结构包括源漏导电层；
所述源漏导电层位于所述外延区的部分通过过孔电性连接于所述绑定导电层。
在本申请实施例的所述显示面板中，所述绑定导电层包括多条扇出走线和多个绑定端子，所述多条扇出走线电性连接于所述源漏导电层，所述绑定端子一一对应地连接于所述扇出走线，所述绑定端子电性连接所述外置的驱动芯片。
在本申请实施例的所述显示面板中，所述绑定模组还包括第一衬底结构，所述第一衬底结构设置在所述绑定导电层背向所述显示模组的一侧，所述第一衬底结构上开设有一开口，所述开口对应所述多个绑定端子设置，且裸露出所述多个绑定端子。
在本申请实施例的所述显示面板中，所述第一衬底结构包括支撑层和第一柔性衬底，所述第一柔性衬底设置在所述支撑层和所述绑定导电层之间。
在本申请实施例的所述显示面板中，所述显示模组还包括第二衬底结构，所述第二衬底结构设置在所述绑定模组和所述薄膜晶体管阵列结构之间；
所述薄膜晶体管阵列结构还包括依次设置在所述第二衬底结构上的有源层、第一绝缘层、第一栅极导电层、第二绝缘层、第二栅极导电层、介电层和平坦层，所述源漏导电层设置在所述介电层和所述平坦层之间；
所述过孔位于所述外延区，所述过孔贯穿所述介电层、第二绝缘层、第一绝缘层、第二衬底结构，且连接于所述扇出走线。
在本申请实施例的所述显示面板中，所述第二衬底结构包括依次设置在所述绑定导电层上的第一阻挡层、第二柔性衬底、第二阻挡层和缓冲层。
本申请的实施例还涉及一种显示面板的制备方法，其包括以下步骤：
提供一基板，所述基板包括显示区和设置在所述显示区外侧的外延区；
在所述基板上形成绑定导电层，所述绑定导电层覆盖所述显示区和外延区，所述绑定导电层电性连接于外置的驱动芯片；
在所述绑定导电层上形成显示模组，所述显示模组覆盖所述显示区和外延区，所述显示模组包括薄膜晶体管阵列结构，所述薄膜晶体管阵列结构包括源漏导电层；所述源漏导电层位于所述外延区的部分通过过孔电性连接于所述绑定导电层。
在本申请实施例的所述显示面板的制备方法中，所述绑定导电层包括多条扇出走线和多个绑定端子，所述多条扇出走线电性连接于所述源漏导电层，所述绑定端子一一对应地连接于所述扇出走线，所述绑定端子电性连接所述外置的驱动芯片。
在本申请实施例的所述显示面板的制备方法中，所述在所述绑定导电层上形成显示模组，包括以下步骤：
在所述绑定导电层上形成第二衬底结构；
在所述第二衬底结构上依次形成有源层、第一绝缘层、第一栅极导电层、第二绝缘层、第二栅极导电层和介电层；
对所述介电层位于所述外延区的部分进行图案化处理，以形成过孔，所述过孔贯穿所述介电层、第二绝缘层、第一绝缘层和第二衬底结构；
在所述介电层上依次形成所述源漏导电层和平坦层，所述源漏导电层的部分填充所述过孔，并连接于所述扇出走线。
在本申请实施例的所述显示面板的制备方法中，所述在所述基板上形成绑定导电层，之前还包括以下步骤：在所述基板上形成第一柔性衬底；
所述在所述绑定导电层上形成显示模组，之后还包括以下步骤：
剥离所述基板；
在所述第一柔性衬底背向所述显示模组的一侧贴合支撑层，所述第一柔性衬底和支撑层形成第一衬底结构；
在所述第一衬底结构对应于所述多个绑定端子的区域进行开孔处理，以露出所述多个绑定端子。
 有益效果
本申请的显示面板将用于绑定外置驱动芯片的绑定模组设置在显示模组的背面，并将显示模组中的源漏导电层通过过孔与绑定模组的绑定导电层电性连接，从而节省了设置绑定模组的平面空间，达到窄边框化的效果。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本申请的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为本申请实施例的显示面板的正视结构示意图；
图2为本申请实施例的显示面板的剖视结构示意图；
图3为本申请实施例的显示面板的后视结构示意图；
图4为本申请实施例的显示面板的制备方法的流程图；
图5为本申请实施例的显示面板的制备方法的步骤S4的流程图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参照图1至图3，图1为本申请实施例的显示面板的正视结构示意图；图2为本申请实施例的显示面板的剖视结构示意图；图3为本申请实施例的显示面板的后视结构示意图。
本申请实施例提供一种显示面板100，显示面板100包括显示区AA和设置在显示区AA外侧的外延区NA。显示面板100包括绑定模组10和显示模组20。绑定模组10覆盖显示区AA和外延区NA。绑定模组10包括绑定导电层11，绑定导电层11电性连接于外置的驱动芯片（图中未示出）。该外置的驱动芯片为本实施例的显示面板100之外的部件。
显示模组20覆盖显示区AA和外延区NA。显示模组20设置在绑定模组10上。显示模组20包括薄膜晶体管阵列结构21，薄膜晶体管阵列结构21包括源漏导电层211。源漏导电层211位于外延区NA的部分通过过孔21a电性连接于绑定导电层11。
本实施例的显示面板100将用于绑定外置驱动芯片的绑定模组10设置在显示模组20的背面，并将显示模组20中的源漏导电层211通过过孔21a与绑定模组10的绑定导电层11电性连接，从而使得显示面板100节省了设置绑定模组10的平面空间，达到窄边框化的效果。
具体的，绑定导电层11包括多条扇出走线111和多个绑定端子112。多条扇出走线111电性连接于源漏导电层211。绑定端子112一一对应地连接于扇出走线111，且绑定端子112电性连接外置的驱动芯片。
绑定导电层11的材料可以纯金属、金属合金、半导体材料或其他导电性质的材料。可选的，在本实施例中，绑定导电层11由多层金属堆叠形成。
在本实施例的显示面板100中，将扇出走线111和绑定端子112均设置在显示模组20的背面，相较于现有技术，缩小下边框的宽度。
采用过孔21a的方式将显示模组20中的源漏导电层211和扇出走线111进行连接，相较于将绑定区弯折至显示模组背面的显示面板，节省了弯折半径的宽度，进一步缩小了下边框的宽度。另外，采用过孔21a的连接方式，提高了显示模组20和绑定模组10电性连接的稳定性；相较于现有的显示面板，避免了扇出走线进行弯折时，受弯折应力作用导致扇出走线损坏甚至断裂的情况。
其中，源漏导电层211包括源极、漏极、数据线和驱动引线，源极和漏极用于形成薄膜晶体管。驱动引线的一端连接数据线，另一端连接扇出走线111。
在本实施例的显示面板100中，参照图2和图3，绑定模组10还包括第一衬底结构12。第一衬底结构12设置在绑定导电层11背向显示模组10的一侧。第一衬底结构12上开设有一开口12a，开口12a对应多个绑定端子112设置，且裸露出多个绑定端子112。
开口12a设置在于裸露出绑定端子112，以便于外置的驱动芯片与绑定端子112电性连接。其中，在本实施例中，绑定端子112直接与外置驱动芯片绑定连接；在一些实施例中，绑定端子112也可以与具有外置驱动芯片的电路板的端子绑定连接。
在本实施例的显示面板100中，第一衬底结构12包括支撑层121和第一柔性衬底122。第一柔性衬底122设置在支撑层121和绑定导电层11之间。也就是说，绑定模组10包括依次设置的支撑层121、第一柔性衬底122和绑定导电层11。
具体的，第一柔性衬底122和支撑层121上均开设有子开口，两个子开口重叠设置且相互连通形成开口12a。
在本实施例的显示面板100中，显示模组20还包括第二衬底结构22，第二衬底结构22设置在绑定模组10和薄膜晶体管阵列结构21之间。
薄膜晶体管阵列结构21还包括依次设置在第二衬底结构22上的有源层212、第一绝缘层213、第一栅极导电层214、第二绝缘层215、第二栅极导电层216、介电层217、平坦层218、阳极层219和像素定义层210。源漏导电层211设置在介电层217和平坦层218之间。需要说明的是，本实施例显示面板100还包括有机发光结构和封装层，由于有机发光结构和封装层为现有技术，此处不再赘述。
过孔21a位于外延区NA。过孔21a贯穿介电层217、第二绝缘层215、第一绝缘层213、第二衬底结构22，且连接于扇出走线111。
另外，第二衬底结构22包括依次设置在绑定导电层11上的第一阻挡层221、第二柔性衬底222、第二阻挡层223和缓冲层224。在一些实施例中，第二衬底结构22也可以包括设置在绑定导电层11上的阻挡层和缓冲层。当然，第二衬底结构22也可以是其他结构。
也就是说，在本实施例中，显示模组20包括依次设置在绑定导电层11上的第一阻挡层221、第二柔性衬底222、第二阻挡层223、缓冲层224、有源层212、第一绝缘层213、第一栅极导电层214、第二绝缘层215、第二栅极导电层216、介电层217、源漏导电层211、平坦层218、阳极层219和像素定义层210。
其中，第一栅极导电层214和第二栅极导电层216的材料分别可以纯金属、金属合金、半导体材料或其他导电性质的材料。可选的，在本实施例中，第一栅极导电层214和第二栅极导电层216分别由多层金属堆叠形成。
请参照图4，本申请的实施例还涉及一种显示面板的制备方法，该显示面板为上述实施例的显示面板100，显示面板100结构示意图请参照图1至图3。显示面板的制备方法包括以下步骤：
步骤S1：提供一基板，所述基板包括显示区和设置在所述显示区外侧的外延区；
步骤S2：在所述基板上形成第一柔性衬底，所述第一柔性衬底覆盖所述显示区和外延区；
步骤S3：在所述基板上形成绑定导电层，所述绑定导电层覆盖所述显示区和外延区，所述绑定导电层电性连接于外置的驱动芯片；
步骤S4：在所述绑定导电层上形成显示模组，所述显示模组覆盖所述显示区和外延区，所述显示模组包括薄膜晶体管阵列结构，所述薄膜晶体管阵列结构包括源漏导电层；所述源漏导电层位于所述外延区的部分通过过孔电性连接于所述绑定导电层；
步骤S5：剥离所述基板；
步骤S6：在所述第一柔性衬底背向所述显示模组的一侧贴合支撑层，所述第一柔性衬底和支撑层形成第一衬底结构；
步骤S7：在所述第一衬底结构对应于所述多个绑定端子的区域进行开孔处理，以露出所述多个绑定端子。
本实施例的显示面板的制备方法将用于绑定外置驱动芯片的绑定导电层形成在显示模组的背面，并将显示模组中的源漏导电层通过过孔与绑定导电层电性连接，从而使得显示面板节省了设置绑定导电层的平面空间，达到窄边框化的效果。
现在对本实施例的显示面板的制备方法进行阐述。
在步骤S1中，提供一基板，基板包括显示区AA和设置在显示区AA外侧的外延区NA。所述基板为硬性基板，比如玻璃基板。所述基板为形成显示面板100的载板。随后转入步骤S2。
在步骤S2中，在所述基板上形成第一柔性衬底122。所述第一柔性衬底122覆盖显示区AA和外延区NA。第一柔性衬底122的材料可以为聚酰亚胺，第一柔性衬底122的作用一方面在于隔离基板和后续形成的膜层，避免在剥离基板时损伤后续形成的膜层，另一方面在于增加防水汽入侵的性能。随后转入步骤S3。
在步骤S3中，在基板上形成绑定导电层11。绑定导电层11覆盖显示区AA和外延区NA。绑定导电层11电性连接于外置的驱动芯片。需要说明的是，外置的驱动芯片为本实施例的显示面板之外的部件。
具体的，绑定导电层11包括多条扇出走线111和多个绑定端子112。多条扇出走线111电性连接于后续形成的源漏导电层211。绑定端子112一一对应地连接于扇出走线111。绑定端子112电性连接外置的驱动芯片。
绑定导电层11的材料可以纯金属、金属合金、半导体材料或其他导电性质的材料。可选的，在本实施例中，绑定导电层11由多层金属堆叠形成。
将扇出走线111和绑定端子112均设置在后续形成的显示模组20的背面，相较于现有技术，缩小下边框的宽度。随后转入步骤S4。
在步骤S4中，在绑定导电层11上形成显示模组20。显示模组20覆盖显示区AA和外延区NA。显示模组20包括薄膜晶体管阵列结构21。薄膜晶体管阵列结构21包括源漏导电层211。源漏导电层211位于外延区NA的部分通过过孔21a电性连接于绑定导电层11。
具体的，请参照图5，步骤S4还包括以下步骤：
S41：在所述绑定导电层11上形成第二衬底结构22；
S42：在所述第二衬底结构22上依次形成有源层212、第一绝缘层213、第一栅极导电层214、第二绝缘层215、第二栅极导电层216和介电层217；
S43：对所述介电层217位于所述外延区NA的部分进行图案化处理，以形成过孔21a，所述过孔21a贯穿所述介电层217、第二绝缘层215、第一绝缘层213和第二衬底结构22；
S44：在所述介电层217上依次形成所述源漏导电层211、平坦层218、阳极层219和像素定义层210。所述源漏导电层211的部分填充所述过孔21a，并连接于所述扇出走线111。
在步骤S41中，在所述绑定导电层11上形成第二衬底结构22。具体的，步骤S41为在所述绑定导电层11上依次形成第一阻挡层221、第二柔性衬底222、第二阻挡层223和缓冲层224。第一阻挡层221具有一定的流平性，为后续膜层提供平坦的膜层基面，另外，第一阻挡层221和第二阻挡层223均具有阻挡水汽进入薄膜晶体管阵列结构21的性能。随后转入步骤S42。
在步骤S42中，在所述第二衬底结构22上依次形成有源层212、第一绝缘层213、第一栅极导电层214、第二绝缘层215、第二栅极导电层216和介电层217。其中，第一栅极导电层214和第二栅极导电层216的材料分别可以纯金属、金属合金、半导体材料或其他导电性质的材料。可选的，在本实施例中，第一栅极导电层214和第二栅极导电层216分别由多层金属堆叠形成。随后转入步骤S43。
在步骤S43中，对所述介电层217位于所述外延区NA的部分进行图案化处理，以形成过孔21a，所述过孔21a贯穿所述介电层217、第二绝缘层215、第一绝缘层213和第二衬底结构22。
具体的，采用光刻工艺对介电层217进行曝光和显影处理，在外延区NA对应于扇出走线111的位置形成多个过孔21a。随后，对过孔21a进行贯穿性蚀刻，可以采用干法蚀刻、湿法蚀刻或激光蚀刻。最后，过孔21a贯穿所述介电层217、第二绝缘层215、第一绝缘层213和第二衬底结构22，且裸露出扇出走线111。随后转入步骤S44。
在步骤S44中，在所述介电层217上依次形成所述源漏导电层211、平坦层218、阳极层219和像素定义层210。所述源漏导电层211的部分填充所述过孔21a，并连接于所述扇出走线111。
需要说明的是，在步骤S44中，还包括在像素定义层210形成有机发光结构和封装层等其它膜层和模组制程。由于其它膜层和模组制程为现有技术，故此处不再赘述。
另外，在形成源漏导电层211时，源漏导电层的材料会沉积在过孔21a内，使得外延区NA的源漏导电层211的引线与扇出走线111相连。
显示模组20包括第二衬底结构22和薄膜晶体管阵列机构21。采用过孔21a的方式将显示模组20中的源漏导电层211和扇出走线111进行连接，相较于将绑定区弯折至显示模组背面的显示面板，节省了弯折半径的宽度，进一步缩小了下边框的宽度，且提高了显示模组20和绑定模组10电性连接的稳定性；相较于现有的显示面板，避免了扇出走线进行弯折受弯折应力作用导致扇出走线损坏甚至断裂的情况。
随后转入步骤S5。
在步骤S5中，剥离所述基板。具体的，采用激光剥离所述基板。随后转入步骤S6。
在步骤S6中，在所述第一柔性衬底122背向所述显示模组20的一侧贴合支撑层121，所述第一柔性衬底122和支撑层121形成第一衬底结构12。此时，第一衬底结构12和绑定导电层11形成绑定模组10。随后，转入步骤S7。
在步骤S7中，在所述第一衬底结构12对应于所述多个绑定端子112的区域进行开孔处理，形成开口12a以露出所述多个绑定端子112。露出绑定端子112便于外置的驱动芯片与绑定端子112电性连接。
这样便完成了本实施例的显示面板100的制备过程。
本申请的显示面板将用于绑定外置驱动芯片的绑定模组设置在显示模组的背面，并将显示模组中的源漏导电层通过过孔与绑定模组的绑定导电层电性连接，从而节省了设置绑定模组的平面空间，达到窄边框化的效果。
以上对本申请实施例所提供的一种显示面板及其制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (15)

  1. 一种显示面板，所述显示面板包括显示区和设置在所述显示区外侧的外延区，其中，所述显示面板包括：
    绑定模组，所述绑定模组覆盖所述显示区和外延区，所述绑定模组包括绑定导电层，所述绑定导电层电性连接于外置的驱动芯片；
    显示模组，所述显示模组覆盖所述显示区和外延区，所述显示模组设置在所述绑定模组上，所述显示模组包括薄膜晶体管阵列结构，所述薄膜晶体管阵列结构包括源漏导电层；
    所述源漏导电层位于所述外延区的部分通过过孔电性连接于所述绑定导电层；
    所述绑定导电层包括多条扇出走线和多个绑定端子，所述多条扇出走线电性连接于所述源漏导电层，所述绑定端子一一对应地连接于所述扇出走线，所述绑定端子电性连接所述外置的驱动芯片；
    所述绑定导电层的材料可以纯金属、金属合金或半导体材料。
  2. 根据权利要求1所述的显示面板，其中，所述绑定模组还包括第一衬底结构，所述第一衬底结构设置在所述绑定导电层背向所述显示模组的一侧，所述第一衬底结构上开设有一开口，所述开口对应所述多个绑定端子设置，且裸露出所述多个绑定端子。
  3. 根据权利要求2所述的显示面板，其中，所述第一衬底结构包括支撑层和第一柔性衬底，所述第一柔性衬底设置在所述支撑层和所述绑定导电层之间。
  4. 根据权利要求3所述的显示面板，其中，所述显示模组还包括第二衬底结构，所述第二衬底结构设置在所述绑定模组和所述薄膜晶体管阵列结构之间；
    所述薄膜晶体管阵列结构还包括依次设置在所述第二衬底结构上的有源层、第一绝缘层、第一栅极导电层、第二绝缘层、第二栅极导电层、介电层和平坦层，所述源漏导电层设置在所述介电层和所述平坦层之间；
    所述过孔位于所述外延区，所述过孔贯穿所述介电层、第二绝缘层、第一绝缘层、第二衬底结构，且连接于所述扇出走线。
  5. 根据权利要求4所述的显示面板，其中，所述第二衬底结构包括依次设置在所述绑定导电层上的第一阻挡层、第二柔性衬底、第二阻挡层和缓冲层。
  6. 一种显示面板，所述显示面板包括显示区和设置在所述显示区外侧的外延区，其中，所述显示面板包括：
    绑定模组，所述绑定模组覆盖所述显示区和外延区，所述绑定模组包括绑定导电层，所述绑定导电层电性连接于外置的驱动芯片；
    显示模组，所述显示模组覆盖所述显示区和外延区，所述显示模组设置在所述绑定模组上，所述显示模组包括薄膜晶体管阵列结构，所述薄膜晶体管阵列结构包括源漏导电层；
    所述源漏导电层位于所述外延区的部分通过过孔电性连接于所述绑定导电层。
  7. 根据权利要求6所述的显示面板，其中，所述绑定导电层包括多条扇出走线和多个绑定端子，所述多条扇出走线电性连接于所述源漏导电层，所述绑定端子一一对应地连接于所述扇出走线，所述绑定端子电性连接所述外置的驱动芯片。
  8. 根据权利要求7所述的显示面板，其中，所述绑定模组还包括第一衬底结构，所述第一衬底结构设置在所述绑定导电层背向所述显示模组的一侧，所述第一衬底结构上开设有一开口，所述开口对应所述多个绑定端子设置，且裸露出所述多个绑定端子。
  9. 根据权利要求8所述的显示面板，其中，所述第一衬底结构包括支撑层和第一柔性衬底，所述第一柔性衬底设置在所述支撑层和所述绑定导电层之间。
  10. 根据权利要求9所述的显示面板，其中，所述显示模组还包括第二衬底结构，所述第二衬底结构设置在所述绑定模组和所述薄膜晶体管阵列结构之间；
    所述薄膜晶体管阵列结构还包括依次设置在所述第二衬底结构上的有源层、第一绝缘层、第一栅极导电层、第二绝缘层、第二栅极导电层、介电层和平坦层，所述源漏导电层设置在所述介电层和所述平坦层之间；
    所述过孔位于所述外延区，所述过孔贯穿所述介电层、第二绝缘层、第一绝缘层、第二衬底结构，且连接于所述扇出走线。
  11. 根据权利要求10所述的显示面板，其中，所述第二衬底结构包括依次设置在所述绑定导电层上的第一阻挡层、第二柔性衬底、第二阻挡层和缓冲层。
  12. 一种显示面板的制备方法，其中，包括以下步骤：
    提供一基板，所述基板包括显示区和设置在所述显示区外侧的外延区；
    在所述基板上形成绑定导电层，所述绑定导电层覆盖所述显示区和外延区，所述绑定导电层电性连接于外置的驱动芯片；
    在所述绑定导电层上形成显示模组，所述显示模组覆盖所述显示区和外延区，所述显示模组包括薄膜晶体管阵列结构，所述薄膜晶体管阵列结构包括源漏导电层；所述源漏导电层位于所述外延区的部分通过过孔电性连接于所述绑定导电层。
  13. 根据权利要求12所述的显示面板的制备方法，其中，所述绑定导电层包括多条扇出走线和多个绑定端子，所述多条扇出走线电性连接于所述源漏导电层，所述绑定端子一一对应地连接于所述扇出走线，所述绑定端子电性连接所述外置的驱动芯片。
  14. 根据权利要求13所述的显示面板的制备方法，其中，所述在所述绑定导电层上形成显示模组，包括以下步骤：
    在所述绑定导电层上形成第二衬底结构；
    在所述第二衬底结构上依次形成有源层、第一绝缘层、第一栅极导电层、第二绝缘层、第二栅极导电层和介电层；
    对所述介电层位于所述外延区的部分进行图案化处理，以形成过孔，所述过孔贯穿所述介电层、第二绝缘层、第一绝缘层和第二衬底结构；
    在所述介电层上依次形成所述源漏导电层和平坦层，所述源漏导电层的部分填充所述过孔，并连接于所述扇出走线。
  15. 根据权利要求13所述的显示面板的制备方法，其中，所述在所述基板上形成绑定导电层，之前还包括以下步骤：在所述基板上形成第一柔性衬底；
    所述在所述绑定导电层上形成显示模组，之后还包括以下步骤：
    剥离所述基板；
    在所述第一柔性衬底背向所述显示模组的一侧贴合支撑层，所述第一柔性衬底和支撑层形成第一衬底结构；
    在所述第一衬底结构对应于所述多个绑定端子的区域进行开孔处理，以露出所述多个绑定端子。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111584562A (zh) * 2020-05-08 2020-08-25 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN112185984B (zh) * 2020-09-17 2022-07-12 武汉华星光电半导体显示技术有限公司 一种阵列基板及显示面板
CN112701129B (zh) * 2021-01-07 2023-10-31 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
KR20220129141A (ko) * 2021-03-15 2022-09-23 삼성디스플레이 주식회사 표시 장치 및 이를 포함하는 타일형 표시 장치
CN113488577A (zh) * 2021-06-25 2021-10-08 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法
CN116096168A (zh) * 2021-11-02 2023-05-09 武汉华星光电半导体显示技术有限公司 显示面板和显示装置
CN114188381B (zh) * 2021-12-03 2023-05-09 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN114067694A (zh) * 2021-12-08 2022-02-18 Tcl华星光电技术有限公司 显示母板及其制备方法
CN114220822A (zh) * 2021-12-13 2022-03-22 武汉华星光电半导体显示技术有限公司 显示面板、拼接屏

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002040465A (ja) * 2000-07-31 2002-02-06 Seiko Epson Corp 液晶装置および電子機器
CN202816322U (zh) * 2012-09-19 2013-03-20 深圳市柔宇科技有限公司 一种显示屏
CN104992956A (zh) * 2015-05-15 2015-10-21 深圳市华星光电技术有限公司 无边框显示装置及其制作方法
CN107833978A (zh) * 2017-10-31 2018-03-23 昆山国显光电有限公司 一种显示器件
CN108155220A (zh) * 2018-01-29 2018-06-12 武汉华星光电半导体显示技术有限公司 显示装置及其制造方法、显示面板
CN207517684U (zh) * 2017-11-30 2018-06-19 云谷（固安）科技有限公司 阵列基板及显示屏
CN109872637A (zh) * 2019-04-02 2019-06-11 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制作方法、显示装置
CN110010627A (zh) * 2019-04-12 2019-07-12 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
US20190271873A1 (en) * 2018-03-01 2019-09-05 Panasonic Liquid Crystal Display Co., Ltd. Display device and manufacturing method for display device
CN110518054A (zh) * 2019-03-05 2019-11-29 友达光电股份有限公司 显示装置及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI532162B (zh) * 2013-06-25 2016-05-01 友達光電股份有限公司 可撓式顯示面板及其製造方法
KR20180100013A (ko) * 2017-02-28 2018-09-06 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
CN110034150B (zh) * 2019-03-25 2020-11-27 厦门天马微电子有限公司 显示面板及其制作方法、显示装置
CN110310575A (zh) * 2019-06-28 2019-10-08 云谷（固安）科技有限公司 一种显示面板及其制作方法和显示装置
CN111584562A (zh) * 2020-05-08 2020-08-25 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002040465A (ja) * 2000-07-31 2002-02-06 Seiko Epson Corp 液晶装置および電子機器
CN202816322U (zh) * 2012-09-19 2013-03-20 深圳市柔宇科技有限公司 一种显示屏
CN104992956A (zh) * 2015-05-15 2015-10-21 深圳市华星光电技术有限公司 无边框显示装置及其制作方法
CN107833978A (zh) * 2017-10-31 2018-03-23 昆山国显光电有限公司 一种显示器件
CN207517684U (zh) * 2017-11-30 2018-06-19 云谷（固安）科技有限公司 阵列基板及显示屏
CN108155220A (zh) * 2018-01-29 2018-06-12 武汉华星光电半导体显示技术有限公司 显示装置及其制造方法、显示面板
US20190271873A1 (en) * 2018-03-01 2019-09-05 Panasonic Liquid Crystal Display Co., Ltd. Display device and manufacturing method for display device
CN110518054A (zh) * 2019-03-05 2019-11-29 友达光电股份有限公司 显示装置及其制造方法
CN109872637A (zh) * 2019-04-02 2019-06-11 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制作方法、显示装置
CN110010627A (zh) * 2019-04-12 2019-07-12 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

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