WO2021215445A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2021215445A1
WO2021215445A1 PCT/JP2021/016068 JP2021016068W WO2021215445A1 WO 2021215445 A1 WO2021215445 A1 WO 2021215445A1 JP 2021016068 W JP2021016068 W JP 2021016068W WO 2021215445 A1 WO2021215445 A1 WO 2021215445A1
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Prior art keywords
layer
mosfet
gate
trench
semiconductor device
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PCT/JP2021/016068
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English (en)
French (fr)
Japanese (ja)
Inventor
河野　憲司
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Denso Corp
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Denso Corp
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Priority to CN202180029678.0A priority Critical patent/CN115485856A/zh
Publication of WO2021215445A1 publication Critical patent/WO2021215445A1/ja
Priority to US17/969,023 priority patent/US20230038806A1/en
Anticipated expiration legal-status Critical
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    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
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    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
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    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0051—Diode reverse recovery losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K2017/6875—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors using self-conductive, depletion FETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/117—Shapes of semiconductor bodies

Definitions

  • the present disclosure relates to a semiconductor device having a MOSFET having a trench gate structure (abbreviation for Metal Oxide Semiconductor Field Effect Transistor).
  • the MOSFET of this semiconductor device is configured by using a semiconductor substrate that constitutes an N-type drift layer.
  • a channel layer is formed on one side of the semiconductor substrate, and a plurality of trenches are formed so as to penetrate the channel layer and reach the drift layer.
  • Each trench is extended so that one direction in the surface direction of the semiconductor substrate is the longitudinal direction.
  • a trench gate structure is formed by forming a gate insulating film and a gate electrode in each trench in order.
  • An N + type source region is formed on the surface layer of the channel layer so as to be in contact with the trench.
  • An N + type drain layer is formed on the other surface side of the semiconductor substrate.
  • Non-Patent Document 1 describes a configuration in which a P-type impurity layer is arranged so as to cover a part of a portion of the trench that protrudes into the drift layer.
  • the object of the present disclosure is to provide a semiconductor device capable of sufficiently reducing recovery loss.
  • the MOSFET of the semiconductor device is formed into a first conductive type drift layer, a second conductive type channel layer arranged on the drift layer, and a drift layer penetrating the channel layer.
  • a trench gate structure having a gate insulating film arranged on the wall surface of the trench formed so as to reach, a gate electrode arranged on the gate insulating film, and a surface layer portion of the channel layer formed so as to be in contact with the trench.
  • the first conductive type source layer having a higher impurity concentration than the drift layer, the first conductive type drain layer arranged on the opposite side of the drift layer from the channel layer, the channel layer, the source layer, and electricity.
  • a source electrode that is specifically connected and a drain electrode that is electrically connected to the drain layer are provided, and the entire region of the trench that reaches the drift layer is a well layer of the second conductive type. It is covered and the well layer is connected to the channel layer.
  • the entire region of the trench protruding into the drift layer is covered with a well layer. Therefore, it is possible to suppress the occurrence of electric field concentration at the bottom of the trench, and it is possible to suppress the generation of holes by the dynamic avalanche. Therefore, the recovery loss can be reduced.
  • the semiconductor device of the present embodiment includes a normally-on type junction FET (Field Effect Transistor: hereinafter simply referred to as JFET) 10 and a normally-off type MOSFET 20.
  • the semiconductor device is configured by cascode-connecting the JFET 10 and the MOSFET 20.
  • the JFET 10 and the MOSFET 20 are each N-channel type.
  • the JFET 10 has a source electrode 11, a drain electrode 12, and a gate layer (that is, a gate electrode) 13, although a specific configuration will be described later.
  • the MOSFET 20 has a source electrode 21, a drain electrode 22, and a gate electrode 23, although the specific configuration will be described later.
  • the source electrode 11 of the JFET 10 and the drain electrode 22 of the MOSFET 20 are electrically connected. Further, the drain electrode 12 of the JFET 10 is connected to the first terminal 31, and the source electrode 21 of the MOSFET 20 is connected to the second terminal 32.
  • the gate electrode 23 of the MOSFET 20 is connected to the gate drive circuit 50 via a gate pad 24 and an adjustment resistor 41.
  • the gate layer 13 of the JFET 10 is electrically connected to the source electrode 21 of the MOSFET 20 via the gate pad 14.
  • the diode 15 is connected between the drain electrode 12 and the source electrode 11 of the JFET 10. Specifically, as will be described later, in the present embodiment, as shown in FIG. 4, a P-type body layer 115 is formed in the N-type channel layer 114 in the JFET 10. The diode 15 is configured to include the body layer 115. In this diode 15, the cathode is electrically connected to the drain electrode 12, and the anode is electrically connected to the source electrode 11.
  • a diode 25 is connected between the drain electrode 22 and the source electrode 21 of the MOSFET 20.
  • the diode 25 is a parasitic diode formed in the configuration of the MOSFET 20, and the cathode is electrically connected to the drain electrode 22 and the anode is electrically connected to the source electrode 21.
  • the first terminal 31 is connected to the power supply line 61 to which the voltage Vcc is applied from the power supply 60, and the second terminal 32 is connected to the ground line 62 for use.
  • the JFET 10 is formed on the first semiconductor chip 100 as shown in FIG.
  • the first semiconductor chip 100 has a rectangular shape in a plane, and has a cell region 101 having an inner edge cell region 101a and an outer edge cell region 101b surrounding the inner edge cell region 101a, and a cell region 101. It has an outer peripheral region 102 that surrounds the cell region 101. Then, the JFET 10 is formed in the cell region 101.
  • the first semiconductor chip 100 includes a semiconductor substrate 110 having a drain layer 111 composed of an N ++ type silicon carbide (hereinafter referred to as SiC) substrate.
  • SiC N ++ type silicon carbide
  • I have.
  • An N + type buffer layer 112 having a lower impurity concentration than the drain layer 111 is arranged on the drain layer 111, and N having a lower impurity concentration than the buffer layer 112 is placed on the buffer layer 112.
  • a ⁇ type drift layer 113 is arranged.
  • the buffer layer 112 and the drift layer 113 are configured by growing an epitaxial film of SiC on a SiC substrate constituting the drain layer 111.
  • a channel layer 114, a gate layer 13, a body layer 115, and a source layer 116 are formed on the one side 110a side of the semiconductor substrate 110.
  • an N-type channel layer 114 having a higher impurity concentration than the drift layer 113 is arranged on the drift layer 113.
  • the channel layer 114 is formed by, for example, growing an epitaxial film of SiC.
  • One side 110a of the semiconductor substrate 110 is configured to include the surface of the channel layer 114.
  • the channel layer 114 is formed with a P + type gate layer 13 and a P + type body layer 115 having a higher impurity concentration than the channel layer 114.
  • the gate layer 13 and the body layer 115 have the same impurity concentration and are formed along the depth direction from one surface 110a (that is, the surface of the channel layer 114) of the semiconductor substrate 110.
  • the body layer 115 is formed deeper than the gate layer 13. That is, the body layer 115 is configured to protrude toward the drain layer 111 side from the gate layer 13.
  • the gate layer 13 and the body layer 115 are extended along one direction in the plane direction of the semiconductor substrate 110, and are alternately arranged in the plane direction and in the direction orthogonal to the extending direction. That is, in FIG. 4, the gate layer 13 and the body layer 115 are extended along the vertical direction of the paper surface, and are alternately arranged in a state of being separated from each other along the left-right direction of the paper surface.
  • the depth direction of the semiconductor substrate 110 can be said to be the stacking direction of the drain layer 111, the drift layer 113, and the channel layer 114.
  • the gate layer 13 and the body layer 115 are configured by, for example, ion implantation or growth of a SiC embedded epitaxial film.
  • the gate layer 13 extends from the inner edge cell region 101a to the outer edge cell region 101b.
  • the gate layer 13 has an annular structure by being routed at both ends in the extending direction located in the outer edge cell region 101b, and the annular structure is connected to each other. Therefore, it can be said that the body layer 115 in FIG. 4 is arranged in the region on the inner edge side of the gate layer 13 having an annular structure.
  • the body layer 115 is also formed in the outer edge cell region 101b, and as will be described later, a plurality of body layers 115 are formed in the outer peripheral region 102. It is connected to one of the guard rings 121 of.
  • an N + type source layer 116 having a higher impurity concentration than the channel layer 114 is formed on the surface layer portion of the channel layer 114 so as to be in contact with the body layer 115. ..
  • the source layer 116 is formed by, for example, ion implantation.
  • a gate that electrically connects the gate pad 14 and the gate pad 14 and the gate layer 13 to the outer edge cell region 101b.
  • Wiring 118 is formed.
  • the first semiconductor chip 100 is also formed with a temperature sense, a current sense, and the like.
  • a pad 16 electrically connected to these various senses and a wiring are also formed.
  • an interlayer insulating film 119 is formed on one surface 110a of the semiconductor substrate 110 so as to cover the gate wiring 118.
  • the interlayer insulating film 119 is formed in the cell region 101 and the outer peripheral region 102.
  • a contact hole 119a is formed in the interlayer insulating film 119 to expose the channel layer 114, the body layer 115, and the source layer 116 in the cell region 101.
  • a source electrode 11 that is electrically connected to the source layer 116 and the body layer 115 is formed on the interlayer insulating film 119 through the contact hole 119a.
  • a drain electrode 12 electrically connected to the drain layer 111 is formed on the other surface 110b side of the semiconductor substrate 110.
  • the outer peripheral region 102 has a mesa structure by forming a recess 120 for removing a portion corresponding to the channel layer 114 of the cell region 101.
  • a plurality of guard rings 121 having a multi-ring structure surrounding the cell region 101 are formed in the outer peripheral region 102.
  • one of the plurality of guard rings 121 on the most cell region 101 side is electrically connected to the body layer 115 formed in the outer edge cell region 101b, but is electrically connected. It does not have to be.
  • the semiconductor substrate 110 includes the drain layer 111, the buffer layer 112, the drift layer 113, the channel layer 114, the body layer 115, the source layer 116, and the gate layer 13. .
  • the drain layer 111 is composed of a SiC substrate, and the buffer layer 112, the drift layer 113, the channel layer 114, and the like are configured by growing an epitaxial film of SiC. ing.
  • the first semiconductor chip 100 of the present embodiment is a SiC semiconductor device. Further, in the present embodiment, the first semiconductor chip 100 has a P-shaped body layer 115 formed therein. The diode 15 in FIG. 1 is formed by the body layer 115.
  • the MOSFET 20 is formed on the second semiconductor chip 200 as shown in FIG.
  • the second semiconductor chip 200 has a rectangular shape in a plane, and has a cell region 201 and an outer peripheral region 202 surrounding the cell region 201. Then, the MOSFET 20 is formed in the cell region 201.
  • the second semiconductor chip 200 includes a semiconductor substrate 210 having a drain layer 211 composed of an N + type silicon (hereinafter referred to as Si) substrate. ing.
  • An N-type drift layer 212 having a lower impurity concentration than the drain layer 211 is arranged on the drain layer 211.
  • a P-type channel layer 213 having a higher impurity concentration than the drift layer 212 is arranged on the drift layer 212.
  • a plurality of trenches 214 are formed so as to penetrate the channel layer 213 and reach the drift layer 212, and the channel layer 213 is separated into a plurality of pieces by the trench 214.
  • the plurality of trenches 214 are formed in stripes at equal intervals along one of the surface directions of one surface 210a of the semiconductor substrate 210 (that is, the depth direction of the paper surface in FIG. 8).
  • the plurality of trenches 214 may have an annular structure by being routed at the tip end portion.
  • each trench 214 is embedded by a gate insulating film 215 formed so as to cover the wall surface of each trench 214 and a gate electrode 23 formed of polysilicon or the like formed on the gate insulating film 215. It has been. As a result, a trench gate structure is constructed.
  • the channel layer 213 is formed with an N + type source layer 216 and a P + type contact layer 217 so as to be sandwiched between the source layers 216.
  • the source layer 216 is configured to have a higher impurity concentration than the drift layer 212, is terminated in the channel layer 213, and is formed so as to be in contact with the side surface of the trench 214.
  • the contact layer 217 is composed of a higher impurity concentration than the channel layer 213, and is formed so as to terminate in the channel layer 213 like the source layer 216.
  • the source layer 216 extends in a rod shape along the longitudinal direction of the trench 214 so as to be in contact with the side surface of the trench 214 in the region between the trenches 214, and terminates inside the tip of the trench 214.
  • the contact layer 217 is sandwiched between the two source layers 216 and extends in a rod shape along the longitudinal direction of the trench 214 (that is, the source layer 216).
  • the contact layer 217 of the present embodiment is formed deeper than the source layer 216 with reference to one surface 210a of the semiconductor substrate 210.
  • An interlayer insulating film 218 is formed on the channel layer 213 (that is, one side 210a of the semiconductor substrate 210).
  • the interlayer insulating film 218 is also formed in the outer peripheral region 202 as shown in FIG.
  • a contact hole 218a that exposes a part of the source layer 216 and the contact layer 217 is formed in the interlayer insulating film 218.
  • a source electrode 21 that is electrically connected to the source layer 216 and the contact layer 217 is formed on the interlayer insulating film 218 through the contact hole 218a.
  • a drain electrode 22 electrically connected to the drain layer 211 is formed on the other surface 210b side of the semiconductor substrate 210.
  • a gate pad 24, a gate wiring (not shown), and the like are formed in the outer peripheral region 202.
  • the gate wiring is appropriately electrically connected to the gate electrode 23 in a cross section different from that in FIGS. 8 and 9.
  • the second semiconductor chip 200 is also formed with a temperature sense, a current sense, and the like.
  • a pad 26 electrically connected to these various senses and wiring (not shown) are also formed in the outer peripheral region 202.
  • a P-shaped deep layer 220 is formed on the inner edge portion on the cell region 201 side so that the pressure resistance can be improved, and a plurality of P-shaped deep layers 220 are formed on the outer edge portion side of the deep layer 220.
  • P-shaped guard ring 221 is formed as a multiple ring structure.
  • the deep layer 220 of the present embodiment is connected to the channel layer 213 and is formed deeper than the channel layer 213.
  • a protective film 222 that covers the interlayer insulating film 218 is formed in the outer peripheral region 202, and an opening 222a that exposes the source electrode 21 is formed in the protective film 222.
  • the MOSFET 20 is configured as described above to form the diode 25 of FIG. 1, which is composed of the channel layer 213, the drift layer 212, and the drain layer 211.
  • a P-shaped well layer 223 along the wall surface of the trench 214 is formed in the entire region of the drift layer 212 in contact with the trench 214.
  • the portion of the trench 214 that protrudes into the drift layer 212 is in a state where the entire region is covered by the well layer 223.
  • the well layer 223 is formed so as to be connected to the channel layer 213.
  • the well layer 223 can suppress the generation of electric field concentration at the bottom of the trench 214, and the dynamic avalanche can suppress the generation of holes. Therefore, the recovery loss can be reduced.
  • the well layer 223 is formed by ion-implanting impurities such as boron into the wall surface of the trench 214 after forming the trench 214 and before forming the gate insulating film 215, the gate electrode 23, and the like. Will be done.
  • the MOSFET 20 when a predetermined gate voltage is applied to the gate electrode 23, an inversion layer that functions as a channel is formed in a portion of the channel layer 213 and the well layer 223 that is in contact with the trench 214. Turns on. In this case, if the impurity surface density of the well layer 223 is too high, channels may not be properly formed in the well layer 223, and the on-voltage may increase.
  • the present inventors further determine the surface density ratio of the impurity surface density of the well layer 223 to the impurity surface density of the drift layer 212 (hereinafter, also simply referred to as the surface density ratio), and the on-voltage and recovery loss.
  • the relationship was enthusiastically examined and the results shown in FIG. 10 were obtained.
  • the recovery loss is indicated by Err
  • the on-voltage is indicated by RonA.
  • the surface density ratio is the impurity surface density of the well layer 223 / the impurity surface density of the drift layer 212.
  • the recovery loss is reduced by forming the well layer 223. Specifically, it is confirmed that the recovery loss sharply decreases until the surface density ratio becomes 3.0 ⁇ 10-5. Then, it is confirmed that the recovery loss becomes almost constant when the surface density ratio is 3.0 ⁇ 10-5 or more.
  • the on-voltage is almost constant up to the surface density ratio of 4.0 ⁇ 10-5. Then, it is confirmed that the on-voltage gradually increases when the surface density ratio becomes larger than 4.0 ⁇ 10-5.
  • the intersection of the tangent line S1 at the portion having the smallest slope and the tangent line S2 at the portion having the largest slope at the on-voltage is a portion where the surface density ratio is 2.0 ⁇ 10 -4 . Therefore, it can be said that the on-voltage sharply increases when the surface density ratio becomes larger than 2.0 ⁇ 10 -4.
  • the surface density ratio is 3.0 ⁇ 10 -5 or more and 2.0 ⁇ 10 -4 or less. As a result, it is possible to suppress an increase in the on-voltage while reducing the recovery loss.
  • the surface density ratio is preferably 3.0 ⁇ 10-5 or more and 4.0 ⁇ 10-5 or less. As a result, it is possible to sufficiently suppress an increase in the on-voltage while reducing the recovery loss.
  • the semiconductor substrate 210 includes the drain layer 211, the drift layer 212, the channel layer 213, the source layer 216, the contact layer 217, and the well layer 223.
  • the second semiconductor chip 200 is configured by using the Si substrate as described above. Therefore, it can be said that the second semiconductor chip 200 is a Si semiconductor device.
  • the semiconductor device of the present embodiment is electrically connected so that the JFET 10 formed on the first semiconductor chip 100 and the MOSFET 20 formed on the second semiconductor chip 200 are cascode-connected. It is composed of.
  • the semiconductor device of the present embodiment has the MOSFET 20 which is normally off, it operates as a normal off as a whole.
  • a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 23 of the MOSFET 20 from the gate drive circuit 50.
  • the normally-off type MOSFET 20 is turned on.
  • the gate layer 13 is connected to the second terminal 32. Therefore, the normalion type JFET 10 is turned on because the potential difference between the gate layer 13 and the source electrode 11 becomes almost zero. Therefore, a current flows between the first terminal 31 and the second terminal 32, and the semiconductor device is finally turned on.
  • the gate voltage applied to the gate electrode 23 of the MOSFET 20 is set to be smaller than the threshold voltage (for example, set to 0V).
  • the threshold voltage for example, set to 0V
  • the normally-off type MOSFET 20 is turned off.
  • the MOSFET 20 when the MOSFET 20 is turned off, the voltage of the drain electrode 22 of the MOSFET 20 and the source electrode 11 of the JFET 10 connected to the drain electrode 22 rises, and the gate layer of the JFET 10 connected to the source electrode 11 and the second terminal 32.
  • a potential difference is generated between the two and the thirteenth.
  • the potential difference between the source electrode 11 and the gate layer 13 reaches the threshold value, the channel disappears and the JFET 10 is turned off.
  • the MOSFET 20 is in a state in which the entire region of the portion of the trench 214 protruding from the drift layer 212 is covered with the well layer 223. Therefore, it is possible to suppress the occurrence of electric field concentration at the bottom of the trench 214, and it is possible to suppress the generation of holes by the dynamic avalanche. Therefore, the recovery loss can be reduced.
  • the MOSFET 20 has a surface density ratio of 3.0 ⁇ 10 -5 or more and 2.0 ⁇ 10 -4 or less. As a result, it is possible to suppress an increase in the on-voltage while reducing the recovery loss.
  • the surface density ratio is preferably 3.0 ⁇ 10-5 or more and 4.0 ⁇ 10-5 or less. As a result, it is possible to sufficiently suppress an increase in the on-voltage while reducing the recovery loss.
  • the body layer 115 is deeper than the gate layer 13. Therefore, the electric field strength tends to be higher on the bottom side of the body layer 115 than on the bottom side of the gate layer 13. Therefore, when a surge occurs, breakdown is likely to occur in the region on the bottom side of the body layer 115, and the surge current is likely to flow into the body layer 115. As a result, it is possible to suppress the destruction of the semiconductor device due to the fusing of the gate wiring 118, and it is possible to improve the surge resistance.
  • the drift layer 212 has a super junction (hereinafter, also simply referred to as SJ) structure as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
  • SJ super junction
  • an N-type buffer layer 224 is formed on the drain 211 layer.
  • An N-type column region 212a and a P-type column region 212b as the drift layer 212 are formed on the buffer layer 224 so as to form an SJ structure.
  • the N-type column region 212a and the P-type column region 212b extend in one direction parallel to the plane direction of the semiconductor substrate 210 (that is, in the direction perpendicular to the paper surface in FIG. 11). Further, the N-type column region 212a and the P-type column region 212b are repeatedly arranged in a direction orthogonal to the one direction (that is, in the left-right direction on the paper surface in FIG. 11).
  • the N-type column region 212a and the P-type column region 212b are formed along the extending direction of the trench 214 and are repeatedly arranged along the arrangement direction of the trench 214.
  • the P-type column region 212b is connected to the channel layer 213.
  • the first embodiment can be applied to a semiconductor device having an SJ structure.
  • a third embodiment will be described.
  • an inverter is configured by using the semiconductor device of the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
  • the adjusting resistor 41 has the following configuration. That is, the adjusting resistor 41 is a first resistor circuit 411 in which the first diode 411a and the first resistor 411b are connected in series, and a second resistor circuit in which the second diode 412a and the second resistor 412b are connected in series. It is configured to have 412 and.
  • the first resistance circuit 411 and the second resistance circuit 412 are arranged in parallel so that the cathode of the first diode 411a and the anode of the second diode 412a are connected to the gate electrode 23 of the MOSFET 20, respectively.
  • the gate electrode 23 of the MOSFET 20 and the gate drive circuit 50 are connected via such an adjustment resistor 41. Therefore, the switching speed of the MOSFET 20 is adjusted by different resistance circuits in the case of switching on operation and the case of switching off operation.
  • the gate electrode 23 of the MOSFET 20 is in a state of being connected to the gate drive circuit 50 via the first resistance circuit 411 when the switching on operation is performed. That is, the first resistor circuit 411 functions as a speed adjusting resistor for the switching on operation of the MOSFET 20. Further, the gate electrode 23 of the MOSFET 20 is in a state of being connected to the gate drive circuit 50 via the second resistance circuit 412 during the switching off operation. That is, the second resistor circuit 412 functions as a speed adjusting resistor for the switching off operation of the MOSFET 20. Therefore, the switching speed of the MOSFET 20 can be appropriately adjusted by adjusting the resistance values of the respective resistance circuits 411 and 412.
  • Such a semiconductor device is used, for example, as a switching element of an inverter for driving a three-phase motor, as shown in FIG.
  • the inverter has three circuits of U phase, V phase, and W phase between the power supply line 610 to which the voltage Vcc from the power supply 600 is applied and the ground line 620 connected to the ground. It is said that the configuration is provided with.
  • Each layer is connected to the gate drive circuit 50 and the three-phase motor M, respectively.
  • the detailed configuration of the U layer will be described with reference to FIG. Since the detailed configurations of the V layer and the W layer are the same as those of the U layer, they will be omitted.
  • the U layer has a configuration in which the two semiconductor devices shown in FIG. 12 are provided. Then, in the U layer, the drain electrode 12 of the JFET 10 in the upper arm UA is connected to the power supply line 610 via the first terminal 31. In the U layer, the source electrode 21 of the MOSFET 20 in the lower arm LA is connected to the ground line 620 via the second terminal 32. Further, in the MOSFET 20 in the upper arm UA, the source electrode 21 is electrically connected to the drain electrode 12 of the JFET 10 in the lower arm LA. That is, the second terminal 32 of the upper arm UA is electrically connected to the first terminal 31 of the lower arm LA.
  • each MOSFET 20 in the upper arm UA and the lower arm LA is connected to the gate drive circuit 50.
  • the semiconductor device of this embodiment can also be used as a switching element of an inverter.
  • the first conductive type may be P type and the second conductive type may be N type. That is, the JFET 10 and the MOSFET 20 may be of the P channel type.
  • the semiconductor device in which the JFET 10 and the MOSFET 20 are cascode-connected has been described.
  • the semiconductor device may not be provided with the JFET 10 and may have only the MOSFET 20 having a trench gate structure.
  • the gate layer 13 and the body layer 115 may have the same depth. Further, the configuration in which the electric field strength is higher on the bottom side of the body layer 115 than on the bottom side of the gate layer 13 can be appropriately changed. For example, by making the bottom of the body layer 115 tapered or making the width of the body layer 115 narrower than the width of the gate layer 13, the electric field strength of the bottom side of the body layer 115 is higher than that of the bottom side of the gate layer 13. The configuration may be such that it is easy to become.
  • the JFET 10 may be configured by using a silicon substrate, or may be configured by using another compound semiconductor substrate or the like.
  • the MOSFET 20 may be configured using a SiC substrate or may be configured using another compound semiconductor substrate.
  • the drift layer 212 in the MOSFET 20 is set so that the impurity concentration gradually decreases from the drain layer 211 side to the channel layer 213 side so that a high withstand voltage can be achieved. You may.
  • the inverter may be configured by combining the second embodiment and the third embodiment and using the MOSFET 20 having the SJ structure. Moreover, you may further combine the combination of each of the above-mentioned embodiments.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Junction Field-Effect Transistors (AREA)
PCT/JP2021/016068 2020-04-22 2021-04-20 半導体装置 Ceased WO2021215445A1 (ja)

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