WO2021212333A1 - 显示装置、显示面板及其制造方法 - Google Patents

显示装置、显示面板及其制造方法 Download PDF

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Publication number
WO2021212333A1
WO2021212333A1 PCT/CN2020/085955 CN2020085955W WO2021212333A1 WO 2021212333 A1 WO2021212333 A1 WO 2021212333A1 CN 2020085955 W CN2020085955 W CN 2020085955W WO 2021212333 A1 WO2021212333 A1 WO 2021212333A1
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WO
WIPO (PCT)
Prior art keywords
layer
flat
substrate
electrode
display panel
Prior art date
Application number
PCT/CN2020/085955
Other languages
English (en)
French (fr)
Inventor
黄冠达
童慧
袁雄
申晓斌
王宇
王青
李世鹏
杨超
施尚权
董永发
李东升
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000564.9A priority Critical patent/CN113826233B/zh
Priority to PCT/CN2020/085955 priority patent/WO2021212333A1/zh
Priority to US17/264,446 priority patent/US11882731B2/en
Priority to PCT/CN2021/088701 priority patent/WO2021213439A1/zh
Priority to CN202310487217.9A priority patent/CN116963536A/zh
Priority to KR1020217016207A priority patent/KR20230002018A/ko
Priority to US17/428,326 priority patent/US20230165061A1/en
Priority to CN202180000830.2A priority patent/CN114097092B/zh
Priority to CN202310505881.1A priority patent/CN116782705A/zh
Priority to JP2021530217A priority patent/JP2023522135A/ja
Priority to EP21726546.1A priority patent/EP4141944A4/en
Priority to CN202310485818.6A priority patent/CN116709834A/zh
Publication of WO2021212333A1 publication Critical patent/WO2021212333A1/zh
Priority to US18/336,196 priority patent/US20230329044A1/en
Priority to US18/336,892 priority patent/US20230337474A1/en
Priority to US18/336,883 priority patent/US20230337473A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device, a display panel, and a manufacturing method of the display panel.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • the light-emitting device usually includes a plurality of OLED light-emitting devices distributed in an array, and each light-emitting device can emit light independently in order to display images.
  • the luminescence stability of the OLED light-emitting device still needs to be improved.
  • the purpose of the present disclosure is to provide a display device, a display panel, and a manufacturing method of the display panel, which can improve the stability of light emission.
  • a display panel including:
  • a flat layer is provided on one side of the substrate, and a surface of the flat layer facing away from the substrate is provided with a plurality of separation grooves to divide a plurality of driving regions distributed in an array;
  • the first electrode layer is provided on the surface of the flat layer facing away from the substrate and includes a plurality of first electrodes; the orthographic projection of each of the first electrodes on the flat layer corresponds to each of the driving Within the region; the first electrode includes a flat middle part and an edge part surrounding the middle part; the edge part includes a flat part surrounding the middle part and connected between the middle part and the flat part The climbing part, the thickness of the flat part is smaller than the middle part;
  • a pixel definition layer arranged on the surface of the flat layer away from the substrate, and exposing at least a part of the middle portion;
  • a light-emitting functional layer covering the pixel defining layer and the intermediate portion and the flat layer exposed by the pixel defining layer;
  • the second electrode covers the light-emitting function layer.
  • the maximum depth of the separation groove is not less than 30% of the sum of the thicknesses of the light-emitting function layer and the first electrode.
  • the maximum depth of the separation groove is not more than 60% of the sum of the thicknesses of the light-emitting function layer and the first electrode.
  • the maximum depth of the separation groove is
  • the separation groove includes two opposite side walls and a bottom surface connected between the two side walls, and the maximum distance between the two side walls is 0.2 ⁇ m- 0.7 ⁇ m.
  • the separation groove includes two opposite side walls and a bottom surface connected between the two side walls, and the bottom surface is convex in a direction away from the substrate.
  • the curved surface is convex in a direction away from the substrate.
  • the separation groove includes two opposite side walls and a bottom surface connected between the two side walls; the two side walls are parallel.
  • the separation groove includes two opposite side walls and a bottom surface connected between the two side walls; the distance between the two side walls is close to the bottom surface The direction decreases.
  • the slope of the two side walls is not less than 70°.
  • the distance between the boundary of the orthographic projection of the substrate and the boundary of the projection of the driving area on the substrate of the intermediate portion is not less than 0.15 ⁇ m.
  • the distance between the boundary of the orthographic projection of the substrate and the driving area of the flat portion is greater than zero.
  • the pixel definition layer extends into the separation groove and is recessed in a region corresponding to the separation groove.
  • a display panel including:
  • the flat layer is provided on one side of the substrate
  • the first electrode layer is provided on the surface of the flat layer facing away from the substrate and includes a plurality of first electrodes; the first electrode includes a flat middle part and an edge part surrounding the middle part; the edge The part includes a flat part surrounding the middle part and a climbing part connected between the middle part and the flat part, the thickness of the flat part is smaller than the middle part;
  • the second electrode covers the light-emitting functional layer, and includes a recessed portion and a plurality of smooth portions separated by the recessed portion, and the orthographic projection of each smooth portion on the flat layer corresponds to each of the Within the first electrode; the recessed portion is recessed toward the side of the smooth portion close to the substrate, and the orthographic projection of the recessed portion on the flat layer is at least partially located outside the middle portion.
  • the orthographic projection of the lowest point of the recessed portion on the flat layer is located outside the middle portion.
  • the recessed portion includes a first side surface, a second side surface, and a bottom surface, the first side surface and the second side surface are relatively connected to both sides of the bottom surface, and The first side surface and the second side surface shrink in a direction approaching the substrate.
  • the bottom surface of the recess includes a first slope surface, a second slope surface, and a connecting surface connected between the first slope surface and the second slope surface,
  • the connecting surface is located on a side of the first side surface and the bottom side of the second side surface away from the substrate, the first slope surface is connected to the bottom side of the first side surface, and the second slope The surface is connected with the bottom edge of the second side surface.
  • the slope of the first slope surface relative to the middle portion is not less than the slope of the first side surface relative to the middle portion
  • the slope of the second slope surface relative to the middle portion is not less than the slope of the second side surface relative to the middle portion.
  • the first slope surface and the second slope surface are symmetrical with respect to the connection surface, and the first side surface It is symmetrical to the second side surface with respect to the bottom surface.
  • the minimum thickness of the area of the second electrode corresponding to the first side surface and the second side surface is larger than that corresponding to the first slope surface and the second side surface. The minimum thickness of the slope area.
  • a surface of the flat layer facing away from the substrate is provided with a plurality of separation grooves to divide a plurality of driving regions distributed in an array, and each of the first electrodes is located in the The orthographic projection of the flat layer is located within each of the first electrodes in a one-to-one correspondence;
  • the display panel also includes:
  • the pixel definition layer is provided on the surface of the flat layer facing away from the substrate, and at least part of the area of the middle part is exposed; at least part of the area of the recessed part in the orthographic projection of the flat layer is located in the separation groove Inside.
  • the display panel further includes:
  • the first encapsulation layer covers the second electrode and forms a pit in a region corresponding to the recessed portion.
  • the two sidewalls of the pit are narrowed and connected in a direction approaching the substrate.
  • a method of manufacturing a display panel including:
  • a first electrode layer including a plurality of first electrodes is formed on the surface of the flat layer facing away from the substrate; the orthographic projection of each of the first electrodes on the flat layer is located within each of the driving regions in a one-to-one correspondence
  • the first electrode includes a flat middle part and an edge part surrounding the middle part; the edge part includes a flat part surrounding the middle part and a climb connected between the middle part and the flat part Slope portion, the thickness of the flat portion is smaller than the middle portion;
  • a second electrode covering the light-emitting function layer is formed.
  • a method of manufacturing a display panel including:
  • a first electrode layer including a plurality of first electrodes and a separation layer are formed on the surface of the flat layer facing away from the substrate;
  • the first electrode includes a flat middle part and an edge part surrounding the middle part;
  • the edge part includes a flat part surrounding the middle part and a climbing part connected between the middle part and the flat part, the thickness of the flat part is smaller than the middle part;
  • the separation groove is in the flat part
  • the layer is divided into a plurality of driving regions distributed in an array; each of the first electrodes is located within each of the driving regions in a one-to-one correspondence with the orthographic projection of the flat layer;
  • a second electrode covering the light-emitting function layer is formed.
  • a method of manufacturing a display panel including:
  • a first electrode layer including a plurality of first electrodes is formed on the surface of the flat layer facing away from the substrate;
  • the first electrode includes a flat middle part and an edge part surrounding the middle part;
  • the edge part includes A flat part surrounding the middle part and a climbing part connected between the middle part and the flat part, the thickness of the flat part is smaller than the middle part;
  • a second electrode covering the light-emitting function layer is formed, the second electrode includes a recessed portion and a plurality of smooth portions separated by the recessed portion, and the orthographic projection of each smooth portion on the flat layer corresponds to one-to-one ⁇ is located within each of the first electrodes; the recessed portion is recessed toward the side of the smooth portion close to the substrate, and the orthographic projection of the recessed portion on the flat layer is at least partially located outside the middle portion .
  • a display device including the display panel described in any one of the above.
  • FIG. 1 is a schematic diagram of an embodiment of the first display panel of the present disclosure.
  • FIG. 2 is a partial electron micrograph of an embodiment of the first display panel of the present disclosure.
  • FIG. 3 is a schematic diagram of another embodiment of the first display panel of the present disclosure.
  • FIG. 4 is a schematic diagram of still another embodiment of the first display panel of the present disclosure.
  • FIG. 5 is a top view of a pixel definition layer in an embodiment of the first display panel of the present disclosure.
  • FIG. 6 is a top view of a pixel defining layer and a first electrode in an embodiment of the first display panel of the present disclosure.
  • FIG. 7 is a schematic diagram of an embodiment of the second display panel of the present disclosure.
  • Fig. 8 is an enlarged view of part A in Fig. 7.
  • FIG. 9 is a partial electron micrograph of an embodiment of the second display panel of the present disclosure.
  • FIG. 10 is a schematic diagram of an embodiment of the first method of manufacturing a display panel of the present disclosure.
  • FIG. 11 is a schematic diagram of another embodiment of the first method of manufacturing a display panel of the present disclosure.
  • FIG. 12 is a schematic diagram of an embodiment of a method for manufacturing a second display panel of the present disclosure.
  • an OLED display panel includes a driving backplane, a plurality of first electrodes, a pixel definition layer, a light-emitting function layer, a second electrode, and a color film layer.
  • the first electrode array is distributed on the driving backplane; the pixel definition layer Set on the surface of the driving backplane where the first electrode is provided, and each first electrode is exposed; the light-emitting function layer covers the pixel definition layer and the surface of the first electrode facing away from the driving backplane, and the second electrode covers the light-emitting function layer facing away from the driving backplane
  • a plurality of light-emitting devices can be defined by the pixel definition layer.
  • the color filter layer is arranged on the side of the second electrode away from the driving backplane, and has a plurality of filter regions corresponding to each light-emitting device one by one, and each filter region and its corresponding light-emitting device can be used as a sub-pixel.
  • the thickness of the pixel definition layer is greater than that of the first electrode, when the light-emitting function layer is formed by the evaporation process, the light-emitting function layer will be recessed at the junction of the first electrode and the pixel definition layer, that is, at the edge of the light-emitting device, so that The second electrode correspondingly forms a recessed area, and the distance between the recessed area of the second electrode and the first electrode is relatively close, which is prone to tip discharge or even short circuit, which affects the stability of the light-emitting device and makes it difficult for the display panel to emit light stably.
  • the recessed area of the second electrode corresponds to the first electrode, and therefore also emits light.
  • the topography of the recessed area is a structure recessed toward the driving backplane, rather than a planar structure, the light is emitted within the range of the recessed area.
  • the light is in a scattered state, and at least part of the light is skewed toward adjacent sub-pixels, so that the light emission of the adjacent sub-pixels interferes with each other and affects the display effect.
  • the light-emitting function layer is recessed in the second electrode at the junction of the first electrode and the pixel definition layer, so that the second electrode forms a recessed area in the area corresponding to the recessed area, and the recessed area is directly opposite to the first electrode, that is, the recessed area is driving back.
  • the orthographic projection of the plate is located in the first electrode, so that a sharp discharge or even a short circuit may occur between the two.
  • the recessed area emits light, and because the shape of the recessed area is curved, the light emitted by the recessed area is in a scattered state, which interferes with the light emission of adjacent sub-pixels.
  • the light-emitting function layer is a continuous film layer, so that the sub-pixels are connected to each other, at least a part of the film layer (including but not limited to the hole injection layer) in the light-emitting function layer will cause the gap between adjacent sub-pixels. Produce crosstalk.
  • the light-emitting function layer includes a plurality of light-emitting unit layers, and two adjacent light-emitting unit layers are connected in series through a charge generation layer.
  • the charge generation layer has good charge conduction characteristics, which will cause crosstalk between adjacent sub-pixels and affect the light-emitting effect.
  • the embodiments of the present disclosure provide two kinds of display panels.
  • the display panel may include a substrate 1, a flat layer 2, a first electrode layer 3, a pixel definition layer 4, a light-emitting function layer 5 and a second electrode 6, wherein:
  • the planarization layer 2 is provided on the side of the substrate 1, and the surface of the planarization layer 2 facing away from the substrate 1 is provided with a plurality of separation grooves 201 to divide a plurality of driving regions 202 on the planarization layer 2, and the driving regions 202 are arranged in an array .
  • the first electrode layer 3 is provided on the surface of the flat layer 2 facing away from the substrate 1 and includes a plurality of first electrodes 31 distributed in an array. Each first electrode 31 is located in each driving area 202 in a one-to-one correspondence with the orthographic projection of the flat layer 2 Within.
  • the first electrode 31 includes a flat middle part 310 and an edge part 311 surrounding the middle part 310; the edge part 311 includes a flat part 3110 surrounding the middle part 310 and a climbing part 3111 connected between the middle part 310 and the flat part 3110,
  • the thickness of the flat portion 3110 is smaller than that of the middle portion 310.
  • the pixel definition layer 4 is disposed on the surface of the flat layer 2 away from the substrate 1 and exposes at least a part of the middle portion 310.
  • the light-emitting function layer 5 covers the pixel defining layer 4 and the intermediate portion 310 and the flat layer 2 exposed by the pixel defining layer 4.
  • the second electrode 6 covers the light-emitting function layer 5.
  • the area where the middle portion 310 of each first electrode 31 is exposed by the pixel defining layer 4 and its corresponding light-emitting function layer 5 and second electrode 6 can constitute a light-emitting device to emit light.
  • the orthographic projection of the first electrode 31 on the flat layer 2 is located within each driving area 202 in a one-to-one correspondence, so that the separation groove 201 is located outside the first electrode 31, when the light-emitting function layer 5 is formed, the light-emitting function layer 5 can be located in the separation groove
  • the position of 201 is recessed toward the substrate 1, so that the recess 61 formed by the second electrode 6 in the recess, and the orthographic projection of the recess 61 on the flat layer 2 is at least partially located outside the middle portion 310 of the first electrode 31, and also That is, it is located outside the light-emitting device.
  • the position of the recess 61 of the second electrode 6 can be restricted by the separation groove 201 to prevent the tip discharge or even a short circuit between the recess 61 and the middle portion 310, which is beneficial to ensure the light-emitting device. Stable light. At the same time, light emission within the range of the recess 61 can be reduced or even avoided, thereby reducing the mutual interference of the light emission of adjacent light-emitting devices.
  • FIG. 2 is a partial electron microscope diagram of an embodiment of the first display panel of the present disclosure.
  • the risk of sharp discharge between the first electrode 31 and the first electrode 31 is reduced. At the same time, it can reduce or even prevent the recess 61 from emitting light, and prevent interference to adjacent sub-pixels.
  • the material of the substrate 1 may be a semiconductor material such as single crystal silicon or polycrystalline silicon, or other hard or soft materials such as glass.
  • a plurality of driving transistors may be provided on the substrate 1 to drive each light-emitting device to emit light to display an image.
  • the display panel further includes a gate insulating layer 7, a gate electrode 8, a first insulating layer 9 and a first wiring layer 10.
  • the material of the substrate 1 can be monocrystalline silicon or Semiconductor materials such as polysilicon, and the substrate 1 includes an active region 101 and a source electrode 1011 and a drain electrode 1012 located at both ends of the active region 101.
  • the gate insulating layer 7 covers the active region 101; the gate 8 is provided on the surface of the gate insulating layer 7 away from the substrate 1, and the material of the gate 8 may include polysilicon material.
  • the first insulating layer 9 covers the gate 8 and the substrate 1, and its material may include at least one of silicon oxide and silicon nitride.
  • the first wiring layer 10 is provided on the surface of the first insulating layer 9 away from the substrate 1, and the gate electrode 8, the source electrode 1011 and the drain electrode 1012 are all connected to the first wiring layer 10 through via holes filled with tungsten or other metals .
  • the display panel may further include a second insulating layer 11 and a second wiring layer 12.
  • the second insulating layer 11 covers the first wiring layer 10 and the first insulating layer 9, and the second wiring layer 12 is provided on the second insulating layer.
  • the layer 11 is away from the surface of the substrate 1, the specific pattern of the second wiring layer 12 is not particularly limited here, and it can be connected to the first wiring layer 10 through via holes filled with tungsten or other metals.
  • the flat layer 2 is provided on one side of the substrate 1.
  • the flat layer 2 can cover the second wiring layer 12, and the first electrode 31 can be filled with tungsten or other metals.
  • the vias are connected to the second wiring layer 12.
  • the material of the flat layer 2 may include at least one of silicon nitride and silicon oxide, and of course, may also include other insulating materials.
  • the planarization layer 2 can be planarized by a polishing process.
  • the surface of the flat layer 2 facing away from the substrate 1 can be provided with a plurality of separation grooves 201, and the depth of the separation groove 201 is smaller than the thickness of the flat layer 2, that is, the separation groove 201 does not penetrate the flat layer 2 in the depth direction.
  • a plurality of driving regions 202 can be divided on the flat layer 2 by the separation grooves 201, and the driving regions 202 are arranged in an array.
  • the shape of the orthographic projection of the driving area 202 on the substrate 1 may be a rectangle, a pentagon, a hexagon or other polygons. Of course, it may also be a circle or other shapes, which is not specifically limited here. At the same time, the shape and size of different driving regions 202 may be different.
  • the separation groove 201 may include a first separation groove and a second separation groove, wherein the number of the first separation groove is multiple, and each first separation groove extends linearly along the first direction , And distributed along the second direction at intervals; the number of the second partition grooves is multiple, and each second partition groove extends linearly along the second direction, and is distributed at intervals along the first direction; the first direction and the second direction cross each other For example, the first direction and the second direction are mutually perpendicular directions. In this way, a plurality of driving regions 202 distributed in an array can be divided on the flat layer 2 by the staggered first partition grooves and second partition grooves.
  • the first separation groove and the second separation groove may also extend along a curved or broken line track, thereby dividing the driving area 202 with other shapes.
  • Each separation groove 201 may include two opposite side walls 2011 and a bottom wall 2012 connected between the two side walls 2011.
  • the two sidewalls 2011 may be arranged in parallel, that is, in a direction perpendicular to the substrate 1, the two sidewalls 2011 and their extension surfaces do not intersect.
  • the two side walls 2011 may also be arranged at a certain angle.
  • the bottom wall 2012 may be approximately parallel to the surface of the flat layer 2 facing away from the substrate 1, or, as shown in FIG. 1, the bottom wall 2012 may also be a convex curved surface in a direction away from the substrate 1.
  • the curvature and shape of is not specifically limited here, and in the section perpendicular to the substrate 1, the contour of the bottom wall 2012 can be roughly arc-shaped, parabolic or wavy. Of course, it can also be other regular or irregular shapes. The regular shape only needs to be convex in the direction away from the substrate 1.
  • the two side walls 2011 shrink toward the bottom wall 2012, that is, the distance between the two side walls 2011 gradually decreases toward the bottom wall 2012, so that the side walls 2011 are relatively flat.
  • the slope of the surface of the layer 2 away from the substrate 1 is the angle between the sidewall 2011 and the surface of the flat layer 2 away from the substrate 1. Further, the slope is not less than 70° and not more than 90°, for example, the slope may be 70°, 80°, 90°, and so on.
  • the maximum distance S between the two sidewalls 2011 of the separation groove 201 may be 0.2 ⁇ m-0.7 ⁇ m, such as 0.2 ⁇ m 0.3 ⁇ m, 0.5 ⁇ m, or 0.7 ⁇ m.
  • the first electrode layer 3 is disposed on the surface of the flat layer 2 facing away from the substrate 1, and includes a plurality of first electrodes 31 distributed in an array, and the orthographic projection of each first electrode 31 on the flat layer 2 corresponds one to one.
  • each driving area 202 that is, the boundary of the orthographic projection of each first electrode 31 on the substrate 1 is located within the boundary of the orthographic projection of each driving area 202 on the substrate 1 in a one-to-one correspondence.
  • Only one first electrode 31 is provided on each driving area 202. Since the driving area 202 is separated by the separation groove 201 and the first electrode 31 is located on the driving area 202, the separation groove 201 is located outside the first electrode 31.
  • the shape of the orthographic projection of each first electrode 31 on the flat layer 2 may be the same as the shape of the driving area 202 where it is located, and the boundary of the first electrode 31 is located within the driving area 202 where it is located.
  • the at least one first electrode 31 may include a middle part 310 and an edge part 311 surrounding the middle part 310.
  • the middle part 310 has a flat structure, that is, the middle part 310 and the flat layer 2 are away from the substrate. The surfaces of 1 are roughly parallel.
  • the boundary of the orthographic projection of the intermediate portion 310 of each first electrode 31 on the substrate 1 may be located within the boundary of the orthographic projection of the driving area 202 on the substrate 1, that is, the middle
  • the boundary of the orthographic projection of the portion 310 on the substrate 1 and the boundary of the orthographic projection of the driving area 202 on the substrate 1 has a distance L that is not zero. Further, the distance L is not less than 0.15 ⁇ m, for example, the distance may be 0.15 ⁇ m, 0.2 ⁇ m, 0.25 ⁇ m, or the like.
  • the edge portion 311 may include a flat portion 3110 and a climbing portion 3111, wherein the flat portion 3110 is located on the surface of the flat layer 2 facing away from the substrate 1 and arranged around the middle portion 310, and the flat portion 3110 and the flat layer 2 facing away from the substrate 1 The surfaces are roughly parallel. At the same time, the thickness of the flat portion 3110 is smaller than the thickness of the middle portion 310.
  • the flat portion 3110 has a non-zero distance between the boundary of the orthographic projection of the substrate 1 and the boundary of the driving area 202 on the substrate 1 where it is located. Of course, the boundary of the orthographic projection of the flat portion 3110 on the substrate 1 overlaps the boundary of the orthographic projection of the driving area 202 on the substrate 1 where it is located.
  • the climbing part 3111 is connected between the middle part 310 and the flat part 3110, that is, the climbing part 3111 surrounds the middle part 310, and the flat part 3110 is arranged around the climbing part 3111.
  • the slope of the climbing portion 3111 relative to the surface of the flat layer 2 facing away from the substrate 1 is not less than 30°, and the slope is the surface of the climbing portion 3111 and the surface of the flat layer 2 facing away from the substrate 1 ⁇ The included angle.
  • the first electrode 31 includes a first conductive layer 320, a second conductive layer 321, and a third conductive layer 322.
  • the first conductive layer 320 is provided on the surface of the flat layer 2 away from the substrate 1, and the second conductive layer 321 is provided on the first conductive layer.
  • the layer 320 is away from the surface of the substrate 1, and the third conductive layer 322 is provided on the surface of the second conductive layer 321 away from the substrate 1, and extends to the flat layer 2 at a certain slope, thereby covering the first conductive layer 320 and the second conductive layer.
  • the conductive layer 321 protects the first conductive layer 320 and the second conductive layer 321.
  • the middle portion 310 of the first electrode 31 includes the third conductive layer 322 located in the area of the second conductive layer 321 away from the surface of the substrate 1 and the first conductive layer 320 and the second conductive layer 321, and the edge portion 311 includes the third conductive layer 322
  • the area covering the edges of the first conductive layer 320 and the second conductive layer 321 is the area extending toward the flat layer 2.
  • the material of the first conductive layer 320 may include titanium (Ti)
  • the material of the second conductive layer 321 includes silver (Ag)
  • the material of the third conductive layer 322 includes indium tin oxide (ITO). Of course, it may also be Use other materials.
  • the pixel definition layer 4 is made of insulating material, and is provided on the surface of the flat layer 2 away from the substrate 1 with the first electrode layer 3. At the same time, the pixel definition layer 4 exposes at least a part of the middle portion 310 of the first electrode 31, and the middle portion 310 exposed by the pixel definition layer 4 can form a light emitting device with the corresponding light emitting function layer 5 and the second electrode 6.
  • each first electrode 31 does not completely cover the driving area 202 in which it is located, and the boundary of the orthographic projection of the flat portion 3110 of the first electrode 31 on the substrate 1 and the driving area 202 in which it is located
  • the boundary of the orthographic projection of the substrate 1 has a certain distance.
  • the pixel definition layer 4 extends to the side walls 2011 and the bottom wall 2012 of the separation groove 201, that is, the pixel definition layer 4 is conformally attached to the driving area 202 not covered by the first electrode 31, so that the pixel definition layer 4 is in the corresponding separation groove 201
  • the area is sunken.
  • the pixel definition layer 4 is provided with a plurality of openings 401 that expose at least a part of each middle portion 310 in a one-to-one correspondence, so that the light-emitting range of the light-emitting device can be defined by the pixel definition layer 4.
  • the opening 401 of the pixel definition layer 4 may have a hexagonal or other polygonal structure
  • the first electrode 31 may also have a polygonal structure, and is connected to the opening 401.
  • the shape is the same.
  • the first electrode 31 may also have other shapes.
  • the light-emitting functional layer 5 can be a continuous film layer, and at least partially covers the middle portion 310 of each first electrode 31, that is, covers the area exposed by the opening 401. At the same time, the light-emitting functional layer 5 also covers the pixel definition. In the areas of the layer 4 and the flat layer 2 not covered by the pixel definition layer 4 and the first electrode 31, when the light-emitting functional layer 5 is formed by evaporation or other processes, the light-emitting functional layer 5 is closer to the substrate in the area corresponding to the separation groove 201 The direction of 1 is recessed.
  • the light-emitting function layer 5 includes a multilayer light-emitting unit layer 501, and the hole injection layer, the hole transport layer, the light-emitting layer, and the electron transport layer of each light-emitting unit layer 501 Same as the distribution of the electron injection layer.
  • a charge generation layer 502 is provided between two adjacent light-emitting unit layers 501, so that the light-emitting unit layers 501 are connected in series through the charge generation layer 502, so as to form a series-type OLED light-emitting device.
  • the light-emitting function layer 5 includes a light-emitting unit layer, and the light-emitting unit layer includes a hole injection layer, a hole transport layer, Emitting layer, electron transport layer and electron injection layer.
  • the charge generation layer 502 cannot cover the sidewall 2011 of the separation groove 201, so that the charge generation layer 502 of the light-emitting device can be cut off by the separation groove 201 to avoid crosstalk between two adjacent light-emitting devices.
  • the separation groove 201 can also cut off the hole injection layer or other film layers, which can also prevent crosstalk.
  • the second electrode 6 covers the light-emitting functional layer 5, and can apply driving signals to the first electrode 31 and the second electrode 6, so that the light-emitting functional layer 5 is located between the first electrode 31 and the second electrode 6. Glow.
  • the topography of the second electrode 6 matches that of the light-emitting functional layer 5, which is recessed in the recess of the light-emitting functional layer 5 to form a recess 61, and a smooth portion 62 is formed in the region corresponding to the middle portion 310 of the first electrode 31,
  • the orthographic projection of the recessed portion 61 on the flat layer 2 is at least partially located outside the middle portion 310 of the first electrode 31 to reduce or avoid the tip discharge of the recessed portion 61 of the first electrode 31 and the second electrode 6.
  • the material of the second electrode 6 may be an alloy material.
  • the material of the second electrode 6 may include Mg and Ag; or, the second electrode 6 may also be an alloy of Al and Li.
  • the second electrode 6 can also use other alloys or elemental metals, which will not be listed here.
  • the smooth part 62 can be convex in the direction away from the substrate 1 in the area corresponding to the pixel definition layer 4 covering the middle part 310, but the height of the convexity is It is smaller than the thickness of the first middle portion 310 so that the smooth portion 62 is generally smooth.
  • the lowest point of the recess 61 of the second electrode 6 on the cross section perpendicular to the substrate 1 is completely located in the orthographic projection of the flat layer 2 Inside the separation groove 201, that is, completely outside the middle portion 310.
  • the separation groove 201 In order to ensure that the separation groove 201 can cut off the hole injection layer, the charge generation layer 502 or other film layers, the separation groove 201 should be made to have a certain depth, but the separation groove 201 should also be prevented from being too deep to penetrate the flat layer 2 and affecting Drive the device. Therefore, in some embodiments of the present disclosure, in the direction perpendicular to the substrate 1, the maximum depth H of the separation groove 201 is not less than 30% of the sum of the thicknesses of the light-emitting function layer 5 and the first electrode 31; at the same time, the separation groove The maximum depth H of 201 is not more than 60% of the sum of the thickness of the light-emitting function layer 5 and the first electrode 31.
  • the maximum depth of the separation groove 201 is: the point on the bottom wall 2012 of the separation groove 201 in the direction perpendicular to the substrate 1 and the surface of the flat layer 2 away from the substrate 1 with the largest distance and the flat layer 2 away from the substrate 1 The distance from the surface.
  • the maximum depth H of the separation groove 201 is
  • the first type of display panel may further include a first encapsulation layer 13, a color film layer 14, a second encapsulation layer 15, and a transparent cover plate 16, wherein:
  • the first encapsulation layer 13 may cover the second electrode 6.
  • the first encapsulation layer 13 may include two inorganic layers and an organic layer between the two inorganic layers.
  • the first encapsulation layer 13 may be recessed to form a pit 1301 in the region corresponding to the recess 61.
  • the first encapsulation layer 13 is away from the substrate 1
  • the surface can also be roughly flat
  • the color filter layer 14 is disposed on the side of the first encapsulation layer 13 away from the second electrode 6, and the color filter layer 14 includes filter regions corresponding to each first electrode 31 one by one.
  • the color filter regions have multiple colors, such as Red, blue and green.
  • the second encapsulation layer 15 can cover the color filter layer 14, and its structure can be the same as that of the first encapsulation layer 13.
  • the transparent cover plate 16 can cover the second encapsulation layer 15, and its material can be glass or material.
  • the first type of display panel may further include a light extraction layer 17, which covers the surface of the second electrode 6 away from the substrate 1, and is positioned on the surface of the second electrode 6 away from the substrate 1.
  • the area with the recess 61 is recessed, and the first encapsulation layer 13 is provided on the side of the light extraction layer 17 away from the substrate 1.
  • the refractive index of the light extraction layer 17 is greater than that of the second electrode 6, which can improve the light extraction efficiency, and the higher the refractive index, the higher the light extraction efficiency.
  • the second display panel of the present disclosure may include a substrate 1, a flat layer 2, a first electrode layer 3, a light-emitting function layer 5, and a second electrode 6, wherein:
  • the flat layer 2 is provided on the side of the substrate 1;
  • the first electrode layer 3 is provided on the surface of the flat layer 2 facing away from the substrate 1 and includes a plurality of first electrodes 31; the first electrode 31 includes a flat middle portion 310 and an edge portion 311 surrounding the middle portion 310; the edge portion 311 includes Surrounding the flat part 3110 of the middle part 310 and the climbing part 3111 connected between the middle part 310 and the flat part 3110, the thickness of the flat part 3110 is smaller than that of the middle part 310.
  • the light-emitting function layer 5 covers at least a part of the middle portion 310.
  • the second electrode 6 covers the light-emitting function layer 5, and includes a recess 61 and a plurality of smooth portions 62 separated by the recess 61.
  • the orthographic projection of each smooth portion 62 on the flat layer 2 corresponds to each first electrode 31.
  • the recessed portion 61 is recessed toward the side of the flat portion 62 close to the substrate 1, and the orthographic projection of the recessed portion 61 on the flat layer 2 is at least partially located outside the middle portion 310.
  • each first electrode 31 and its corresponding light-emitting function layer 5 and second electrode 6 can constitute a light-emitting device, which can emit light.
  • the gap between the concave portion 61 and the first electrode 31 can be reduced.
  • the risk of a sharp discharge occurring between the two is conducive to ensuring that the light-emitting device emits light stably.
  • the light emission within the range of the recessed portion 61 can be reduced, thereby reducing the mutual interference of the light emission of adjacent light-emitting devices.
  • a plurality of driving transistors may be provided on the substrate 1 to drive each light-emitting device to emit light to display an image.
  • the display panel further includes a gate insulating layer 7, a gate electrode 8, a first insulating layer 9 and a first wiring layer 10.
  • the material of the substrate 1 can be monocrystalline silicon or Semiconductor materials such as polysilicon, and the substrate 1 may include an active region 101 and a source electrode 1011 and a drain electrode 1012 located at both ends of the active region 101.
  • the gate insulating layer 7 covers the active region 101; the gate 8 is provided on the surface of the gate insulating layer 7 away from the substrate 1.
  • the first insulating layer 9 covers the gate 8 and the substrate 1, and its material may include at least one of silicon oxide and silicon nitride.
  • the first wiring layer 10 is provided on the surface of the first insulating layer 9 away from the substrate 1, and the gate electrode 8, the source electrode 1011 and the drain electrode 1012 are all connected to the first wiring layer 10 through via holes filled with tungsten or other metals .
  • the display panel may further include a second insulating layer 11 and a second wiring layer 12.
  • the second insulating layer 11 covers the first wiring layer 10 and the first insulating layer 9, and the second wiring layer 12 is provided on the second insulating layer.
  • the layer 11 is away from the surface of the substrate 1, the specific pattern of the second wiring layer 12 is not particularly limited here, and it can be connected to the first wiring layer 10 through via holes filled with tungsten or other metals.
  • the planarization layer 2 is provided on one side of the substrate 1.
  • the planarization layer 2 can cover the second wiring layer 12, and the first electrode 31 can be filled with tungsten or other metals.
  • the vias are connected to the second wiring layer 12.
  • the material of the flat layer 2 may include at least one of silicon nitride and silicon oxide, and of course, may also include other insulating materials.
  • the first electrode layer 3 is provided on the side of the flat layer 2 facing away from the substrate 1, and includes a plurality of first electrodes 31, the first electrodes 31 are arranged in an array, and adjacent first electrodes 31 are arranged at intervals.
  • each first electrode 31 may include a middle part 310 and an edge part 311 surrounding the middle part 310.
  • the middle part 310 is a flat structure, that is, the middle part 310 and the flat layer 2 are away from the substrate. The surfaces of 1 are roughly parallel.
  • the edge portion 311 may include a flat portion 3110 and a climbing portion 3111, wherein the flat portion 3110 is located on the surface of the flat layer 2 facing away from the substrate 1 and arranged around the middle portion 310, and the flat portion 3110 and the flat layer 2 facing away from the substrate 1 The surfaces are roughly parallel. At the same time, the thickness of the flat portion 3110 is smaller than the thickness of the middle portion 310. In some embodiments of the present disclosure, there is a non-zero interval between the flat portion 3110 and the boundary of the driving region 202 where it is located. Of course, the boundary of the flat portion 3110 may also overlap the boundary of the driving area 202.
  • the climbing part 3111 is connected between the middle part 310 and the flat part 3110, that is, the climbing part 3111 surrounds the middle part 310, and the flat part 3110 is arranged around the climbing part 3111.
  • the slope of the climbing portion 3111 relative to the surface of the flat layer 2 facing away from the substrate 1 is not less than 30°, and the slope is the surface of the climbing portion 3111 and the surface of the flat layer 2 facing away from the substrate 1 ⁇ The included angle.
  • the first electrode 31 includes a first conductive layer 320, a second conductive layer 321, and a third conductive layer 322.
  • the first conductive layer 320 is provided on the surface of the flat layer 2 away from the substrate 1, and the second conductive layer 321 is provided on the first conductive layer.
  • the layer 320 is away from the surface of the substrate 1, and the third conductive layer 322 is provided on the surface of the second conductive layer 321 away from the substrate 1, and extends at a certain slope to the surface of the driving area 202 where it is away from the substrate 1, thereby
  • the first conductive layer 320 and the second conductive layer 321 are covered to protect the first conductive layer 320 and the second conductive layer 321.
  • the middle portion 310 of the first electrode 31 includes the third conductive layer 322 located in the area of the second conductive layer 321 away from the surface of the substrate 1 and the first conductive layer 320 and the second conductive layer 321, and the edge portion 311 includes the third conductive layer 322
  • the area covering the edges of the first conductive layer 320 and the second conductive layer 321 is the area extending toward the flat layer 2.
  • the material of the first conductive layer 320 may include titanium (Ti)
  • the material of the second conductive layer 321 includes silver (Ag)
  • the material of the third conductive layer 322 includes indium tin oxide (ITO). Of course, it may also be Use other materials.
  • the light-emitting function layer 5 may be a continuous film layer, and at the same time cover at least a part of the area of each first electrode 31.
  • the light-emitting functional layer 5 includes a light-emitting unit layer, and the light-emitting unit layer includes a hole injection, a hole transport layer, and a light-emitting layer that are sequentially stacked from the first electrode 31 in a direction away from the substrate 1. , Electron transport layer and electron injection layer.
  • the light-emitting functional layer 5 includes multiple light-emitting unit layers, and the hole injection, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer of each light-emitting unit layer are distributed in the same manner.
  • a charge generation layer is provided between two adjacent light-emitting unit layers, so that the light-emitting unit layers are connected in series through the charge generation layer, so as to form a series-type OLED light-emitting device.
  • the second electrode 6 covers the light-emitting functional layer 5, and a driving signal can be applied to the first electrode 31 and the second electrode 6, so that the light-emitting functional layer 5 is located between the first electrode 31 and the second electrode 6. Glow.
  • the second electrode 6 includes a plurality of recessed portions 61 and a plurality of smooth portions 62, wherein:
  • the smooth portions 62 are arranged in an array and are arranged in a one-to-one correspondence with the middle portion 310 of each first electrode 31, that is, the orthographic projection of each smooth portion 62 on the flat layer 2 is located within each first electrode 31 in a one-to-one correspondence.
  • the gentle portion 62 is parallel or substantially parallel to the middle portion 310.
  • the recessed portion 61 corresponds to the area of the flat layer 2 that is not covered by the intermediate portion 310, and is used to separate the smooth portion 62, and the recessed portion 61 is recessed toward the side of the smooth portion 62 close to the substrate 1.
  • the recessed portion 61 has a ring structure, and the number is multiple, and each recessed portion 61 surrounds each smooth portion 62 in a one-to-one correspondence, that is, the recessed portion 61 is a transition area of two adjacent smooth portions 62.
  • the orthographic projection of the recess 61 on the substrate 1 is at least partially located outside the middle portion 310 of the first electrode 31, so as to be directly opposite to the area other than the first electrode 31 or the edge portion 311 with a smaller thickness, but not with the larger thickness.
  • the middle portion 310 is directly opposite, which can reduce the risk of tip discharge and short circuit between the recessed portion 61 and the first electrode 31, thereby improving the stability of the light-emitting device.
  • the orthographic projection of the lowest point of the recess 61 on the flat layer 2 is located outside the middle part 310, for example, the lowest point and the climbing part 3111 and 3111
  • One of the flat portions 3110 corresponds to the middle portion 310 to avoid tip discharge.
  • the lowest point of the recess 61 on the cross section perpendicular to the substrate 1 is: on the cross section perpendicular to the substrate 1, the recess 61 is the point closest to the first electrode 31, that is, the point farthest from the gentle portion 62.
  • the number of recesses 61 in the section perpendicular to the substrate 1 may be multiple, and the lowest point on different sections may be different.
  • the lowest point may be the middle part from the first electrode 31 in the depth direction.
  • the nearest point 310 may also be another point in the depth direction, depending on the position of the cross section perpendicular to the substrate 1.
  • the recess 61 has two side surfaces, including a first side surface 611, a second side surface 612, and a bottom surface 613, wherein the first side surface 611 and the second side surface 612 are arranged oppositely and connected to both sides of the bottom surface 613.
  • the first side surface 611 and the second side surface 612 may shrink in a direction close to the substrate 1.
  • the first side surface 611 and the second side surface 612 may be curved surfaces or flat surfaces, which are not specifically limited here.
  • the bottom surface 613 may be a curved surface convex in a direction away from the substrate 1.
  • the bottom surface 613 of the recess 61 includes a first slope surface 6131, a second slope surface 6132, and a connecting surface 6133, wherein, Both the first slope surface 6131 and the second slope surface 6132 can be curved or flat.
  • the connecting surface 6133 is located on the side of the first side surface 611 and the second side surface 612 facing away from the substrate 1, and the connecting surface 6133 is connected to the first side surface 611 and the second side surface 612. Between the slope surface 6131 and the second slope surface 6132.
  • the first slope surface 6131 is connected to the bottom edge of the first side surface 611
  • the second slope surface 6132 is connected to the bottom edge of the second side surface 612.
  • the slope of the first slope surface 6131 relative to the middle portion 310 is not less than the slope of the first side surface 611 relative to the middle portion 310.
  • the slope of the second slope surface 6132 relative to the middle portion 310 is not less than the slope of the second side surface 612 relative to the middle portion 310.
  • the first slope surface 6131 and the second slope surface 6132 are symmetrical with respect to the connecting surface 6133, that is, the cross section of the first slope surface 6131 perpendicular to the substrate 1 and the second slope surface 6132
  • the cross-section perpendicular to the substrate 1 is symmetrical with respect to the cross-section perpendicular to the substrate 1 of the connection surface 6133.
  • the first side surface 611 and the second side surface 612 are symmetrical with respect to the bottom surface 613, that is, the cross section of the first side surface 611 is perpendicular to the substrate 1 and the second side surface 612 is perpendicular to the substrate 1.
  • the cross section of is symmetrical with respect to the cross section of the bottom surface 613 perpendicular to the substrate 1.
  • the minimum thickness of the area of the second electrode 6 corresponding to the first side surface 611 and the second side surface 612 is larger than the area of the second electrode 6 corresponding to the first slope surface 6131 and the second slope surface 6132 The minimum thickness.
  • the depth H of the recess 61 is less than twice the maximum thickness of the second electrode 6.
  • the maximum thickness of the second electrode 6 is 90 nm
  • the recess The depth of the portion 61 is less than 180 nm, for example, 120 nm, 100 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, and the like.
  • the depth H of the recessed portion 61 refers to the maximum depth of the recessed portion 61, that is, in the direction perpendicular to the substrate 1, the distance between the closest point of the recessed portion 61 to the substrate 1 and the surface of the smooth portion 62 away from the substrate 1.
  • the orthographic projection of each recess 61 on the flat layer 2 surrounds the middle part 310 of a first electrode 31, and the bottom surface 613 of the recess 61 is connected to
  • the minimum value of the distance between the middle portion 310 of the adjacent first electrode 31 is not less than the flat portion 62 and 70% of the total thickness of the light-emitting functional layer 5, the total thickness of the smooth portion 62 and the light-emitting functional layer 5 is the sum of the thickness of the smooth portion 62 and the light-emitting functional layer 5, for example, the total thickness of the smooth portion 62 and the light-emitting functional layer 5 is about If it is 365 nm, the minimum value of the distance between the bottom of the recess 61 in the direction perpendicular to the substrate 1 and the middle portion 310 of the adjacent first electrode
  • the maximum value of the distance between the bottom of the recess 61 and the middle part 310 of the adjacent first electrode 31 is not less than 400nm, and the maximum value is not greater than 450nm.
  • a plurality of separation grooves 201 may be provided on the surface of the flat layer 2 facing away from the substrate 1, and the depth of the separation groove 201 is less than that of the flat layer 2.
  • the thickness of the layer 2, that is, the separation groove 201 does not penetrate the flat layer 2 in the depth direction.
  • a plurality of driving regions 202 can be divided on the flat layer 2 by the separation grooves 201, and the driving regions 202 are arranged in an array.
  • the specific structure of the partition groove 201 can refer to the above-mentioned first implementation of the display panel, which will not be described in detail here.
  • the second display panel of the present disclosure further includes a pixel definition layer 4, which is made of insulating material, and is provided on the surface of the flat layer 2 away from the substrate 1 with the first electrode layer 3.
  • the pixel definition layer 4 exposes at least part of the area of the middle portion 310 of the first electrode 31 and is recessed in the area corresponding to the separation groove 201.
  • the middle portion 310 exposed by the pixel definition layer 4 can be connected to the corresponding light emitting function layer 5 and
  • the second electrode 6 constitutes a light emitting device.
  • the structure of the pixel definition layer 4 can refer to the implementation of the first display panel described above, which will not be described in detail here.
  • the light-emitting functional layer 5 also covers the pixel defining layer 4 and the area of the flat layer 2 not covered by the pixel defining layer 4 and the first electrode 31.
  • the light-emitting functional layer 5 is separated from each other.
  • the area of the groove 201 is recessed toward the substrate 1.
  • the recess 61 of the second electrode 6 is at least partially located within the range of the separation groove 201 in the orthographic projection of the flat layer 2.
  • the first display panel of the present disclosure may further include a first encapsulation layer 13, and the first encapsulation layer 13 may cover the second electrode 6.
  • the first encapsulation layer 13 may include two layers. The inorganic layer and the organic layer between the two inorganic layers. The first encapsulation layer 13 forms a pit 1301 in an area corresponding to the recess 61, the two sidewalls of the pit 1301 are narrowed toward the substrate 1, and the two sidewalls are connected.
  • the display panel may further include a color film layer 14, a second encapsulation layer 15, and a transparent cover plate 16, wherein:
  • the color filter layer 14 is disposed on the side of the first encapsulation layer 13 away from the second electrode 6, and the color filter layer 14 includes filter regions corresponding to each first electrode 31 one by one.
  • the color filter regions have multiple colors, such as Red, blue and green.
  • the second encapsulation layer 15 can cover the color filter layer 14, and its structure can be the same as that of the first encapsulation layer 13.
  • the transparent cover plate 16 can cover the second encapsulation layer 15, and its material can be glass or material.
  • the second type of display panel may further include a light extraction layer 17, which covers the surface of the second electrode 6 facing away from the substrate 1
  • the area with the recess 61 is recessed, and the first encapsulation layer 13 is provided on the side of the light extraction layer 17 away from the substrate 1.
  • the refractive index of the light extraction layer 17 is greater than that of the second electrode 6, which can improve the light extraction efficiency, and the higher the refractive index, the higher the light extraction efficiency.
  • the embodiments of the present disclosure also provide a method for manufacturing a display panel, which may be the first display panel described above. As shown in FIG. 10, the manufacturing method includes steps S110 to S160, wherein:
  • Step S110 forming a flat layer on one side of a substrate
  • Step S120 forming a plurality of separation grooves on the surface of the flat layer away from the substrate, so as to divide a plurality of driving regions distributed in an array;
  • Step S130 forming a first electrode layer including a plurality of first electrodes on the surface of the flat layer away from the substrate; the orthographic projection of each first electrode on the flat layer is located in each of the Within the driving area; the first electrode includes a flat middle part and an edge part surrounding the middle part; the edge part includes a flat part surrounding the middle part and connected to the middle part and the flat part Between the climbing part, the thickness of the flat part is smaller than the middle part;
  • Step S140 forming a pixel definition layer on the surface of the flat layer facing away from the substrate, the pixel definition layer exposing at least a part of the middle portion.
  • Step S150 The light-emitting function layer covers the pixel definition layer, the intermediate portion and the flat layer exposed by the pixel definition layer.
  • Step S160 forming a second electrode covering the light-emitting function layer.
  • the embodiments of the present disclosure also provide a method for manufacturing a display panel, which may be the first type of display panel described above. As shown in FIG. 11, the manufacturing method includes step S210-step S250, wherein:
  • Step S210 forming a flat layer on one side of a substrate
  • Step S220 forming a first electrode layer including a plurality of first electrodes and a separation groove on the surface of the flat layer facing away from the substrate;
  • the first electrode includes a flat middle part and an edge part surrounding the middle part
  • the edge part includes a flat part surrounding the middle part and a climbing part connected between the middle part and the flat part, the thickness of the flat part is smaller than the middle part;
  • the separation groove is in The flat layer is divided into a plurality of driving regions distributed in an array; the orthographic projection of each of the first electrodes on the flat layer is located within each of the driving regions in a one-to-one correspondence;
  • Step S230 forming a pixel definition layer on the surface of the flat layer away from the substrate, and the pixel definition layer exposes at least a part of the middle portion;
  • Step S240 forming a light-emitting functional layer, the light-emitting functional layer covering the pixel defining layer and the intermediate portion and the flat layer exposed by the pixel defining layer;
  • Step S250 forming a second electrode covering the light-emitting function layer.
  • a conductive layer can be formed on the surface of the flat layer away from the substrate first, and the conductive layer can be patterned through a gray-scale mask process to obtain the first electrode layer.
  • the step mask process can simultaneously form the separation grooves. Compared with the method of separately forming the first electrode layer and the separation groove through two mask processes, the manufacturing process of the display panel can be simplified.
  • the embodiments of the present disclosure also provide a method for manufacturing a display panel, which may be the above-mentioned second display panel. As shown in FIG. 12, the manufacturing method includes step S310-step S340, wherein:
  • Step S310 forming a flat layer on one side of a substrate
  • Step S320 forming a plurality of separation grooves on the surface of the flat layer facing away from the substrate to divide a plurality of driving regions distributed in an array;
  • Step S330 forming a first electrode layer including a plurality of first electrodes on the surface of the flat layer away from the substrate; the orthographic projection of each first electrode on the flat layer is located in each of the Within the driving area; each of the first electrodes includes a flat middle part and an edge part surrounding the middle part; the edge part includes a flat part surrounding the middle part and connected to the middle part and the flat part In the climbing section between the sections, the thickness of the flat section is smaller than that of the middle section;
  • Step S340 forming a pixel definition layer on the surface of the flat layer facing away from the substrate, the pixel definition layer exposing at least a part of the middle portion and the separation groove;
  • the embodiments of the present disclosure also provide a display device, which may include any one of the above-mentioned first-type display panel and second-type display panel.
  • a display device which may include any one of the above-mentioned first-type display panel and second-type display panel.
  • the display device of the present disclosure can be used in electronic devices such as mobile phones, tablet computers, and televisions.

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Abstract

本公开是关于一种显示装置、显示面板及其制造方法，涉及显示技术领域。该显示面板包括衬底、平坦层、第一电极层、像素定义层、发光功能层和第二电极。平坦层设于衬底一侧，平坦层背离衬底的表面设有多个分隔槽，以分割出阵列分布的多个驱动区；第一电极层设于平坦层背离衬底的表面，包括多个第一电极；第一电极在平坦层的正投影位于各驱动区以内；第一电极包括平坦的中间部和围绕中间部的边缘部；边缘部包括围绕中间部的平坦部以及连接于中间部和平坦部之间的爬坡部；像素定义层设于平坦层上，且露出中间部的至少部分区域；发光功能层覆盖像素定义层以及被像素定义层露出的中间部和平坦层；第二电极覆盖发光功能层。

Description

显示装置、显示面板及其制造方法 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示装置、显示面板及显示面板的制造方法。
背景技术
目前，OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板的应用越来越广泛。在OLED显示面板中，发光器件通常包括阵列分布的多个OLED发光器件，每个发光器件可独立发光，以便显示图像。但是，由于制造工艺的原因，OLED发光器件发光的稳定性仍有待提高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种显示装置、显示面板及显示面板的制造方法，可提高发光的稳定性。
根据本公开的一个方面，提供一种显示面板，包括：
衬底；
平坦层，设于所述衬底一侧，所述平坦层背离所述衬底的表面设有多个分隔槽，以分割出阵列分布的多个驱动区；
第一电极层，设于所述平坦层背离所述衬底的表面，且包括多个第一电极；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
像素定义层，设于所述平坦层背离所述衬底的表面，且露出所述中间部的至少部分区域；
发光功能层，覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述平坦层；
第二电极，覆盖所述发光功能层。
在本公开的一种示例性实施例中，所述分隔槽的最大深度不小于所述发光功能层和所述第一电极的厚度和的30％。
在本公开的一种示例性实施例中，所述分隔槽的最大深度不大于所述发光功能层和所述第一电极的厚度和的60％。
在本公开的一种示例性实施例中，所述分隔槽的最大深度为
Figure PCTCN2020085955-appb-000001
在本公开的一种示例性实施例中，所述分隔槽包括两个相对的侧壁以及连接于两个所述侧壁之间的底面，两个所述侧壁的最大间距为0.2μm-0.7μm。
在本公开的一种示例性实施例中，所述分隔槽包括两个相对的侧壁以及连接于两个所述侧壁之间的底面，所述底面为向背离所述衬底的方向凸起的曲面。
在本公开的一种示例性实施例中，所述分隔槽包括两个相对的侧壁以及连接于两个所述侧壁之间的底面；两个所述侧壁平行。
在本公开的一种示例性实施例中，所述分隔槽包括两个相对的侧壁以及连接于两个所述侧壁之间的底面；两个所述侧壁的间距向靠近所述底面的方向减小。
在本公开的一种示例性实施例中，两个所述侧壁的坡度不小于70°。
在本公开的一种示例性实施例中，所述中间部在所述衬底的正投影的边界与其所处的驱动区在所述衬底的投影的边界之间的间距不小于0.15μm。
在本公开的一种示例性实施例中，所述平坦部在所述衬底的正投影的边界与其所处的驱动区在所述衬底的正投影的边界之间的间距大于0。
在本公开的一种示例性实施例中，所述像素定义层延伸至所述分隔槽内，且在对应于所述分隔槽的区域凹陷。
根据本公开的一个方面，提供一种显示面板，包括：
衬底；
平坦层，设于所述衬底一侧；
第一电极层，设于所述平坦层背离所述衬底的表面，且包括多个第一电极；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
发光功能层，覆盖所述中间部的至少部分区域；
第二电极，覆盖所述发光功能层，且包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述平坦层上的正投影一一对应的位于各所述第一电极以内；所述凹陷部向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述平坦层上的正投影至少部分位于所述中间部以外。
在本公开的一种示例性实施例中，在垂直于所述衬底的截面上，所述凹陷部的最低点在所述平坦层上的正投影位于所述中间部以外。
在本公开的一种示例性实施例中，所述凹陷部包括第一侧面、第二侧面和底面，所述第一侧面和所述第二侧面相对连接于所述底面的两侧，且所述第一侧面和所述第二侧面沿靠近所述衬底的方向收缩。
在本公开的一种示例性实施例中，所述凹陷部的底面包括第一坡面、第二坡面以及连接于所述第一坡面和所述第二坡面之间的连接面，所述连接面位于所述第一侧面和所述第二侧面的底边背离所述衬底的一侧，所述第一坡面与所述第一侧面的底边连接，所述第二坡面与所述第二侧面的底边连接。
在本公开的一种示例性实施例中，所述第一坡面相对于所述中间部的坡度不小于所述第一侧面相对于所述中间部的坡度；
所述第二坡面相对于所述中间部的坡度不小于所述第二侧面相对于所述中间部的坡度。
在本公开的一种示例性实施例中，在垂直于所述衬底的截面中，所述第一坡面与所述第二坡面关于所述连接面对称，且所述第一侧面与所述第二侧面关于所述底面对称。
在本公开的一种示例性实施例中，所述第二电极对应于所述第一侧面和所述第二侧面的区域的最小厚度，大于对应于所述第一坡面和所述第二坡面的区域的最小厚度。
在本公开的一种示例性实施例中，所述平坦层背离所述衬底的表面设有多个分隔槽，以分割出阵列分布的多个驱动区，各所述第一电极在所述平坦层的正投影一一对应的位于各所述第一电极以内；
所述显示面板还包括：
像素定义层，设于所述平坦层背离所述衬底的表面，且露出所述中间部的至少部分区域；所述凹陷部在所述平坦层的正投影的至少部分区域位于所述分隔槽内。
在本公开的一种示例性实施例中，所述显示面板还包括：
第一封装层，覆盖所述第二电极，且在对应于所述凹陷部的区域形成凹坑。
在本公开的一种示例性实施例中，所述凹坑的两个侧壁向靠近所述衬底的方向收窄且连接。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
在一衬底一侧形成平坦层；
在所述平坦层背离所述衬底的表面形成多个分隔槽，以分割出阵列分布的多个驱动区；
在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及 连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域；
形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述平坦层；
形成覆盖所述发光功能层的第二电极。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
在一衬底一侧形成平坦层；
在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层和分隔层；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；所述分隔槽在所述平坦层分割出阵列分布的多个驱动区；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；
在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域；
形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述平坦层；
形成覆盖所述发光功能层的第二电极。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
在一衬底一侧形成平坦层；
在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
形成覆盖所述中间部的至少部分区域的发光功能层；
形成覆盖所述发光功能层的第二电极，所述第二电极包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述平坦层上的正投影一一对应的位于各所述第一电极以内；所述凹陷部向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述平坦层上的正投影至少部分位于所述中间部以外。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的第一种显示面板一实施方式的示意图。
图2为本公开的第一种显示面板一实施方式的局部电镜图。
图3为本公开的第一种显示面板另一实施方式的示意图。
图4为本公开的第一种显示面板再一实施方式的示意图。
图5为本公开的第一种显示面板一实施方式中像素定义层的俯视图。
图6为本公开的第一种显示面板一实施方式中像素定义层和第一电极的俯视图。
图7为本公开的第二种显示面板一实施方式的示意图。
图8为图7中A部的放大图。
图9为本公开的第二种显示面板一实施方式的局部电镜图。
图10为本公开的第一种显示面板的制造方法一实施方式的示意图。
图11为本公开的第一种显示面板的制造方法另一实施方式的示意图。
图12为本公开的第二种显示面板的制造方法一实施方式的示意图。
附图标记说明：
1、衬底；101、有源区；1011、源极；1012、漏极；2、平坦层；201、分隔槽；2011、侧壁；2012、底壁；202、驱动区；3、第一电极层；31、第一电极；310、中间部；311、边缘部；3110、平坦部；3111、爬坡部3111；320、第一导电层；321、第二导电层；322、第三导电层；4、像素定义层；401、开口；5、发光功能层；501、发光单元层；502、电荷产生层；6、第二电极；61、凹陷部；611、第一侧面；612、第二侧面；613、底面；6131、第一坡面；6132、第二坡面；6133、连接面；62、平缓部；7、栅绝缘层；8、栅极；9、第一绝缘层；10、第一走线层；11、第二绝缘层；12、第二走线层；13、第一封装层；1301、凹坑；14、彩膜层；15、第二封装层；16、透明盖板；17、光提取层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的 附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”仅作为标记使用，不是对其对象的数量限制。
相关技术中，OLED显示面板包括驱动背板、多个第一电极、像素定义层、发光功能层、第二电极和彩膜层，其中，第一电极阵列分布于驱动背板上；像素定义层设于驱动背板设有第一电极的表面，且露出各个第一电极；发光功能层覆盖像素定义层和第一电极背离驱动背板的表面，第二电极覆盖于发光功能层背离驱动背板的表面，从而可通过像素定义层限定出多个发光器件。在驱动信号的驱动下，第一电极注入的空穴和第二电极注入的电子进入到发光功能层，并形成激子，激子辐射跃迁发射光子从而形成电致发光。彩膜层设于第二电极背离驱动背板的一侧，且具有一一对应于各个发光器件的多个滤光区，每个滤光区及其对应的发光器件可作为一子像素。
由于像素定义层的厚度大于第一电极，在通过蒸镀工艺形成发光功能层时，在第一电极与像素定义层交界处，即在发光器件的边缘位置，发光功能层会出现凹陷，从而使第二电极相应的形成凹陷区，第二电极的凹陷区与第一电极的距离较近，容易出现尖端放电，甚至短路，影响发光器件的稳定性，从而使显示面板难以稳定发光。同时，第二电极的凹陷区与第一电极对应，因而也会发射光线，但由于凹陷区的形貌为向驱动背板凹陷的结构，而非平面结构，使得该凹陷区的范围内发射的光线为散射状态，且至少部分光线向相邻的子像素偏斜，使得相邻的子像素的发光互相干扰，影响显示效果。
发光功能层在第二电极在第一电极与像素定义层的交界处凹陷，使第二电极在对应该凹陷的区域形成凹陷区，该凹陷区与第一电极正对，即凹陷区在驱动背板的正投影位于第一电极内，使得二者之间可能会出现尖端放电，甚至短路。同时，凹陷区会发光，且由于凹陷区的形貌为弯曲状，使得其发出的光线呈散射状态，从而对相邻的子像素的发光产生干扰。
此外，由于发光功能层为整层连续的膜层，使得子像素之间相互连接，发光功能层中的至少一部分膜层(包括但不限于空穴注入层)会使相邻的子像素之间产生串扰。特别地，对于串联式OLED显示面板，发光功能层包括多个发光单元层，相邻的两层发光单元层通过电荷产生层串联。但是，电荷产生层具有良好电荷传导特性，会使相邻的子像素之间产生串扰，影响发光效果。
为了解决上述相关技术中的至少一个技术问题，本公开的实施方式提供了两种显示面板。
第一种显示面板
如图1和图2所示，显示面板可包括衬底1、平坦层2、第一电极层3、像素定义层4、发光功能层5和第二电极6，其中：
平坦层2设于衬底1一侧，且平坦层2背离衬底1的表面设有多个分隔槽201，以在平坦层2上分割出多个驱动区202，且各驱动区202阵列分布。
第一电极层3设于平坦层2背离衬底1的表面，且包括阵列分布的多个第一电极31，各第一电极31在平坦层2的正投影一一对应的位于各驱动区202以内。第一电极31包括平坦的中间部310和围绕中间部310的边缘部311；边缘部311包括围绕中间部310的平坦部3110以及连接于中间部310和平坦部3110之间的爬坡部3111，平坦部3110的厚度小于中间部310。
像素定义层4设于平坦层2背离衬底1的表面，且露出中间部310的至少部分区域。
发光功能层5覆盖像素定义层4以及被像素定义层4露出的中间部310和平坦层2。
第二电极6覆盖发光功能层5。
本公开实施方式的显示面板，每个第一电极31的中间部310被像素定义层4露出的区域及其对应的发光功能层5和第二电极6可构成一发光器件，以便发光。
由于第一电极31在平坦层2的正投影一一对应的位于各驱动区202以内，使得分隔槽201位于第一电极31以外，在形成发光功能层5时，发光功能层5可在分隔槽201的位置向衬底1凹陷，进而使第二电极6在该凹陷处形成的凹陷部61，且凹陷部61在平坦层2的正投影至少部分位于第一电极31的中间部310以外，也即位于发光器件以外，由此，可通过分隔槽201对第二电极6的凹陷部61的位置进行限制，防止凹陷部61与中间部310之间发生尖端放电，甚至短路，有利于保证发光器件稳定发光。同时，可减少、甚至避免凹陷部61的范围内发光，从而降低相邻发光器件发光的互相干扰。
如图2所示，图2为本公开第一种显示面板一实施方式的局部电镜图，可以看出，凹陷部61在平坦层2的正投影至少部分位于第一电极31的范围外，可降低与第一电极31之间出现尖端放电的风险。同时，可减少甚至避免凹陷部61发光，防止对相邻的子 像素产生干扰。
下面对本公开实施方式第一种显示面板的各部分进行详细说明：
如图1所示，衬底1的材料可为单晶硅或多晶硅等半导体材料，也可以是玻璃等其它硬质或软质材料。
在本公开的一些实施方式中，衬底1上可设有多个驱动晶体管，用于驱动各个发光器件发光，以显示图像。以一个顶栅结构的驱动晶体管为例，显示面板还包括栅绝缘层7、栅极8、第一绝缘层9和第一走线层10，其中：衬底1的材料可为单晶硅或多晶硅等半导体材料，且衬底1包括有源区101和位于有源区101两端的源极1011和漏极1012。栅绝缘层7覆盖有源区101；栅极8设于栅绝缘层7背离衬底1的表面，栅极8的材料可包括多晶硅材料。第一绝缘层9覆盖栅极8和衬底1，其材料可包括氧化硅和氮化硅中至少一个。第一走线层10设于第一绝缘层9背离衬底1的表面，且栅极8、源极1011和漏极1012均通过钨或其它金属填充的过孔与第一走线层10连接。
此外，显示面板还可包括第二绝缘层11和第二走线层12，第二绝缘层11覆盖第一走线层10和第一绝缘层9，第二走线层12设于第二绝缘层11背离衬底1的表面，第二走线层12的具体图案在此不做特殊限定，其可通过钨或其它金属填充的过孔与第一走线层10连接。
如图1所示，平坦层2设于衬底1的一侧，在本公开的一些实施方式中，平坦层2可覆盖第二走线层12，第一电极31可通过钨或其它金属填充的过孔与第二走线层12连接。平坦层2的材料可包括氮化硅和氧化硅中至少一种，当然，还可以包括其它绝缘材料。举例而言，平坦层2可通过抛光工艺实现平坦化。
平坦层2背离衬底1的表面可开设多个分隔槽201，分隔槽201的深度小于平坦层2的厚度，即分隔槽201在深度方向上不会贯穿平坦层2。通过分隔槽201可在平坦层2上分割出多个驱动区202，且各驱动区202阵列分布。
驱动区202在衬底1的正投影的形状可以是矩形、五边形、六边形或其它多边形，当然，也可以是圆形或其它形状，在此不作特殊限定。同时，不同驱动区202的形状和尺寸可以不同。
在本公开的一些实施方式中，例如，分隔槽201可包括第一分隔槽和第二分隔槽，其中，第一分隔槽的数量为多个，且各第一分隔槽沿第一方向直线延伸，并沿第二方向间隔分布；第二分隔槽的数量为多个，且各第二分隔槽沿第二方向直线延伸，并沿第一方向间隔分布；第一方向和第二方向为相互交叉的方向，例如，第一方向和第二方向为相互垂直的方向。由此，可通过交错的第一分隔槽和第二分隔槽在平坦层2上分割出阵列分布的多个驱动区202。
在本公开的其它实施方式中，第一分隔槽和第二分隔槽也可沿曲线或折线轨迹延伸，从而分割出其他形状的驱动区202。
每个分隔槽201可包括两个相对的侧壁2011以及连接于两个侧壁2011之间的底壁2012。其中，两个侧壁2011可平行设置，即在垂直于衬底1的方向上，两个侧壁2011及其延伸面不相交。或者，两个侧壁2011也可呈一定夹角设置。
如图3所示，底壁2012可与平坦层2背离衬底1的表面大致平行，或者，如图1所示，底壁2012也可是沿背离衬底1的方向凸起的曲面，该曲面的曲率和形状在此不做特殊限定，且在垂直于衬底1的截面中，底壁2012的轮廓可以大致呈圆弧状、抛物线状或波浪线状，当然，也可以是其它规则或不规则的形状，只要向背离衬底1的方向凸起即可。
在本公开的一些实施方式中，两个侧壁2011向靠近底壁2012的方向收缩，即两个侧壁2011的间距向靠近底壁2012的方向逐渐减小，使得侧壁2011具有相对于平坦层2背离衬底1的表面的坡度，该坡度为侧壁2011与平坦层2背离衬底1的表面的夹角。进一步的，该坡度不小于70°，且不大于90°，例如，该坡度可以是70°、80°和90°等。
在本公开的一些实施方式中，分隔槽201的两个侧壁2011的最大间距S可为0.2μm-0.7μm，例如0.2μm 0.3μm、0.5μm或0.7μm等。
如图1所示，第一电极层3设于平坦层2背离衬底1的表面，且包括阵列分布的多个第一电极31，各第一电极31在平坦层2的正投影一一对应的位于各驱动区202以内，即各第一电极31在衬底1的正投影的边界一一对应的位于各驱动区202在衬底1的正投影的边界以内。每个驱动区202上只设置一个第一电极31。由于驱动区202是分隔槽201分隔而成，而第一电极31位于驱动区202上，因此，分隔槽201位于第一电极31以外。每个第一电极31在平坦层2的正投影的形状可与其所处的驱动区202的形状相同，第一电极31的边界位于其所处的驱动区202以内。
在平行于衬底1的方向上，至少一个第一电极31可包括中间部310和围绕中间部310边缘部311，其中，中间部310为平坦结构，即中间部310与平坦层2背离衬底1的表面大致平行。
在本公开的一些实施方式中，每个第一电极31的中间部310在衬底1的正投影的边界可位于其所处的驱动区202在衬底1的正投影的边界以内，即中间部310在衬底1的正投影的边界与其所处的驱动区202在衬底1的正投影的边界具有不为0的间距L。进一步的，该间距L不小于0.15μm，例如，该间距可以是0.15μm、0.2μm、0.25μm等。
边缘部311可包括平坦部3110以及爬坡部3111，其中，平坦部3110位于平坦层2背离衬底1的表面，并围绕中间部310设置，且平坦部3110与平坦层2背离衬底1的表面大致平行。同时，平坦部3110的厚度小于中间部310的厚度。在本公开的一些实施方式中，平坦部3110在衬底1的正投影的边界与其所处的驱动区202在衬底1的正投影的边界之间具有不为0的间距。当然，平坦部3110在衬底1的正投影的边界与其所处的驱动区202在衬底1的正投影的边界重叠。
爬坡部3111连接于中间部310和平坦部3110之间，即爬坡部3111围绕中间部310，平坦部3110围绕爬坡部3111设置。在本公开的一些实施方式中，爬坡部3111相对于平坦层2背离衬底1的表面的坡度不小于30°，该坡度为爬坡部3111的表面与平坦层2背离衬底1的表面的夹角。
第一电极31包括第一导电层320、第二导电层321和第三导电层322，第一导电层320设于平坦层2背离衬底1的表面，第二导电层321设于第一导电层320背离衬底1的表面，第三导电层322设于第二导电层321背离衬底1的表面，并以一定的坡度延伸至平坦层2，从而包覆第一导电层320和第二导电层321，对第一导电层320和第二导电层321进行保护。
第一电极31的中间部310包括第三导电层322位于第二导电层321背离衬底1的表面的区域以及第一导电层320和第二导电层321，边缘部311包括第三导电层322包覆第一导电层320和第二导电层321边缘的区域，即向平坦层2延伸的区域。示例性的，第一导电层320的材料可包括钛(Ti)、第二导电层321的材料包括银(Ag)、第三导电层322的材料包括氧化铟锡(ITO)，当然，也可以采用其他材料。
如图1所示，像素定义层4为绝缘材质，且与第一电极层3均设于平坦层2背离衬底1的表面。同时，像素定义层4露出第一电极31的中间部310的至少部分区域，被像素定义层4露出的中间部310可与对应的发光功能层5和第二电极6构成发光器件。
在本公开的一些实施方式中，每个第一电极31不完全覆盖其所在的驱动区202，且第一电极31的平坦部3110在衬底1的正投影的边界与其所处的驱动区202在衬底1的正投影的边界具有一定的间距。像素定义层4延伸至分隔槽201的侧壁2011和底壁2012，即像素定义层4与未被第一电极31覆盖的驱动区202随形贴合，使得像素定义层4在对应分隔槽201的区域凹陷。像素定义层4设有一一对应露出各中间部310的至少部分区域的多个开口401，从而可通过像素定义层4对发光器件的发光范围进行限定。
如图5和图6所示，在本公开的一些实施方式中，像素定义层4的开口401可为六边形或其它多边形结构，第一电极31也可为多边形结构，且与开口401的形状相同，当然，第一电极31也可以是其它形状。
如图1所示，发光功能层5可为连续的膜层，且至少部分覆盖各第一电极31的中间部310，即覆盖被开口401露出的区域，同时，发光功能层5还覆盖像素定义层4以及平坦层2未被像素定义层4和第一电极31覆盖的区域，在通过蒸镀或其它工艺形成发光功能层5时，发光功能层5在对应分隔槽201的区域向靠近衬底1的方向凹陷。
在本公开的一实施方式中，如图4所示，发光功能层5包括多层发光单元层501，每层发光单元层501的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层的分布方式相同。同时，相邻两发光单元层501之间设有电荷产生层502，从而通过电荷产生层502将各发光单元层501串联，以便形成串联式的OLED发光器件。
在本公开的另一些实施方式中，发光功能层5包括一层发光单元层，发光单元层包括由第一电极31向背离衬底1的方向依次层叠的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层。
电荷产生层502无法覆盖分隔槽201的侧壁2011，从而可通过分隔槽201将发光器件的电荷产生层502截断，避免相邻两个发光器件之间出现串扰。当然，分隔槽201还可将空穴注入层或其它膜层截断，同样可防止串扰。
如图1所示，第二电极6覆盖发光功能层5，可向第一电极31和第二电极6施加驱动信号，使发光功能层5位于第一电极31和第二电极6之间的部分发光。
第二电极6的形貌与发光功能层5相匹配，其在发光功能层5的凹陷处凹陷，形成凹陷部61，并在对应于第一电极31的中间部310的区域形成平缓部62，使凹陷部61在平坦层2上的正投影至少部分位于第一电极31的中间部310以外，减少或避免第一电极31与第二电极6的凹陷部61发生尖端放电。第二电极6的材料可以是合金材料，例如第二电极6的材料可包括Mg和Ag；或者，第二电极6还可采用Al和Li合金。当然，第二电极6还可以采用其他合金或单质金属，在此不再一一列举。
需要说明的是，若像素定义层4覆盖中间部310的边缘，则平缓部62在对应于像素定义层4覆盖中间部310的区域可向背离衬底1的方向凸起，但凸起的高度小于第一中间部310的厚度，以使平缓部62大致保持平缓。
进一步的，如图1和图2所示，在本公开的一些实施方式中，第二电极6的凹陷部61在垂直于衬底1的截面上的最低点在平坦层2的正投影完全位于分隔槽201以内，即完全位于中间部310以外。
为了保证分隔槽201能将空穴注入层、电荷产生层502或其它膜层截断，应使分隔槽201具有一定的深度，但还应防止分隔槽201过深导致穿透平坦层2，而影响驱动器件。因此，在本公开的一些实施方式中，在垂直于衬底1的方向上，分隔槽201的最大深度H不小于发光功能层5和第一电极31的厚度和的30％；同时，分隔槽201的最大 深度H不大于发光功能层5和第一电极31的厚度之和的60％。其中，分隔槽201的最大深度为：在垂直于衬底1的方向上分隔槽201的底壁2012上与平坦层2背离衬底1的表面的距离最大的一点与平坦层2背离衬底1的表面的距离。举例而言，在本公开的一些实施方式中，分隔槽201的最大深度H为
Figure PCTCN2020085955-appb-000002
此外，在本公开的一些实施方式中，如图1所示，第一种显示面板还可包括第一封装层13、彩膜层14、第二封装层15和透明盖板16，其中：
第一封装层13可覆盖第二电极6，举例而言，第一封装层13可包括两层无机层和两层无机层之间的有机层。
在本公开的一些实施方式中，第一封装层13在对应凹陷部61的区域可凹陷形成凹坑1301，当然，若第一封装层13厚度较大，第一封装层13背离衬底1的表面也可大致保持平坦
彩膜层14设于第一封装层13背离第二电极6的一侧，且彩膜层14包括一一对应于各第一电极31的滤光区，滤光区的颜色有多种，例如红色、蓝色和绿色。
第二封装层15可覆盖彩膜层14，其结构可与第一封装层13相同。
透明盖板16可覆盖第二封装层15，其材质可以是玻璃或材料。
此外，在本公开的一些实施方式中，如图1所示，第一种显示面板还可包括光提取层17，光提取层17覆盖于第二电极6背离衬底1的表面，且在对应与凹陷部61的区域凹陷，第一封装层13设于光提取层17背离衬底1的一侧。光提取层17的折射率大于第二电极6，可提高出光效率，且折射率越高，出光效率越高。
第二种显示面板
如图7-图9所示，本公开的第二种显示面板可包括衬底1、平坦层2、第一电极层3、发光功能层5和第二电极6，其中：
平坦层2设于衬底1一侧；
第一电极层3设于平坦层2背离衬底1的表面，且包括多个第一电极31；第一电极31包括平坦的中间部310和围绕中间部310的边缘部311；边缘部311包括围绕中间部310的平坦部3110以及连接于中间部310和平坦部3110之间的爬坡部3111，平坦部3110的厚度小于中间部310。
发光功能层5覆盖中间部310的至少部分区域。
第二电极6覆盖发光功能层5，且包括凹陷部61和被凹陷部61分隔的多个平缓部62，各平缓部62在平坦层2上的正投影一一对应的位于各第一电极31以内；凹陷部61向平缓部62靠近衬底1的一侧凹陷，凹陷部61在平坦层2上的正投影至少部分位于中 间部310以外。
本公开实施方式的显示面板，每个第一电极31及其对应的发光功能层5和第二电极6可构成一发光器件，可进行发光。通过使第二电极6的凹陷部61在平坦层2上的正投影至少部分位于厚度较大的中间部310以外，而不与中间部310正对，可降低凹陷部61与第一电极31之间发生尖端放电的风险，有利于保证发光器件稳定发光。同时，可减少凹陷部61的范围内发光，从而降低相邻发光器件发光的互相干扰。
下面对本公开第二种显示面板的各部分进行详细说明：
在本公开的一些实施方式中，如图7所示，衬底1上可设有多个驱动晶体管，用于驱动各个发光器件发光，以显示图像。以一个顶栅结构的驱动晶体管为例，显示面板还包括栅绝缘层7、栅极8、第一绝缘层9和第一走线层10，其中：衬底1的材料可为单晶硅或多晶硅等半导体材料，且衬底1可包括有源区101和位于有源区101两端的源极1011和漏极1012。栅绝缘层7覆盖有源区101；栅极8设于栅绝缘层7背离衬底1的表面。第一绝缘层9覆盖栅极8和衬底1，其材料可包括氧化硅和氮化硅中至少一个。第一走线层10设于第一绝缘层9背离衬底1的表面，且栅极8、源极1011和漏极1012均通过钨或其它金属填充的过孔与第一走线层10连接。
此外，显示面板还可包括第二绝缘层11和第二走线层12，第二绝缘层11覆盖第一走线层10和第一绝缘层9，第二走线层12设于第二绝缘层11背离衬底1的表面，第二走线层12的具体图案在此不做特殊限定，其可通过钨或其它金属填充的过孔与第一走线层10连接。
如图7所示，平坦层2设于衬底1的一侧，在本公开的一些实施方式中，平坦层2可覆盖第二走线层12，第一电极31可通过钨或其它金属填充的过孔与第二走线层12连接。平坦层2的材料可包括氮化硅和氧化硅中至少一种，当然，还可以包括其它绝缘材料。
如图7所示，第一电极层3设于平坦层2背离衬底1的一面，且包括多个第一电极31，第一电极31阵列分布，相邻的第一电极31间隔设置。
在平行于衬底1的方向上，每个第一电极31可包括中间部310和围绕中间部310边缘部311，其中，中间部310为平坦结构，即中间部310与平坦层2背离衬底1的表面大致平行。
边缘部311可包括平坦部3110以及爬坡部3111，其中，平坦部3110位于平坦层2背离衬底1的表面，并围绕中间部310设置，且平坦部3110与平坦层2背离衬底1的表面大致平行。同时，平坦部3110的厚度小于中间部310的厚度。在本公开的一些实施方式中，平坦部3110与其所处的驱动区202的边界之间具有不为0的间距。当然，平坦部 3110的边界也可与驱动区202的边界重叠。
爬坡部3111连接于中间部310和平坦部3110之间，即爬坡部3111围绕中间部310，平坦部3110围绕爬坡部3111设置。在本公开的一些实施方式中，爬坡部3111相对于平坦层2背离衬底1的表面的坡度不小于30°，该坡度为爬坡部3111的表面与平坦层2背离衬底1的表面的夹角。
第一电极31包括第一导电层320、第二导电层321和第三导电层322，第一导电层320设于平坦层2背离衬底1的表面，第二导电层321设于第一导电层320背离衬底1的表面，第三导电层322设于第二导电层321背离衬底1的表面，并以一定的坡度延伸至其所处的驱动区202背离衬底1的表面，从而包覆第一导电层320和第二导电层321，对第一导电层320和第二导电层321进行保护。
第一电极31的中间部310包括第三导电层322位于第二导电层321背离衬底1的表面的区域以及第一导电层320和第二导电层321，边缘部311包括第三导电层322包覆第一导电层320和第二导电层321边缘的区域，即向平坦层2延伸的区域。示例性的，第一导电层320的材料可包括钛(Ti)、第二导电层321的材料包括银(Ag)、第三导电层322的材料包括氧化铟锡(ITO)，当然，也可以采用其他材料。
如图7所示，发光功能层5可为连续的膜层，且同时覆盖各第一电极31的至少部分区域。在本公开的一些实施方式中，发光功能层5包括一层发光单元层，发光单元层包括由第一电极31向背离衬底1的方向依次层叠的空穴注入、空穴传输层、发光层、电子传输层和电子注入层。
在本公开的另一实施方式中，发光功能层5包括多层发光单元层，每层发光单元层的空穴注入、空穴传输层、发光层、电子传输层和电子注入层的分布方式相同。同时，相邻两发光单元层之间设有电荷产生层，从而通过电荷产生层将各发光单元层串联，以便形成串联式的OLED发光器件。
如图7所示，第二电极6覆盖发光功能层5，可向第一电极31和第二电极6施加驱动信号，使发光功能层5位于第一电极31和第二电极6之间的部分发光。第二电极6包括多个凹陷部61和多个平缓部62，其中：
各平缓部62阵列分布，且与各第一电极31的中间部310一一对应设置，即各平缓部62在平坦层2上的正投影一一对应的位于各第一电极31以内。平缓部62平行或大致平行于中间部310。
凹陷部61与平坦层2未被中间部310覆盖的区域对应，用于分隔平缓部62，凹陷部61向平缓部62靠近衬底1的一侧凹陷。凹陷部61为环形结构，且数量为多个，各个凹陷部61一一对应的围绕各平缓部62，也就是说，凹陷部61为相邻两个平缓部62的 过渡区域。
凹陷部61在衬底1上的正投影至少部分位于第一电极31的中间部310以外，从而与第一电极31以外的区域或厚度较小的边缘部311正对，而不与厚度较大的中间部310正对，可降低凹陷部61与第一电极31之间出现尖端放电和短路的风险，从而提高发光器件发光的稳定性。
在本公开的一些实施方式中，在垂直于衬底1的截面上，凹陷部61的最低点在平坦层2上的正投影位于中间部310以外，例如，该最低点与爬坡部3111和平坦部3110之一对应，以避免与中间部310之间发生尖端放电。凹陷部61在垂直于衬底1的截面上的最低点为：在垂直于衬底1的截面上，凹陷部61距离第一电极31最近的一点，也即距离平缓部62最远的一点。
需要说明的是，凹陷部61在垂直于衬底1的截面的数量可以有多个，不同截面上的最低点可能不同，例如，该最低点可以是深度方向上距离第一电极31的中间部310最近的一点，也可以是深度方向上的其它点，具体视垂直于衬底1的截面的位置而定。
如图7-图9所示，在本公开的一些实施方式中，凹陷部61具有两个侧面，包括第一侧面611、第二侧面612和底面613，其中，第一侧面611和第二侧面612相对设置，且连接于底面613的两侧。同时，第一侧面611和第二侧面612可沿靠近衬底1的方向收缩。第一侧面611和第二侧面612可以是曲面或平面，在此不做特殊限定。
底面613可为向背离衬底1的方向凸起的曲面，在本公开的一些实施方式中，凹陷部61的底面613包括第一坡面6131、第二坡面6132和连接面6133，其中，第一坡面6131和第二坡面6132均可为曲面或平面，连接面6133位于第一侧面611和第二侧面612的底边背离衬底1的一侧，且连接面6133连接于第一坡面6131和第二坡面6132之间。第一坡面6131与第一侧面611的底边连接，第二坡面6132与第二侧面612的底边连接。
在本公开的一些实施方式中，第一坡面6131相对于中间部310的坡度不小于第一侧面611相对于中间部310的坡度。同时，第二坡面6132相对于中间部310的坡度不小于第二侧面612相对于中间部310的坡度。
进一步对，在垂直于衬底1的截面中，第一坡面6131与第二坡面6132关于连接面6133对称，即第一坡面6131的垂直于衬底1的截面与第二坡面6132的垂直于衬底1的截面关于连接面6133的垂直于衬底1的截面对称。同时，在垂直于衬底1的截面中，第一侧面611和第二侧面612关于底面613对称，即第一侧面611的垂直于衬底1的截面和第二侧面612的垂直于衬底1的截面关于底面613的垂直于衬底1的截面对称。
在本公开的一些实施方式中，第二电极6对应于第一侧面611和第二侧面612的区域的最小厚度，大于第二电极6对应于第一坡面6131和第二坡面6132的区域的最小厚 度。
进一步的，如图7所示，在本公开的一些实施方式中，凹陷部61的深度H小于第二电极6最大厚度的两倍，举例而言，第二电极6的最大厚度为90nm，凹陷部61的深度小于180nm，例如120nm、100nm、80nm、70nm、60nm、50nm、40nm等。凹陷部61的深度H指凹陷部61的最大深度，即：在垂直于衬底1的方向上，凹陷部61距离衬底1最近的一点与平缓部62背离衬底1的表面的距离。
在本公开的一些实施方式中，如图7和图8所示，每个凹陷部61在平坦层2的正投影围绕于一第一电极31的中间部310外，凹陷部61的底面613与相邻的第一电极31的中间部310的距离的最小值(在垂直于衬底1的方向上，凹陷部61距离中间部310最近的一点与中间部310的距离)不小于平缓部62和发光功能层5的总厚度的70％，平缓部62和发光功能层5的总厚度为平缓部62和发光功能层5的厚度之和，例如，平缓部62和发光功能层5的总厚度约为365nm，则凹陷部61在垂直于衬底1的方向的底部与相邻的第一电极31的中间部310距离的最小值的最大值约为255nm。
进一步的，凹陷部61的底部与相邻的第一电极31的中间部310的距离的最大值(在垂直于衬底1的方向上，凹陷部61距离中间部310最近的一点与中间部310的距离)的最大值不小于400nm，且该最大值不大于450nm。
如图7所示，为了便于形成上文中的第二电极6，在本公开的一些实施方式中，平坦层2背离衬底1的表面可开设多个分隔槽201，分隔槽201的深度小于平坦层2的厚度，即分隔槽201在深度方向上不会贯穿平坦层2。通过分隔槽201可在平坦层2上分割出多个驱动区202，且各驱动区202阵列分布。分隔槽201的具体结构可参考上述第一种显示面板的实施方式，在此不再详述。同时，本公开的第二种显示面板还包括像素定义层4，像素定义层4为绝缘材质，且与第一电极层3均设于平坦层2背离衬底1的表面。同时，像素定义层4露出第一电极31的中间部310的至少部分区域，并在对应于分隔槽201的区域凹陷，被像素定义层4露出的中间部310可与对应的发光功能层5和第二电极6构成发光器件。像素定义层4的结构可参考上述第一种显示面板的实施方式，在此不再详述。
发光功能层5还覆盖像素定义层4以及平坦层2未被像素定义层4和第一电极31覆盖的区域，在通过蒸镀或其它工艺形成发光功能层5时，发光功能层5在对应分隔槽201的区域向靠近衬底1的方向凹陷。第二电极6的凹陷部61在平坦层2的正投影至少部分位于分隔槽201的范围内。
此外，如图7所示，本公开的第一种显示面板还可包括第一封装层13，第一封装层13可覆盖第二电极6，举例而言，第一封装层13可包括两层无机层和两层无机层之间的 有机层。第一封装层13在对应于凹陷部61的区域形成凹坑1301，凹坑1301的两个侧壁向靠近衬底1的方向收窄，且两个侧壁连接。
此外，该显示面板还可包括彩膜层14、第二封装层15和透明盖板16，其中：
彩膜层14设于第一封装层13背离第二电极6的一侧，且彩膜层14包括一一对应于各第一电极31的滤光区，滤光区的颜色有多种，例如红色、蓝色和绿色。
第二封装层15可覆盖彩膜层14，其结构可与第一封装层13相同。
透明盖板16可覆盖第二封装层15，其材质可以是玻璃或材料。
此外，在本公开的一些实施方式中，如图7所示，第二种显示面板还可包括光提取层17，光提取层17覆盖于第二电极6背离衬底1的表面，且在对应与凹陷部61的区域凹陷，第一封装层13设于光提取层17背离衬底1的一侧。光提取层17的折射率大于第二电极6，可提高出光效率，且折射率越高，出光效率越高。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述的第一种显示面板，如图10所示，该制造方法包括步骤S110-步骤S160，其中：
步骤S110、在一衬底一侧形成平坦层；
步骤S120、在所述平坦层背离所述衬底的表面形成多个分隔槽，以分割出阵列分布的多个驱动区；
步骤S130、在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
步骤S140、在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域。
步骤S150、所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述平坦层。
步骤S160、形成覆盖所述发光功能层的第二电极。
本公开实施方式的制造方法的各层结构的细节及有益效果已在上文的第一种显示面板的实施方式中进行了说明，在此不再赘述。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述的第一种显示面板，如图11所示，该制造方法包括步骤S210-步骤S250，其中：
步骤S210、在一衬底一侧形成平坦层；
步骤S220、在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层和分隔槽；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；所述分隔槽在所述平坦层分割出阵列分布的多个驱动区；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；
步骤S230、在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域；
步骤S240、形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述平坦层；
步骤S250、形成覆盖所述发光功能层的第二电极。
在本实施方式的制造方法中，可先在平坦层背离衬底的表面形成用于导电层，通过一次灰阶掩膜工艺对导电层进行图案化得到第一电极层，同时，通过该次灰阶掩膜工艺可一并形成分隔槽，相较于通过两次掩膜工艺分别形成第一电极层和分隔槽的方式，可使显示面板的制造工艺得以简化。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述的第二种显示面板，如图12所示，该制造方法包括步骤S310-步骤S340，其中：
步骤S310、在一衬底一侧形成平坦层；
步骤S320、在所述平坦层背离所述衬底的表面形成多个分隔槽，以分割出阵列分布的多个驱动区；
步骤S330、在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；每个所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
步骤S340、在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域和所述分隔槽；
本公开实施方式的制造方法的各层结构的细节及有益效果已在上文的第二种显示面板的实施方式中进行了说明，在此不再赘述。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个 步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施方式还提供一种显示装置，该显示装置可包括上述的第一种显示面板和第二种显示面板的各实施方式中的任意一个，具体结构可参考上文的实施方式，在此不再赘述。本公开的显示装置可用于手机、平板电脑、电视等电子设备。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (26)

  1. 一种显示面板，其中，包括：
    衬底；
    平坦层，设于所述衬底一侧，所述平坦层背离所述衬底的表面设有多个分隔槽，以分割出阵列分布的多个驱动区；
    第一电极层，设于所述平坦层背离所述衬底的表面，且包括多个第一电极；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
    像素定义层，设于所述平坦层背离所述衬底的表面，且露出所述中间部的至少部分区域；
    发光功能层，覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述平坦层；
    第二电极，覆盖所述发光功能层。
  2. 根据权利要求1所述的显示面板，其中，所述分隔槽的最大深度不小于所述发光功能层和所述第一电极的厚度和的30％。
  3. 根据权利要求1所述的显示面板，其中，所述分隔槽的最大深度不大于所述发光功能层和所述第一电极的厚度和的60％。
  4. 根据权利要求2或3所述的显示面板，其中，所述分隔槽的最大深度为
    Figure PCTCN2020085955-appb-100001
  5. 根据权利要求1所述的显示面板，其中，所述分隔槽包括两个相对的侧壁以及连接于两个所述侧壁之间的底面，两个所述侧壁的最大间距为0.2μm-0.7μm。
  6. 根据权利要求1所述的显示面板，其中，所述分隔槽包括两个相对的侧壁以及连接于两个所述侧壁之间的底面，所述底面为向背离所述衬底的方向凸起的曲面。
  7. 根据权利要求1所述的显示面板，其中，所述分隔槽包括两个相对的侧壁以及连接于两个所述侧壁之间的底面；两个所述侧壁平行。
  8. 根据权利要求1所述的显示面板，其中，所述分隔槽包括两个相对的侧壁以及连接于两个所述侧壁之间的底面；两个所述侧壁的间距向靠近所述底面的方向减小。
  9. 根据权利要求8所述的显示面板，其中，两个所述侧壁的坡度不小于70°。
  10. 根据权利要求1所述的显示面板，其中，所述中间部在所述衬底的正投影 的边界与其所处的驱动区在所述衬底的投影的边界之间的间距不小于0.15μm。
  11. 根据权利要求1所述的显示面板，其中，所述平坦部在所述衬底的正投影的边界与其所处的驱动区在所述衬底的正投影的边界之间的间距大于0。
  12. 根据权利要求11所述的显示面板，其中，所述像素定义层延伸至所述分隔槽内，且在对应于所述分隔槽的区域凹陷。
  13. 一种显示面板，其中，包括：
    衬底；
    平坦层，设于所述衬底一侧；
    第一电极层，设于所述平坦层背离所述衬底的表面，且包括多个第一电极；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
    发光功能层，覆盖所述中间部的至少部分区域；
    第二电极，覆盖所述发光功能层，且包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述平坦层上的正投影一一对应的位于各所述第一电极以内；所述凹陷部向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述平坦层上的正投影至少部分位于所述中间部以外。
  14. 根据权利要求13所述的显示面板，其中，在垂直于所述衬底的截面上，所述凹陷部的最低点在所述平坦层上的正投影位于所述中间部以外。
  15. 根据权利要求13所述的显示面板，其中，所述凹陷部包括第一侧面、第二侧面和底面，所述第一侧面和所述第二侧面相对连接于所述底面的两侧，且所述第一侧面和所述第二侧面沿靠近所述衬底的方向收缩。
  16. 根据权利要求15所述的显示面板，其中，所述凹陷部的底面包括第一坡面、第二坡面以及连接于所述第一坡面和所述第二坡面之间的连接面，所述连接面位于所述第一侧面和所述第二侧面的底边背离所述衬底的一侧，所述第一坡面与所述第一侧面的底边连接，所述第二坡面与所述第二侧面的底边连接。
  17. 根据权利要求16所述的显示面板，其中，所述第一坡面相对于所述中间部的坡度不小于所述第一侧面相对于所述中间部的坡度；
    所述第二坡面相对于所述中间部的坡度不小于所述第二侧面相对于所述中间部的坡度。
  18. 根据权利要求16所述的显示面板，其中，在垂直于所述衬底的截面中，所述第一坡面与所述第二坡面关于所述连接面对称，且所述第一侧面与所述第二侧面 关于所述底面对称。
  19. 根据权利要求16所述的显示面板，其中，所述第二电极对应于所述第一侧面和所述第二侧面的区域的最小厚度，大于对应于所述第一坡面和所述第二坡面的区域的最小厚度。
  20. 根据权利要求13-19任一项所述的显示面板，其中，所述平坦层背离所述衬底的表面设有多个分隔槽，以分割出阵列分布的多个驱动区，各所述第一电极在所述平坦层的正投影一一对应的位于各所述第一电极以内；
    所述显示面板还包括：
    像素定义层，设于所述平坦层背离所述衬底的表面，且露出所述中间部的至少部分区域；所述凹陷部在所述平坦层的正投影的至少部分区域位于所述分隔槽内。
  21. 根据权利要求13-19任一项所述的显示面板，其中，所述显示面板还包括：
    第一封装层，覆盖所述第二电极，且在对应于所述凹陷部的区域形成凹坑。
  22. 根据权利要求21所述的显示面板，其中，所述凹坑的两个侧壁向靠近所述衬底的方向收窄且连接。
  23. 一种显示面板的制造方法，其中，包括：
    在一衬底一侧形成平坦层；
    在所述平坦层背离所述衬底的表面形成多个分隔槽，以分割出阵列分布的多个驱动区；
    在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
    在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域；
    形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述平坦层；
    形成覆盖所述发光功能层的第二电极。
  24. 一种显示面板的制造方法，其中，包括：
    在一衬底一侧形成平坦层；
    在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层和分隔层；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括 围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；所述分隔槽在所述平坦层分割出阵列分布的多个驱动区；各所述第一电极在所述平坦层的正投影一一对应的位于各所述驱动区以内；
    在所述平坦层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域；
    形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述平坦层；
    形成覆盖所述发光功能层的第二电极。
  25. 一种显示面板的制造方法，其中，包括：
    在一衬底一侧形成平坦层；
    在所述平坦层背离所述衬底的表面形成包括多个第一电极的第一电极层；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
    形成覆盖所述中间部的至少部分区域的发光功能层；
    形成覆盖所述发光功能层的第二电极，所述第二电极包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述平坦层上的正投影一一对应的位于各所述第一电极以内；所述凹陷部向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述平坦层上的正投影至少部分位于所述中间部以外。
  26. 一种显示装置，其中，包括权利要求1-22任一项所述的显示面板。
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