WO2020253336A1 - 显示基板及其制造方法、有机发光二极管显示装置 - Google Patents

显示基板及其制造方法、有机发光二极管显示装置 Download PDF

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Publication number
WO2020253336A1
WO2020253336A1 PCT/CN2020/084001 CN2020084001W WO2020253336A1 WO 2020253336 A1 WO2020253336 A1 WO 2020253336A1 CN 2020084001 W CN2020084001 W CN 2020084001W WO 2020253336 A1 WO2020253336 A1 WO 2020253336A1
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Prior art keywords
layer
source
drain
planarization
forming
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PCT/CN2020/084001
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English (en)
French (fr)
Inventor
田宏伟
牛亚男
李栋
刘明
刘政
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京东方科技集团股份有限公司
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Publication of WO2020253336A1 publication Critical patent/WO2020253336A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to a display substrate, a manufacturing method thereof, and an organic light emitting diode display device.
  • OLED Organic Electro Luminescent Display
  • IR-drop refers to the phenomenon that the voltage in the power supply and ground network in the current circuit drops or rises.
  • a display substrate including:
  • An array substrate having a display area, the display area including a pixel area and a non-pixel area surrounding the pixel area;
  • the protruding structure is located on the array substrate along a first direction and located in the non-pixel area, and the first direction is the light emitting direction of the display substrate or the opposite direction of the light emitting direction;
  • a first metal layer located on the protruding structure along the first direction and conductively connected to the working voltage terminal;
  • a first planarization layer located on the array substrate along the first direction
  • a plurality of functional layers and cathode layers are sequentially arranged on the first planarization layer along the first direction,
  • the cathode layer is electrically connected to the first metal layer through via holes.
  • the via is provided in at least one of the plurality of functional layers and the first planarization layer, and the orthographic projection of the via on the array substrate and the protrusion The orthographic projection of the structure on the array substrate at least partially overlaps,
  • the cathode layer directly contacts the first metal layer in the via hole.
  • the multiple functional layers include:
  • the second metal layer is located on the first metal layer along the first direction, is electrically connected to the first metal layer, and directly contacts the cathode layer through the via hole.
  • the multiple functional layers further include:
  • a pixel definition layer located on the second metal layer along the first direction
  • An organic light emitting layer located on the pixel defining layer along the first direction;
  • the via hole is arranged in the pixel definition layer and the organic light emitting layer.
  • the display substrate further includes:
  • the anode layer is located on the first planarization layer along the first direction, and is provided in the same layer as the second metal layer.
  • the maximum height of the raised structure relative to the array substrate is 1200 nm to 3000 nm.
  • the array substrate includes:
  • a thin film transistor located on the substrate along the first direction and including a gate layer and a first source and drain layer,
  • the first source drain layer and the first metal layer are provided in the same layer.
  • the display substrate further includes:
  • a thin film transistor located on the substrate along the first direction and including a gate layer and a first source and drain layer;
  • An interlayer insulating layer located between the gate layer and the first source and drain layer;
  • the protruding structure is located on the interlayer insulating layer along the first direction.
  • the array substrate further has a bending area, and the bending area is provided with a groove and a filling material located in the groove, and the filling material is the same as the material of the protruding structure.
  • the array substrate includes:
  • a thin film transistor located on the substrate along the first direction and including a gate layer, a second source and drain layer, and a first source and drain layer;
  • An interlayer insulating layer located between the gate layer and the second source and drain layer;
  • a second planarization layer located on the interlayer insulating layer along the first direction and covering the second source and drain layer;
  • first source and drain layer and the protruding structure are located on the second planarization layer along the first direction, and the source and drain of the first source and drain layer are respectively connected to the The source and drain of the second source-drain layer are electrically connected.
  • the protruding structure is made of the same material as the second planarization layer.
  • the display substrate includes a plurality of raised structures located on the second planarization layer along the first direction; the array substrate has a bending area, and the bending area is provided with a concave
  • a part of the plurality of convex structures is the same as the material of the second planarization layer, and the other part is the same as the material of the filling material.
  • a method for manufacturing a display substrate including:
  • an array substrate with a display area, the display area including a pixel area and a non-pixel area surrounding the pixel area;
  • the cathode layer before forming the cathode layer, it further includes:
  • a via hole is formed in at least one of the plurality of functional layers and the first planarization layer, so that the cathode layer is electrically connected to the first metal layer through the via hole.
  • the orthographic projection of the via on the array substrate and the orthographic projection of the protrusion structure on the array substrate are at least partially overlapped.
  • the operation of forming the first planarization layer includes:
  • the thickness of the material, the processing area is at least part of the orthographic projection of the convex structure on the planarized material layer on the planarized material layer.
  • the operation of forming the via includes:
  • a via is formed in the plurality of functional layers and the first planarization layer to expose a part of the first metal layer at the bottom of the via.
  • the operation of forming the first planarization layer includes:
  • the material in the processing area of the planarization material layer is removed to expose the first metal layer, and the processing area is an orthographic projection of the protruding structure on the planarization material layer on the planarization material layer At least part of it.
  • the operation of forming the plurality of functional layers includes:
  • the operation of forming the via includes:
  • a via hole is formed in the organic light emitting layer and the pixel definition layer, and the portion of the second metal layer at the bottom of the via hole is exposed, so that the cathode layer passes through the via hole and the second metal layer direct contact.
  • the operation of forming the via includes:
  • the via hole is formed in the plurality of functional layers, and the portion of the first metal layer at the bottom of the via hole is exposed.
  • the manufacturing method further includes:
  • An anode layer is formed on the first planarization layer, and the anode layer and the second metal layer are formed by the same patterning process.
  • the step of providing the array substrate includes:
  • the thin film transistor including a gate layer and a first source and drain layer
  • the first source and drain layer and the first metal layer are formed by the same patterning process.
  • the step of providing the array substrate includes:
  • the thin film transistor including a gate layer and a first source and drain layer;
  • an interlayer insulating layer is formed on the gate layer, and the protrusion structure is formed on the interlayer insulating layer.
  • the array substrate further has a bending area
  • the manufacturing method further includes:
  • the protruding structure and the filling material are formed by the same patterning process.
  • the operation of providing the array substrate includes:
  • the thin film transistor including a gate layer, a second source drain layer, and a first source drain layer;
  • an interlayer insulating layer is formed on the gate layer, and the second source and drain layer is formed on the interlayer insulating layer, and then a second source and drain layer is formed on the interlayer insulating layer.
  • Two planarization layers, and the second planarization layer covers the second source and drain layers;
  • the protruding structure and the first source and drain layer are formed on the second planarization layer, and the source and drain of the first source and drain layer are respectively connected to the second source and drain.
  • the source and drain of the electrode layer are electrically connected.
  • the protrusion structure and the second planarization layer are formed by the same patterning process.
  • the operation of providing the array substrate includes:
  • the thin film transistor including a gate layer, a second source drain layer, and a first source drain layer;
  • an interlayer insulating layer is formed on the gate layer, and the second source and drain layer is formed on the interlayer insulating layer, and then a second source and drain layer is formed on the interlayer insulating layer.
  • Two planarization layers, and the second planarization layer covers the second source and drain layers;
  • the array substrate further has a bending area
  • the manufacturing method further includes:
  • the operation of forming the convex structure includes:
  • a plurality of raised structures are formed on the second planarization layer, and a part of the plurality of raised structures and the filling material are formed by the same patterning process, and another part of the plurality of raised structures is formed with The second planarization layer is formed by the same patterning process.
  • an organic light emitting diode display device including the aforementioned display substrate.
  • FIG. 1 is a schematic diagram of a connection between a display area and a common electrode in an embodiment of a display substrate according to the present disclosure
  • FIGS. 2 to 6 are respectively structural schematic diagrams of some embodiments of the display substrate according to the present disclosure.
  • FIG. 7 is a schematic flowchart of an embodiment of a method for manufacturing a display substrate according to the present disclosure.
  • FIGS. 8-10 are schematic diagrams of the flow from the step of forming the first planarization layer to the step of forming via holes in some embodiments of the method for manufacturing a display substrate according to the present disclosure
  • FIG. 11 is a schematic flow chart of a bending area process in an embodiment of a method for manufacturing a substrate according to the present disclosure
  • FIG. 12 is a schematic flowchart of another embodiment of a method for manufacturing a display substrate according to the present disclosure.
  • FIG. 13(a)-FIG. 13(k) are schematic diagrams of the manufacturing process of an embodiment of the display substrate according to the present disclosure.
  • a specific device when it is described that a specific device is located between the first device and the second device, there may or may not be an intermediate device between the specific device and the first device or the second device.
  • the specific device When it is described that a specific device is connected to another device, the specific device may be directly connected to the other device without an intervening device, or may not be directly connected to the other device but with an intervening device.
  • the cathode in the related art is generally not formed very thick.
  • the cathode usually uses a current conduction path from the periphery to the center, which makes the resistance of the cathode itself relatively larger. As the display area increases, the resistance will have a greater impact on IR-Drop. Based on the difference in voltage and current in different areas, the display brightness of each area is different, and the corresponding display effects have obvious differences, which affect the viewing experience of consumers.
  • some related technologies When facing a larger area display circuit, some related technologies use auxiliary cathodes to overcome IR-Drop caused by excessive cathode resistance.
  • some related technologies remove the film layer under the cathode layer in the display area by laser or other methods, and then connect the cathode layer with a circuit that has a lower resistance and is electrically connected to the common electrode terminal. Thereby reducing the IR-Drop caused by excessive cathode resistance.
  • the thicker film layer under the cathode layer needs to be removed in order to expose the circuit that needs to be electrically connected to the cathode layer.
  • the thicker the film removed the more film material is removed, which makes the removal process produce more products, and too many products are easier for the packaging and evaporation to emit light.
  • the film layer adversely affects the yield of the display substrate.
  • a large step difference between the removed area and the non-removed area may be caused, which is prone to fracture when the cathode layer is formed, and it also limits the cathode to a certain extent. Choice of layer material.
  • embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and an organic light emitting diode display device, which can improve the climbing angle of the cathode layer at the via hole.
  • FIG. 1 is a schematic diagram of the connection between the display area and the common electrode in an embodiment of the display substrate according to the present disclosure.
  • the display substrate includes an array substrate 30.
  • the array substrate 30 may have a display area 10 and other areas that implement non-display functions.
  • the display area 10 of the array substrate 30 may be provided with a plurality of pixel units to realize the display function.
  • the display area 10 includes a pixel area 11 for arranging pixel units and a non-pixel area 12 surrounding the pixel area 11.
  • the non-pixel area 12 can be used to define the range of the pixel area 11.
  • a negative power signal layer 20 can be provided around the display area 10 of the array substrate 30.
  • the negative power signal 20 is electrically connected to the cathode layer of the display substrate and can pass through a terminal 21 is electrically connected to the working voltage terminal (for example, Vss).
  • an auxiliary cathode can be used to reduce the resistance from the negative power signal layer to the cathode layer.
  • a metal layer that is conductive to the working voltage terminal is provided in the display area 10 of the array substrate 30, and a plurality of via holes 80 are arranged in the non-pixel area 12 to realize electrical connection between the cathode layer and the metal layer under the via holes. In this way, the resistance between the cathode of the pixel unit and the working voltage terminal can be reduced, thereby effectively reducing IR-Drop.
  • the number and location of the vias 80 can be designed according to the pixel ratio.
  • the relationship between the number of vias 80 and the pixels in the display area 10 is set to 1:4 to 1:400.
  • Adjacent via holes 80 can be arranged at intervals of 4 to 400 pixels.
  • the plurality of via holes 80 may be arranged in a regular or irregular distribution according to the shape of the display area 10.
  • Figures 2 to 6 are respectively structural schematic diagrams of some embodiments of the display substrate according to the present disclosure.
  • the display substrate includes: an array substrate 30, a convex structure 40, a first metal layer 22, a first planarization layer 50, a plurality of functional layers, and a cathode layer 70.
  • the protruding structure 40 is located on the array substrate 30 along the first direction (ie, the vertical direction from bottom to top in FIGS. 2 to 4), and is located in the non-pixel area.
  • the first direction may be the light-emitting direction of the display substrate or the opposite direction of the light-emitting direction of the display substrate.
  • the first direction is the light emitting direction of the display substrate.
  • the first direction is the opposite direction of the light-emitting direction of the display substrate.
  • the convex structure 40 protrudes upward relative to the array substrate 30.
  • the shape of the convex structure 40 may be a circle, an ellipse or a polygon.
  • the material of the protrusion structure 40 may include at least one of silicon oxide, silicon nitride, and polyimide.
  • the number of raised structures 40 may be determined according to the number of via holes 80 distributed in the display area. For example, the number of raised structures 40 is equal to or less than the number of via holes 80.
  • the protrusion structure 40 may be arranged on the array substrate 30 along at least one second direction perpendicular to the first direction.
  • the maximum height h1 of the raised structure 40 relative to the array substrate can be determined according to one or more factors of the thickness of the first planarization layer on the array substrate 30, the thickness of multiple functional layers, and the climbing ability of the cathode layer.
  • h1 can be set to 1200nm ⁇ 3000nm.
  • the first metal layer 22 is located on the protruding structure 40 along the first direction, and can be used as an auxiliary cathode to be electrically connected to the working voltage terminal. Referring to FIGS. 2 to 4, the first metal layer 22 may also be located on the periphery of the protrusion structure 40 and be integrally formed with the first metal layer 22 on the protrusion structure 40.
  • the first planarization layer 50 may be located on the array substrate 30 along the first direction, and is used to provide a flat surface for the formation of multiple functional layers.
  • the composition of multiple functional layers may be different.
  • the multiple functional layers include a pixel definition layer 61 and an organic light emitting layer 62.
  • the multiple functional layers include a second metal layer 63, a pixel definition layer 61, and an organic light emitting layer 62.
  • the organic light emitting layer 62 may include, for example, a light emitting function layer such as an electron injection layer, an electron blocking layer, an electron transport layer, a light emitting layer, a hole injection layer, a hole blocking layer, or a hole transport layer.
  • the multiple functional layers may also include functional layers that implement other functions, such as a touch sensor layer.
  • a plurality of functional layers and the cathode layer 70 may be sequentially disposed on the first planarization layer 50 along the first direction.
  • the cathode layer 70 In order to electrically connect the cathode layer 70 to the first metal layer 22 underneath, referring to FIGS. 2 to 4, in some embodiments, at least one of the plurality of functional layers and the first planarization layer 50 With vias 81, 82 or 83.
  • the cathode layer 70 is electrically connected to the first metal layer 22 through the vias 81, 82 or 83, so as to reduce the resistance from the operating voltage terminal to the cathode layer by means of an auxiliary cathode.
  • the orthographic projection of the via 81, 82, or 83 on the array substrate 30 and the orthographic projection of the protrusion structure 40 on the array substrate 30 at least partially overlap, that is, the via 81, 82, or 83 is on the array substrate 30.
  • the orthographic projection of the raised structure 40 can completely overlap with the orthographic projection of the protruding structure 40 on the array substrate 30, or only partially overlap.
  • the orthographic projection of the vias 81, 82, and 83 on the array substrate 30 refers to the orthographic projection of the hole walls of the vias 81, 82, and 83 on the array substrate 30 and the surrounding area.
  • the orthographic projection of the raised structure 40 on the array substrate 30 refers to the orthographic projection of the entire entity of the raised structure 40 on the array substrate 30.
  • the bottom of the via hole portion can be formed above the raised structure 40, and accordingly the bottom can be made relative to the uppermost layer of the multiple functional layers (for example, the organic light-emitting layer 62 in FIG. 2).
  • the height difference is relatively small.
  • the cathode layer 70 is formed, the height difference h2 between the via hole and the area around the via hole is also relatively small, which improves the climbing angle of the cathode layer at the via hole, so that the cathode layer is not easy to pass during the formation.
  • the hole is broken.
  • the via 81 penetrates the organic light emitting layer 62, the pixel defining layer 61 and the first planarization layer 50 from top to bottom, so that the cathode layer 70 can directly contact the first metal layer 22 in the via 81 . Since the first metal layer 22 located above the raised structure 40 is at a higher position than the array substrate 30, when the first planarization layer 50 is formed, the first planarization layer 50 can be made above the raised structure 40 The material is thinner, or the planarization layer material above the raised structure 40 is removed to expose the first metal layer 22.
  • the first planarization layer 50 When forming the first planarization layer 50, if a smaller thickness of the planarization layer material remains above the raised structure 40, after the formation of multiple functional layers, and before the formation of the cathode layer 70, it can be moved by laser or the like. A plurality of functional layers and the planarization layer material located above the protrusion structure 40 are removed, so that the first metal layer 22 above the protrusion structure 40 is exposed at the bottom of the formed via 81.
  • the first planarization layer 50 When the first planarization layer 50 is formed, if the planarization layer material above the convex structure 40 has been removed, it can be moved by laser or the like after the formation of multiple functional layers and before the formation of the cathode layer 70. A plurality of functional layers are removed to form the via 81 so that the bottom of the via 81 exposes the first metal layer 22 above the protrusion structure 40.
  • some embodiments of the present disclosure thin or remove the protruding structure when forming the first planarization layer 50
  • the upper material, after forming the organic light-emitting layer can reduce the thickness of the planarization layer material that needs to be removed when forming the via hole, or there is no need to remove the planarization layer material above the convex structure, so the generation of the removal process can be reduced It reduces the adverse effect of the product on the organic light-emitting layer, thereby improving the yield of the display substrate.
  • the second metal layer 63 is located on the first metal layer 22 along the first direction, and is electrically connected to the first metal layer 22.
  • the second metal layer 63 may also be located on the first planarization layer 50 on the periphery of the first metal layer 22 and formed integrally with the second metal layer 63 on the first metal layer 22.
  • the display substrate further includes an anode layer located on the first planarization layer 50 along the first direction, which can be used to form an anode of an OLED light-emitting panel.
  • the second metal layer 63 may be provided in the same layer as the anode layer.
  • the same layer here may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous.
  • These specific graphics may also be at different heights or have different thicknesses.
  • the second metal layer and the anode layer can be formed by the same patterning process during formation, so as to simplify the processing procedure.
  • the second metal layer and the anode layer can be made of the same material, for example, conductive materials including conductive oxides (such as indium tin oxide and indium zinc oxide) or reflective metals (silver, aluminum, etc.).
  • the same patterning process here means that the same film forming process is used to form a film layer for forming a specific pattern, and then the same mask is used to form a layer structure through a single patterning process.
  • the pixel definition layer 61 is located on the second metal layer 63 along the first direction.
  • the organic light emitting layer 62 is located on the pixel defining layer 61 along the first direction.
  • the cathode layer 70 is located on the organic light emitting layer along the first direction.
  • the material of the cathode layer may include at least one of Li, Ag, Ca, Al, and Mg.
  • via holes 82 are provided in the pixel defining layer 61 and the organic light emitting layer 62, and the cathode layer 70 directly contacts the second metal layer 63 through the via holes 82. Retaining the second metal layer 63 when forming the via hole can reduce the thickness of the material under the cathode layer 60 that needs to be removed when the via hole is formed, and reduce the production of the removal process; on the other hand, it can avoid the second metal layer when removing the material. A metal layer is removed by mistake, thereby improving the reliability of the electrical connection.
  • the via hole 83 is provided in the second metal layer 63, the pixel defining layer 61 and the organic light emitting layer 62.
  • the cathode layer 70 directly contacts the first metal layer 22 through the via hole 83, which can further reduce the cathode layer 70.
  • the resistance between the pixel unit and the first metal layer 22 reduces the resistance between the cathode of the pixel unit and the working voltage terminal, thereby effectively reducing IR-Drop.
  • the array substrate includes a substrate 31 and a thin film transistor (TFT) located on the substrate 31.
  • the thin film transistor includes a gate layer and a first source and drain layer.
  • the first source-drain layer can be used to form the source (Source Pole) and drain (Drain Pole) of the thin film transistor device.
  • the thin film transistor may further include an active layer 91, and the source 94 and the drain 95 in the first source and drain layer are connected to the active layer 91.
  • the first metal layer 22 may be provided in the same layer as the first source and drain layer. In this way, the first metal layer 22 and the first source/drain layer can be formed by the same patterning process during formation, so as to simplify the processing procedure.
  • the array substrate further includes a buffer layer 32, a gate insulating layer, an interlayer insulating layer 35 and the like.
  • the buffer layer 32 of the array substrate is disposed on the substrate 31
  • the active layer 91 is disposed on the buffer layer 32
  • the first gate insulating layer 33 covers the active layer 91
  • the first gate layer 92 is disposed on the first gate insulating layer 33
  • the second gate insulating layer 34 covers the first gate layer 92
  • the second gate layer 93 is disposed on the second gate insulating layer 34
  • the interlayer insulating layer 34 covers the second gate layer 93.
  • the thin film transistor may include a gate layer and a corresponding gate insulating layer.
  • the raised structure 40 in FIG. 5 may be located on the surface of the interlayer insulating layer 35 along the first direction.
  • the first source and drain layer may also be provided on the surface of the interlayer insulating layer 35, and the source electrode 94 and the drain electrode 95 in the first source and drain layer penetrate the interlayer insulating layer 35, the second gate insulating layer 34 and the first A gate insulating layer 33 is connected to the active layer 91.
  • the source 94 and the drain 95 in the first source and drain layer may be arranged in the same layer as the first metal layer 22.
  • the source 94 and the drain 95 in the first source and drain layer can be formed of the same material as the first metal layer 22, for example, at least one of conductive materials such as molybdenum, copper, aluminum, gold, silver, or titanium. And can be formed by the same patterning process to save processing procedures.
  • the array substrate may also have a bending area 100 for realizing the bendability of the display substrate.
  • a recess penetrating the interlayer insulating layer 35, the second gate insulating layer 34, the first gate insulating layer 33, and the buffer layer 32 may be formed in the bending area 100 (for example, by an exposure-etching process).
  • the bottom of the groove and the groove exposes a substrate 31 made of flexible material.
  • a filling material 110 may be filled in the groove, and the filling material 110 may be formed by the same patterning process as the protrusion structure 40.
  • a halftone (Halftone) process is used to obtain the Pad-Bending pattern while forming the convex structure 40.
  • Both the filling material 110 and the convex structure 40 can use polyimide.
  • the maximum height of the filling material 110 is 500-1200 nm
  • the maximum height of the convex structure 40 is 1200-3000 nm, which is larger than the filling material. The maximum height of the material relative to the array substrate.
  • the array substrate includes a substrate 31, a thin film transistor, an interlayer insulating layer 35 and a second planarization layer 36.
  • the thin film transistor includes a gate layer, a second source and drain layer, and a first source and drain layer.
  • the source and drain of the second source-drain layer are electrically connected to the source and drain of the first source-drain layer, respectively. Both the source and drain of the first source-drain layer are electrically connected to the active layer 91.
  • the array substrate further includes a buffer layer 32, a gate insulating layer and the like.
  • the buffer layer 32 of the array substrate is disposed on the substrate 31
  • the active layer 91 is disposed on the buffer layer 32
  • the first gate insulating layer 33 covers the active layer 91
  • the first gate layer 92 is disposed on the first gate insulating layer 33
  • the second gate insulating layer 34 covers the first gate layer 92
  • the second gate layer 93 is disposed on the second gate insulating layer 34
  • the interlayer insulating layer 34 covers the second gate layer 93.
  • the buffer layer 32, the first gate insulating layer 33, the second gate insulating layer 34, the interlayer insulating layer 35, and the second planarization layer 36 can be made of the same material or different materials.
  • the material may include at least one of silicon oxide, silicon nitride, and polyimide.
  • the thin film transistor may include a gate layer and a corresponding gate insulating layer.
  • the second source and drain layer may be disposed on the interlayer insulating layer 35 along the first direction, that is, the interlayer insulating layer 35 is located on the gate layer and the second source and drain electrodes. Between layers. The source 94' and the drain 95' in the second source and drain layer penetrate the interlayer insulating layer 35, the second gate insulating layer 34, and the first gate insulating layer 33 to connect to the active layer 91.
  • the second planarization layer 36 is located on the interlayer insulating layer 35 along the first direction and covers the second source and drain layers, and the raised structure 40' may be disposed on the second planarization layer 36.
  • the raised structure 40' may be the same material as the second planarization layer 36.
  • the convex structure 40' may be formed by the same patterning process when forming the second planarization layer 36.
  • the first source and drain layer may be disposed on the second planarization layer 36, and the source 94 and the drain 95 of the first source and drain layer penetrate through the second planarization layer 36 to connect with the second source and drain respectively.
  • the source 94' and drain 95' of the layer are connected.
  • the source electrode 94 and the drain electrode 95 in the first source-drain layer can be formed by the same patterning process as the first metal layer 22 to save processing steps.
  • the material of the protrusion structure may be the same as the material of multiple parts in the display substrate.
  • the display substrate includes a plurality of raised structures located on the second planarization layer.
  • the array substrate has a bending area, the bending area is provided with a groove and a filling material in the groove, a part of the plurality of convex structures is the same as the material of the second planarization layer, and the other part is with The material of the filling material is the same.
  • the protruding structure can be made of the same material as the multiple parts of the display substrate, the protruding structure can be formed at the same time through the preparation process of the corresponding part of the display substrate, thereby reducing the preparation process of the display substrate and improving the manufacturing efficiency.
  • a part of the plurality of raised structures can be formed by the same patterning process with the filling material filled in the grooves of the bending area, and the plurality of raised structures The other part and the second planarization layer are formed by the same patterning process.
  • FIG. 7 is a schematic flowchart of an embodiment of a method for manufacturing a display substrate according to the present disclosure.
  • the manufacturing method of the display substrate includes steps S100-S700.
  • step S100 an array substrate having a display area is provided.
  • the display area includes a pixel area and a non-pixel area surrounding the pixel area.
  • step S200 a convex structure is formed on the non-pixel area of the array substrate.
  • the maximum height of the convex structure relative to the array substrate may be 1200 nm to 3000 nm.
  • step S300 a first metal layer conductively connected to the working voltage terminal is formed on the protrusion structure.
  • step S400 a first planarization layer is formed on the array substrate.
  • step S500 a plurality of functional layers are formed on the first planarization layer.
  • a via is formed in at least one of the plurality of functional layers and the first planarization layer.
  • the orthographic projection of the via hole on the array substrate and the orthographic projection of the protrusion structure on the array substrate may at least partially overlap.
  • a cathode layer is formed on the plurality of functional layers, and the cathode layer is electrically connected to the first metal layer through the via hole.
  • FIGS. 8-10 are schematic diagrams of the specific flow from the step of forming the first planarization layer to the step of forming via holes in some embodiments of the method for manufacturing a display substrate according to the present disclosure.
  • step S400 may include step S410 and step S420.
  • step S410 a planarization material layer is formed on the array substrate, and the planarization material layer covers the first metal layer.
  • step S420 the thickness of the first material in the processing area of the planarization material layer is adjusted to form the first planarization layer, and the thickness of the first material is smaller than that on the planarization material layer.
  • the processing area is at least a part of the planarization material layer located on the orthographic projection of the protruding structure on the planarization material layer.
  • step S600 specifically includes step S610, that is, forming via holes in the plurality of functional layers and the first planarization layer to expose the bottom of the first metal layer at the bottom of the via hole. section. Since the material thickness of the processing area has been adjusted to a smaller thickness in step S420, compared to the need to remove a thicker planarization layer when forming a via hole in the related art, the thickness of the material that needs to be removed when forming a via hole in step S610 Less, less products are produced.
  • step S400 may include step S410 and step S430.
  • step S410 a planarization material layer is formed on the array substrate, and the planarization material layer is covered on the first metal layer.
  • step S430 the material in the processing area of the planarization material layer is removed to expose the first metal layer.
  • the processing area is at least a part of the planarization material layer located on the orthographic projection of the protruding structure on the planarization material layer.
  • step S600 specifically includes step S620, that is, forming via holes in the plurality of functional layers to expose the portion of the first metal layer at the bottom of the via hole. Since the material in the processing area has been removed in step S430, compared to the need to remove the thicker planarization layer when forming vias in the related art, it is not necessary to remove the first planarization layer when forming vias in step S620, so it needs to be removed The thickness of the material is less, and the products produced are also less.
  • step S400 may include step S410 and step S430.
  • step S410 a planarization material layer is formed on the array substrate, and the planarization material layer covers the first metal layer.
  • step S430 the material in the processing area of the planarization material layer is removed to expose the first metal layer.
  • the processing area is at least a part of the planarization material layer located on the orthographic projection of the protruding structure on the planarization material layer.
  • step S500 may specifically include step S510 to step S530.
  • step S510 a second metal layer electrically connected to the first metal layer is formed on the first metal layer.
  • step S520 a pixel definition layer is formed on the second metal layer.
  • step S530 an organic light emitting layer is formed on the pixel definition layer.
  • step S600 specifically includes step S630, that is, forming a via hole in the organic light-emitting layer and the pixel definition layer, and exposing the portion of the second metal layer at the bottom of the via hole so as to The cathode layer directly contacts the second metal layer through the via hole.
  • step S630 Since the material in the processing area has been removed in step S430, compared to the material of the thicker planarization layer that needs to be removed when forming the via hole in the related art, only the organic light-emitting layer and the pixel definition layer need to be removed when forming the via hole in step S630 There is no need to remove the second metal layer and the first planarization layer, so the thickness of the material to be removed is less, and fewer products are generated. On the other hand, when removing the material, the first metal layer can be prevented from being removed by mistake, thereby improving the reliability of the electrical connection.
  • the step of providing an array substrate may include: providing a substrate, and forming a thin film transistor on the substrate, the thin film transistor including a gate layer and a first source and drain layer.
  • the thin film transistor may further include an active layer, and the source and drain of the first source-drain layer may be electrically connected to the active layer.
  • the first source and drain layer may be formed by the same patterning process as the first metal layer in the embodiment of FIGS. 8-10 to save processing steps.
  • an interlayer insulating layer may be formed on the gate layer.
  • the protrusion structure may be formed on the interlayer insulating layer.
  • an anode layer may also be formed on the first planarization layer.
  • the anode layer may be formed by the same patterning process as the second metal layer in the embodiment of FIG. 9 and FIG. 10 to save processing steps.
  • FIG. 11 is a schematic flowchart of a bending area process in an embodiment of a method for manufacturing a display substrate according to the present disclosure.
  • the array substrate further has a bending area.
  • the manufacturing method may further include step S100' and step S700.
  • step S100' an array substrate having a display area and a bending area is provided.
  • the display area includes a pixel area and a non-pixel area surrounding the pixel area.
  • Step S100' may be included in step S100.
  • step S700 a groove is formed in the bending area.
  • Step S200 may include step S210, that is, filling the groove with a filling material, and forming a convex structure on the non-pixel area of the array substrate through the same patterning process. In this way, the convex structure can be formed at the same time when filling the bending area, thereby saving process.
  • FIG. 12 is a schematic flowchart of another embodiment of a method for manufacturing a display substrate according to the present disclosure.
  • the operation of providing the array substrate may include: providing a substrate, and forming a thin film transistor on the substrate, the thin film transistor including a gate layer, a second source and drain layer And the first source and drain layer.
  • the thin film transistor may further include an active layer, and the source and drain of the second source and drain layer may be electrically connected to the active layer.
  • an interlayer insulating layer may be formed on the gate layer, and the second source and drain layer may be formed on the interlayer insulating layer, and then a second layer may be formed on the interlayer insulating layer.
  • a planarization layer, and the second planarization layer covers the second source and drain layer.
  • the raised structure and the first source-drain layer are formed on the second planarization layer, and the source and drain of the first source-drain layer are respectively connected to the second source-drain layer
  • the source and drain are electrically connected.
  • the protruding structure and the second planarization layer may be formed by the same patterning process. In other embodiments, the formation of the protrusion structure may also be after the formation of the second planarization layer.
  • the step of providing an array substrate includes step S110 to step S190.
  • step S110 a substrate is provided, and a buffer layer is formed on the substrate.
  • step S120 an active layer is formed on the buffer layer.
  • step S130 a first gate insulating layer is covered on the active layer.
  • step S140 a first gate layer is formed on the first gate insulating layer.
  • step S150 a second gate insulating layer is covered on the first gate layer.
  • a second gate layer is formed on the second gate insulating layer.
  • step S170 an interlayer insulating layer is covered on the second gate layer.
  • a second source and drain layer is formed on the interlayer insulating layer, and the source and drain in the second source and drain layer penetrate the interlayer insulating layer, the second gate insulating layer and the first gate.
  • the polar insulating layer is connected to the active layer.
  • a second planarization layer is formed on the interlayer insulating layer, and the second planarization layer covers the second source and drain layers.
  • Step S200 can be independent of step S190, or can be combined with step S190, that is, when forming the second planarization layer, the convex structure in the non-pixel area of the array substrate is formed through the same patterning process to save the process.
  • step S190 when a plurality of raised structures are formed in the non-pixel area, a part of the plurality of raised structures and the filling material are formed by the same patterning process, and among the plurality of raised structures The other part and the second planarization layer are formed by the same patterning process.
  • FIG. 13(a)-FIG. 13(k) are schematic diagrams of the manufacturing process of an embodiment of the display substrate according to the present disclosure.
  • a substrate 31 is provided.
  • a buffer layer 32 is formed on the substrate 31, and an active layer 91 is formed on the buffer layer 32.
  • the first gate insulating layer 33 is covered on the active layer 91, and the first gate insulating layer 33 is also covered on the buffer layer 32.
  • a first gate layer 92 is formed on the first gate insulating layer 33, and a second gate insulating layer is covered on the first gate layer 92.
  • the second gate insulating layer 34 also covers the first gate.
  • a second gate layer 93 is formed on the second gate insulating layer 34, and an interlayer insulating layer 35 is covered on the second gate layer 93, and the interlayer insulating layer 35 also covers the second gate insulating layer 34. on.
  • the array substrate may have a display area and a bending area.
  • via holes A and B penetrating the interlayer insulating layer 35, the second gate insulating layer 34, and the first gate insulating layer 33 may be formed in the display area, and the penetrating layer may be formed in the bending area
  • the via holes A, B and the groove C may be formed in the same process, or may be formed in different processes.
  • the groove C is filled with a filling material 110 as a substrate bending pattern by a halftone process, and a convex structure 40 is formed on the non-pixel area of the interlayer insulating layer 35.
  • Both the filling material 110 and the protrusion structure 40 can use polyimide, and relative to the interlayer insulating layer 35, the maximum height of the filling material 110 is 500-1200 nm, and the maximum height of the protrusion structure 40 is 1200-3000 nm .
  • the first metal layer 22 and the first source/drain layer are formed on the interlayer insulating layer 35, and the first metal layer 22 is made to cover the protrusion structure 40.
  • the first metal layer 22 can be electrically connected to the working voltage terminal.
  • the source electrode 94 and the drain electrode 95 in the first source-drain layer are electrically connected to the active layer 91 through the via holes A and B, thereby forming the thin film transistor in the array substrate.
  • the first metal layer 22 and the first source and drain layers can be formed by the same patterning process.
  • the first metal layer 22 may or may not cover the bending area.
  • a planarization material layer 50' is formed on the interlayer insulating layer 35, and the planarization material layer 50' covers the first metal layer 22, the source 94 and the drain of the first source and drain layer. ⁇ 95.
  • the planarization material layer 50' may or may not cover the bending area.
  • the height of the planarization material layer 50' at different positions relative to the interlayer insulating layer 35 is different, and the area 51 located on the upper side of the raised structure 40 is higher than other areas.
  • the planarization material layer 50' is processed to form a first planarization layer 50 that is flatter.
  • the material in the processing area 51 of the planarization material layer 50' can be removed to expose the first metal layer 22.
  • the second metal layer 63, the pixel definition layer 61 and the organic light emitting layer 62 are sequentially formed on the first planarization layer 50.
  • the second metal layer 63 covers the first metal layer 22 and directly contacts and is electrically connected to the first metal layer 22.
  • the anode layer may be formed through the same patterning process.
  • a via hole D is formed in the pixel defining layer 61 and the organic light emitting layer 62 corresponding to the position above the raised structure 40, exposing the second metal layer 63 at the bottom of the via hole D.
  • the thickness of the material that needs to be removed when forming the via is thinner, and there are fewer products during removal.
  • a cathode layer 70 is formed on the organic light-emitting layer 62.
  • the cathode layer 70 can cover the sidewall and bottom of the via hole D, and is in direct contact with and electrically connected to the second metal layer 63. In this way, the cathode layer 70 can establish an electrical connection with the working voltage terminal through the second metal layer 63 and the first metal layer 22 above each convex structure 40, thereby realizing the function of an auxiliary cathode.
  • the foregoing various display substrate embodiments can be applied to an organic light emitting diode display device. Accordingly, the present disclosure also provides an organic light emitting diode display device including any of the foregoing display substrate embodiments.
  • the organic light emitting diode display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种显示基板及其制造方法、有机发光二极管显示装置。显示基板包括：阵列基板(30)，具有显示区域(10)，显示区域(10)包括像素区(11)和围绕像素区(11)的非像素区(12)；凸起结构(40)，沿第一方向位于阵列基板(30)上，且位于非像素区(12)，第一方向为显示基板的出光方向或出光方向的相反方向；第一金属层(22)，沿第一方向位于凸起结构(40)上，并与工作电压端导电连接；第一平坦化层(50)，沿第一方向位于阵列基板(30)上；多个功能层和阴极层(70)，沿第一方向在第一平坦化层(50)上依次设置；其中，阴极层(70)通过过孔(82)与第一金属层(22)电连接。

Description

显示基板及其制造方法、有机发光二极管显示装置
相关申请的交叉引用
本申请是以CN申请号为201910524464.5，申请日为2019年6月18日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
技术领域
本公开涉及一种显示基板及其制造方法、有机发光二极管显示装置。
背景技术
有机电致发光显示器(Organic Electro Luminescent Display，简称OLED)凭借其低功耗、高色饱和度、广视角、薄厚度、可实现柔性化等优异性能，逐渐成为显示领域的主流，并可广泛应用于智能手机、平板电脑、电视等终端产品。在这其中，柔性OLED因其可满足各种特殊结构的需求而逐渐成为OLED中的主流产品。
IR压降(IR-drop)是指出现在电路中电源和地网络中电压下降或升高的现象。随着柔性工艺的发展，显示尺寸的增大、显示分辨率的提高、线宽的缩小等对于IR-Drop具有显著的影响。
发明内容
在本公开的一个方面，提供一种显示基板，包括：
阵列基板，具有显示区域，所述显示区域包括像素区和围绕所述像素区的非像素区；
凸起结构，沿第一方向位于所述阵列基板上，且位于所述非像素区，所述第一方向为所述显示基板的出光方向或所述出光方向的相反方向；
第一金属层，沿所述第一方向位于所述凸起结构上，并与工作电压端导电连接；
第一平坦化层，沿所述第一方向位于所述阵列基板上；
多个功能层和阴极层，沿所述第一方向在所述第一平坦化层上依次设置，
其中，所述阴极层通过过孔与所述第一金属层电连接。
在一些实施例中，所述过孔设置在所述多个功能层和所述第一平坦化层中的至少一层，且所述过孔在所述阵列基板的正投影与所述凸起结构在所述阵列基板的正投影 至少部分重合，
在一些实施例中，所述阴极层在所述过孔内与所述第一金属层直接接触。
在一些实施例中，所述多个功能层包括：
第二金属层，沿所述第一方向位于所述第一金属层上，与所述第一金属层电连接，并通过所述过孔与所述阴极层直接接触。
在一些实施例中，所述多个功能层还包括：
像素定义层，沿所述第一方向位于所述第二金属层上；
有机发光层，沿所述第一方向位于所述像素定义层上；
其中，所述过孔设置在所述像素定义层和所述有机发光层内。
在一些实施例中，所述显示基板还包括：
阳极层，沿所述第一方向位于所述第一平坦化层上，且与所述第二金属层同层设置。
在一些实施例中，所述凸起结构相对于所述阵列基板的最大高度为1200nm～3000nm。
在一些实施例中，所述阵列基板包括：
衬底；和
薄膜晶体管，沿所述第一方向位于所述衬底上，且包括栅极层和第一源漏极层，
其中，第一源漏极层与所述第一金属层同层设置。
在一些实施例中，所述显示基板还包括：
衬底；
薄膜晶体管，沿所述第一方向位于所述衬底上，且包括栅极层和第一源漏极层；和
层间绝缘层，位于所述栅极层和所述第一源漏极层之间；
其中，所述凸起结构沿所述第一方向位于所述层间绝缘层上。
在一些实施例中，所述阵列基板还具有弯折区域，所述弯折区域设有凹槽和位于凹槽内的填充材料，所述填充材料与所述凸起结构的材料相同。
在一些实施例中，所述阵列基板包括：
衬底；
薄膜晶体管，沿所述第一方向位于所述衬底上，且包括栅极层、第二源漏极层和第一源漏极层；
层间绝缘层，位于所述栅极层和所述第二源漏极层之间；和
第二平坦化层，沿所述第一方向位于所述层间绝缘层上，并覆盖所述第二源漏极层；
其中，所述第一源漏极层和所述凸起结构沿所述第一方向位于所述第二平坦化层上，且所述第一源漏极层的源极和漏极分别与所述第二源漏极层的源极和漏极电连接。
在一些实施例中，所述凸起结构与所述第二平坦化层的材料相同。
在一些实施例中，所述显示基板包括多个凸起结构，沿所述第一方向位于所述第二平坦化层上；所述阵列基板具有弯折区域，所述弯折区域设有凹槽和位于凹槽内的填充材料，所述多个凸起结构中的一部分与所述第二平坦化层的材料相同，另一部分与所述填充材料的材料相同。
在本公开的一个方面，提供一种显示基板的制造方法，包括：
提供具有显示区域的阵列基板，所述显示区域包括像素区和围绕所述像素区的非像素区；
在所述阵列基板的非像素区上形成凸起结构；
在所述凸起结构上形成与工作电压端导电连接的第一金属层；
在所述阵列基板上形成第一平坦化层；
在所述第一平坦化层上依次形成多个功能层和阴极层；
其中，在形成所述阴极层之前，还包括：
在所述多个功能层和所述第一平坦化层中的至少一层形成过孔，以使所述阴极层通过所述过孔与所述第一金属层电连接。
在一些实施例中，在形成所述过孔时，使所述过孔在所述阵列基板的正投影与所述凸起结构在所述阵列基板的正投影至少部分重合。
在一些实施例中，形成所述第一平坦化层的操作包括：
在所述阵列基板上形成平坦化材料层，并使所述平坦化材料层覆盖所述第一金属层；
调整所述平坦化材料层的处理区域的第一材料厚度，以形成所述第一平坦化层，并使所述第一材料厚度小于所述平坦化材料层上位于所述处理区域外周的第二材料厚度，所述处理区域为所述平坦化材料层上位于所述凸起结构在所述平坦化材料层的正投影的至少部分。
在一些实施例中，形成所述过孔的操作包括：
在所述多个功能层和所述第一平坦化层形成过孔，以露出所述第一金属层位于所述过孔底部的部分。
在一些实施例中，形成所述第一平坦化层的操作包括：
在所述阵列基板上形成平坦化材料层，并使所述平坦化材料层覆盖所述第一金属层；
去除所述平坦化材料层的处理区域的材料，以露出所述第一金属层，所述处理区域为所述平坦化材料层上位于所述凸起结构在所述平坦化材料层的正投影的至少部分。
在一些实施例中，形成所述多个功能层的操作包括：
在所述第一金属层上形成与所述第一金属层电连接的第二金属层；
在所述第二金属层上形成像素定义层；
在所述像素定义层上形成有机发光层；
其中，形成所述过孔的操作包括：
在所述有机发光层和所述像素定义层形成过孔，并露出所述第二金属层位于所述过孔底部的部分，以便所述阴极层通过所述过孔与所述第二金属层直接接触。
在一些实施例中，形成所述过孔的操作包括：
在所述多个功能层形成所述过孔，并露出所述第一金属层位于所述过孔底部的部分。
在一些实施例中，所述制造方法还包括：
在所述第一平坦化层上形成阳极层，且所述阳极层与所述第二金属层通过同一构图工艺形成。
在一些实施例中，提供所述阵列基板的步骤包括：
提供衬底；
在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层和第一源漏极层，
其中，所述第一源漏极层与所述第一金属层通过同一构图工艺形成。
在一些实施例中，提供所述阵列基板的步骤包括：
提供衬底；
在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层和第一源漏极层；
其中，在形成薄膜晶体管时，在所述栅极层上形成层间绝缘层，所述凸起结构形 成在所述层间绝缘层上。
在一些实施例中，所述阵列基板还具有弯折区域，所述制造方法还包括：
在所述弯折区域形成凹槽；
向所述凹槽填入填充材料；
其中，所述凸起结构与所述填充材料通过同一构图工艺形成。
在一些实施例中，提供所述阵列基板的操作包括：
提供衬底；
在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层、第二源漏极层和第一源漏极层；
其中，在形成薄膜晶体管时，在所述栅极层上形成层间绝缘层，并在所述层间绝缘层上形成所述第二源漏极层，然后在所述层间绝缘层形成第二平坦化层，并使所述第二平坦化层覆盖所述第二源漏极层；
其中，所述凸起结构和所述第一源漏极层形成在所述第二平坦化层上，且所述第一源漏极层的源极和漏极分别与所述第二源漏极层的源极和漏极电连接。
在一些实施例中，所述凸起结构与所述第二平坦化层通过同一构图工艺形成。
在一些实施例中，提供所述阵列基板的操作包括：
提供衬底；
在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层、第二源漏极层和第一源漏极层；
其中，在形成薄膜晶体管时，在所述栅极层上形成层间绝缘层，并在所述层间绝缘层上形成所述第二源漏极层，然后在所述层间绝缘层形成第二平坦化层，并使所述第二平坦化层覆盖所述第二源漏极层；
其中，所述阵列基板还具有弯折区域，所述制造方法还包括：
在所述弯折区域形成凹槽；
向所述凹槽填入填充材料；
其中，形成所述凸起结构的操作包括：
在所述第二平坦化层上形成多个凸起结构，并且，所述多个凸起结构的一部分与所述填充材料通过同一构图工艺形成，所述多个凸起结构中的另一部分与所述第二平坦化层通过同一构图工艺形成。
在本公开的一个方面，提供一种有机发光二极管显示装置，包括前述的显示基板。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是根据本公开显示基板的一个实施例中显示区域及公共电极连接的示意图；
图2-图6分别是根据本公开显示基板的一些实施例的结构示意图；
图7是根据本公开显示基板的制造方法的一个实施例的流程示意图；
图8-图10分别是根据本公开显示基板的制造方法的一些实施例中从形成第一平坦化层的步骤到形成过孔的步骤的流程示意图；
图11是根据本公开显示基板的制造方法的一个实施例中弯折区域工艺的流程示意图；
图12是根据本公开显示基板的制造方法的另一个实施例的流程示意图；
图13(a)-图13(k)是根据本公开显示基板的一个实施例的制造过程的示意图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包括”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特 定器件连接其它器件时，该特定器件可以与所述其它器件直接连接而不具有居间器件，也可以不与所述其它器件直接连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
为了保证位于像素区域的阴极的透过率，相关技术中的阴极普遍不会被形成的很厚。并且阴极通常采用从周边到中心的电流传导路径，这就使得阴极本身的电阻相对更大，随着显示面积增大该电阻会对IR-Drop造成更大的影响。基于不同区域的电压和电流的不同，各个区域的显示亮度有所不同，对应的显示效果存在较明显的差异，影响消费者的观看体验。
在面对较大面积的显示电路时，在一些相关技术采用辅助阴极的方式来克服阴极电阻过大所造成的IR-Drop。为了实现辅助阴极，一些相关技术将显示区域内的阴极层下方的膜层通过激光或其他的方式进行移除，再将阴极层与下方电阻较小且与公共电极端电连接的线路进行连接，从而减少阴极电阻过大造成的IR-Drop。
在相关技术中，需要移除阴极层下方较厚的膜层，以便露出需要与阴极层电连接的线路。以激光移除为例，移除的膜层越厚，移除的膜层材料越多，这使得移除过程的生成物也越多，而过多的生成物容易对封装及蒸镀的发光膜层产生不利影响，进而影响显示基板的良率。另一方面，在移除阴极层下方的膜层时，可能造成移除区域与非移除区域之间的较大段差，在形成阴极层时容易发生断裂，并且也在一定程度上限制了阴极层材料的选择。
有鉴于此，本公开实施例提供一种显示基板及其制造方法、有机发光二极管显示装置，能够改善阴极层在过孔部位的爬坡角度。
图1是根据本公开显示基板的一个实施例中显示区域及公共电极连接的示意图。
参考图1，在一些实施例中，显示基板包括阵列基板30。阵列基板30可具有显示区域10和实现非显示功能的其它区域。阵列基板30的显示区域10可设置多个像素单元，以实现显示功能。显示区域10包括用于设置像素单元的像素区11和围绕像素区11的非像素区12。非像素区12可用于限定像素区11的范围。
在图1的显示基板的出光方向上，在阵列基板30的显示区域10的周边可设置负性电源信号层20，该负性电源信号20与显示基板的阴极层电连接，并可通过接线端21与工作电压端(例如Vss)电连接。
为了降低负性电源信号层20与显示区域10中设置的像素单元的阴极之间的IR-Drop，在一些实施例中可采用辅助阴极的方式来降低负性电源信号层到阴极层的电阻，例如在阵列基板30的显示区域10设置与工作电压端导电的金属层，并在非像素区12内布置多个过孔80来实现阴极层与过孔下方的金属层之间的电连接。通过这种方式，可以减少像素单元的阴极与工作电压端之间的电阻，从而有效地降低IR-Drop。过孔80的数量及设置位置可以根据像素比例进行设计，例如将过孔80与显示区域10中的像素的数量关系设置成1:4到1:400。相邻的过孔80可间隔4～400个像素进行设置。多个过孔80可根据显示区域10的形状按照规则或非规则的分布进行排布。
图2-图6分别是根据本公开显示基板的一些实施例的结构示意图。
参考图2-图4，在一些实施例中，显示基板包括：阵列基板30、凸起结构40、第一金属层22、第一平坦化层50、多个功能层和阴极层70。凸起结构40沿第一方向(即图2-图4中从下到上的竖直方向)位于阵列基板30上，且位于所述非像素区。该第一方向可以为显示基板的出光方向或者显示基板的出光方向的相反方向。例如对于顶发射方式(即从阴极侧出射光)的显示基板来说，第一方向为显示基板的出光方向。而对于底发射方式(即从阳极侧出射光)的显示基板来说，第一方向为显示基板的出光方向的相反方向。
凸起结构40相对于阵列基板30向上凸出。凸起结构40的形状可以为圆形、椭圆形或多边形。凸起结构40的材料可以包括硅的氧化物、硅的氮化物、聚酰亚胺中的至少一种。参考图1，凸起结构40的数量可根据分布在显示区域中的过孔80的数量进行确定，例如凸起结构40的数量等于或小于过孔80的数量。凸起结构40在阵列基板30上可沿着与第一方向垂直的至少一个第二方向进行排布。
凸起结构40相对于所述阵列基板的最大高度h1可根据阵列基板30上的第一平坦化层的厚度、多个功能层的厚度以及阴极层的爬坡能力中一个或多个因素进行确定，例如可设置h1为1200nm～3000nm。
第一金属层22沿第一方向位于所述凸起结构40上，并可作为辅助阴极与工作电压端导电连接。参考图2-图4，第一金属层22也可以位于凸起结构40的周边，与凸 起结构40上的第一金属层22一体形成。
第一平坦化层50可沿第一方向位于所述阵列基板30上，用于为多个功能层的形成提供平坦表面。在不同实施例中，多个功能层的组成可以有所不同。例如，在图2中，多个功能层包括像素定义层61和有机发光层62。在图3和图4中，多个功能层包括第二金属层63、像素定义层61和有机发光层62。有机发光层62可以包括例如电子注入层、电子阻挡层、电子传输层、发光层、空穴注入层、空穴阻挡层或空穴传输层等发光功能层。多个功能层还可以包括实现其他功能的功能层，例如触控传感器层等。多个功能层和阴极层70可沿第一方向在第一平坦化层50上依次设置。
为了使阴极层70与其下方的第一金属层22电连接，参考图2-图4，在一些实施例中，在所述多个功能层和所述第一平坦化层50中的至少一层设有过孔81、82或83。所述阴极层70通过所述过孔81、82或83与所述第一金属层22电连接，以便通过辅助阴极的方式来降低工作电压端到阴极层的电阻。
过孔81、82或83在所述阵列基板30的正投影与所述凸起结构40在所述阵列基板30的正投影至少部分重合，即过孔81、82或83在所述阵列基板30的正投影可以与凸起结构40在所述阵列基板30的正投影完全重合，或者只有一部分重合。这里过孔81、82及83在阵列基板30的正投影是指过孔81、82及83的孔壁在阵列基板30的正投影及其围绕的区域。凸起结构40在阵列基板30的正投影是指凸起结构40的整个实体在阵列基板30的正投影。
通过这种结构，可使得过孔部位的底部的至少部分形成在凸起结构40的上方，相应可使得该底部相对于多个功能层的最上层(例如图2中的有机发光层62)的高度差相对较小。在形成阴极层70时，过孔部位和过孔周围区域的高度差h2也相对较小，这样就改善了阴极层在过孔部位的爬坡角度，从而使阴极层在形成时不容易在过孔部位发生断裂。
在图2中，过孔81从上至下贯穿了有机发光层62、像素定义层61和第一平坦化层50，从而使得阴极层70能够在过孔81内与第一金属层22直接接触。由于位于凸起结构40上方的第一金属层22相比于阵列基板30处于较高的位置，因此在形成第一平坦化层50时，可使得第一平坦化层50在凸起结构40上方的材料更薄，或者移除凸起结构40上方的平坦化层材料而露出第一金属层22。
在形成第一平坦化层50时，如果在凸起结构40上方保留较小厚度的平坦化层材料，则在继续形成多个功能层之后，且形成阴极层70之前，可通过激光等方式移除 多个功能层和位于凸起结构40上方的平坦化层材料，以便在形成的过孔81的底部露出凸起结构40上方的第一金属层22。
在形成第一平坦化层50时，如果凸起结构40上方的平坦化层材料已被移除，则可在继续形成多个功能层之后，且形成阴极层70之前，可通过激光等方式移除多个功能层来形成过孔81，使得过孔81的底部露出凸起结构40上方的第一金属层22。
相比于相关技术中需要在形成有机发光层之后，移除阴极层下方较厚的平坦化层材料，本公开的一些实施例在形成第一平坦化层50时减薄或移除凸起结构上方的材料，在形成有机发光层后，可以减少形成过孔时需要移除的平坦化层材料的厚度，或者无需移除凸起结构上方的平坦化层材料，因此可以减少移除过程的生成物，降低生成物对有机发光层的不利影响，从而提高显示基板的良率。
在图3和图4中，第二金属层63沿所述第一方向位于所述第一金属层22上，并与所述第一金属层22电连接。参考图3，第二金属层63也可以位于第一金属层22周边的第一平坦化层50上，并与第一金属层22上的第二金属层63一体形成。在一些实施例中，显示基板还包括沿所述第一方向位于所述第一平坦化层50上的阳极层，可用于形成OLED发光面板的阳极。第二金属层63可以与阳极层同层设置。
这里的同层可以为采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
这样，第二金属层和阳极层在形成时可通过同一构图工艺形成，以简化加工工序。第二金属层和阳极层可采用相同材料，例如包括导电氧化物(例如氧化铟锡和氧化铟锌等)或反射金属(银、铝等)等导电材料。这里的同一构图工艺是指采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成层结构。
在图3和图4中，像素定义层61沿所述第一方向位于所述第二金属层63上。有机发光层62沿所述第一方向位于所述像素定义层61上。阴极层70沿第一方向位于有机发光层上。阴极层的材料可以包括Li、Ag、Ca、Al、Mg中的至少一种。
在图3中，过孔82设置在所述像素定义层61和所述有机发光层62内，所述阴极层70通过所述过孔82与所述第二金属层63直接接触。在形成过孔时保留第二金 属层63，一方面可以减少形成过孔时需要移除的阴极层60下方材料厚度，减少移除过程的生成物；另一方面在移除材料时可避免第一金属层被错误移除，从而提高电连接的可靠性。
在图4中，过孔83设置在第二金属层63、像素定义层61和有机发光层62内，阴极层70通过过孔83与第一金属层22直接接触，这样能够进一步降低阴极层70与第一金属层22之间的电阻，从而使像素单元的阴极与工作电压端之间的电阻得以减小，从而有效地降低IR-Drop。
参考图5，在一些实施例中，阵列基板包括衬底31和位于衬底31上的薄膜晶体管(Thin Film Transistor，TFT)。薄膜晶体管包括栅极层和第一源漏极层。第一源漏极层可用于构成薄膜晶体管器件的源极(Source Pole)和漏极(Drain Pole)。薄膜晶体管还可以包括有源层91，第一源漏极层中的源极94和漏极95与有源层91连接。第一金属层22可以与第一源漏极层同层设置。这样，第一金属层22和第一源漏极层在形成时可通过同一构图工艺形成，以简化加工工序。
在图5中，阵列基板还包括缓冲层32、栅极绝缘层、层间绝缘层35等。沿竖直从下到上的第一方向，阵列基板的缓冲层32设置在衬底31上，有源层91设置在缓冲层32上，第一栅极绝缘层33覆盖在有源层91上，第一栅极层92设置在第一栅极绝缘层33上，第二栅极绝缘层34覆盖在第一栅极层92上，第二栅极层93设置在第二栅极绝缘层34上，层间绝缘层34覆盖在第二栅极层93上。在另一些实施例中，薄膜晶体管可以包括一个栅极层和对应的栅极绝缘层。
图5中的凸起结构40可沿第一方向位于层间绝缘层35的表面。第一源漏极层可同样设置在层间绝缘层35的表面，并且第一源漏极层中的源极94和漏极95贯穿层间绝缘层35、第二栅极绝缘层34和第一栅极绝缘层33与有源层91连接。第一源漏极层中的源极94和漏极95可以与第一金属层22同层设置。另外，第一源漏极层中的源极94和漏极95可以与第一金属层22采用相同材料形成，例如钼、铜、铝、金、银或钛等导电材料中的至少一种，并可以通过同一构图工艺形成，以节省加工工序。
参考图5，在一些实施例中，阵列基板除了具有显示区域10，还可以具有弯折区域100，用于实现显示基板的可弯折性。在形成上述阵列基板后，可在弯折区域100形成(例如通过曝光-蚀刻工艺)贯穿层间绝缘层35、第二栅极绝缘层34、第一栅极绝缘层33和缓冲层32的凹槽，凹槽的底部露出柔性材质的衬底31。凹槽内可填入填充材料110，该填充材料110可以与凸起结构40通过同一构图工艺形成。例如在基板 弯折(Pad-Bending)工艺中，采用半色调(Halftone)工艺来得到Pad-Bending图形的同时，形成凸起结构40。填充材料110和凸起结构40均可采用聚酰亚胺，且相对于阵列基板来说，填充材料110的最大高度为500～1200nm，而凸起结构40的最大高度为1200～3000nm，大于填充材料相对于阵列基板的最大高度。
参考图6，在一些实施例中，阵列基板包括衬底31、薄膜晶体管、层间绝缘层35和第二平坦化层36。薄膜晶体管包括栅极层、第二源漏极层和第一源漏极层。所述第二源漏极层的源极和漏极分别与所述第一源漏极层的源极和漏极电连接。所述第一源漏极层的源极和漏极均与所述有源层91电连接。
在图6中，阵列基板还包括缓冲层32、栅极绝缘层等。沿竖直从下到上的第一方向，阵列基板的缓冲层32设置在衬底31上，有源层91设置在缓冲层32上，第一栅极绝缘层33覆盖在有源层91上，第一栅极层92设置在第一栅极绝缘层33上，第二栅极绝缘层34覆盖在第一栅极层92上，第二栅极层93设置在第二栅极绝缘层34上，层间绝缘层34覆盖在第二栅极层93上。缓冲层32、第一栅极绝缘层33、第二栅极绝缘层34、层间绝缘层35和第二平坦化层36可以采用相同材料，也可以采用不同材料。该材料可以包括硅的氧化物、硅的氮化物、聚酰亚胺中的至少一种。在另一些实施例中，薄膜晶体管可以包括一个栅极层和对应的栅极绝缘层。
参考图6，在一些实施例中，第二源漏极层可沿第一方向设置在层间绝缘层35上，即层间绝缘层35位于所述栅极层和所述第二源漏极层之间。第二源漏极层中的源级94’和漏极95’贯穿层间绝缘层35、第二栅极绝缘层34和第一栅极绝缘层33与有源层91连接。第二平坦化层36沿所述第一方向位于所述层间绝缘层35上，并覆盖所述第二源漏极层，而凸起结构40’可设置在第二平坦化层36上。凸起结构40’可以与第二平坦化层36的材料相同。相应的，为了简化工序，可以在形成第二平坦化层36时通过同一构图工艺形成凸起结构40’。
在图6中，第一源漏极层可设置在第二平坦化层36上，第一源漏极层的源级94和漏极95贯穿第二平坦化层36分别与第二源漏极层的源极94’和漏极95’连接。第一源漏极层中的源极94和漏极95可以与第一金属层22通过同一构图工艺形成，以节省加工工序。
参考图5和图6，在一些实施例中，凸起结构的材料可以与显示基板中的多个部分的材料相同。例如显示基板包括多个凸起结构，位于所述第二平坦化层上。阵列基板具有弯折区域，所述弯折区域设有凹槽和位于凹槽内的填充材料，所述多个凸起结 构中的一部分与所述第二平坦化层的材料相同，另一部分与所述填充材料的材料相同。
由于凸起结构可与显示基板中的多个部分的材料相同，因此凸起结构可通过显示基板的相应部分的制备工艺一并形成，从而减少显示基板的制备工序，提高制造效率。举例来说，对于在非像素区形成的多个凸起结构，多个凸起结构的一部分可与填入到弯折区域的凹槽内的填充材料通过同一构图工艺形成，多个凸起结构中的另一部分与第二平坦化层通过同一构图工艺形成。
图7是根据本公开显示基板的制造方法的一个实施例的流程示意图。
参考图7，在一些实施例中，显示基板的制造方法包括步骤S100～S700。在步骤S100中，提供具有显示区域的阵列基板，所述显示区域包括像素区和围绕所述像素区的非像素区。在步骤S200中，在所述阵列基板的非像素区上形成凸起结构。凸起结构相对于所述阵列基板的最大高度可以为1200nm～3000nm。在步骤S300中，在所述凸起结构上形成与工作电压端导电连接的第一金属层。在步骤S400中，在所述阵列基板上形成第一平坦化层。在步骤S500中，在所述第一平坦化层上形成多个功能层。在步骤S600中，在所述多个功能层和所述第一平坦化层中的至少一层形成过孔。在形成所述过孔时，可使所述过孔在所述阵列基板的正投影与所述凸起结构在所述阵列基板的正投影至少部分重合。在步骤S700中，在所述多个功能层上形成阴极层，且所述阴极层通过所述过孔与所述第一金属层电连接。
图8-图10分别是根据本公开显示基板的制造方法的一些实施例中从形成第一平坦化层的步骤到形成过孔的步骤的具体流程示意图。
参考图8，在一些实施例中，步骤S400可包括步骤S410和步骤S420。在步骤S410中，在所述阵列基板上形成平坦化材料层，并使所述平坦化材料层覆盖所述第一金属层。在步骤S420，调整所述平坦化材料层的处理区域的第一材料厚度，以形成所述第一平坦化层，并使所述第一材料厚度小于所述平坦化材料层上位于所述处理区域外周的第二材料厚度。所述处理区域为所述平坦化材料层上位于所述凸起结构在所述平坦化材料层的正投影的至少部分。
在步骤S500形成多个功能层之后，步骤S600具体包括步骤S610，即在所述多个功能层和所述第一平坦化层形成过孔，以露出所述第一金属层位于过孔底部的部分。由于步骤S420中已将处理区域的材料厚度调整到较小的厚度，相比于相关技术中形成过孔时需要移除较厚的平坦化层，步骤S610形成过孔时需要移除的材料厚度较少， 产生的生成物也较少。
参考图9，在一些实施例中，步骤S400可包括步骤S410和步骤S430。在步骤S410中，在所述阵列基板上形成平坦化材料层，并使所述平坦化材料层覆盖在所述第一金属层上。在步骤S430，去除所述平坦化材料层的处理区域的材料，以露出所述第一金属层。所述处理区域为所述平坦化材料层上位于所述凸起结构在所述平坦化材料层的正投影的至少部分。
在步骤S500形成多个功能层之后，步骤S600具体包括步骤S620，即在所述多个功能层形成过孔，以露出所述第一金属层位于过孔底部的部分。由于步骤S430中已去除处理区域的材料，相比于相关技术中形成过孔时需要移除较厚的平坦化层，步骤S620形成过孔时无需移除第一平坦化层，因此需要移除的材料厚度更少，产生的生成物也更少。
参考图10，在一些实施例中，步骤S400可包括步骤S410和步骤S430。在步骤S410中，在所述阵列基板上形成平坦化材料层，并使平坦化材料层覆盖所述第一金属层。在步骤S430，去除所述平坦化材料层的处理区域的材料，以露出所述第一金属层。所述处理区域为所述平坦化材料层上位于所述凸起结构在所述平坦化材料层的正投影的至少部分。
在图10中，步骤S500可具体包括步骤S510到步骤S530。在步骤S510中，在所述第一金属层上形成与所述第一金属层电连接的第二金属层。在步骤S520中，在所述第二金属层上形成像素定义层。在步骤S530中，在所述像素定义层上形成有机发光层。
在形成多个功能层之后，步骤S600具体包括步骤S630，即在所述有机发光层和所述像素定义层形成过孔，并露出所述第二金属层位于所述过孔底部的部分，以便所述阴极层通过所述过孔与所述第二金属层直接接触。
由于步骤S430中已去除处理区域的材料，相比于相关技术中形成过孔时需要移除较厚的平坦化层的材料，步骤S630形成过孔时只需要移除有机发光层和像素定义层，而无需移除第二金属层和第一平坦化层，因此需要移除的材料厚度更少，产生的生成物也更少。另一方面，在移除材料时可避免第一金属层被错误移除，从而提高电连接的可靠性。
在一些实施例中，提供阵列基板的步骤可以包括：提供衬底，并在在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层和第一源漏极层。薄膜晶体管还可以包 括有源层，所述第一源漏极层的源极和漏极可与所述有源层电连接。第一源漏极层可以与图8-图10的实施例中的所述第一金属层通过同一构图工艺形成，以节省加工工序。另外，在形成薄膜晶体管时，可以在所述栅极层上形成层间绝缘层。所述凸起结构可形成在所述层间绝缘层上。
在一些实施例中，还可以在所述第一平坦化层上形成阳极层。阳极层可与图9和图10的实施例中的所述第二金属层通过同一构图工艺形成，以节省加工工序。
图11是根据本公开显示基板的制造方法的一个实施例中弯折区域工艺的流程示意图。
参考图11，在一些实施例中，所述阵列基板还具有弯折区域。所述制造方法还可以包括步骤S100’和步骤S700。在步骤S100’中，提供具有显示区域和弯折区域的阵列基板，显示区域包括像素区和围绕像素区的非像素区。步骤S100’可以包括在步骤S100中。在步骤S700中，在所述弯折区域形成凹槽。步骤S200可包括步骤S210，即向凹槽填入填充材料，并通过同一构图工艺在阵列基板的非像素区上形成凸起结构。这样可在填充弯折区域时同时形成凸起结构，从而节省工序。
图12是根据本公开显示基板的制造方法的另一个实施例的流程示意图。
参考图12，在一些实施例中，提供所述阵列基板的操作可包括：提供衬底，并在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层、第二源漏极层和第一源漏极层。薄膜晶体管还可以包括有源层，所述第二源漏极层的源极和漏极可与所述有源层电连接。在形成薄膜晶体管时，可在所述栅极层上形成层间绝缘层，并在所述层间绝缘层上形成所述第二源漏极层，然后在所述层间绝缘层形成第二平坦化层，并使所述第二平坦化层覆盖所述第二源漏极层。所述凸起结构和所述第一源漏极层形成在所述第二平坦化层上，且所述第一源漏极层的源极和漏极分别与所述第二源漏极层的源极和漏极电连接。为了节省工序，所述凸起结构可以与所述第二平坦化层通过同一构图工艺形成。在另一些实施例中，凸起结构的形成也可以在第二平坦化层形成之后。
举例来说，在图12中，提供阵列基板的步骤包括步骤S110至步骤S190。在步骤S110中，提供衬底，并在衬底上形成缓冲层。在步骤S120中，在缓冲层上形成有源层。在步骤S130中，在有源层上覆盖第一栅极绝缘层。在步骤S140中，在第一栅极绝缘层上形成第一栅极层。在步骤S150中，在第一栅极层上覆盖第二栅极绝缘层。在步骤S160中，在第二栅极绝缘层上形成第二栅极层。在步骤S170中，在第二栅极层上覆盖层间绝缘层。在步骤S180中，在层间绝缘层上形成第二源漏极层，并使第 二源漏极层中的源级和漏极贯穿层间绝缘层、第二栅极绝缘层和第一栅极绝缘层与有源层连接。在步骤S190中，在所述层间绝缘层形成第二平坦化层，并使所述第二平坦化层覆盖所述第二源漏极层。
步骤S200可以独立于步骤S190，也可以与步骤S190合并，即在形成第二平坦化层时，通过同一构图工艺形成位于阵列基板的非像素区的凸起结构，以节省工序。在另一些实施例中，在所述非像素区形成多个凸起结构时，所述多个凸起结构的一部分与所述填充材料通过同一构图工艺形成，所述多个凸起结构中的另一部分与所述第二平坦化层通过同一构图工艺形成。
图13(a)-图13(k)是根据本公开显示基板的一个实施例的制造过程的示意图。
下面结合图13(a)至图13(k)对本公开的一个显示基板实施例的制造过程进行说明。在图13(a)中，提供衬底31。在图13(b)中，在衬底31上形成缓冲层32，并在缓冲层32上形成有源层91。在图13(c)中，在有源层91上覆盖第一栅极绝缘层33，第一栅极绝缘层33也覆盖在缓冲层32上。接下来在第一栅极绝缘层33上形成第一栅极层92，并在第一栅极层92上覆盖第二栅极绝缘层，第二栅极绝缘层34也覆盖在第一栅极绝缘层33上。然后，在第二栅极绝缘层34上形成第二栅极层93，并在第二栅极层93上覆盖层间绝缘层35，层间绝缘层35也覆盖在第二栅极绝缘层34上。
对于需要实现弯折功能的显示基板来说，其阵列基板可具有显示区域和弯折区域。在图13(d)中，可在显示区域形成贯穿层间绝缘层35、第二栅极绝缘层34和第一栅极绝缘层33的过孔A和B，并在弯折区域形成贯穿层间绝缘层35、第二栅极绝缘层34、第一栅极绝缘层33和缓冲层32的凹槽C。过孔A、B与凹槽C可在同一工序中形成，也可在不同工序中形成。
在图13(e)中，通过半色调工艺既向凹槽C填入填充材料110作为基板弯折图形，又在层间绝缘层35的非像素区上形成凸起结构40。填充材料110和凸起结构40均可采用聚酰亚胺，且相对于层间绝缘层35来说，填充材料110的最大高度为500～1200nm，而凸起结构40的最大高度为1200～3000nm。
在图13(f)中，在层间绝缘层35上形成第一金属层22和第一源漏极层，并且使得第一金属层22覆盖在凸起结构40上。在形成显示基板时，可使第一金属层22与工作电压端导电连接。这样第一源漏极层中的源极94和漏极95分别通过过孔A和B与有源层91电连接，从而形成了阵列基板中的薄膜晶体管。第一金属层22和第一源漏极层可通过同一构图工艺形成。第一金属层22可以覆盖或不覆盖到弯折区域。
在图13(g)中，在层间绝缘层35上形成平坦化材料层50’，并使得平坦化材料层50’覆盖第一金属层22、第一源漏极层的源极94和漏极95。平坦化材料层50’可以覆盖或不覆盖到弯折区域。不同位置的平坦化材料层50’相对于层间绝缘层35的高度有所不同，其中位于凸起结构40上侧的区域51相比于其他区域更高。
在图13(h)中，对平坦化材料层50’进行处理，以形成更平坦的第一平坦化层50。在此过程中，可去除平坦化材料层50’的处理区域51的材料，以露出所述第一金属层22。
在图13(i)中，在第一平坦化层50上依次形成第二金属层63、像素定义层61和有机发光层62。第二金属层63覆盖在第一金属层22上，并与第一金属层22直接接触并电连接。在形成第二金属层63时，可以通过同一构图工艺形成阳极层。
在图13(j)中，在像素定义层61和有机发光层62对应于凸起结构40上方的部位形成过孔D，露出过孔D底部的第二金属层63。此时，形成过孔时需要移除的材料厚度较薄，移除时的生成物较少。
在图13(k)中，在有机发光层62上形成阴极层70，阴极层70能够覆盖过孔D的侧壁和底部，并与第二金属层63直接接触并电连接。这样阴极层70就能够通过各个凸起结构40上方的第二金属层63和第一金属层22与工作电压端建立起电连接，从而实现辅助阴极的作用。
前述的各个显示基板的实施例可应用在用于有机发光二极管显示装置，相应的，本公开还提供了包括前述任一种显示基板实施例的有机发光二极管显示装置。该有机发光二极管显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种显示基板，包括：
    阵列基板，具有显示区域，所述显示区域包括像素区和围绕所述像素区的非像素区；
    凸起结构，沿第一方向位于所述阵列基板上，且位于所述非像素区，所述第一方向为所述显示基板的出光方向或所述出光方向的相反方向；
    第一金属层，沿所述第一方向位于所述凸起结构上，并与工作电压端导电连接；
    第一平坦化层，沿所述第一方向位于所述阵列基板上；
    多个功能层和阴极层，沿所述第一方向在所述第一平坦化层上依次设置，
    其中，所述阴极层通过过孔与所述第一金属层电连接。
  2. 根据权利要求1所述的显示基板，其中，所述过孔设置在所述多个功能层和所述第一平坦化层中的至少一层，且所述过孔在所述阵列基板的正投影与所述凸起结构在所述阵列基板的正投影至少部分重合；
    可选地，所述阴极层在所述过孔内与所述第一金属层直接接触；
    可选地，所述凸起结构相对于所述阵列基板的最大高度为1200nm～3000nm。
  3. 根据权利要求1所述的显示基板，其中，所述多个功能层包括：
    第二金属层，沿所述第一方向位于所述第一金属层上，与所述第一金属层电连接，并通过所述过孔与所述阴极层直接接触；
    可选地，所述显示基板还包括：
    阳极层，沿所述第一方向位于所述第一平坦化层上，且与所述第二金属层同层设置。
  4. 根据权利要求3所述的显示基板，其中，所述多个功能层还包括：
    像素定义层，沿所述第一方向位于所述第二金属层上；
    有机发光层，沿所述第一方向位于所述像素定义层上；
    其中，所述过孔设置在所述像素定义层和所述有机发光层内。
  5. 根据权利要求1～4任一所述的显示基板，其中，所述阵列基板包括：
    衬底；和
    薄膜晶体管，沿所述第一方向位于所述衬底上，且包括栅极层和第一源漏极层，
    其中，第一源漏极层与所述第一金属层同层设置。
  6. 根据权利要求1～4任一所述的显示基板，还包括：
    衬底；
    薄膜晶体管，沿所述第一方向位于所述衬底上，且包括栅极层和第一源漏极层；和
    层间绝缘层，位于所述栅极层和所述第一源漏极层之间；
    其中，所述凸起结构沿所述第一方向位于所述层间绝缘层上。
  7. 根据权利要求1～4任一所述的显示基板，其中，所述阵列基板还具有弯折区域，所述弯折区域设有凹槽和位于凹槽内的填充材料，所述填充材料与所述凸起结构的材料相同。
  8. 根据权利要求1～4任一所述的显示基板，其中，所述阵列基板包括：
    衬底；
    薄膜晶体管，沿所述第一方向位于所述衬底上，且包括栅极层、第二源漏极层和第一源漏极层；
    层间绝缘层，位于所述栅极层和所述第二源漏极层之间；和
    第二平坦化层，沿所述第一方向位于所述层间绝缘层上，并覆盖所述第二源漏极层；
    其中，所述第一源漏极层和所述凸起结构沿所述第一方向位于所述第二平坦化层上，且所述第一源漏极层的源极和漏极分别与所述第二源漏极层的源极和漏极电连接。
  9. 根据权利要求8所述的显示基板，其中，所述凸起结构与所述第二平坦化层的材料相同，或者
    所述显示基板包括多个凸起结构，沿所述第一方向位于所述第二平坦化层上；所述阵列基板具有弯折区域，所述弯折区域设有凹槽和位于凹槽内的填充材料，所述多个凸起结构中的一部分与所述第二平坦化层的材料相同，另一部分与所述填充材料的材料相同。
  10. 一种有机发光二极管显示装置，包括权利要求1～9任一所述的显示基板。
  11. 一种显示基板的制造方法，包括：
    提供具有显示区域的阵列基板，所述显示区域包括像素区和围绕所述像素区的非像素区；
    在所述阵列基板的非像素区上形成凸起结构；
    在所述凸起结构上形成与工作电压端导电连接的第一金属层；
    在所述阵列基板上形成第一平坦化层；
    在所述第一平坦化层上依次形成多个功能层和阴极层；
    其中，在形成所述阴极层之前，还包括：
    在所述多个功能层和所述第一平坦化层中的至少一层形成过孔，以使所述阴极层通过所述过孔与所述第一金属层电连接。
  12. 根据权利要求11所述的制造方法，其中，在形成所述过孔时，使所述过孔在所述阵列基板的正投影与所述凸起结构在所述阵列基板的正投影至少部分重合。
  13. 根据权利要求11所述的制造方法，其中，形成所述第一平坦化层的操作包括：
    在所述阵列基板上形成平坦化材料层，并使所述平坦化材料层覆盖所述第一金属层；
    调整所述平坦化材料层的处理区域的第一材料厚度，以形成所述第一平坦化层，并使所述第一材料厚度小于所述平坦化材料层上位于所述处理区域外周的第二材料厚度，所述处理区域为所述平坦化材料层上位于所述凸起结构在所述平坦化材料层的正投影的至少部分；
    可选地，形成所述过孔的操作包括：
    在所述多个功能层和所述第一平坦化层形成过孔，以露出所述第一金属层位于所述过孔底部的部分。
  14. 根据权利要求11所述的制造方法，其中，形成所述第一平坦化层的操作包括：
    在所述阵列基板上形成平坦化材料层，并使所述平坦化材料层覆盖所述第一金属层；
    去除所述平坦化材料层的处理区域的材料，以露出所述第一金属层，所述处理区域为所述平坦化材料层上位于所述凸起结构在所述平坦化材料层的正投影的至少部分；
    可选地，形成所述过孔的操作包括：
    在所述多个功能层形成所述过孔，并露出所述第一金属层位于所述过孔底部的部分。
  15. 根据权利要求14所述的制造方法，其中，形成所述多个功能层的操作包括：
    在所述第一金属层上形成与所述第一金属层电连接的第二金属层；
    在所述第二金属层上形成像素定义层；
    在所述像素定义层上形成有机发光层；
    其中，形成所述过孔的操作包括：
    在所述有机发光层和所述像素定义层形成过孔，并露出所述第二金属层位于所述过孔底部的部分，以便所述阴极层通过所述过孔与所述第二金属层直接接触；
    可选地，所述制造方法还包括：
    在所述第一平坦化层上形成阳极层，且所述阳极层与所述第二金属层通过同一构图工艺形成。
  16. 根据权利要求11～15任一所述的制造方法，其中，提供所述阵列基板的步骤包括：
    提供衬底；
    在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层和第一源漏极层，
    其中，所述第一源漏极层与所述第一金属层通过同一构图工艺形成。
  17. 根据权利要求11～15任一所述的制造方法，其中，提供所述阵列基板的步骤包括：
    提供衬底；
    在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层和第一源漏极层；
    其中，在形成薄膜晶体管时，在所述栅极层上形成层间绝缘层，所述凸起结构形成在所述层间绝缘层上。
  18. 根据权利要求11～15任一所述的制造方法，其中，所述阵列基板还具有弯折区域，所述制造方法还包括：
    在所述弯折区域形成凹槽；
    向所述凹槽填入填充材料；
    其中，所述凸起结构与所述填充材料通过同一构图工艺形成。
  19. 根据权利要求11～15任一所述的制造方法，其中，提供所述阵列基板的操作包括：
    提供衬底；
    在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层、第二源漏极层和第一源漏极层；
    其中，在形成薄膜晶体管时，在所述栅极层上形成层间绝缘层，并在所述层间绝缘层上形成所述第二源漏极层，然后在所述层间绝缘层形成第二平坦化层，并使所述第二平坦化层覆盖所述第二源漏极层；
    其中，所述凸起结构和所述第一源漏极层形成在所述第二平坦化层上，且所述第一源漏极层的源极和漏极分别与所述第二源漏极层的源极和漏极电连接，可选地，所述凸起结构与所述第二平坦化层通过同一构图工艺形成。
  20. 根据权利要求11～15任一所述的制造方法，其中，提供所述阵列基板的操作包括：
    提供衬底；
    在所述衬底上形成薄膜晶体管，所述薄膜晶体管包括栅极层、第二源漏极层和第一源漏极层；
    其中，在形成薄膜晶体管时，在所述栅极层上形成层间绝缘层，并在所述层间绝缘层上形成所述第二源漏极层，然后在所述层间绝缘层形成第二平坦化层，并使所述第二平坦化层覆盖所述第二源漏极层；
    其中，所述阵列基板还具有弯折区域，所述制造方法还包括：
    在所述弯折区域形成凹槽；
    向所述凹槽填入填充材料；
    其中，形成所述凸起结构的操作包括：
    在所述第二平坦化层上形成多个凸起结构，并且，所述多个凸起结构的一部分与所述填充材料通过同一构图工艺形成，所述多个凸起结构中的另一部分与所述第二平坦化层通过同一构图工艺形成。
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CN109599502A (zh) * 2019-01-02 2019-04-09 京东方科技集团股份有限公司 显示基板及其制备方法和显示面板
CN110112205A (zh) * 2019-06-18 2019-08-09 京东方科技集团股份有限公司 显示基板及其制造方法、有机发光二极管显示装置

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