WO2021098610A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021098610A1
WO2021098610A1 PCT/CN2020/128809 CN2020128809W WO2021098610A1 WO 2021098610 A1 WO2021098610 A1 WO 2021098610A1 CN 2020128809 W CN2020128809 W CN 2020128809W WO 2021098610 A1 WO2021098610 A1 WO 2021098610A1
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Prior art keywords
electrode
storage electrode
transistor
gate
storage
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PCT/CN2020/128809
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English (en)
French (fr)
Inventor
袁粲
李永谦
袁志东
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/433,435 priority Critical patent/US11882729B2/en
Publication of WO2021098610A1 publication Critical patent/WO2021098610A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device.
  • Self-luminous display substrates such as Organic Light-Emitting Diode (OLED) display substrates have the advantages of self-luminescence, lightness and thinness, low power consumption, good color reproduction, responsiveness, and wide viewing angle, and have been more and more widely used. It has become one of the mainstreams in the current market in display devices such as mobile phones, notebook computers, and televisions.
  • OLED Organic Light-Emitting Diode
  • inventions of the present disclosure provide a display substrate.
  • the display substrate includes a substrate, a pixel driving circuit and a bottom emission type light emitting device arranged in a display area on the substrate and located in each sub-pixel.
  • the light emitting device includes a first electrode electrically connected to a pixel driving circuit.
  • the pixel driving circuit includes a first storage capacitor and a second storage capacitor connected in parallel.
  • the first storage capacitor includes: a first storage electrode and a second storage electrode arranged oppositely.
  • the first electrode is multiplexed as the first storage electrode.
  • the second storage capacitor includes: the second storage electrode, and a third storage electrode disposed opposite to the second storage electrode.
  • the second storage electrode is located between the first storage electrode and the third storage electrode.
  • the first storage electrode is electrically connected to the third storage electrode.
  • the first electrode, the second storage electrode, and the third storage electrode are all transparent electrodes.
  • the display substrate further includes: a power cord.
  • the pixel driving circuit further includes a first transistor, and the first transistor is a driving transistor.
  • the first transistor includes a first gate, a first semiconductor active pattern, and a first source.
  • the first semiconductor active pattern includes a first channel region, a first source region, and a first drain region, and the conductivity of the first source region and the first drain region is greater than that of the first drain region. The conductivity of the channel region.
  • the first source is in direct contact with the first source region.
  • the first source is electrically connected to the power line.
  • the third storage electrode is a conductive semiconductor pattern, and the third storage electrode is connected to the first drain region and has an integral structure.
  • the display substrate further includes: a gate line and a data line electrically connected to the pixel driving circuit; and a first connection electrode provided in each of the sub-pixels.
  • the pixel driving circuit further includes a second transistor including a second gate, a second semiconductor active pattern, a second source, and a second drain. A part of the gate line is multiplexed as the second gate.
  • the second source electrode is electrically connected to the data line.
  • the second drain and the first connecting electrode are an integral structure.
  • the first connection electrode is electrically connected to the first gate and the second storage electrode.
  • the first connection electrode is in direct contact with the second storage electrode, and the first connection electrode is electrically connected to the first gate through a via hole.
  • the display substrate further includes a sensing signal line electrically connected to the pixel driving circuit.
  • the pixel driving circuit further includes a third transistor; the first transistor and the third transistor are respectively located on both sides of the first storage capacitor.
  • the third transistor includes a third gate, a third semiconductor active pattern, and a third drain.
  • the third semiconductor active pattern includes a third channel region, a third source region, and a third drain region, and the conductivity of the third source region and the third drain region is greater than that of the third drain region.
  • the third source region is connected to the third storage electrode and has an integral structure.
  • the third drain is in direct contact with the third drain region, and the third drain is electrically connected to the sensing signal line.
  • the third gate of the third transistor located in any row of sub-pixels is multiplexed by a portion of the gate line corresponding to the adjacent row of sub-pixels closest to the third transistor constitute.
  • the power line, the sensing signal line, and the data line are parallel and arranged in the same layer.
  • every two adjacent sub-pixels constitute a group, and two data lines are arranged between the two sub-pixels in each group.
  • One side of the sub-pixels of each group is provided with a power line, and the opposite side is provided with a sensing signal line, and the power line and the sensing signal line are spaced apart.
  • the pixel driving circuit in the two sub-pixels located on one side of the power line and close to the power line, and located on the other side of the power line and close to the power line.
  • the pixel driving circuits in the two sub-pixels are all electrically connected to the power line.
  • the pixel driving circuit in the two sub-pixels located on one side of the sensing signal line and close to the sensing signal line, and the other located on the sensing signal line are all electrically connected to the sensing signal line.
  • the display substrate further includes: a first auxiliary electrode provided for any one of the power lines, and a second auxiliary electrode provided for any one of the sensing signal lines.
  • the orthographic projection of the first auxiliary electrode on the substrate is located within the orthographic projection of the power line on the substrate.
  • the first auxiliary electrode and the power line are electrically connected through a plurality of first via holes.
  • the orthographic projection of the second auxiliary electrode on the substrate is located within the orthographic projection of the sensing signal line on the substrate.
  • the second auxiliary electrode and the sensing signal line are electrically connected through a plurality of second via holes.
  • the first auxiliary electrode, the second auxiliary electrode and the first gate electrode have the same layer and the same material.
  • the display substrate further includes: a filter unit provided between the first storage electrode and the second storage electrode in each sub-pixel; and, provided at the filter unit The flat layer on the side close to the first storage electrode.
  • the first transistor is a top-gate thin film transistor.
  • the display substrate further includes: a metal pattern disposed on a side of the first semiconductor active pattern close to the substrate. Along the thickness direction of the substrate, the orthographic projection of the first semiconductor active pattern on the substrate is within the orthographic projection of the metal pattern on the substrate.
  • the display substrate further includes: a second connection electrode arranged in each of the sub-pixels. The metal pattern, the first storage electrode, and the third storage electrode are electrically connected through a second connection electrode. The second connecting electrode and the first source electrode have the same layer and the same material.
  • the embodiments of the present disclosure also provide a method for preparing a display substrate.
  • the preparation method of the display substrate includes the following steps.
  • a pixel driving circuit located in each sub-pixel is formed in the display area on the substrate.
  • the pixel driving circuit includes a first storage capacitor and a second storage capacitor connected in parallel.
  • the first storage capacitor includes a first storage electrode and a second storage electrode that are arranged oppositely.
  • the second storage capacitor includes the second storage electrode and a third storage electrode disposed opposite to the second storage electrode.
  • the second storage electrode is located between the first storage electrode and the third storage electrode.
  • the first storage electrode is electrically connected to the third storage electrode, and is located on a side of the second storage electrode away from the substrate.
  • the first storage electrode, the second storage electrode, and the third storage electrode are all transparent electrodes.
  • a bottom emission type light emitting device located on the side of the pixel driving circuit away from the substrate is formed.
  • the light emitting device includes a first electrode electrically connected to the pixel driving circuit, and the first electrode is formed by multiplexing the first storage electrode.
  • the pixel driving circuit further includes a first transistor, and the first transistor is a driving transistor.
  • the first transistor includes a first gate, a first semiconductor active pattern, and a first source.
  • the first semiconductor active pattern includes a first channel region, a first source region, and a first drain region, and the conductivity of the first source region and the first drain region is greater than that of the first drain region. The conductivity of the channel region.
  • the first source is in contact with the first source region.
  • Forming the pixel driving circuit further includes: in the process of forming the first semiconductor active pattern, synchronously forming the third storage electrode so that the third storage electrode is connected to the first drain region and As a one-piece structure.
  • the display substrate further includes a gate line and a data line electrically connected to the pixel driving circuit, and a first connection electrode provided in each sub-pixel.
  • the pixel driving circuit further includes a second transistor.
  • the second transistor includes a second gate, a second semiconductor active pattern, a second source, and a second drain.
  • the second semiconductor active pattern includes a second channel region, a second source region, and a second drain region, and the conductivity of the second source region and the second drain region is greater than that of the second drain region.
  • the second source is in direct contact with the second source region
  • the second drain is in direct contact with the second drain region.
  • the manufacturing method of the display substrate further includes: synchronously forming the gate line and the first gate.
  • the second source electrode is electrically connected to the data line.
  • the second drain electrode is electrically connected to the first connection electrode, and the two are in an integral structure.
  • the first connection electrode is also electrically connected to both the first gate and the second storage electrode.
  • the manufacturing method of the display substrate further includes: synchronously forming the second semiconductor active pattern and the first semiconductor active pattern; synchronously forming the first connecting electrode, the second source electrode, and the first semiconductor active pattern; A second drain, the data line, and the first source.
  • the display substrate further includes a power line and a sensing signal line that are electrically connected to the pixel driving circuit.
  • the first source is electrically connected to the power line.
  • the pixel driving circuit further includes a third transistor.
  • the third transistor includes a third gate, a third semiconductor active pattern, and a third drain.
  • the third semiconductor active pattern includes a third channel region, a third source region, and a third drain region, and the conductivity of the third source region and the third drain region is greater than that of the third drain region.
  • the third source region is connected to the third storage electrode and has an integral structure.
  • the third drain is in direct contact with the third drain region, and the third drain is electrically connected to the sensing signal line.
  • the first transistor and the third transistor are respectively located on both sides of the first storage capacitor.
  • the third gate of the third transistor located in any row of sub-pixels is formed by multiplexing a part of the gate line corresponding to the adjacent row of sub-pixels closest to the third transistor.
  • the manufacturing method of the display substrate further includes: synchronously forming the third semiconductor active pattern and the second semiconductor active pattern; synchronously forming the third drain, the power line, and the sensing signal Line with the data line.
  • the manufacturing method of the display substrate further includes: before forming the pixel driving circuit, forming a metal pattern on the substrate, so that after the pixel driving circuit is formed, the In the thickness direction of the substrate, the orthographic projection of the first semiconductor active pattern on the substrate is within the orthographic projection of the metal pattern on the substrate.
  • the display substrate further includes: a second connection electrode disposed in each of the sub-pixels.
  • the manufacturing method of the display substrate further includes: in the process of forming the first source electrode, synchronously forming the second connection electrode, so that the second connection electrode is in contact with the metal pattern and the first memory Both the electrode and the third storage electrode are electrically connected.
  • embodiments of the present disclosure provide a display device, including the display substrate described in any of the foregoing embodiments.
  • FIG. 1 is a schematic diagram of a partial area of a display substrate according to some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of a sub-pixel S in a display substrate shown in FIG. 1;
  • Fig. 3a is a schematic structural diagram of a bottom emission type light-emitting device in some embodiments according to the present disclosure
  • Fig. 3b is a schematic structural diagram of another bottom emission type light emitting device in some embodiments of the present disclosure.
  • FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 2 in the AA' direction;
  • FIG. 6 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 2 in the BB' direction;
  • FIG. 7 is a schematic cross-sectional view of the sub-pixel S shown in FIG. 2 in the CC' direction;
  • FIG. 8 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 2 in the DD' direction;
  • FIG. 9 is a schematic diagram of a partial area of another display substrate according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a sub-pixel S in a display substrate shown in FIG. 9;
  • FIG. 11 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 10 in the FF' direction;
  • FIG. 12 is a schematic cross-sectional view of a sub-pixel S shown in FIG. 10 in the direction HH';
  • FIG. 13 is a schematic diagram of the structure in the R area in the display substrate shown in FIG. 9;
  • FIG. 14 is a schematic cross-sectional view of the display substrate shown in FIG. 13 in the EE' direction;
  • FIG. 15 is a schematic cross-sectional view of the display substrate shown in FIG. 13 in the GG' direction;
  • FIG. 16 is a schematic flowchart of a method for preparing a display substrate according to some embodiments of the present disclosure
  • FIG. 17 is a schematic diagram of a manufacturing process of a display substrate according to some embodiments of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.
  • the expressions of "electrical connection” and “contact” and their extensions may be used.
  • the terms “electrically connected” or “contact” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • the term “if” is optionally interpreted as meaning “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • each sub-pixel of the self-luminous display substrate is provided with a pixel drive circuit and a light-emitting device electrically connected to the pixel drive circuit.
  • the storage capacitor and the light-emitting device in the pixel driving circuit are located in different areas of the sub-pixel, which causes a cross-line at the electrical connection between the storage capacitor and the light-emitting device, thereby increasing the risk of crosstalk.
  • the storage capacitor needs to occupy a larger area of the sub-pixel.
  • the pixel driving circuit is located on the light-emitting side of the light-emitting device, and the storage capacitor occupies a larger area of the sub-pixel, which easily leads to a smaller aperture ratio of the sub-pixel, resulting in a smaller light-emitting area of the light-emitting device. Therefore, when the display brightness is the same, the smaller the light-emitting area of the light-emitting device, the greater the current density it needs, which tends to accelerate the aging speed of the light-emitting device and affect the life of the light-emitting device. However, if the facing area of the storage capacitor is set to be small, the capacitance of the storage capacitor is likely to be small, and the problem of uneven display image quality of the display substrate may occur.
  • some embodiments of the present disclosure provide a display substrate 1.
  • the display substrate 1 has a display area AA, and a plurality of sub-pixels S are arranged in the display area AA of the display substrate 1.
  • the display substrate 1 includes: a substrate 10, and a pixel driving circuit and a bottom light emitting device disposed in the display area AA on the substrate 10 and located in each sub-pixel S Type light emitting device 110.
  • the light emitting device includes a first electrode 111 electrically connected to the pixel driving circuit.
  • the pixel driving circuit includes a first storage capacitor 120 and a second storage capacitor 130 connected in parallel.
  • the first storage capacitor 120 includes a first storage electrode 121 and a second storage electrode 122 disposed oppositely.
  • the second storage capacitor 130 includes the aforementioned second storage electrode 122 and the third storage electrode 123 disposed opposite to the second storage electrode 122.
  • the second storage electrode 122 is located between the first storage electrode 121 and the third storage electrode 123.
  • the first electrode 111 is multiplexed as a first storage electrode 121, and the first storage electrode 121 is electrically connected to the third storage electrode 123.
  • the first electrode 111, the second storage electrode 122, and the third storage electrode 123 are all transparent electrodes.
  • the light emitting device 110 is a bottom emitting type, that is, the pixel driving circuit is located on the light emitting side of the light emitting device 110. Therefore, those skilled in the art should understand that when the first electrode 111 is multiplexed as the first storage electrode 121, the third storage The electrode 123 is located on the side of the second storage electrode 122 close to the substrate 10.
  • the first storage electrode 121 and the second storage electrode 122 are arranged opposite to each other, which means that the orthographic projections of the two on the substrate 10 at least partially overlap.
  • the second storage electrode 122 and the third storage electrode 123 are arranged opposite to each other, which means that the orthographic projections of the two on the substrate 10 at least partially overlap.
  • the first storage capacitor 120 and the second storage capacitor 130 adopt the above structure, which can also be regarded as: the two together form a storage capacitor C adopting a sandwich structure.
  • FIG. 1 only schematically shows the distribution and structure of the sub-pixels S in a partial area of the display substrate 1, and the structure of the light-emitting device 110 is also only partially shown.
  • the light-emitting device 110 includes a first electrode 111 and a second electrode 112, and a light-emitting layer 113 located between the first electrode 111 and the second electrode 112.
  • the first electrode 111 is an anode and the second electrode 112 is a cathode; or, the first electrode 111 is a cathode and the second electrode 112 is an anode.
  • the light-emitting device 110 when the first electrode 111 is an anode and the second electrode 112 is a cathode, the light-emitting device 110 is upright. When the first electrode 111 is a cathode and the second electrode 112 is an anode, the light-emitting device 110 is inverted.
  • the light-emitting device 110 when the first electrode 111 is an anode and the second electrode 112 is a cathode, the light-emitting device 110 further includes a hole transport between the light-emitting layer 113 and the first electrode 111.
  • the layer 114 and the electron transport layer 115 located between the light-emitting layer 113 and the second electrode 112.
  • a hole injection layer may be provided between the hole transport layer 114 and the first electrode 111
  • an electron injection layer may be provided between the electron transport layer 115 and the second electrode 112.
  • the light-emitting device 110 when the first electrode 111 is a cathode and the second electrode 112 is an anode, the light-emitting device 110 further includes a hole transport layer 114 located between the light-emitting layer 113 and the second electrode 112. , An electron transport layer 115 located between the light-emitting layer 113 and the first electrode 111.
  • a hole injection layer can also be provided between the hole transport layer 114 and the second electrode 112, and an electron injection layer can be provided between the electron transport layer 115 and the first electrode 111.
  • the light-emitting layer 113 may be an organic light-emitting layer or a quantum dot light-emitting layer.
  • the material of the first electrode 111 is indium tin oxide (ITO), and the material of the second electrode 112 is silver (Ag). But it is not limited to this.
  • the pixel driving circuit involved in the subsequent embodiments of the present disclosure will be described with the light-emitting device 110 as an upright light-emitting device.
  • the display substrate 1 is usually provided with a pixel defining layer, and the light emitting device 110 is formed in the corresponding opening of the pixel defining layer, and the light emitting area of the sub-pixel S can be defined by the opening area of the pixel defining layer.
  • the material of the pixel defining layer can be a light-transmitting resin material.
  • the first electrode 111 of the light emitting device 110 is multiplexed as the first storage electrode 121, and the first electrode 111, the second storage electrode 122, and the third storage electrode are located in different layers.
  • the storage electrodes 123 are all set as transparent electrodes, so that the storage capacitor C (that is, the first storage capacitor 120 and the second storage capacitor 130 connected in parallel) in the pixel driving circuit are disposed in the area directly opposite to the light-emitting device 110, that is, in the light-emitting device.
  • the light emitting area of the device 110 does not affect the light emitting effect of the light emitting device 110.
  • the second storage electrode 122 is arranged opposite to the first storage electrode 121, and the third storage electrode 123 It is arranged opposite to the second storage electrode 122, and the first storage electrode 121 is electrically connected to the third storage electrode 123, which can avoid cross-line generation when the light emitting device 110 is electrically connected to the first storage capacitor 120 and the second storage capacitor 130. Thereby avoiding the risk of crosstalk.
  • the first storage capacitor 120 and the second storage capacitor 130 may not occupy an area other than the light-emitting area in the sub-pixel S.
  • the light-emitting area of the light-emitting device 110 can occupy more area in the sub-pixel S, thereby increasing the aperture ratio of the sub-pixel S and increasing the service life of the light-emitting device 110.
  • the first electrode 111, the second storage electrode 122, and the third storage electrode 123 are all transparent electrodes, the area of the second storage electrode 122 and the third storage electrode 123 can be set as large as possible, and the first A storage capacitor 120 is connected in parallel with the second storage capacitor 130, so that the capacitance of the storage capacitor C in the pixel driving circuit can be effectively increased, so as to avoid the problem of uneven display quality of the display substrate 1.
  • the display substrate 1 in the embodiment of the present disclosure is applied to an 8K high pixel density (Pixels Per Inch, PPI) display substrate, compared with the average aperture ratio of sub-pixels in the related art of about 12%, the display substrate
  • the average aperture ratio of the pixels in Central Asia can be increased to about 28%, which effectively increases by about 160%.
  • the structure of the pixel drive circuit can be selected and set according to actual needs, for example, the 3T1C pixel circuit shown in FIG. 4; that is, the pixel circuit can be composed of three transistors T and a storage capacitor C, wherein the three transistors are respectively It is the first transistor T1, the second transistor T2, and the third transistor T3; the storage capacitor C is the first storage capacitor 120 in some of the foregoing embodiments.
  • the pixel driving circuit may also be a structure including other numbers of transistors or other numbers of storage capacitors, which is not limited in the embodiments of the present disclosure.
  • a pixel circuit with a 3T1C pixel driving circuit is taken as an example for description.
  • the pixel driving circuit further includes a first transistor T1, and the first transistor T1 is a driving transistor.
  • the first transistor T1 includes a first gate 141, a first semiconductor active pattern 142, and a first source 143.
  • the first semiconductor active pattern 142 includes a first channel region 1421, a first source region 1422, and a first drain region 1423.
  • the conductivity of the first source region 1422 and the first drain region 1423 is greater than that of the first channel
  • the first source electrode 143 is in contact with the first source region 1422.
  • the first source 143 is electrically connected to the power line 18.
  • the power supply line 18 is used to supply power to the pixel driving circuit.
  • the third storage electrode 123 can be obtained by conducting a semiconductor pattern, that is, the third storage electrode 123 can be a semiconductor pattern after conducting a conductorization process. Based on this, the third storage electrode 123 is connected to the first drain region 1423 and has an integral structure. Since the third storage electrode 123 is electrically connected to the first storage electrode 121, the first storage electrode 121 can be multiplexed as the first electrode 111 of the light emitting device 110. Therefore, there is no need to fabricate an independent first drain in the first transistor T1. The electrode is electrically connected to the first electrode 111 by the first drain electrode.
  • the semiconductor pattern located at the position of the first transistor T1 and the position of the third storage electrode 123 is first formed, and then the semiconductor pattern is conductorized except for the position of the first channel region 1421 of the first transistor T1 .
  • ion implantation can be used to conduct conductorization, and the ions can be boron ions or phosphorus ions.
  • the source and drain respectively refer to the other two electrodes except the gate. According to the different types of carriers in the transistor, the source and drain of the transistor can be interchanged. The embodiments of the present disclosure do not limit this, and are only used to assist in explaining the structure of the transistor and the corresponding electrical connection relationship.
  • the first transistor T1 in FIG. 2 and FIG. 5 is illustrated by taking a top-gate thin film transistor as an example.
  • the first semiconductor active pattern 142 is disposed on the side of the first gate 141 close to the substrate 10, and the first semiconductor active pattern 142 and the first gate 141 are insulated by the first gate.
  • the pattern 145 is isolated, and the first source 143 and the first gate 141 are isolated by the interlayer insulating layer 20. Based on this, after the first gate 141 is formed, the above-mentioned conductorization process can be performed.
  • the first gate insulating pattern 145 and the first gate 141 may be formed synchronously. Based on this, the first source electrode 143 directly contacts the first semiconductor active pattern 142 through the via hole penetrating the interlayer insulating layer 20.
  • the simultaneous formation refers to the formation by the same patterning process, such as a mask process. All the "synchronization formation” involved in the embodiments of the present disclosure can be understood in this way, but it is not limited to this.
  • the first source electrode 143 passes through the interlayer insulating layer 20 and the gate insulating layer.
  • the via holes of the two layers are in direct contact with the first semiconductor active pattern 142.
  • the third storage electrode 123 is prepared while preparing the first semiconductor active pattern 142 of the first transistor T1, and the third storage electrode 123 can be formed without additional patterning process.
  • the pixel driving circuit further includes a second transistor T2, and the second transistor T2 includes a second gate 151, a second semiconductor active pattern 152, and a second source 153 And second drain 154.
  • the second semiconductor active pattern 152 includes a second channel region 1521, a second source region 1522 and a second drain region 1523. The conductivity of the second source region 1522 and the second drain region 1523 is greater than the conductivity of the second channel region 1521.
  • the second source electrode 153 is in direct contact with the portion of the second semiconductor active pattern 152 corresponding to the second source region 1522, and the second drain electrode 154 is directly in contact with the portion of the second semiconductor active pattern 152 corresponding to the second drain region 1523. contact.
  • the second semiconductor active pattern 152 in the second transistor T2 is also similar to the first semiconductor active pattern 142.
  • the second transistor T2 and the first transistor T1 can be formed synchronously, that is, the second gate 151 in the second transistor T2 and the first gate 141 in the first transistor T1 are formed synchronously;
  • the second semiconductor active pattern 152 in T2 is formed synchronously with the first semiconductor active pattern 142 in the first transistor T1; the second source 153, the second drain 154 in the second transistor T2 and the first transistor T1
  • the first source 143 is formed simultaneously.
  • the second transistor T2 in FIG. 2 and FIG. 6 is illustrated by taking a top-gate thin film transistor as an example.
  • the second semiconductor active pattern 152 is disposed on the side of the second gate 151 close to the substrate 10, and the second semiconductor active pattern 152 and the second gate 151 are isolated by the second gate insulating pattern 156.
  • the two source electrodes 153 and the second drain electrode 154 are separated from the second gate electrode 151 by the interlayer insulating layer 20.
  • the second gate insulating pattern 156 and the second gate 151 can be formed simultaneously. Based on this, the second source electrode 153 and the second drain electrode 154 pass through the interlayer insulating layer 20, respectively. The hole is in contact with the second semiconductor active pattern 152.
  • the second source 153 and the second drain 154 pass through The via holes of the interlayer insulating layer 20 and the gate insulating layer are in direct contact with the second semiconductor active pattern 152.
  • the display substrate 1 further includes: a gate line 16 and a data line 17 electrically connected to the pixel driving circuit.
  • a part of the gate line 16 is multiplexed as the second gate 151 of the second transistor T2, which can effectively reduce the area occupied by the pixel driving circuit in the sub-pixel S and increase the aperture ratio of the sub-pixel.
  • the second source 153 of the second transistor T2 is electrically connected to the data line 17.
  • the display substrate 1 further includes: a first connection electrode 155 arranged in each sub-pixel S.
  • the second drain electrode 154 of the second transistor T2 is electrically connected to the first connection electrode 155, and the two have an integral structure.
  • the first connection electrode 155 is electrically connected to both the first gate 141 and the second storage electrode 122 of the first transistor T1. That is, the first transistor T1 and the second transistor T2, the first storage capacitor 120, and the second storage capacitor 130 can be electrically connected through the first connection electrode 155.
  • the first connection electrode 155 is in direct contact with the second storage electrode 122, and the first connection electrode 155 and the first gate 141 are electrically connected through a via 1483.
  • the first connection electrode 155 is in direct contact with the second storage electrode 122, which means that the first connection electrode 155 covers the part of the second storage electrode 122, thereby realizing the overlap between the two.
  • the display substrate 1 further includes: a second connection electrode 148 arranged in each sub-pixel S.
  • the first storage electrode 121 and the third storage electrode 123 are electrically connected through the second connection electrode 148.
  • the second connection electrode 148 may pass through the via hole 1481 and the third layer passing through the interlayer insulating layer 20.
  • the storage electrode 123 is in direct contact, and the second connection electrode 148 is in direct contact with the first storage electrode 121 through the via 1482 penetrating through the two layers of the planarization layer 70 and the passivation layer 50, so that the first storage electrode 121 and the third storage electrode 123 can be electrically connected. connection.
  • connection electrode 148 and the first connection electrode 155 have the same layer and the same material.
  • the pixel driving circuit when the pixel driving circuit includes a second transistor T2, the pixel driving circuit further includes a third transistor T3, and the third transistor T3 includes a third gate 191, The third semiconductor active pattern 192 and the third drain electrode 193.
  • the third transistor T3 in FIGS. 2 and 8 is illustrated by taking a top-gate thin film transistor as an example.
  • the third semiconductor active pattern 192 is disposed near the substrate of the third gate 191.
  • the third semiconductor active pattern 192 and the third gate electrode 191 are separated by the third gate insulating pattern 195, and the third drain electrode 193 and the third gate electrode 191 are separated by the interlayer insulating layer 20.
  • the third gate insulating pattern 195 and the third gate electrode 191 are formed synchronously. Based on this, the third drain electrode 193 contacts the third semiconductor active pattern 192 through the via hole penetrating the interlayer insulating layer 20.
  • the third drain electrode 193 is in contact with the third semiconductor active pattern 192 through a via hole penetrating through the interlayer insulating layer 20 and the gate insulating layer. .
  • the third semiconductor active pattern 192 includes a third channel region 1921, a third source region 1922, and a third drain region 1923.
  • the third source region 1922 And the conductivity of the third drain region 1923 is greater than that of the third channel region 1921.
  • the display substrate 1 also includes a sensing signal line 40.
  • the third drain electrode 193 is in contact with the third drain region 1923, and the third drain electrode 193 is electrically connected to the sensing signal line 40.
  • the third source region 1922 is connected to the third storage electrode 123 and has an integral structure.
  • the third storage electrode 123 is electrically connected to the first storage electrode 121, the first storage electrode 121 can be multiplexed as the first electrode 111 of the light emitting device 110. Therefore, there is no need to fabricate an independent third source in the third transistor T3.
  • the third source is electrically connected to the first electrode 111.
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a first storage capacitor 120, and a second storage capacitor 130
  • its equivalent circuit diagram is as shown in FIG. 4.
  • the first storage capacitor 120 and the second storage capacitor 130 together form a storage capacitor C.
  • the pixel drive circuit is a 3T1C drive circuit. Based on this, the parameter of the first transistor T1 can be sensed through the sensing signal line 40, and then the threshold voltage of the first transistor T1 can be compensated externally.
  • the materials of the gate line 16, the data line 17, the sensing signal line 40, and the power line 18 may be selected from copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr) and tungsten ( At least one of W) elemental metal and a metal alloy composed of these elemental metals.
  • the materials of the first gate insulating pattern 145, the second gate insulating pattern 156, the third gate insulating pattern 195, and the interlayer insulating layer 20 may be selected from inorganic oxides such as silicon nitride (SiNx) and silicon dioxide (SiO2). One or more of them, and the first gate insulating pattern 145, the second gate insulating pattern 156, the third gate insulating pattern 195, and the interlayer insulating layer 20 may adopt a single-layer structure or a multilayer laminated structure.
  • the materials in the first semiconductor active pattern 142, the second semiconductor active pattern 152, and the third semiconductor active pattern 192 may be selected from transparent semiconductor oxides, such as indium zinc oxide (IGZO).
  • the data line 17, the power supply line 18, and the sensing signal line 40 extend in the first direction.
  • the first transistor T1 and the third transistor T3 are respectively located on two sides of the first storage capacitor 120 along the first direction.
  • the third gate 191 of the third transistor T3 in any row of sub-pixels S is determined by the gate corresponding to the adjacent row of sub-pixels S closest to the third transistor T3.
  • a part of the line 16 is multiplexed. Therefore, it is beneficial to reduce the area occupied by the pixel driving circuit in the sub-pixel S in the case where a plurality of sub-pixels S are arranged in an array, so as to increase the aperture ratio of the sub-pixels.
  • the third gate 191 of the third transistor T3 in any sub-pixel S is the second transistor T2 in the sub-pixel S in the adjacent row closest to the third transistor T3.
  • the second gate 151 can be formed by multiplexing different parts of the same gate line 16. Therefore, the total number of gate lines 16 in the display substrate 1 can be reduced to simplify the manufacturing process.
  • the display substrate 1 further includes a substrate 10 disposed on the first semiconductor active pattern 142.
  • Metal pattern 147 on one side.
  • the orthographic projection of the first semiconductor active pattern 142 on the substrate 10 is within the orthographic projection of the metal pattern 147 on the substrate 10.
  • the metal pattern 147, the first storage electrode 121 and the third storage electrode 123 are electrically connected by the second connection electrode 148, and the second connection electrode 148 and the first source electrode 143 have the same layer and the same material.
  • the display substrate 1 when the display substrate 1 includes the metal pattern 147, the display substrate 1 further includes a buffer layer 60 located on the side of the metal pattern 147 away from the substrate 10 and covering the metal pattern 147.
  • the second connection electrode 148 contacts the metal pattern 147 through a via 1481 penetrating through the two layers of the interlayer insulating layer 20 and the buffer layer 60, and at the same time contacts the third storage electrode 123 via the via 1481.
  • the first storage electrode 121 is in contact with the second connection electrode 148 through a via 1482 penetrating through the two layers of the planarization layer 70 and the passivation layer 50.
  • electrical connection between the metal pattern 147, the first storage electrode 121 and the third storage electrode 123 is realized.
  • the metal pattern 147 can prevent external light from entering the first semiconductor active pattern 142, thereby preventing the external light from adversely affecting the performance of the first transistor T1. At the same time, when the metal pattern 147 is provided in the display substrate 1, by electrically connecting the metal pattern 147 to the third storage electrode 123 and the first storage electrode 121, it is possible to avoid the occurrence of the metal pattern 147 during the use of the display substrate 1. Parasitic capacitance.
  • the power line 18, the sensing signal line 40 and the data line 17 are arranged in parallel and in the same layer, which is beneficial to simplify the wiring design of each signal line in the display substrate 1.
  • every two adjacent sub-pixels S is a group, and two data lines 17 are arranged between the two sub-pixels S in each group.
  • a power line 18 is provided on one side of each group of sub-pixels S, and a sensing signal line 40 is provided on the opposite side, and the power line 18 and the sensing signal line 40 are spaced apart.
  • the pixel driving circuit in the two sub-pixels S located on one side of the power line 18 and close to the power line 18, and the two sub-pixels located on the other side of the power line 18 and close to the power line 18 are all electrically connected to the power line 18.
  • the pixel driving circuit in the two sub-pixels S located on one side of the sensing signal line 40 and close to the sensing signal line 40, and the pixel driving circuit located on the other side of the sensing signal line 40 and close to the sensing signal line 40 are electrically connected to the sensing signal line 40.
  • the total number of power lines 18 and sensing signal lines 40 can be reduced, thereby simplifying the manufacturing process of the display substrate 1.
  • the display substrate 1 further includes: a first auxiliary electrode 181 provided for any power line 18.
  • a first auxiliary electrode 181 provided for any power line 18.
  • the orthographic projection of the first auxiliary electrode 181 on the substrate 10 is within the orthographic projection of the power line 18 on the substrate 10.
  • the first auxiliary electrode 181 and the power line 18 are electrically connected through a plurality of first via holes 1811. That is, the first auxiliary electrode 181 is connected in parallel with the power supply line 18. In this way, it is beneficial to reduce the equivalent resistance of the power line 18, thereby reducing the loss of the signal transmitted by the power line 18.
  • the display substrate 1 further includes: a second auxiliary electrode 401 provided for any one of the sensing signal lines 40.
  • the orthographic projection of the second auxiliary electrode 401 on the substrate 10 is located within the orthographic projection of the sensing signal line 40 on the substrate 10.
  • the second auxiliary electrode 401 and the sensing signal line 40 are electrically connected through a plurality of second via holes 4011; that is, the second auxiliary electrode 401 is connected in parallel with the sensing signal line 40. In this way, it is beneficial to reduce the equivalent resistance of the sensing signal line 40, thereby reducing the loss of the signal transmitted by the sensing signal line 40.
  • the first auxiliary electrode 181, the second auxiliary electrode 401 and the first gate 141 have the same layer and the same material. Based on this, the first auxiliary electrode 181 and the second auxiliary electrode 401 can be prepared at the same time as the first gate 141 is prepared, thereby simplifying the preparation process of the display substrate 1.
  • the display substrate 1 further includes a filter unit disposed in each sub-pixel S, so as to realize the color display of the display substrate 1 by using the filter unit. Based on this, optionally, as shown in FIGS. 6 and 11, the display substrate 1 further includes: a filter unit 30 disposed between the first storage electrode 121 and the second storage electrode 122 in each sub-pixel S, and The flat layer 70 is disposed on the side of the filter unit 30 close to the first storage electrode 121.
  • the filter unit 30 is a color filter film.
  • the filter unit 30 located in the red sub-pixel is a red filter unit
  • the filter unit 30 located in the green sub-pixel is a green filter unit
  • the filter unit 30 located in the blue sub-pixel is a blue filter unit.
  • the light-emitting layer 113 in the light-emitting device 110 emits white light
  • the light-emitting layers 113 in all the sub-pixels can be connected as a whole layer.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all top-gate thin film transistors.
  • the embodiment of the present disclosure provides a method for preparing the display substrate 1. As shown in FIG. 16, the preparation method of the display substrate 1 includes: S10 to S20.
  • a pixel driving circuit located in each sub-pixel S is formed in the display area AA on the substrate 10.
  • the aforementioned pixel driving circuit includes a first storage capacitor 120 and a second storage capacitor 130 connected in parallel.
  • the first storage capacitor 120 includes a first storage electrode 121 and a second storage electrode 122 disposed oppositely.
  • the second storage capacitor 130 includes a second storage electrode 122 and a third storage electrode 123 disposed opposite to the second storage electrode 122.
  • the second storage electrode 122 is located between the first storage electrode 121 and the third storage electrode 123.
  • the first storage electrode 121 is electrically connected to the third storage electrode 123, and the first storage electrode 121 is located on the side of the second storage electrode 122 away from the substrate 10.
  • the first storage electrode 121, the second storage electrode 122, and the third storage electrode 123 are all transparent electrodes.
  • each sub-pixel S on the substrate 10 a bottom-emitting light-emitting device located on the side of the pixel driving circuit away from the substrate 10 is formed.
  • the light emitting device 110 includes a first electrode 111. As shown in FIG. 7, the first electrode 111 is connected to the pixel driving circuit. In addition, the first electrode 111 is formed by multiplexing the first storage electrode 121.
  • the beneficial effects that can be achieved by the manufacturing method of the display substrate 1 provided by the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display substrate 1 provided by the above-mentioned embodiments, and will not be repeated here.
  • the pixel driving circuit further includes a first transistor T1, and the first transistor T1 includes a first gate 141, a first semiconductor active pattern 142, and a first source 143 .
  • the first transistor T1 is a driving transistor.
  • the first semiconductor active pattern 142 includes a first channel region 1421, a first source region 1422, and a first drain region 1423. The conductivity of the first source region 1422 and the first drain region 1423 is greater than that of the first channel The conductivity of the area 1421.
  • the first source electrode 143 is in contact with the first source region 1422.
  • forming the pixel driving circuit further includes: in the process of forming the first semiconductor active pattern 142, synchronously forming the third storage electrode 123, so that the third storage electrode 123 is connected to the first drain region 1423 and has an integral structure .
  • the third storage electrode 123 is a semiconductor pattern that has undergone a conductive process. Since the third storage electrode 123 is electrically connected to the first storage electrode 121, the first storage electrode 121 can be multiplexed as the first electrode 111 of the light emitting device 110. Therefore, there is no need to fabricate an independent first drain in the first transistor T1. The electrode is electrically connected to the first electrode 111 by the first drain electrode.
  • the semiconductor pattern located at the position of the first transistor T1 and the position of the third storage electrode 123 is first formed, and then the semiconductor pattern is conductorized except for the position of the first channel region 1421 of the first transistor T1 .
  • ion implantation can be used to conduct conductorization, and the ions can be boron ions or phosphorus ions.
  • the display substrate 1 further includes: a gate line 16 and a data line 17 electrically connected to the pixel driving circuit.
  • the pixel driving circuit further includes a second transistor T2, and the second transistor T2 includes a second gate 151, a second semiconductor active pattern 152, a second source 153, and a second drain 154.
  • the second semiconductor active pattern 152 includes a second channel region 1521, a second source region 1522, and a second drain region 1523.
  • the conductivity of the second source region 1522 and the second drain region 1523 is greater than that of the second channel
  • the second source 153 is in contact with the second source region 1522, and the second drain 154 is in contact with the second drain region 1523.
  • Each sub-pixel S corresponds to a gate line 16, and a part of the gate line 16 can be multiplexed as the second gate 151.
  • the manufacturing method of the display substrate 1 further includes: simultaneously forming the gate line 16 and the first gate 141 in the process of performing S10. Therefore, the manufacturing process of the display substrate 1 can be simplified.
  • the display substrate 1 further includes: a first connection electrode 155 arranged in each sub-pixel S.
  • the second source electrode 153 is electrically connected to the data line 17, and the second drain electrode 154 is electrically connected to the first connection electrode 155, and the two are integrated.
  • the first connection electrode 155 is also electrically connected to both the first gate 141 and the second storage electrode 122. That is, through the first connection electrode 155, the first transistor T1 and the second transistor T2, the first storage capacitor 120, and the second storage capacitor 130 can be electrically connected.
  • the manufacturing method of the display substrate 1 further includes: synchronously forming the second semiconductor active pattern 152 and the first semiconductor active pattern 142; and synchronously forming the first connection electrode 155, the second source electrode 153, and the second drain electrode 154, The data line 17 and the first source 143. Therefore, the manufacturing process of the display substrate 1 can be simplified.
  • the display substrate 1 further includes a power line 18 and a sensing signal line 40.
  • the first source 143 is electrically connected to the power line 18.
  • the pixel driving circuit further includes a third transistor T3, and the third transistor T3 includes a third gate 191, a third semiconductor active pattern 192, and a third drain 193.
  • the third semiconductor active pattern 192 includes a third channel region 1921, a third source region 1922, and a third drain region 1923, and the conductivity of the third source region 1922 and the third drain region 1923 is greater than that of the third channel The conductivity of the region 1921.
  • the third source region 1922 is connected to the third storage electrode 123 and has an integral structure.
  • the third drain 1923 is in contact with the third drain region 1923, and the third drain 1923 is electrically connected to the sensing signal line 40.
  • the first transistor T1 and the third transistor T3 are respectively located on both sides of the first storage capacitor 120.
  • the third gate 191 of the third transistor T3 located in any row of sub-pixels S is formed by multiplexing a part of the gate line 16 corresponding to the adjacent row of sub-pixels S closest to the third transistor T3.
  • the manufacturing method of the display substrate 1 further includes: synchronously forming the third semiconductor active pattern 192 and the second semiconductor active pattern 152; synchronously forming the third drain 193, the power line 18, the sensing signal line 40 and the data line 17. Therefore, the preparation process of the display substrate 1 can be further simplified.
  • the preparation method of the display substrate 1 further includes:
  • the metal pattern 147 is formed on the substrate 10, so that after the pixel driving circuit is formed, the first semiconductor active pattern 142 is formed on the substrate 10 along the thickness direction of the substrate.
  • the orthographic projection is within the orthographic projection of the metal pattern 147 on the substrate 10.
  • the structure and function of the metal pattern 147 are as described in the previous embodiments, and will not be described in detail here.
  • the preparation method of the display substrate 1 further includes: in the process of forming the first source electrode 143, simultaneously forming The second connection electrode 148 makes the second connection electrode 148 electrically connected to the metal pattern 147, the first storage electrode 121, and the third storage electrode 123.
  • the display substrate 1 when the display substrate 1 includes the metal pattern 147, the display substrate 1 further includes a buffer layer 60 located on the side of the metal pattern 147 away from the substrate and covering the metal pattern 147.
  • the second connection electrode 148 directly contacts the metal pattern 147 through the via hole 1481 penetrating the two layers of the interlayer insulating layer 20 and the buffer layer 60, and at the same time directly contacts the third storage electrode 123 through the via hole 1481.
  • the first storage electrode 121 is in direct contact with the second connection electrode 148 through the via 1482 penetrating the two layers of the planarization layer 70 and the passivation layer 50, thereby realizing electrical connection between the metal pattern 147 and the first storage electrode 121 and the third storage electrode 123 .
  • the display substrate 1 includes the first connection electrode 155 and the second connection electrode 148
  • the second connection electrode 148 is connected to the metal
  • the pattern 147, the first storage electrode 121, and the third storage electrode 123 are all electrically connected, and the preparation method of the first connection electrode 155 and the second connection electrode 148 is as follows.
  • an interlayer The insulating film 201 is then formed to form a second storage electrode 122.
  • a patterning process is performed on the interlayer insulating film 201 to form a via 1483 penetrating the interlayer insulating film 201, so that part of the first gate 141 is in the via 1483 Exposed; and synchronously form a via 1481 penetrating the interlayer insulating film 201 and the buffer layer 60, so that the metal pattern 147 and the third storage electrode 123 are exposed in the via 1481.
  • the interlayer insulating film after the via hole is formed by the patterning process is the interlayer insulating layer 20.
  • the first connection electrode 155 and the second connection electrode 148 are simultaneously formed.
  • the first connection electrode 155 overlaps the second storage electrode 122 and directly contacts the second storage electrode 122.
  • the first connection electrode 155 is electrically connected to the first gate 141 through a via 1483 penetrating the interlayer insulating layer 20.
  • the second connection electrode 148 is electrically connected to the metal pattern 147 and the third storage electrode 123 through a via 1481 penetrating through the two layers of the interlayer insulating layer 20 and the buffer layer 60.
  • the second source electrode 153, the second drain electrode 154, the data line 17, the first source electrode 143, etc. can also be formed simultaneously.
  • the passivation layer 50, the filter unit 30 located in the sub-pixels, and the flattening layer 70 are sequentially formed.
  • the passivation layer 50 and the flattening layer 70 include passing through the two layers. ⁇ via 1482.
  • the part of the second connection electrode 148 is exposed in the via hole 1482.
  • the first storage electrode 121 (or the first electrode 111) is formed so that the first storage electrode 121 passes through the via hole 1482 penetrating the passivation layer 50 and the planarization layer 70. It is electrically connected to the second connection electrode 148. Then, the pixel defining layer 80, the light emitting layer 113, the second electrode 112, and the like are sequentially formed.
  • the metal pattern 147 can prevent external light from being incident on the first semiconductor active pattern 142 and affect the performance of the first transistor T1. At the same time, when the metal pattern 147 is provided in the display substrate 1, by electrically connecting the metal pattern 147 with the first storage electrode 121 and the third storage electrode 123, it is possible to prevent the metal pattern 147 from being placed on the metal pattern 147 during the use of the display substrate 1. Generate parasitic capacitance.
  • the embodiment of the present disclosure provides a display device.
  • the display device 1000 includes the display substrate 1 in any of the foregoing embodiments.
  • the beneficial effects that can be achieved by the display device 1000 provided by the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display substrate 1 provided by the above-mentioned embodiments, and will not be repeated here.
  • the display device 1000 is an OLED display substrate, an OLED display, an OLED television, a mobile phone, a tablet computer, a notebook computer, an electronic paper, a digital photo frame, or a navigator and other products or components with display functions.

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Abstract

本公开实施例提供一种显示基板及其制备方法、显示装置，不仅能够避免发光器件和像素驱动电路中的存储电容电连接时产生跨线以减少串扰，还方便制备，能够有效提高像素开口率。所述显示基板包括：衬底和设置于衬底上的像素驱动电路与底发光型发光器件。发光器件包括与像素驱动电路电连接的第一电极。像素驱动电路包括第一存储电容和第二存储电容。第一存储电容包括第一存储电极和第二存储电极，第二存储电容包括第二存储电极和第三存储电极。第二存储电极位于第一存储电极与第三存储电极之间。第一电极复用为第一存储电极。第一存储电极与第三存储电极电连接。第一电极、第二存储电极和第三存储电极均为透明电极。

Description

显示基板及其制备方法、显示装置
本申请要求于2019年11月19日提交中国专利局、申请号为201911135746.2、申请名称为“显示面板及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
自发光显示基板例如有机发光二极管(Organic Light-Emitting Diode，OLED)显示基板具有自发光、轻薄、功耗低、色彩还原度好、反应灵敏以及广视角等优点，已经被越来越广泛的应用在手机、笔记本电脑以及电视等显示装置中，成为目前市场的主流之一。
发明内容
一方面，本公开实施例提供一种显示基板。所述显示基板包括：衬底、以及设置于所述衬底上的显示区内且位于每个亚像素中的像素驱动电路与底发光型发光器件。所述发光器件包括与像素驱动电路电连接的第一电极。所述像素驱动电路包括并联的第一存储电容和第二存储电容。所述第一存储电容包括：相对设置的第一存储电极和第二存储电极。所述第一电极复用为所述第一存储电极。所述第二存储电容包括：所述第二存储电极、和与所述第二存储电极相对设置的第三存储电极。沿所述衬底的厚度方向，所述第二存储电极位于第一存储电极与第三存储电极之间。所述第一存储电极与所述第三存储电极电连接。所述第一电极、所述第二存储电极和所述第三存储电极均为透明电极。
在一些实施例中，所述显示基板，还包括：电源线。所述像素驱动电路还包括第一晶体管，所述第一晶体管为驱动晶体管。所述第一晶体管包括第一栅极、第一半导体有源图案、第一源极。所述第一半导体有源图案包括第一沟道区、第一源极区和第一漏极区，所述第一源极区和所述第一漏极区的导电性大于所述第一沟道区的导电性。所述第一源极与所述第一源极区直接接触。所述第一源极与所述电源线电连接。所述第三存储电极为经过导体化处理后的半导体图案，所述第三存储电极与所述第一漏极区连接且为一体结构。
在一些实施例中，所述显示基板，还包括：与所述像素驱动电路电连接的栅线和数据线；以及，设置于所述每个亚像素中的第一连接电极。所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极、第二半导体有源图案、第二源极和第二漏极。所述栅线中的一部分复用为所述第二栅极。所述第二源极与所述数据线电连接。所述第二漏极与所述第一连接电极为一体结构。所述第一连接电极与所述第一栅极、所述第二存储电极均电连接。
在一些实施例中，所述第一连接电极与所述第二存储电极直接接触，所述第一连接电极与所述第一栅极通过过孔电连接。
在一些实施例中，所述显示基板，还包括：与所述像素驱动电路电连接的感测信号线。所述像素驱动电路还包括第三晶体管；所述第一晶体管和所述第三晶体管分别位于所述第一存储电容的两侧。所述第三晶体管包括第三栅极、第三半导体有源图案和第三漏极。所述第三半导体有源图案包括第三沟道区、第三源极区和第三漏极区，所述第三源极区和所述第三漏极区的导电性大于所述第三沟道区的导电性。所述第三源极区与所述第三存储电极连接且为一体结构。所述第三漏极与所述第三漏极区直接接触，且所述第三漏极与所述感测信号线电连接。
在一些实施例中，位于任一行亚像素中的所述第三晶体管的所述第三栅极，由距离所述第三晶体管最近的相邻行亚像素对应的所述栅线的一部分复用构成。
在一些实施例中，所述电源线、所述感测信号线以及所述数据线平行且同层设置。
每行所述亚像素中，每相邻的两个所述亚像素为一组，每组的两个所述亚像素之间设置有两根所述数据线。每组所述亚像素的一侧设置有一根所述电源线，相对的另一侧设置有一根所述感测信号线，且所述电源线和所述感测信号线间隔设置。
针对每行所述亚像素，位于所述电源线的一侧且靠近该电源线的两个所述亚像素中的所述像素驱动电路、以及位于该电源线的另一侧且靠近该电源线的两个所述亚像素中的所述像素驱动电路，均与该电源线电连接。
针对每行所述亚像素，位于所述感测信号线的一侧且靠近该感测信号线的两个所述亚像素中的所述像素驱动电路、以及位于该感测信号线的另一侧且靠近该感测信号线的两个所述亚像素中的所述像素驱动电路，均与该感测信号线电连接。
在一些实施例中，所述显示基板，还包括：针对任一根所述电源线设置的第一辅助电极，以及针对任一根所述感测信号线设置的第二辅助电极。沿所述衬底的厚度方向，所述第一辅助电极在所述衬底上的正投影位于所述电源线在所述衬底上的正投影内。所述第一辅助电极与所述电源线通过多个第一过孔电连接。沿所述衬底的厚度方向，所述第二辅助电极在所述衬底上的正投影位于所述感测信号线在所述衬底上的正投影内。所述第二辅助电极与所述感测信号线通过多个第二过孔电连接。所述第一辅助电极、所述第二辅助电极与所述第一栅极同层同材料。
在一些实施例中，所述显示基板，还包括：设置于每个亚像素中所述第一存储电极与所述第二存储电极之间的滤光单元；以及，设置于所述滤光单元的靠近所述第一存储电极的一侧的平坦层。
在一些实施例中，所述第一晶体管为顶栅型薄膜晶体管。所述显示基板，还包括：设置于所述第一半导体有源图案的靠近所述衬底的一侧的金属图案。沿所述衬底的厚度方向，所述第一半导体有源图案在所述衬底上的正投影位于所述金属图案在所述衬底上的正投影内。所述显示基板，还包括：设置于所述每个亚像素中的第二连接电极。所述金属图案、所述第一存储电极与所述第三存储电极，三者通过第二连接电极电连接。所述第二连接电极与所述第一源极同层同材料。
另一方面，本公开实施例还提供了一种显示基板的制备方法。所述显示基板的制备方法包括以下步骤。
在衬底上的显示区内形成位于每个亚像素中的像素驱动电路。所述像素驱动电路包括并联的第一存储电容和第二存储电容。所述第一存储电容包括相对设置的第一存储电极和第二存储电极。所述第二存储电容包括所述第二存储电极和与所述第二存储电极相对设置的第三存储电极。沿所述衬底的厚度方向，所述第二存储电极位于所述第一存储电极与所述第三存储电极之间。所述第一存储电极与所述第三存储电极电连接，且位于所述第二存储电极的远离所述衬底的一侧。所述第一存储电极、所述第二存储电极和所述第三存储电极均为透明电极。
在所述衬底上的每个所述亚像素中，形成位于所述像素驱动电路的远离所述衬底一侧的底发光型发光器件。所述发光器件包括与所述像素驱动电路电连接的第一电极，所述第一电极由所述第一存储电极复用构成。
在一些实施例中，所述像素驱动电路还包括第一晶体管，所述第一晶体管为驱动晶体管。所述第一晶体管包括第一栅极、第一半导体有源图案、第一源极。所述第一半导体有源图案包括第一沟道区、第一源极区和第一漏极区，所述第一源极区和所述第一漏极区的导电性大于所述第一沟道区的导电性。所述第一源极与所述第一源极区接触。
形成所述像素驱动电路，还包括：在形成所述第一半导体有源图案的过程中，同步形成所述第三存储电极，使得所述第三存储电极与所述第一漏极区连接且为一体结构。
在一些实施例中，所述显示基板还包括：与所述像素驱动电路电连接的栅线和数据线，以及设置于所述每个亚像素中的第一连接电极。所述像素驱动电路还包括第二晶体管。所述第二晶体管包括第二栅极、第二半导体有源图案、第二源极和第二漏极。所述第二半导体有源图案包括第二沟道区、第二源极区和第二漏极区，所述第二源极区和所述第二漏极区的导电性大于所述第二沟道区的导电性。所述第二源极与所述第二源极区直接接触，所述第二漏极与所述第二漏极区直接接触。
所述栅线中的一部分复用为所述第二栅极。所述显示基板的制备方法，还包括：同步形成所述栅线和所述第一栅极。
所述第二源极与所述数据线电连接。所述第二漏极与所述第一连接电极电连接，且二者为一体结构。所述第一连接电极还与所述第一栅极、所述第二存储电极均电连接。所述显示基板的制备方法，还包括：同步形成所述第二半导体有源图案与所述第一半导体有源图案；同步形成所述第一连接电极、所述第二源极、所述第二漏极、所述数据线以及所述第一源极。
在一些实施例中，所述显示基板还包括与所述像素驱动电路电连接的电源线和感测信号线。所述第一源极与所述电源线电连接。所述像素驱动电路还包括第三晶体管。所述第三晶体管包括第三栅极、第三半导体有源图案和第三漏极。所述第三半导体有源图案包括第三沟道区、第三源极区和第三漏极区，所述第三源极区和所述第三漏极区的导电性大于所述第三沟道区的导电性。所述第三源极区与所述第三存储电极连接且为一体结构。所述第三漏极与所述第三漏极区直接接触，且所述第三漏极与所述感测信号线电连接。
所述第一晶体管和所述第三晶体管分别位于所述第一存储电容的两侧。位于任一 行亚像素中的所述第三晶体管的所述第三栅极，由距离所述第三晶体管最近的相邻行亚像素对应的所述栅线的一部分复用构成。
所述显示基板的制备方法，还包括：同步形成所述第三半导体有源图案与所述第二半导体有源图案；同步形成所述第三漏极、所述电源线、所述感测信号线与所述数据线。
在一些实施例中，所述显示基板的制备方法，还包括：在形成所述像素驱动电路之前，在所述衬底上形成金属图案，以使得在形成所述像素驱动电路之后，沿所述衬底的厚度方向，所述第一半导体有源图案在所述衬底上的正投影位于所述金属图案在所述衬底上的正投影内。
在一些实施例中，所述显示基板还包括：设置于所述每个亚像素中的第二连接电极。所述显示基板的制备方法，还包括：在形成所述第一源极的过程中，同步形成所述第二连接电极，使得所述第二连接电极与所述金属图案、所述第一存储电极和所述第三存储电极均电连接。
又一方面，本公开实施例提供一种显示装置，包括上述任一些实施例所述的显示基板。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开一些实施例中的一种显示基板的部分区域的结构示意图；
图2为图1所示的一种显示基板中一种亚像素S的结构示意图；
图3a为根据本公开一些实施例中的一种底发光型发光器件的结构示意图；
图3b为根据本公开一些实施例中的另一种底发光型发光器件的结构示意图；
图4为根据本公开一些实施例中的一种像素驱动电路的等效电路图；
图5为图2所示的一种亚像素S在AA'向的剖面示意图；
图6为图2所示的一种亚像素S在BB'向的剖面示意图；
图7为图2所示的一种亚像素S在CC'向的剖面示意图；
图8为图2所示的一种亚像素S在DD'向的剖面示意图；
图9为根据本公开一些实施例中的另一种显示基板的部分区域的结构示意图；
图10为图9所示的一种显示基板中一种亚像素S的结构示意图；
图11为图10所示的一种亚像素S在FF'向的剖面示意图；
图12为图10所示的一种亚像素S在HH'向的剖面示意图；
图13为图9所示的一种显示基板中在R区域内的结构示意图；
图14为图13所示的一种显示基板在EE'向的剖面示意图；
图15为图13所示的一种显示基板在GG'向的剖面示意图；
图16为根据本公开一些实施例中的一种显示基板的制备方法的流程示意图；
图17为根据本公开一些实施例中的一种显示基板的制备过程的示意图；
图18为根据本公开一些实施例中的一种显示装置的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”等序数仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“电连接”和“接触”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“电连接”或“接触”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
相关技术中，自发光显示基板的每个亚像素中均设置有像素驱动电路、以及与像素驱动电路电连接的发光器件。在单个亚像素的面积有限的情况下，像素驱动电路中的存储电容与发光器件分别位于亚像素的不同区域，导致存储电容与发光器件的电连接处会产生跨线，从而增加了串扰风险。在此基础上，若存储电容的正对面积设置的较大，则存储电容需要占用亚像素的面积也较大。这样对于底发光型的显示基板，像素驱动电路位于发光器件的出光侧，存储电容占用亚像素的面积较大容易导致亚像素 的开口率较小，导致发光器件的发光面积较小。由此，在显示亮度相同的情况下，发光器件的发光面积越小，其需要的电流密度就越大，从而容易加快发光器件的老化速度，影响发光器件的寿命。而若将存储电容的正对面积设置的较小，则容易导致存储电容的电容量较小，进而出现显示基板显示画质不均的问题。
请参阅图1和图2，本公开一些实施例提供一种显示基板1。显示基板1具有显示区AA，显示基板1的显示区AA内设置有多个亚像素S。请结合图2、图3a、图3b和图4理解，显示基板1包括：衬底10，以及设置于衬底10上显示区AA内且位于每个亚像素S中的像素驱动电路与底发光型发光器件110。发光器件包括与像素驱动电路电连接的第一电极111。
如图1、图2和图4中所示，像素驱动电路包括并联的第一存储电容120和第二存储电容130。第一存储电容120包括相对设置的第一存储电极121和第二存储电极122。第二存储电容130包括上述的第二存储电极122以及与第二存储电极122相对设置的第三存储电极123。沿衬底10的厚度方向，第二存储电极122位于第一存储电极121与第三存储电极123之间。第一电极111复用为第一存储电极121，第一存储电极121与第三存储电极123电连接。第一电极111、第二存储电极122和第三存储电极123均为透明电极。
由于发光器件110为底发光型，即像素驱动电路位于发光器件110的出光侧，因而，本领域技术人员应该明白，在第一电极111复用为第一存储电极121的情况下，第三存储电极123位于第二存储电极122的靠近衬底10的一侧。此处，第一存储电极121和第二存储电极122相对设置，是指二者在衬底10上的正投影至少部分重叠。第二存储电极122和第三存储电极123相对设置，是指二者在衬底10上的正投影至少部分重叠。此外，第一存储电容120和第二存储电容130采用如上结构，也可视为是：二者共同构成一个采用三明治式结构的存储电容C。
需要说明的是，图1仅示意出显示基板1部分区域内亚像素S的分布及结构，其中，发光器件110的结构也仅作了部分示意。
可选的，如图3a和图3b所示，该发光器件110包括第一电极111和第二电极112，以及位于第一电极111和第二电极112之间的发光层113。
可选的，第一电极111为阳极，第二电极112为阴极；或者，第一电极111为阴极，第二电极112为阳极。
可以理解的是，在第一电极111为阳极，第二电极112为阴极的情况下，该发光器件110为正置。在第一电极111为阴极，第二电极112为阳极的情况下，该发光器件110为倒置。
在此基础上，如图3a所示，在第一电极111为阳极，第二电极112为阴极的情况下，该发光器件110还包括位于发光层113和第一电极111之间的空穴传输层114、位于发光层113和第二电极112之间的电子传输层115。当然，根据需要在一些实施例中，还可以在空穴传输层114和第一电极111之间设置空穴注入层，可以在电子传输层115和第二电极112之间设置电子注入层。
示例的，如图3b所示，在第一电极111为阴极，第二电极112为阳极的情况下，该发光器件110还包括位于发光层113和第二电极112之间的空穴传输层114、位于 发光层113和第一电极111之间的电子传输层115。当然，还可以在空穴传输层114和第二电极112之间设置空穴注入层，可以在电子传输层115和第一电极111之间设置电子注入层。
在此基础上，可选的，发光层113可以为有机发光层或者量子点发光层。
可选的，第一电极111的材料采用氧化铟锡(ITO),第二电极112的材料采用金属银(Ag)。但并不仅限于此。
需要说明的是，本公开实施例后续涉及的像素驱动电路，以该发光器件110为正置发光器件进行说明。此外，显示基板1中通常设置有像素界定层，发光器件110形成于像素界定层的对应开口内，可以利用像素界定层的开口面积限定亚像素S的发光面积。像素界定层的材料可以采用透光树脂材料。
在本公开实施例提供的显示基板1中，通过将发光器件110的第一电极111复用为第一存储电极121，并将位于不同层的第一电极111、第二存储电极122和第三存储电极123均设置为透明电极，可以使得像素驱动电路中的存储电容C(即，并联的第一存储电容120和第二存储电容130)设置在发光器件110正对的区域，也即位于发光器件110的发光区且不影响发光器件110的出光效果。这样一来，一方面，由于发光器件110的第一电极111复用为第一存储电容120的第一存储电极121，第二存储电极122与第一存储电极121相对设置，第三存储电极123与第二存储电极122相对设置，且第一存储电极121与第三存储电极123电连接，可以避免发光器件110和第一存储电容120、第二存储电容130之间电连接时产生跨线，从而避免出现串扰风险。再一方面，在保证显示基板1正常显示的情况下，第一存储电容120和第二存储电容130可以不额外占用亚像素S中发光区以外的面积。如此，在亚像素S的面积一定的情况下，发光器件110的发光区可以占用亚像素S中较多的面积，从而提高亚像素S的开口率，以及提升发光器件110的使用寿命。另一方面，由于第一电极111、第二存储电极122和第三存储电极123均为透明电极，因而第二存储电极122和第三存储电极123的面积可以设置的尽可能的大，而且第一存储电容120与第二存储电容130并联，从而可以有效增大像素驱动电路中存储电容C的电容量，以避免显示基板1出现显示画质不均的问题。
当将本公开实施例中的显示基板1应用在8K高像素密度(Pixels Per Inch，PPI)的显示基板中之后，与相关技术中亚像素的平均开口率约为12％相比，该显示基板中亚像素的平均开口率可以提升至约28％左右，从而有效提升了约160％。
像素驱动电路的结构可以根据实际需求选择设置，例如采用图4中所示的3T1C的像素电路；也即，该像素电路可以由三个晶体管T和一个存储电容C构成，其中，三个晶体管分别为第一晶体管T1、第二晶体管T2和第三晶体管T3；存储电容C即为前述一些实施例中的第一存储电容120。当然，像素驱动电路还可以为包括其他数量的晶体管或其他数量的存储电容的结构，本公开实施例对此不作限定。
以下一些实施例以像素驱动电路为3T1C的像素电路为例进行说明。
可选的，单个亚像素S中像素驱动电路的结构如图1、图2和图4所示，像素驱动电路还包括第一晶体管T1，第一晶体管T1为驱动晶体管。如图5所示，第一晶体管T1包括第一栅极141、第一半导体有源图案142和第一源极143。第一半导体有源 图案142包括第一沟道区1421、第一源极区1422和第一漏极区1423，第一源极区1422和第一漏极区1423的导电性大于第一沟道区1421的导电性。第一源极143与第一源极区1422接触。第一源极143与电源线18电连接。电源线18用于给像素驱动电路供电。
请结合图2、图4和图5理解，由于第三存储电极123可以通过对半导体图案进行导体化得到，也即，第三存储电极123可以为经过导体化处理后的半导体图案。基于此，第三存储电极123与第一漏极区1423连接且为一体结构。由于第三存储电极123与第一存储电极121电连接，第一存储电极121又可以复用为发光器件110的第一电极111，因此，第一晶体管T1中无需再制作形成独立的第一漏极，以利用第一漏极与第一电极111电连接。
在制备时，先形成位于第一晶体管T1位置处和第三存储电极123位置处的半导体图案，然后对该半导体图案除第一晶体管T1的第一沟道区1421位置外的其他区域进行导体化。示例的，可以采用离子注入的方式进行导体化，离子可以为硼离子或磷离子。
此外，需要说明的是，对于第一晶体管T1或后续的其他晶体管，源极和漏极分别是指其栅极之外的其他两个电极。按照晶体管中载流子种类的不同，晶体管的源极和漏极可以互换。本公开实施例对此不作限定，仅用于辅助说明晶体管的结构及其相应的电连接关系。
图2和图5中的第一晶体管T1以顶栅型薄膜晶体管为例进行了示意。在此情况下，如图5所示，第一半导体有源图案142设置于第一栅极141靠近衬底10一侧，第一半导体有源图案142与第一栅极141通过第一栅绝缘图案145隔离，第一源极143与第一栅极141之间通过层间绝缘层20隔离。基于此，可在形成第一栅极141后，进行上述的导体化工艺。
可选的，如图5所示，第一栅绝缘图案145与第一栅极141可以同步形成。基于此，第一源极143通过贯穿层间绝缘层20的过孔与第一半导体有源图案142直接接触。
此处，同步形成是指采用同一次构图工艺制作形成，例如光掩膜(Mask)工艺。本公开实施例中涉及的全部的“同步形成”，均可照此理解，但并不仅限于此。
本领域技术人员明白，在位于第一半导体有源图案142与第一栅极141之间的栅绝缘层未图案化的情况下，第一源极143通过贯穿层间绝缘层20和栅绝缘层两层的过孔与第一半导体有源图案142直接接触。
本公开实施例中，在制备第一晶体管T1的第一半导体有源图案142的同时制备第三存储电极123，可以在不额外增加构图工艺的基础上，形成第三存储电极123。
可选的，如图1、图2和图6所示，像素驱动电路还包括第二晶体管T2，第二晶体管T2包括第二栅极151、第二半导体有源图案152、第二源极153和第二漏极154。如图6所示，第二半导体有源图案152包括第二沟道区1521、第二源极区1522和第二漏极区1523。第二源极区1522和第二漏极区1523的导电性大于第二沟道区1521的导电性。第二源极153与第二半导体有源图案152中对应第二源极区1522的部分直接接触，第二漏极154与第二半导体有源图案152中对应第二漏极区1523的部分直接 接触。
可以理解的是，基于上述第一晶体管T1中第一半导体有源图案142的结构，第二晶体管T2中的第二半导体有源图案152也与第一半导体有源图案142类似。在此情况下，第二晶体管T2和第一晶体管T1可同步形成，也即：第二晶体管T2中的第二栅极151与第一晶体管T1中的第一栅极141同步形成；第二晶体管T2中的第二半导体有源图案152与第一晶体管T1中的第一半导体有源图案142同步形成；第二晶体管T2中的第二源极153、第二漏极154与第一晶体管T1中的第一源极143同步形成。
需要说明的是，图2和图6中的第二晶体管T2以顶栅型薄膜晶体管为例进行了示意。在此情况下，第二半导体有源图案152设置于第二栅极151的靠近衬底10一侧，第二半导体有源图案152与第二栅极151通过第二栅绝缘图案156隔离，第二源极153和第二漏极154二者与第二栅极151之间通过层间绝缘层20隔离。
可选的，如图5所示，第二栅绝缘图案156与第二栅极151可以同步形成，基于此，第二源极153和第二漏极154分别通过贯穿层间绝缘层20的过孔与第二半导体有源图案152接触。当然，与第一晶体管T1类似，在位于第二半导体有源图案152与第二栅极151之间的栅绝缘层未图案化的情况下，第二源极153和第二漏极154通过贯穿层间绝缘层20和栅绝缘层两层的过孔与第二半导体有源图案152直接接触。
在此基础上，如图1和图2所示，显示基板1还包括：与像素驱动电路电连接的栅线16和数据线17。栅线16中的一部分复用为第二晶体管T2的第二栅极151，可以有效减小像素驱动电路在亚像素S中占用的面积，提高亚像素的开口率。此外，第二晶体管T2的第二源极153与数据线17电连接。
如图1、图2和图7所示，显示基板1还包括：设置于每个亚像素S中的第一连接电极155。第二晶体管T2的第二漏极154与第一连接电极155电连接，且二者为一体结构。第一连接电极155与第一晶体管T1的第一栅极141、第二存储电极122均电连接。即，通过第一连接电极155可以实现第一晶体管T1与第二晶体管T2、第一存储电容120、第二存储电容130的电连接。
可选的，如图2和图7所示，第一连接电极155与第二存储电极122直接接触，第一连接电极155与第一栅极141通过过孔1483电连接。第一连接电极155与第二存储电极122直接接触，是指：第一连接电极155覆盖第二存储电极122的部分，从而实现二者的搭接。
可选的，如图7所示，显示基板1还包括：设置于每个亚像素S中的第二连接电极148。第一存储电极121与第三存储电极123通过第二连接电极148电连接。例如图7中所示，在显示基板1包括层间绝缘层20、钝化层50和平坦层70的情况下，第二连接电极148可通过贯穿层间绝缘层20的过孔1481与第三存储电极123直接接触，第二连接电极148通过贯穿平坦层70和钝化层50两层的过孔1482与第一存储电极121直接接触，可以实现第一存储电极121与第三存储电极123电连接。
在此基础上，可选的，第二连接电极148与第一连接电极155同层同材料。
可选的，如图1、图2和图8所示，在像素驱动电路包括第二晶体管T2的情况下，像素驱动电路还包括第三晶体管T3，第三晶体管T3包括第三栅极191、第三半导体有源图案192和第三漏极193。
需要说明的是，图2和图8中的第三晶体管T3以顶栅型薄膜晶体管为例进行示意，在此情况下，第三半导体有源图案192设置于第三栅极191的靠近衬底10一侧，第三半导体有源图案192与第三栅极191通过第三栅绝缘图案195隔离，第三漏极193与第三栅极191之间通过层间绝缘层20隔离。
在第一栅绝缘图案145与第一栅极141同步形成的情况下，如图8所示，第三栅绝缘图案195与第三栅极191同步形成。基于此，第三漏极193通过贯穿层间绝缘层20的过孔与第三半导体有源图案192接触。当然，与第一晶体管T1类似，在栅绝缘层未图案化的情况下，第三漏极193通过贯穿层间绝缘层20和栅绝缘层两层的过孔与第三半导体有源图案192接触。
请结合图1、图2、图4和图8理解，第三半导体有源图案192包括第三沟道区1921、第三源极区1922和第三漏极区1923，第三源极区1922和第三漏极区1923的导电性大于第三沟道区1921的导电性。显示基板1还包括感测信号线40。第三漏极193与第三漏极区1923接触，且第三漏极193与感测信号线40电连接。第三源极区1922与第三存储电极123连接且为一体结构。由于第三存储电极123与第一存储电极121电连接，第一存储电极121又可以复用为发光器件110的第一电极111，因此，第三晶体管T3中无需再制作形成独立的第三源极，以利用第三源极与第一电极111电连接。
当像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第一存储电容120和第二存储电容130时，其等效电路图如图4所。第一存储电容120与第二存储电容130共同构成存储电容C。此时，该像素驱动电路为3T1C驱动电路。基于此，可通过感测信号线40感测第一晶体管T1的参数，进而通过外部方式对第一晶体管T1的阈值电压进行补偿。
在上述基础上，示例的，第一栅极141、第二栅极151、第三栅极191，第一源极143、第二源极153、第二漏极154、第三漏极193以及栅线16、数据线17、感测信号线40、电源线18的材料，可以选自铜(Cu)、铝(Al)、钼(Mo)、钛(Ti)、铬(Cr)和钨(W)的金属单质以及由这些金属单质构成的金属合金中的至少一种。
示例的，第一栅绝缘图案145，第二栅绝缘图案156、第三栅绝缘图案195和层间绝缘层20的材料可以选自氮化硅(SiNx)和二氧化硅(SiO2)等无机氧化物中的一种或多种，且第一栅绝缘图案145，第二栅绝缘图案156、第三栅绝缘图案195和层间绝缘层20可以采用单层结构或多层层叠结构。第一半导体有源图案142、第二半导体有源图案152和第三半导体有源图案192中的材料可以选自透明半导体氧化物，例如铟锌氧化物(IGZO)。
如图1中所示，数据线17、电源线18和感测信号线40沿第一方向延伸。可选的，第一晶体管T1和第三晶体管T3分别位于第一存储电容120的沿第一方向的两侧。
在此基础上，可选的，如图1所示，位于任一行亚像素S中第三晶体管T3的第三栅极191，由距离第三晶体管T3最近的相邻行亚像素S对应的栅线16中的一部分复用构成。从而有利于在多个亚像素S阵列排布的情况下，减小像素驱动电路在亚像素S中占用的面积，以提高亚像素的开口率。
请结合图1理解，本公开实施例中，任一亚像素S中第三晶体管T3的第三栅极 191，与距离该第三晶体管T3最近的相邻行的亚像素S中第二晶体管T2的第二栅极151，可以复用同一条栅线16中的不同部分构成。从而可以减少显示基板1中栅线16的总数量，以简化其制备工艺。
可选的，在第一晶体管T1为顶栅型薄膜晶体管的情况下，如图9、图10和图12所示，显示基板1还包括设置于第一半导体有源图案142的靠近衬底10一侧的金属图案147。沿衬底10的厚度方向，第一半导体有源图案142在衬底10上的正投影位于金属图案147在衬底10上的正投影内。
如图11所示，金属图案147、第一存储电极121与第三存储电极123，三者通过第二连接电极148电连接，第二连接电极148与第一源极143同层同材料。
如图11所示，当显示基板1包括金属图案147时，显示基板1还包括位于金属图案147的远离衬底10一侧，且覆盖金属图案147的缓冲层60。此时，第二连接电极148通过贯穿层间绝缘层20和缓冲层60两层中的过孔1481与金属图案147接触，同时通过该过孔1481与第三存储电极123接触。第一存储电极121通过贯穿平坦层70和钝化层50两层中的过孔1482与第二连接电极148接触。从而实现了金属图案147、第一存储电极121与第三存储电极123的电连接。
上述金属图案147可以防止外界光线入射至第一半导体有源图案142，从而避免外界光线对第一晶体管T1的性能产生不良影响。同时，当显示基板1中设置有金属图案147时，通过使金属图案147与第三存储电极123、第一存储电极121电连接，可以在显示基板1的使用过程中避免在金属图案147处产生寄生电容。
可选的，如图1和图9所示，电源线18、感测信号线40以及数据线17平行且同层设置，有利于简化显示基板1中各信号线的布线设计。
在一些实施例中，如图9所示，每行亚像素中，每相邻的两个亚像素S为一组，每组的两个亚像素之S间设置有两根数据线17。每组亚像素S的一侧设置有一根电源线18，相对的另一侧设置有一根感测信号线40，且电源线18和感测信号线40间隔设置。
针对每行亚像素，位于电源线18的一侧且靠近该电源线18的两个亚像素S中像素驱动电路、以及位于该电源线18的另一侧且靠近该电源线18的两个亚像素S中像素驱动电路，均与该电源线18电连接。
针对每行亚像素，位于感测信号线40的一侧且靠近该感测信号线40的两个亚像素S中像素驱动电路、以及位于该感测信号线40的另一侧且靠近该感测信号线40的两个亚像素S中像素驱动电路，均与该感测信号线40电连接。
在此基础上，可以减少电源线18和感测信号线40的总数量，从而简化显示基板1的制备工艺。
可选的，如图9和图13、图14所示，显示基板1还包括：针对任一根电源线18设置的第一辅助电极181。沿衬底10的厚度方向，第一辅助电极181在衬底10上的正投影位于电源线18在衬底10上的正投影内。第一辅助电极181与电源线18通过多个第一过孔1811电连接。也即，第一辅助电极181与电源线18并联。如此，有利于减小电源线18的等效电阻，从而降低电源线18所传输信号的损耗。
此外，如图9和图13、图15所示，显示基板1还包括：针对任一根感测信号线 40设置的第二辅助电极401。沿衬底10厚度方向，第二辅助电极401在衬底10上的正投影位于感测信号线40在衬底10上的正投影内。第二辅助电极401与感测信号线40通过多个第二过孔4011电连接；也即，第二辅助电极401与感测信号线40并联。如此，有利于减小感测信号线40的等效电阻，从而降低感测信号线40所传输信号的损耗。
在一些示例中，第一辅助电极181、第二辅助电极401与第一栅极141同层同材料。基于此，可以在制备第一栅极141的同时制备第一辅助电极181和第二辅助电极401，从而简化显示基板1的制备工艺。
在一些实施例中，显示基板1还包括设置于每个亚像素S中的滤光单元，以利用滤光单元实现显示基板1的彩色化显示。基于此，可选的，如图6和图11所示，显示基板1还包括：设置于每个亚像素S中第一存储电极121与第二存储电极122之间的滤光单元30，以及设置于滤光单元30的靠近第一存储电极121的一侧平坦层70。
此处，可选的，滤光单元30为彩色滤光膜。
基于此，可选的，在采用RGB色彩模式显示的显示基板1中，位于红色亚像素中的滤光单元30为红色滤光单元，位于绿色亚像素中的滤光单元30为绿色滤光单元，位于蓝色亚像素中的滤光单元30为蓝色滤光单元。并且，在此情况下，发光器件110中的发光层113发白光，所有亚像素中的发光层113可连为一体整层铺设。
可选的，第一晶体管T1、第二晶体管T2和第三晶体管T3均为顶栅型薄膜晶体管。
本公开实施例提供一种显示基板1的制备方法。如图16所示，该显示基板1的制备方法包括：S10～S20。
S10、如图1和图2所示，在衬底10上的显示区AA内形成位于每个亚像素S中的像素驱动电路。
上述像素驱动电路包括并联的第一存储电容120和第二存储电容130。第一存储电容120包括相对设置的第一存储电极121和第二存储电极122。第二存储电容130包括第二存储电极122以及与第二存储电极122相对设置的第三存储电极123。沿衬底10的厚度方向，第二存储电极122位于第一存储电极121与第三存储电极123之间。第一存储电极121与第三存储电极123电连接，且第一存储电极121位于第二存储电极122的远离衬底10的一侧。
第一存储电极121、第二存储电极122和第三存储电极123均为透明电极。
S20、在衬底10上的每个亚像素S中，形成位于像素驱动电路的远离衬底10一侧的底发光型发光器件。
如图3a和图3b所示，发光器件110包括第一电极111。如图7所示，第一电极111与像素驱动电路连接。并且，第一电极111由第一存储电极121复用构成。
本公开实施例提供的显示基板1的制备方法所能实现的有益效果，与上述实施例提供的显示基板1所能达到的有益效果相同，在此不做赘述。
可选的，如图1、图2和图5所示，像素驱动电路还包括第一晶体管T1，第一晶体管T1包括第一栅极141、第一半导体有源图案142、第一源极143。第一晶体管T1为驱动晶体管。第一半导体有源图案142包括第一沟道区1421、第一源极区1422和 第一漏极区1423，第一源极区1422和第一漏极区1423的导电性大于第一沟道区1421的导电性。第一源极143与第一源极区1422接触。
S10中，形成像素驱动电路，还包括：在形成第一半导体有源图案142的过程中，同步形成第三存储电极123，使得第三存储电极123与第一漏极区1423连接且为一体结构。
此处，第三存储电极123为经过导体化处理后的半导体图案。由于第三存储电极123与第一存储电极121电连接，第一存储电极121又可以复用为发光器件110的第一电极111，因此，第一晶体管T1中无需再制作形成独立的第一漏极，以利用第一漏极与第一电极111电连接。
在制备时，先形成位于第一晶体管T1位置处和第三存储电极123位置处的半导体图案，然后对该半导体图案除第一晶体管T1的第一沟道区1421位置外的其他区域进行导体化。示例的，可以采用离子注入的方式进行导体化，离子可以为硼离子或磷离子。
可选的，如图1、图2和图6所示，显示基板1还包括：与像素驱动电路电连接的栅线16和数据线17。像素驱动电路还包括第二晶体管T2，第二晶体管T2包括第二栅极151、第二半导体有源图案152、第二源极153和第二漏极154。第二半导体有源图案152包括第二沟道区1521、第二源极区1522和第二漏极区1523，第二源极区1522和第二漏极区1523的导电性大于第二沟道区1521的导电性。第二源极153与第二源极区1522接触，第二漏极154与第二漏极区1523接触。
每个亚像素S对应一条栅线16，该栅线16的一部分可以复用为第二栅极151。如此，显示基板1的制备方法，还包括：在执行S10的过程中，同步形成栅线16和第一栅极141。从而可以简化显示基板1的制备工艺。
如图1、图2和图7所示，显示基板1还包括：设置于每个亚像素S中的第一连接电极155。第二源极153与数据线17电连接，第二漏极154与第一连接电极155电连接，且二者为一体结构。第一连接电极155还与第一栅极141、第二存储电极122均电连接。即，通过第一连接电极155，可以实现第一晶体管T1与第二晶体管T2、第一存储电容120、第二存储电容130的电连接。
显示基板1的制备方法，还包括：同步形成第二半导体有源图案152与第一半导体有源图案142；以及，同步形成第一连接电极155、第二源极153、第二漏极154、数据线17以及第一源极143。从而可以简化显示基板1的制备工艺。
在此基础上，可选的，如图1、图2和图8所示，显示基板1还包括电源线18和感测信号线40。第一源极143与电源线18电连接。像素驱动电路还包括第三晶体管T3，第三晶体管T3包括第三栅极191、第三半导体有源图案192和第三漏极193。第三半导体有源图案192包括第三沟道区1921、第三源极区1922和第三漏极区1923，第三源极区1922和第三漏极区1923的导电性大于第三沟道区1921的导电性。第三源极区1922与第三存储电极123连接且为一体结构。第三漏极1923与第三漏极区1923接触，且第三漏极1923与感测信号线40电连接。
第一晶体管T1和第三晶体管T3分别位于第一存储电容120的两侧。位于任一行亚像素S中的第三晶体管T3的第三栅极191，由距离第三晶体管T3最近的相邻行亚 像素S对应的栅线16的一部分复用构成。
显示基板1的制备方法，还包括：同步形成第三半导体有源图案192与第二半导体有源图案152；同步形成第三漏极193、电源线18、感测信号线40与数据线17。从而可以进一步简化显示基板1的制备工艺。
可选的，如图9～图12所示，在显示基板1还包括金属图案147的情况下，显示基板1的制备方法还包括：
在形成像素驱动电路，即执行S10之前，在衬底10上形成金属图案147，以使得在形成像素驱动电路之后，沿衬底的厚度方向，第一半导体有源图案142在衬底10上的正投影位于金属图案147在衬底10上的正投影内。
金属图案147的结构和功能如前一些实施例中所述，此处不再详述。
可选的，请参阅图7和图11，在显示基板1还包括第二连接电极148的情况下，显示基板1的制备方法，还包括：在形成第一源极143的过程中，同步形成第二连接电极148，使得第二连接电极148与金属图案147、第一存储电极121、第三存储电极123均电连接。
如图11所示，当显示基板1包括金属图案147时，显示基板1还包括位于金属图案147远离衬底一侧，且覆盖金属图案147的缓冲层60。此时，第二连接电极148通过贯穿层间绝缘层20和缓冲层60两层的过孔1481与金属图案147直接接触，同时通过该过孔1481与第三存储电极123直接接触。第一存储电极121通过贯穿平坦层70和钝化层50两层的过孔1482与第二连接电极148直接接触，从而实现金属图案147与第一存储电极121、第三存储电极123的电连接。
在显示基板1包括第一连接电极155和第二连接电极148的情况下，为实现第一连接电极155与第一栅极141、第二存储电极122均电连接，第二连接电极148与金属图案147、第一存储电极121、第三存储电极123均电连接，第一连接电极155和第二连接电极148的制备方式如下所述。
如图17中的(a)所示，在形成有金属图案147、缓冲层60、第一半导体有源图案142、第三存储电极123、第一栅极141的衬底10上，形成层间绝缘薄膜201，之后，形成第二存储电极122。
然后，如图17中的(b)所示，对层间绝缘薄膜201执行构图工艺，形成贯穿层间绝缘薄膜201的过孔1483，以使得第一栅极141的部分于该过孔1483中裸露；并同步形成贯穿层间绝缘薄膜201和缓冲层60的过孔1481，以使得金属图案147和第三存储电极123的部分均于该过孔1481中裸露露出。通过构图工艺形成过孔后的层间绝缘薄膜为层间绝缘层20。
之后，如图17中的(c)所示，同步形成第一连接电极155和第二连接电极148。第一连接电极155搭接在第二存储电极122上，与第二存储电极122直接接触，同时第一连接电极155通过贯穿层间绝缘层20的过孔1483与第一栅极141电连接。此外，第二连接电极148通过贯穿层间绝缘层20和缓冲层60两层的过孔1481与金属图案147以及第三存储电极123均电连接。
可以理解的是，在形成第一连接电极155和第二连接电极148的过程中，还可以同步形成第二源极153、第二漏极154、数据线17以及第一源极143等。
在此基础上，如图17中的(d)所示，依次形成钝化层50和位于亚像素中的滤光单元30、平坦层70，钝化层50和平坦层70包括贯穿该两层的过孔1482。第二连接电极148的部分于该过孔1482中裸露。
之后，如图17中的(e)所示，形成第一存储电极121(或第一电极111)，使得该第一存储电极121通过贯穿钝化层50和平坦层70两层的过孔1482与第二连接电极148电连接。然后依次形成像素界定层80、发光层113和第二电极112等。
金属图案147可以防止外界光线入射至第一半导体有源图案142，影响第一晶体管T1的性能。同时，当显示基板1中设置有金属图案147时，通过使金属图案147与第一存储电极121、第三存储电极123电连接，可以避免在显示基板1的使用过程中，在金属图案147处产生寄生电容。
本公开实施例提供一种显示装置。例如图18中所示，该显示装置1000包括上述任一些实施例中的显示基板1。本公开实施例提供的显示装置1000所能实现的有益效果，与上述实施例提供的显示基板1所能达到的有益效果相同，在此不做赘述。
在一些实施例中，显示装置1000为OLED显示基板、OLED显示器、OLED电视机、手机、平板电脑、笔记本电脑、电子纸、数码相框或导航仪等具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示基板，包括：衬底，以及设置于所述衬底上的显示区内且位于每个亚像素中的像素驱动电路与底发光型发光器件；所述发光器件包括与像素驱动电路电连接的第一电极；所述像素驱动电路包括并联的第一存储电容和第二存储电容；
    所述第一存储电容包括：相对设置的第一存储电极和第二存储电极；所述第一电极复用为所述第一存储电极；
    所述第二存储电容包括：所述第二存储电极、和与所述第二存储电极相对设置的第三存储电极；沿所述衬底厚度方向，所述第二存储电极位于第一存储电极与第三存储电极之间；所述第一存储电极与所述第三存储电极电连接；
    所述第一电极、所述第二存储电极和所述第三存储电极均为透明电极。
  2. 根据权利要求1所述的显示基板，还包括：电源线；
    所述像素驱动电路还包括第一晶体管，所述第一晶体管包括第一栅极、第一半导体有源图案和第一源极；所述第一晶体管为驱动晶体管；
    所述第一半导体有源图案包括第一沟道区、第一源极区和第一漏极区，所述第一源极区和所述第一漏极区的导电性大于所述第一沟道区的导电性；所述第一源极与所述第一源极区接触；所述第一源极与所述电源线电连接；
    所述第三存储电极为经过导体化处理后的半导体图案，所述第三存储电极与所述第一漏极区连接且为一体结构。
  3. 根据权利要求2所述的显示基板，还包括：
    与所述像素驱动电路电连接的栅线和数据线；
    以及，设置于所述每个亚像素中的第一连接电极；
    其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极、第二半导体有源图案、第二源极和第二漏极；
    所述栅线中的一部分复用为所述第二栅极；
    所述第二源极与所述数据线电连接；
    所述第二漏极与所述第一连接电极为一体结构；
    所述第一连接电极与所述第一栅极、所述第二存储电极均电连接。
  4. 根据权利要求3所述的显示基板，其中，所述第一连接电极与所述第二存储电极直接接触，所述第一连接电极与所述第一栅极通过过孔电连接。
  5. 根据权利要求3所述的显示基板，还包括：与所述像素驱动电路电连接的感测信号线；
    其中，所述像素驱动电路还包括第三晶体管；所述第一晶体管和所述第三晶体管分别位于所述第一存储电容的两侧；
    所述第三晶体管包括第三栅极、第三半导体有源图案和第三漏极；其中，所述第三半导体有源图案包括第三沟道区、第三源极区和第三漏极区，所述第三源极区和所述第三漏极区的导电性大于所述第三沟道区的导电性；所述第三源极区与所述第三存储电极连接且为一体结构；所述第三漏极与所述第三漏极区接触，且所述第三漏极与所述感测信号线电连接。
  6. 根据权利要求5所述的显示基板，其中，位于任一行亚像素中的所述第三晶体管的所述第三栅极，由距离所述第三晶体管最近的相邻行亚像素对应的所述栅线的一部分复用构成。
  7. 根据权利要求5所述的显示基板，其中，所述电源线、所述感测信号线以及所述数据线平行且同层设置；
    每行所述亚像素中，每相邻的两个所述亚像素为一组，每组的两个所述亚像素之间设置有两根所述数据线；每组所述亚像素的一侧设置有一根所述电源线，相对的另一侧设置有一根所述感测信号线，且所述电源线和所述感测信号线间隔设置；
    针对每行所述亚像素，位于所述电源线的一侧且靠近该电源线的两个所述亚像素中的所述像素驱动电路、以及位于该电源线的另一侧且靠近该电源线的两个所述亚像素中的所述像素驱动电路，均与该电源线电连接；
    针对每行所述亚像素，位于所述感测信号线的一侧且靠近该感测信号线的两个所述亚像素中的所述像素驱动电路、以及位于该感测信号线的另一侧且靠近该感测信号线的两个所述亚像素中的所述像素驱动电路，均与该感测信号线电连接。
  8. 根据权利要求7所述的显示基板，还包括：针对任一根所述电源线设置的第一辅助电极，以及针对任一根所述感测信号线设置的第二辅助电极；
    沿所述衬底的厚度方向，所述第一辅助电极在所述衬底上的正投影位于所述电源线在所述衬底上的正投影内；所述第一辅助电极与所述电源线通过多个第一过孔电连接；
    沿所述衬底的厚度方向，所述第二辅助电极在所述衬底上的正投影位于所述感测信号线在所述衬底上的正投影内；所述第二辅助电极与所述感测信号线通过多个第二过孔电连接；
    所述第一辅助电极、所述第二辅助电极与所述第一栅极同层同材料。
  9. 根据权利要求1所述的显示基板，还包括：
    设置于每个亚像素中所述第一存储电极与所述第二存储电极之间的滤光单元；
    以及，设置于所述滤光单元的靠近所述第一存储电极的一侧的平坦层。
  10. 根据权利要求2～9中任一项所述的显示基板，其中，
    所述第一晶体管为顶栅型薄膜晶体管；
    所述显示基板，还包括：设置于所述第一半导体有源图案的靠近所述衬底的一侧的金属图案；沿所述衬底的厚度方向，所述第一半导体有源图案在所述衬底上的正投影位于所述金属图案在所述衬底上的正投影内；
    所述显示基板，还包括：设置于所述每个亚像素中的第二连接电极；所述金属图案、所述第一存储电极与所述第三存储电极，三者通过第二连接电极电连接，所述第二连接电极与所述第一源极同层同材料。
  11. 一种显示基板的制备方法，包括：
    在衬底上的显示区内形成位于每个亚像素中的像素驱动电路；所述像素驱动电路包括并联的第一存储电容和第二存储电容；所述第一存储电容包括相对设置的第一存储电极和第二存储电极，所述第二存储电容包括所述第二存储电极和与所述第二存储电极相对设置的第三存储电极；其中，沿所述衬底的厚度方向，所述第二存储电极位于所述第一存储电极与所述第三存储电极之间；所述第一存储电极与所述第三存储电极电连接，且所述第一存储电极位于所述第二存储电极的远离所述衬底的一侧；所述第一存储电极、所述第二存储电极和所述第三存储电极均为透明电极；
    在所述衬底上的每个所述亚像素中，形成位于所述像素驱动电路的远离所述衬底一侧的底发光型发光器件；所述发光器件包括与所述像素驱动电路电连接的第一电极，所述第一电极由所述第一存储电极复用构成。
  12. 根据权利要求11所述的显示基板的制备方法，其中，所述像素驱动电路还包括第一晶体管，所述第一晶体管为驱动晶体管；所述第一晶体管包括第一栅极、第一半导体有源图案、第一源极；所述第一半导体有源图案包括第一沟道区、第一源极区和第一漏极区，所述第一源极区和所述第一漏极区的导电性大于所述第一沟道区的导 电性；所述第一源极与所述第一源极区接触；
    形成所述像素驱动电路，还包括：
    在形成所述第一半导体有源图案的过程中，同步形成所述第三存储电极，使得所述第三存储电极与所述第一漏极区连接且为一体结构。
  13. 根据权利要求12所述的显示基板的制备方法，其中，
    所述显示基板还包括：与所述像素驱动电路电连接的栅线和数据线，以及设置于所述每个亚像素中的第一连接电极；
    所述像素驱动电路还包括第二晶体管，所述第二晶体管包括第二栅极、第二半导体有源图案、第二源极和第二漏极；所述第二半导体有源图案包括第二沟道区、第二源极区和第二漏极区，所述第二源极区和所述第二漏极区的导电性大于所述第二沟道区的导电性；所述第二源极与所述第二源极区接触，所述第二漏极与所述第二漏极区接触；
    其中，所述栅线中的一部分复用为所述第二栅极；所述显示基板的制备方法，还包括：同步形成所述栅线和所述第一栅极；
    其中，所述第二源极与所述数据线电连接；所述第二漏极与所述第一连接电极电连接，且二者为一体结构；所述第一连接电极还与所述第一栅极、所述第二存储电极均电连接；所述显示基板的制备方法，还包括：同步形成所述第二半导体有源图案与所述第一半导体有源图案；同步形成所述第一连接电极、所述第二源极、所述第二漏极、所述数据线以及所述第一源极。
  14. 根据权利要求13所述的显示基板的制备方法，其中，所述显示基板还包括与所述像素驱动电路电连接的电源线和感测信号线；所述第一源极与所述电源线电连接；所述像素驱动电路还包括第三晶体管，所述第三晶体管包括第三栅极、第三半导体有源图案和第三漏极；所述第三半导体有源图案包括第三沟道区、第三源极区和第三漏极区，所述第三源极区和所述第三漏极区的导电性大于所述第三沟道区的导电性；所述第三源极区与所述第三存储电极连接且为一体结构；所述第三漏极与所述第三漏极区接触，且所述第三漏极与所述感测信号线电连接；
    所述第一晶体管和所述第三晶体管分别位于所述第一存储电容的两侧；位于任一行亚像素中的所述第三晶体管的所述第三栅极，由距离所述第三晶体管最近的相邻行亚像素对应的所述栅线的一部分复用构成；
    所述显示基板的制备方法，还包括：
    同步形成所述第三半导体有源图案与所述第二半导体有源图案；
    同步形成所述第三漏极、所述电源线、所述感测信号线与所述数据线。
  15. 根据权利要求13所述的显示基板的制备方法，还包括：
    在形成所述像素驱动电路之前，在所述衬底上形成金属图案，以使得在形成所述像素驱动电路之后，沿所述衬底的厚度方向，所述第一半导体有源图案在所述衬底上的正投影位于所述金属图案在所述衬底上的正投影内。
  16. 根据权利要求15所述的显示基板的制备方法，其中，所述显示基板还包括：设置于所述每个亚像素中的第二连接电极；
    所述显示基板的制备方法，还包括：在形成所述第一源极的过程中，同步形成所述第二连接电极，使得所述第二连接电极与所述金属图案、所述第一存储电极和所述第三存储电极均电连接。
  17. 一种显示装置，包括如权利要求1-10中任一项所述的显示基板。
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CN108550553A (zh) * 2018-06-06 2018-09-18 京东方科技集团股份有限公司 一种薄膜晶体管及制作方法、显示装置
CN208738252U (zh) * 2018-09-07 2019-04-12 北京京东方技术开发有限公司 像素结构以及阵列基板
CN110783490A (zh) * 2019-11-13 2020-02-11 合肥京东方卓印科技有限公司 显示面板及其制备方法
CN110752247A (zh) * 2019-11-19 2020-02-04 合肥京东方卓印科技有限公司 显示面板及其制备方法
CN210467845U (zh) * 2019-11-19 2020-05-05 合肥京东方卓印科技有限公司 显示面板

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