WO2021196605A1 - 集成启动管、采样管和电阻的高压超结dmos结构及其制备方法 - Google Patents

集成启动管、采样管和电阻的高压超结dmos结构及其制备方法 Download PDF

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WO2021196605A1
WO2021196605A1 PCT/CN2020/126045 CN2020126045W WO2021196605A1 WO 2021196605 A1 WO2021196605 A1 WO 2021196605A1 CN 2020126045 W CN2020126045 W CN 2020126045W WO 2021196605 A1 WO2021196605 A1 WO 2021196605A1
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mos tube
tube
sampling
mos
polycrystalline
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French (fr)
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李加洋
胡兴正
陈虞平
刘海波
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南京华瑞微集成电路有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths

Definitions

  • the invention belongs to the field of semiconductor devices, and particularly relates to a DMOS structure and a preparation method thereof.
  • Power integrated circuit refers to an integrated circuit that integrates high-voltage power devices with control circuits, peripheral interface circuits, and protection circuits on the same chip. It is a bridge between the signal processing part and the execution part of the system. Power integration technology must achieve process compatibility between high-voltage devices and low-voltage devices, and in particular, appropriate isolation technology must be selected. In order to control manufacturing costs, the reusability of the process level must also be considered. With the development of electronic system application requirements, power integration technology needs to achieve high and low voltage compatibility, high performance, high efficiency and high reliability on a limited chip area.
  • the power output stage DMOS tube is the core and key of the power integrated circuit.
  • Figure 1 is the plan view of the ordinary DMOS product.
  • the ordinary DMOS product structure there is no start tube, sampling tube and resistance structure.
  • separate current sampling resistors and resistors are usually used.
  • DMOS tube to realize sampling and asynchronous start its circuit conversion efficiency is low, the overall circuit area is large, and the standby loss is high. Such a system cannot meet the development trend of light weight and integration in the electronics industry.
  • the present invention proposes a high-voltage super junction DMOS structure integrating a start tube, a sampling tube, and a resistor, and a preparation method thereof.
  • the high-voltage super-junction DMOS structure that integrates a start tube, a sampling tube, and a resistor includes a main MOS tube, a start MOS tube, a sampling MOS tube, and a poly resistor.
  • the drains of the main MOS tube, the start MOS tube, and the sampling MOS tube are connected to At the same time, the gate of the sampling MOS tube is connected to the gate of the main MOS tube, and the gate of the start-up MOS tube is connected to the drain of the start-up MOS tube via the polyresistor; each MOS tube is alternately arranged by the N column and the P column to form a super Junction structure; an isolation structure is provided between two adjacent MOS tubes; the isolation structure is that the two ends of the P pillar of the cell region of each MOS tube are respectively connected to the top corners of the isosceles triangle injection window, and two adjacent MOS tubes There is a distance d between the isosceles triangle injection windows connected to the P pillars of the cell
  • the apex angle of the isosceles triangle injection window is less than 30°; the width of each side of the isosceles triangle injection window is smaller than the width of the P pillar; the spacing d is equal to the spacing between adjacent P pillars.
  • the method for preparing the above-mentioned high-voltage super-junction DMOS structure includes the following steps:
  • the substrate adopts the N-type ⁇ 100> crystal orientation, doped with arsenic or antimony, and a layer of epitaxial material with a thickness of 5um-10um is grown on the substrate in advance, and the resistivity of the epitaxial material is less than The resistivity of the epitaxial material grown subsequently;
  • Polycrystalline resistance is formed by polycrystalline implantation, photolithography, and etching. This step does not use polycrystalline doping technology
  • the gate area and source area of each MOS tube are formed by aluminum sputtering, photolithography, and etching;
  • the resistivity of the epitaxial material grown in step (1) is 0.4-2 ⁇ /cm; the resistivity of the epitaxial material grown in step (2) is 0.5-5 ⁇ /cm.
  • step (2) the implanted element is boron, and the implanted dose is 4E12 ⁇ 2E13; in step (3), the energy of Ring implantation is 110Kev ⁇ 180Kev, the implanted element is boron, and the implanted The dose is 5E12 ⁇ 2E13; in step (7), the energy of polycrystalline implantation is 20Kev-40Kev, the element of polycrystalline implantation is boron, and the dose of polycrystalline implantation is 1E14 ⁇ 1E15; in step (8), Pbody The implanted energy is 60KeV ⁇ 120Kev, the implanted element is boron, and the implanted dose is determined according to the threshold voltage; in step (9), the NSD implanted energy is 120Kev-160Kev, the implanted element is phosphorus, and the implanted dose is 5E15 ⁇ 1E16.
  • the strip width of the polycrystalline resistor is 0.8um-2.5um, and the resistance value of the polycrystalline resistor is 8M ⁇ -50M ⁇ ; in step (11), the thickness of the sputtered aluminum is 4um.
  • the medium is BPSG, and the thickness of the deposition medium is 11000 angstroms.
  • step (11) and step (12) through passivation layer deposition, photolithography, and etching, the main MOS tube and the opening area of the start MOS tube gate and source and the sampling MOS tube source are formed. Opening area.
  • the passivation layer is silicon nitride, and the thickness of the deposited passivation layer is 7000-12000 angstroms.
  • the present invention integrates sampling and startup functions and power DMOS to improve the integration of the circuit, and at the same time can reduce the startup loss and current sampling loss in the circuit, thereby reducing standby power consumption and improving energy conversion efficiency;
  • the present invention utilizes the excellent conductivity characteristics of high-voltage super-junction DMOS, compared with ordinary DMOS, the chip area is reduced by more than 70%, and the chip cost is greatly reduced;
  • Figure 1 is a plan view of ordinary DMOS products
  • Figure 2 is a connection diagram of the DMOS circuit of the present invention.
  • Figure 3 is a schematic diagram of the isolation structure of the present invention.
  • Figure 4 is a schematic diagram of P column injection in the preparation method of the present invention.
  • Fig. 5 is a schematic diagram of Ring injection in the preparation method of the present invention.
  • Fig. 6 is a schematic diagram of the growth field oxygen layer in the preparation method of the present invention.
  • Fig. 7 is a schematic diagram of polycrystalline deposition in the preparation method of the present invention.
  • Fig. 8 is a schematic diagram of Pbody injection and push trap in the preparation method of the present invention.
  • Fig. 9 is a schematic diagram of the NSD injection trap in the preparation method of the present invention.
  • FIG. 10 is a schematic diagram of deposition medium and hole etching in the preparation method of the present invention.
  • Fig. 11 is a schematic diagram of aluminum sputter etching in the preparation method of the present invention.
  • the present invention designs a high-voltage super junction DMOS structure that integrates a start tube, a sampling tube, and a resistor. It includes a main MOS tube, a start MOS tube, a sampling MOS tube, and a polysilicon resistor.
  • the drain of the start MOS tube and the sampling MOS tube are connected together, the gate of the sampling MOS tube is connected to the gate of the main MOS tube, and the gate of the start MOS tube is connected to the drain of the start MOS tube via the poly resistor.
  • Each MOS tube is alternately arranged with N pillars and P pillars to form a super junction structure.
  • An isolation structure is set between two adjacent MOS transistors; the isolation structure is that the two ends of the P pillar of the cell area of each MOS transistor are connected to the top corners of the isosceles triangle injection window, and the original There is a distance d between the isosceles triangle injection windows connected by the P pillars in the cell area, thereby forming an isolation area between two adjacent MOS transistors; in each isolation area, the tops of the P pillars are connected together by Ring injection, Thereby forming a pressure ring.
  • the apex angle of the isosceles triangle injection window is less than 30°; the width of each side of the isosceles triangle injection window is smaller than the width of the P pillar; the distance d is between the adjacent P pillar The spacing between the two is equal.
  • the present invention also proposes a method for preparing the high-voltage super-junction DMOS structure for the above-mentioned integrated start tube, sampling tube and resistor, and the steps are as follows:
  • Step 1 Substrate preparation: The substrate adopts N-type ⁇ 100> crystal orientation, doped with arsenic or antimony, and a layer of epitaxial material with a thickness of 5um-10um is grown on the substrate in advance, and the resistivity of the epitaxial material is low The resistivity of the epitaxial material grown later. Preferably, the resistivity of the epitaxial material grown in this step is 0.4-2 ⁇ /cm. Through this step, the reverse expansion of the doped elements of the substrate under high temperature can be effectively reduced, and the on-resistance can be further reduced at the same time.
  • Step 2 Form P pillars: continue to grow a layer of epitaxial material with a thickness of 3-15um on the epitaxial material grown in step 1, after photolithography and n (n ⁇ 1) injections of different energy to form N pillars and P pillars
  • the alternately arranged super junction structure obtains the primary cell regions of the main MOS tube, the start MOS tube, and the sampling MOS tube.
  • the resistivity of the epitaxial material grown in this step is 0.5-5 ⁇ /cm; the implanted element is boron, and the implanted dose is 4E12-2E13. The more the injection times, the smoother the P-pillar boundary formed, the higher the pressure division efficiency, and the smaller the cell size.
  • Step 3 Form Ring ring and isolation region: continue to grow a layer of epitaxial material with a thickness of 2-3um on the epitaxial material grown in step 2, the resistivity of the epitaxial material is the same as the resistivity of the N column; by Ring lithography, Expose the voltage-resistant ring implantation area and the isolation area between the MOS tubes, and then Ring implantation.
  • the implanted energy is 110Kev ⁇ 180Kev
  • the implanted element is boron
  • the implanted dose is 5E12 ⁇ 2E13.
  • the energy of Ring implantation is 110Kev-180Kev
  • the implanted element is boron element
  • the implanted dose is 5E12-2E13.
  • the top of the P-pillar is connected in the terminal area to form a gradually varying withstand voltage structure to improve the withstand voltage efficiency of the terminal.
  • the isolation area of the main MOS tube, sampling tube and start tube is formed, so that the main MOS tube, sampling tube, and start tube are isolated from each other and can work independently.
  • the structure corresponding to this step is shown in Figure 5.
  • Step 4 Push the well P pillar and Ring ring to grow a field oxygen layer.
  • the temperature of the trap is 1150° C.
  • the time of the trap is 60 to 300 minutes
  • the thickness of the field oxygen layer to be grown is 12000 to 18000 angstroms.
  • the structure corresponding to this step is shown in Figure 6.
  • Step 5 Open the active area of each MOS transistor by photolithography, and remove the oxide layer on the surface of the active area by wet etching.
  • Step 6 A gate oxide layer is grown on the field oxide layer and the active area of each MOS transistor, and polycrystalline is deposited on the gate oxide layer.
  • the thickness of the grown gate oxide layer is 700-1200 angstroms
  • the growth temperature is 900-1000° C.
  • the thickness of the deposited polycrystal is 6000-8000 angstroms.
  • Step 7 Form polycrystalline resistors by polycrystalline implantation, photolithography, and etching. This step does not use a polycrystalline doping process.
  • the energy of polycrystalline implantation is 20Kev-40Kev
  • the element of polycrystalline implantation is boron element
  • the dose of polycrystalline implantation is 1E14 ⁇ 1E15
  • the width of the polycrystalline resistor is 0.8um-2.5um
  • the resistance of the polycrystalline resistor is 0.8um-2.5um.
  • the value is 8M ⁇ -50M ⁇ .
  • Step 8 Perform Pbody implantation and annealing in the area where there is no polycrystalline and field oxygen barrier.
  • the energy of the Pbody implantation is 60KeV-120Kev
  • the implanted element is boron
  • the implanted dose is determined according to the threshold voltage, usually 1E13-8E13.
  • the structure corresponding to this step is shown in Figure 8.
  • Step 9 In the Pbody area, through NSD lithography, implantation, and well push, the source regions of each MOS transistor are formed.
  • the energy of the NSD implantation is 120Kev-160Kev
  • the implanted element is phosphorus
  • the implanted dose is 5E15-1E16
  • the temperature of the NSD trap is 950°C
  • the time of the trap is 25 minutes.
  • the structure corresponding to this step is shown in Figure 9.
  • Step 10 Depositing a dielectric on the field oxygen layer, polycrystalline and each MOS transistor source region, and etching contact holes on the dielectric.
  • the medium is BPSG (borophosphosilicate glass), and the thickness of the deposition medium is 11000 angstroms. The structure corresponding to this step is shown in Figure 10.
  • Step 11 On the medium and in the contact hole, the gate region and the source region of each MOS tube are formed by aluminum sputtering, photolithography, and etching. Preferably, the thickness of sputtered aluminum is 4um. The structure corresponding to this step is shown in Figure 11.
  • Step 12 Through passivation layer deposition, photolithography, and etching, the opening regions of the gate and source of the main MOS transistor and the start MOS tube and the opening regions of the source of the sampling MOS tube are formed.
  • the passivation layer is silicon nitride, and the thickness of the deposited passivation layer is 7000-12000 angstroms.
  • This step is an optional operation item, which can be operated or not.
  • Step 13 thin the back of the substrate, and then evaporate the Ti-Ni-Ag alloy on the back of the substrate.

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Abstract

本发明公开了集成启动管、采样管和电阻的高压超结DMOS结构。主MOS管、启动MOS管和采样MOS管的漏极连接在一起，采样MOS管的栅极连接主MOS管的栅极，启动MOS管的栅极经多晶电阻与启动MOS管的漏极连接；各MOS管通过N柱与P柱交替排列形成超结结构；相邻两个MOS管之间设置隔离结构，在每个隔离区，通过Ring注入将各P柱的顶端连接在一起，从而形成耐压环。本发明提高了电路的集成度，降低电路中启动损耗和电流采样损耗，从而降低待机功耗，提高能源转换效率。

Description

集成启动管、采样管和电阻的高压超结DMOS结构及其制备方法 技术领域
本发明属于半导体器件领域，特别涉及了一种DMOS结构及其制备方法。
背景技术
功率集成电路是指将高压功率器件与控制电路、外围接口电路及保护电路等集成在同一芯片的集成电路，是系统信号处理部分和执行部分的桥梁。功率集成技术要实现高压器件和低压器件的工艺兼容，尤其要选择合适的隔离技术，为控制制造成本，还必须考虑工艺层次的复用性。随着电子系统应用需求的发展，功率集成技术需要在有限的芯片面积上实现高低压兼容、高性能、高效率与高可靠性。
功率输出级DMOS管是功率集成电路的核心和关键，图1是普通DMOS产品平面图，在普通DMOS产品结构中没有启动管、采样管和电阻结构，在实际应用中通常使用分立的电流采样电阻和DMOS管来实现采样和异步启动，其电路转换效率较低，电路整体面积较大，待机损耗较高，这样的系统无法满足电子行业轻量化和集成化的发展趋势。
发明内容
为了解决上述背景技术提到的技术问题，本发明提出了集成启动管、采样管和电阻的高压超结DMOS结构及其制备方法。
为了实现上述技术目的，本发明的技术方案为：
集成启动管、采样管和电阻的高压超结DMOS结构，包括主MOS管、启动MOS管、采样MOS管和多晶电阻，所述主MOS管、启动MOS管和采样MOS 管的漏极连接在一起，采样MOS管的栅极连接主MOS管的栅极，启动MOS管的栅极经所述多晶电阻与启动MOS管的漏极连接；各MOS管通过N柱与P柱交替排列形成超结结构；相邻两个MOS管之间设置隔离结构；所述隔离结构为，各MOS管的原胞区P柱的两端分别与等腰三角形注入窗口的顶角连接，相邻两个MOS管的原胞区P柱连接的等腰三角形注入窗口之间存在间距d，从而在相邻两个MOS管之间形成隔离区；在每个隔离区，通过Ring注入将各P柱的顶端连接在一起，从而形成耐压环。
进一步地，所述等腰三角形注入窗口的顶角小于30°；所述等腰三角形注入窗口各边的宽度小于P柱的宽度；所述间距d与相邻P柱之间的间距相等。
针对上述高压超结DMOS结构的制备方法，包括以下步骤：
(1)制备衬底：衬底采用N型<100>晶向，掺杂砷元素或锑元素，在衬底上预先生长一层厚度为5um-10um的外延材料，该外延材料的电阻率小于后续生长的外延材料的电阻率；
(2)形成P柱：在步骤(1)生长的外延材料上继续生长一层厚度为3-15um的外延材料，经过光刻和n次不同能量的注入，形成N柱与P柱交替排列的超结结构，得到主MOS管、启动MOS管和采样MOS管的原胞区；其中，n≥1；
(3)形成Ring环和隔离区：在步骤(2)生长的外延材料上继续生长一层厚度为2-3um的外延材料，该外延材料的电阻率与N柱的电阻率相同；通过Ring光刻，将耐压环注入区以及各MOS管之间的隔离区曝光出来，然后Ring注入，注入的能量为110Kev～180Kev，注入的元素为硼元素，注入的剂量为5E12～2E13；
(4)推阱P柱和Ring环，生长场氧层；
(5)通过光刻将各MOS管的有源区打开，并通过湿法腐蚀去除有源区表面的氧化层；
(6)在场氧层和各MOS管有源区上生长栅氧层，在栅氧层上沉积多晶；
(7)通过多晶注入、光刻、腐蚀，形成多晶电阻，此步骤不采用多晶掺杂工艺；
(8)在没有多晶和场氧阻挡的区域，进行Pbody注入和退火；
(9)在Pbody区域，通过NSD光刻、注入、推阱，形成各MOS管的源区；
(10)在场氧层、多晶和各MOS管源区上沉积介质，并在介质上刻蚀出接触孔；
(11)在介质上和接触孔内，通过铝溅射、光刻、腐蚀，形成各MOS管的栅区和源区；
(12)减薄衬底背面，再在衬底背面蒸发Ti-Ni-Ag合金。
进一步地，步骤(1)中生长的外延材料的电阻率为0.4-2Ω/cm；步骤(2)中生长的外延材料的电阻率为0.5-5Ω/cm。
进一步地，在步骤(2)中，注入的元素为硼元素，注入的剂量为4E12～2E13；在步骤(3)中，Ring注入的能量为110Kev～180Kev，注入的元素为硼元素，注入的剂量为5E12～2E13；在步骤(7)中，多晶注入的能量为20Kev-40Kev，多晶注入的元素为硼元素，多晶注入的剂量为1E14～1E15；在步骤(8)中，Pbody注入的能量为60KeV～120Kev，注入的元素为硼元素，注入的剂量根据阈值电压确定；在步骤(9)中，NSD注入的能量为120Kev-160Kev，注入的元素为磷，注入的剂量为5E15～1E16。
进一步地，在步骤(4)中，推阱的温度为1150℃，推阱的时间为60～300分钟，生长的场氧层的厚度为12000～18000埃；在步骤(6)中，生长的栅氧层的厚度为700-1200埃，生长的温度为900-1000℃，沉积多晶的厚度为6000-8000埃；在步骤(9)中，NSD推阱的温度为950℃，推阱的时间为25分钟。
进一步地，多晶电阻的条宽为0.8um-2.5um，多晶电阻的阻值为8MΩ-50MΩ；在步骤(11)中，溅射铝的厚度为4um。
进一步地，在步骤(10)中，所述介质为BPSG，沉积介质的厚度为11000埃。
进一步地，在步骤(11)与步骤(12)之间，通过钝化层沉积、光刻、腐蚀，形成主MOS管和启动MOS管栅极和源极的开口区以及采样MOS管源极的开口区。
进一步地，所述钝化层为氮化硅，沉积钝化层的厚度为7000-12000埃。
采用上述技术方案带来的有益效果：
(1)本发明将采样、启动功能和功率DMOS集成，提高电路的集成度，同时可以降低电路中启动损耗和电流采样损耗，从而降低待机功耗，提高能源转换效率；
(2)本发明利用高压超结DMOS优异的导电特性，相较于普通DMOS，芯片面积缩小70％以上，大幅度降低芯片成本；
(3)本发明集成启动管、采样管、电阻的工艺和超结DMOS工艺兼容，降低成本。
附图说明
图1是普通DMOS产品平面图；
图2是本发明DMOS电路连接图；
图3是本发明中隔离结构的示意图；
图4是本发明制备方法中P柱注入示意图；
图5是本发明制备方法中Ring注入示意图；
图6是本发明制备方法中生长场氧层示意图；
图7是本发明制备方法中沉积多晶示意图；
图8是本发明制备方法中Pbody注入推阱示意图；
图9是本发明制备方法中NSD注入推阱示意图；
图10是本发明制备方法中沉积介质和孔刻蚀示意图；
图11是本发明制备方法中铝溅射刻蚀示意图。
具体实施方式
以下将结合附图，对本发明的技术方案进行详细说明。
本发明设计了一种集成启动管、采样管和电阻的高压超结DMOS结构，包括主MOS管、启动MOS管、采样MOS管和多晶电阻，如图2所示，所述主MOS管、启动MOS管和采样MOS管的漏极连接在一起，采样MOS管的栅极连接主MOS管的栅极，启动MOS管的栅极经所述多晶电阻与启动MOS管的漏极连接。
各MOS管通过N柱与P柱交替排列形成超结结构。相邻两个MOS管之间设置隔离结构；所述隔离结构为，各MOS管的原胞区P柱的两端分别与等腰三角形注入窗口的顶角连接，相邻两个MOS管的原胞区P柱连接的等腰三角形注入窗口之间存在间距d，从而在相邻两个MOS管之间形成隔离区；在每个隔离区，通过Ring注入将各P柱的顶端连接在一起，从而形成耐压环。
在本实施例中，优选地，所述等腰三角形注入窗口的顶角小于30°；所述等腰三角形注入窗口各边的宽度小于P柱的宽度；所述间距d与相邻P柱之间的间距相等。
本发明还提出了针对上述集成启动管、采样管和电阻的高压超结DMOS结构的制备方法，其步骤如下：
步骤1、制备衬底：衬底采用N型<100>晶向，掺杂砷元素或锑元素，在衬底上预先生长一层厚度为5um-10um的外延材料，该外延材料的电阻率低于后续生长的外延材料的电阻率。优选地，本步骤中生长的外延材料的电阻率为 0.4-2Ω/cm。通过本步骤，可以有效减少高温下衬底掺杂元素的反扩，同时进一步降低导通电阻。
步骤2、形成P柱：在步骤1生长的外延材料上继续生长一层厚度为3-15um的外延材料，经过光刻和n(n≥1)次不同能量的注入，形成N柱与P柱交替排列的超结结构，得到主MOS管、启动MOS管和采样MOS管的原胞区。优选地，本步骤中生长的外延材料的电阻率为0.5-5Ω/cm；注入的元素为硼元素，注入的剂量为4E12～2E13。注入次数越多，形成的P柱边界越平滑，分压效率更高，原胞尺寸可以做得更小。经过多次“外延生长-P柱光刻注入”，形成深度约为40-70um的P柱，击穿耐压可做到500V～900V，P柱深度越深，可形成的耐压越高。本步骤对应的结构如图4所示。
步骤3、形成Ring环和隔离区：在步骤2生长的外延材料上继续生长一层厚度为2-3um的外延材料，该外延材料的电阻率与N柱的电阻率相同；通过Ring光刻，将耐压环注入区以及各MOS管之间的隔离区曝光出来，然后Ring注入，注入的能量为110Kev～180Kev，注入的元素为硼元素，注入的剂量为5E12～2E13。优选地，Ring注入的能量为110Kev～180Kev，注入的元素为硼元素，注入的剂量为5E12～2E13。在本步骤中，在终端区域将P柱顶部连接起来，形成缓变耐压结构，提高终端的耐压效率。形成主MOS管、采样管及启动管的隔离区，使得主MOS管，采样管，启动管相互隔离，能够独立工作。本步骤对应的结构如图5所示。
步骤4、推阱P柱和Ring环，生长场氧层。优选地，推阱的温度为1150℃，推阱的时间为60～300分钟，生长的场氧层的厚度为12000～18000埃。本步骤对应的结构如图6所示。
步骤5、通过光刻将各MOS管的有源区打开，并通过湿法腐蚀去除有源区表面的氧化层。
步骤6、在场氧层和各MOS管有源区上生长栅氧层，在栅氧层上沉积多晶。优选地，生长的栅氧层的厚度为700-1200埃，生长的温度为900-1000℃，沉积多晶的厚度为6000-8000埃。本步骤对应的结构如图7所示。
步骤7、通过多晶注入、光刻、腐蚀，形成多晶电阻，此步骤不采用多晶掺杂工艺。优选地，多晶注入的能量为20Kev-40Kev，多晶注入的元素为硼元素，多晶注入的剂量为1E14～1E15；多晶电阻的条宽为0.8um-2.5um，多晶电阻的阻值为8MΩ-50MΩ。
步骤8、在没有多晶和场氧阻挡的区域，进行Pbody注入和退火。优选地，Pbody注入的能量为60KeV～120Kev，注入的元素为硼元素，注入的剂量根据阈值电压确定，通常为1E13-8E13。本步骤对应的结构如图8所示。
步骤9、在Pbody区域，通过NSD光刻、注入、推阱，形成各MOS管的源区。优选地，NSD注入的能量为120Kev-160Kev，注入的元素为磷，注入的剂量为5E15～1E16；NSD推阱的温度为950℃，推阱的时间为25分钟。本步骤对应的结构如图9所示。
步骤10、在场氧层、多晶和各MOS管源区上沉积介质，并在介质上刻蚀出接触孔。优选地，介质为BPSG(硼磷硅玻璃)，沉积介质的厚度为11000埃。本步骤对应的结构如图10所示。
步骤11、在介质上和接触孔内，通过铝溅射、光刻、腐蚀，形成各MOS管的栅区和源区。优选地，溅射铝的厚度为4um。本步骤对应的结构如图11所示。
步骤12、通过钝化层沉积、光刻、腐蚀，形成主MOS管和启动MOS管栅极和源极的开口区以及采样MOS管源极的开口区。优选地，钝化层为氮化硅，沉积钝化层的厚度为7000-12000埃。本步骤为可选操作项，可作业也可不作业。
步骤13、减薄衬底背面，再在衬底背面蒸发Ti-Ni-Ag合金。
实施例仅为说明本发明的技术思想，不能以此限定本发明的保护范围，凡是 按照本发明提出的技术思想，在技术方案基础上所做的任何改动，均落入本发明保护范围之内。

Claims (12)

  1. 集成启动管、采样管和电阻的高压超结DMOS结构，包括主MOS管，其特征在于：还包括启动MOS管、采样MOS管和多晶电阻，所述主MOS管、启动MOS管和采样MOS管的漏极连接在一起，采样MOS管的栅极连接主MOS管的栅极，启动MOS管的栅极经所述多晶电阻与启动MOS管的漏极连接；各MOS管通过N柱与P柱交替排列形成超结结构；相邻两个MOS管之间设置隔离结构；所述隔离结构为，各MOS管的原胞区P柱的两端分别与等腰三角形注入窗口的顶角连接，相邻两个MOS管的原胞区P柱连接的等腰三角形注入窗口之间存在间距d，从而在相邻两个MOS管之间形成隔离区；在每个隔离区，通过Ring注入将各P柱的顶端连接在一起，从而形成耐压环。
  2. 根据权利要求1所述集成启动管、采样管和电阻的高压超结DMOS结构，其特征在于：所述等腰三角形注入窗口的顶角小于30°；所述等腰三角形注入窗口各边的宽度小于P柱的宽度；所述间距d与相邻P柱之间的间距相等。
  3. 针对权利要求1所述高压超结DMOS结构的制备方法，其特征在于，包括以下步骤：
    (1)制备衬底：衬底采用N型<100>晶向，掺杂砷元素或锑元素，在衬底上预先生长一层厚度为5um-10um的外延材料，该外延材料的电阻率低于后续生长的外延材料的电阻率；
    (2)形成P柱：在步骤(1)生长的外延材料上继续生长一层厚度为3-15um的外延材料，经过光刻和n次不同能量的注入，形成N柱与P柱交替排列的超结结构，得到主MOS管、启动MOS管和采样MOS管的原胞区；其中，n≥1；
    (3)形成Ring环和隔离区：在步骤(2)生长的外延材料上继续生长一层厚度为2-3um的外延材料，该外延材料的电阻率与N柱的电阻率相同；通过Ring光刻，将耐压环注入区以及各MOS管之间的隔离区曝光出来，然后Ring注入， 注入的能量为110Kev～180Kev，注入的元素为硼元素，注入的剂量为5E12～2E13；
    (4)推阱P柱和Ring环，生长场氧层；
    (5)通过光刻将各MOS管的有源区打开，并通过湿法腐蚀去除有源区表面的氧化层；
    (6)在场氧层和各MOS管有源区上生长栅氧层，在栅氧层上沉积多晶；
    (7)通过多晶注入、光刻、腐蚀，形成多晶电阻，此步骤不采用多晶掺杂工艺；
    (8)在没有多晶和场氧阻挡的区域，进行Pbody注入和退火；
    (9)在Pbody区域，通过NSD光刻、注入、推阱，形成各MOS管的源区；
    (10)在场氧层、多晶和各MOS管源区上沉积介质，并在介质上刻蚀出接触孔；
    (11)在介质上和接触孔内，通过铝溅射、光刻、腐蚀，形成各MOS管的栅区和源区；
    (12)减薄衬底背面，再在衬底背面蒸发Ti-Ni-Ag合金。
  4. 根据权利要求3所述高压超结DMOS结构的制备方法，其特征在于，步骤(1)中生长的外延材料的电阻率为0.4-2Ω/cm；步骤(2)中生长的外延材料的电阻率为0.5-5Ω/cm。
  5. 根据权利要求3所述高压超结DMOS结构的制备方法，其特征在于，在步骤(2)中，注入的元素为硼元素，注入的剂量为4E12～2E13；在步骤(3)中，Ring注入的能量为110Kev～180Kev，注入的元素为硼元素，注入的剂量为5E12～2E13；在步骤(7)中，多晶注入的能量为20Kev-40Kev，多晶注入的元素为硼元素，多晶注入的剂量为1E14～1E15；在步骤(8)中，Pbody注入的能量为60KeV～120Kev，注入的元素为硼元素，注入的剂量根据阈值电压确定；在步骤(9)中，NSD注入的能量为120Kev-160Kev，注入的元素为磷，注入的剂 量为5E15～1E16。
  6. 根据权利要求3所述高压超结DMOS结构的制备方法，其特征在于，在步骤(4)中，推阱的温度为1150℃，推阱的时间为60～300分钟，生长的场氧层的厚度为12000～18000埃；在步骤(6)中，生长的栅氧层的厚度为700-1200埃，生长的温度为900-1000℃，沉积多晶的厚度为6000-8000埃；在步骤(9)中，NSD推阱的温度为950℃，推阱的时间为25分钟。
  7. 根据权利要求3所述高压超结DMOS结构的制备方法，其特征在于，在步骤(7)中，多晶电阻的条宽为0.8um-2.5um；在步骤(11)中，溅射铝的厚度为4um。
  8. 根据权利要求3所述高压超结DMOS结构的制备方法，其特征在于，在步骤(10)中，所述介质为BPSG，沉积介质的厚度为11000埃。
  9. 根据权利要求3所述高压超结DMOS结构的制备方法，其特征在于，在步骤(11)与步骤(12)之间，通过钝化层沉积、光刻、腐蚀，形成主MOS管和启动MOS管栅极和源极的开口区以及采样MOS管源极的开口区。
  10. 根据权利要求9所述高压超结DMOS结构的制备方法，其特征在于，所述钝化层为氮化硅，沉积钝化层的厚度为7000-12000埃。
  11. 集成启动管、采样管和电阻的高压超结DMOS结构，包括主MOS管，其特征在于：还包括启动MOS管、采样MOS管和多晶电阻，所述主MOS管、启动MOS管和采样MOS管的漏极连接在一起，采样MOS管的栅极连接主MOS管的栅极，启动MOS管的栅极经所述多晶电阻与启动MOS管的漏极连接；各MOS管通过N柱与P柱交替排列形成超结结构；相邻两个MOS管之间设置隔离结构。
  12. 根据权利要求11所述的高压超结DMOS结构，其特征在于，所述隔离结构为，各MOS管的原胞区P柱的两端分别与等腰三角形注入窗口的顶角连接， 相邻两个MOS管的原胞区P柱连接的等腰三角形注入窗口之间存在间距d，从而在相邻两个MOS管之间形成隔离区。
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