WO2021193092A1 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
WO2021193092A1
WO2021193092A1 PCT/JP2021/009763 JP2021009763W WO2021193092A1 WO 2021193092 A1 WO2021193092 A1 WO 2021193092A1 JP 2021009763 W JP2021009763 W JP 2021009763W WO 2021193092 A1 WO2021193092 A1 WO 2021193092A1
Authority
WO
WIPO (PCT)
Prior art keywords
build
layer
insulating layer
core
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/009763
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
俊弘 樋渡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to KR1020227031731A priority Critical patent/KR102763739B1/ko
Priority to EP21776416.6A priority patent/EP4132231A4/en
Priority to US17/913,050 priority patent/US12144105B2/en
Priority to CN202180022103.6A priority patent/CN115299185A/zh
Priority to JP2022509905A priority patent/JP7391184B2/ja
Publication of WO2021193092A1 publication Critical patent/WO2021193092A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09336—Signal conductors in same plane as power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • This disclosure relates to a wiring board.
  • Such pads and lands are usually surrounded by a grounding conductor layer at a predetermined interval in order to guard against electromagnetic noise from the outside.
  • the signal pads and lands located near the bonding allowance of the insulating layer are not completely surrounded by the grounding conductor layer, and a part of the signal pads and lands are opened to the bonding allowance of the insulating layer.
  • electromagnetic noise from the outside is not sufficiently guarded and may affect the transmission characteristics.
  • An object of the present disclosure is to provide a wiring board capable of sufficiently guarding electromagnetic noise from the outside while ensuring good adhesion between insulating layers.
  • the wiring board according to the present disclosure includes a core layer having a core insulating layer and a core conductor layer on the upper and lower surfaces of the core insulating layer, a first build-up portion located on the upper surface of the core layer, and a first build-up portion located on the lower surface of the core layer. It includes two build-up portions, a first mounting area located on the upper surface of the first build-up portion, and a second mounting area located on the lower surface of the second build-up portion.
  • the first build-up portion includes at least one first build-up insulating layer and a first build-up conductor layer located on the upper surface of the first build-up insulating layer and connected to the first mounting region.
  • the second build-up portion includes at least one second build-up insulating layer and a second build-up conductor layer located on the lower surface of the second build-up insulating layer and connected to the second mounting region.
  • the second build-up insulating layer has an adhesion margin between the second build-up insulating layers or between the second build-up insulating layer and the core insulating layer in a region having a predetermined width from the outer peripheral edge of the second build-up insulating layer. ..
  • the second build-up conductor layer includes a grounding conductor layer, a first opening, and a signal pad located within the first opening and away from the grounding conductor layer.
  • the grounding conductor layer has an overhanging portion that follows the grounding conductor layer and projects in a direction approaching the outer peripheral edge to surround the signal pad.
  • the mounting structure according to the present disclosure includes the above-mentioned wiring board, electronic components mounted on the above-mentioned wiring board, and an electric board connected to the above-mentioned wiring board.
  • FIG. 5 is a perspective view schematically showing each layer in the region X shown in FIG. 1 with the solder resist removed.
  • 2 is a plan view of the second build-up portion and the core layer viewed from below
  • FIGS. 2A and 2B are plan views of the second build-up portion viewed from below, respectively
  • FIG. 2C is a plan view of the core. It is a plan view which looked at the layer from the bottom.
  • FIG. 1 is a cross-sectional view showing a main part of the wiring board 1 according to the embodiment of the present disclosure.
  • the wiring board 1 according to one embodiment includes a core layer 2, a first build-up unit 31, a second build-up unit 32, and a solder resist 4.
  • the core layer 2 includes a core insulating layer 21 and a core conductor layer 22 located on the upper and lower surfaces of the core insulating layer 21.
  • the core insulating layer 21 is not particularly limited as long as it is made of a material having an insulating property. Examples of the insulating material include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used.
  • the thickness of the core insulating layer 21 is not particularly limited, and is, for example, 200 ⁇ m or more and 800 ⁇ m or less. The thickness of the core insulating layer 21 is thicker than the thickness of the first build-up insulating layer 311 and the second build-up conductor layer 321 described later.
  • the core insulating layer 21 may contain a reinforcing material.
  • the reinforcing material include insulating cloth materials such as glass fiber, glass non-woven fabric, aramid non-woven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination.
  • the core insulating layer 21 may be dispersed with an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.
  • a through-hole conductor 22T is located in the core insulating layer 21 in order to electrically connect the upper and lower surfaces of the core insulating layer 21.
  • the through-hole conductor 22T is located in a through-hole that penetrates the upper and lower surfaces of the core insulating layer 21.
  • the through-hole conductor 22T is formed of, for example, a metal such as copper, specifically, a metal plating such as copper plating.
  • the through-hole conductor 22T connects the core conductor layer 22 located on the upper and lower surfaces of the core insulating layer 21. As shown in FIG. 1, the through-hole conductor 22T may be located only on the inner wall surface of the through-hole, or may be filled in the through-hole.
  • the core conductor layer 22 is formed of, for example, a metal such as copper, specifically, a metal foil such as copper foil or a metal plating such as copper plating.
  • the through-hole conductor 22T includes a ground through-hole conductor, a power supply through-hole conductor, and a signal through-hole conductor, depending on the core conductor layer 22 to be connected. That is, the ground through-hole conductor is connected to the ground conductor, the power supply through-hole conductor is connected to the power supply conductor, and the signal through-hole conductor is connected to the signal conductor.
  • the first build-up portion 31 is located on the upper surface of the core layer 2, and the second build-up portion 32 is located on the lower surface of the core layer 2.
  • the first build-up unit 31 has a structure in which the first build-up insulating layer 311 and the first build-up conductor layer 312 are alternately laminated.
  • a first via hole conductor 31V is located in the first build-up insulating layer 311 in order to electrically connect the upper and lower surfaces of the first build-up insulating layer 311.
  • the first via hole conductor 31V electrically connects the first build-up conductor layers 312 facing each other vertically via the first build-up insulating layer 311 or the first build-up conductor layer 312 and the core conductor layer 22. ing.
  • the second build-up unit 32 has a structure in which the second build-up insulating layer 321 and the second build-up conductor layer 322 are alternately laminated.
  • a second via hole conductor 32V is located in the second build-up insulating layer 321 in order to electrically connect the upper and lower surfaces of the second build-up insulating layer 321.
  • the second via hole conductor 32V electrically connects the second build-up conductor layers 322 facing each other vertically via the second build-up insulating layer 321 or the second build-up conductor layer 322 and the core conductor layer 22. ing.
  • the first via hole conductor 31V and the second via hole conductor 32V are located in the via holes penetrating the upper and lower surfaces of the first build-up insulating layer 311 and the second build-up insulating layer 321 respectively.
  • the first via hole conductor 31V and the second via hole conductor 32V are formed of a metal such as copper, specifically, metal plating such as copper plating.
  • the first via hole conductor 31V and the second via hole conductor 32V may be filled in the via hole as shown in FIG. 1, or may be located only on the inner wall surface of the via hole.
  • the first via hole conductor 31V and the second via hole conductor 32V provide a ground via hole conductor, a power supply via hole conductor, and a signal via hole conductor according to the connected first build-up conductor layer 312 and the second build-up conductor layer 322. Includes. That is, the ground via hole conductor is connected to the ground conductor, the power supply via hole conductor is connected to the power supply conductor, and the signal via hole conductor is connected to the signal conductor.
  • the first build-up insulating layer 311 and the second build-up insulating layer 321 are not particularly limited as long as they are made of a material having an insulating property like the core insulating layer 21.
  • the insulating material include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used.
  • the first build-up conductor layer 312 and the second build-up conductor layer 322 are not particularly limited as long as they are conductors, like the core conductor layer 22.
  • the first build-up conductor layer 312 and the second build-up conductor layer 322 are formed of, for example, a metal such as copper, specifically, a metal foil such as copper foil or a metal plating such as copper plating.
  • each insulating layer may be the same resin or different resins.
  • the core insulating layer 21, the first build-up insulating layer 311 and the second build-up insulating layer 321 may be made of the same resin or different resins.
  • first build-up insulating layer 311 and the second build-up insulating layer 321 may be dispersed with an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. ..
  • the thickness of the first build-up insulating layer 311 and the second build-up insulating layer 321 is not particularly limited, and is, for example, 25 ⁇ m or more and 50 ⁇ m or less. When two or more layers of the first build-up insulating layer 311 and the second build-up insulating layer 321 are present, the respective insulating layers may have the same thickness or may have different thicknesses.
  • the first build-up unit 31 has a first mounting area 31a on its surface.
  • the first mounting region 31a includes a plurality of first pads P1 formed of a part of the first build-up conductor layer 312 located in the outermost layer.
  • Electronic components such as semiconductor integrated circuit elements are mounted via solder in the first mounting region 31a.
  • the electronic component is not limited as long as it is an electronic component generally mounted on a wiring board.
  • Examples of such electronic components include optoelectronic elements in addition to the above-mentioned semiconductor integrated circuit elements.
  • the second build-up unit 32 has a second mounting area 32a on the surface.
  • the second mounting region 32a includes a plurality of second pads P2 formed of a part of the second build-up conductor layer 322 located in the outermost layer.
  • the second pad P2 provided in the second mounting area 32a has a larger diameter than the first pad P1 provided in the first mounting area 31a.
  • An electric board such as a motherboard is mounted in the second mounting area 32a via solder.
  • the above-mentioned electronic components and electric boards are mounted on the wiring board 1 according to the embodiment and used as a mounting structure.
  • solder resist 4 is formed on a part of both surfaces of the wiring board 1 according to the embodiment.
  • the solder resist 4 is made of, for example, an acrylic-modified epoxy resin.
  • the solder resist 4 has, for example, the first build-up conductor layer 312 and the second build-up from the heat when mounting electronic components in the first mounting area 31a and the heat when connecting the second mounting area 32a to a motherboard or the like. It has a function of protecting the conductor layer 322.
  • the second mounting region 32a is located with an adhesive margin 321a located at a predetermined width from the outer peripheral edge of the second build-up insulating layer 321.
  • the second mounting region 32a is surrounded by the bonding allowance 321a.
  • the adhesive margin 321a including the outer peripheral edge of the second build-up insulating layer 321 basically has no conductor or the like, and the second build-up insulating layers 321 or the second build-up insulating layer 321 and the core insulating layer 21 are basically not located. Is in a state of being directly bonded.
  • the adhesive margin 321a is provided to improve the adhesion between the second build-up insulating layers 321 or between the second build-up insulating layer 321 and the core insulating layer 21.
  • the second pad P2 provided in the second mounting area 32a includes a second pad for power supply, a second pad P2S for signal, and a second pad for grounding. As shown in FIG. 1, at least the second signal pad P2S is located in the outermost row (adhesion allowance 321a side) of the second mounting area 32a.
  • FIG. 2 is a perspective view schematically showing each layer in the region X shown in FIG. 1 with the solder resist 4 removed.
  • a part of the grounding conductor layer 322G exists as a band-shaped body 322G'in the adhesive margin 321a of the second build-up insulating layer 321.
  • the band-shaped body 322G' will be described with reference to FIG.
  • FIG. 3 is a plan view of the second build-up portion 32 and the core layer 2 as viewed from below in FIG.
  • FIG. 3A shows the second build-up insulating layer 321 and the second build located in the outermost layer of the second build-up insulating layer 321 and the second build-up conductor layer 322 included in the second build-up unit 32. It is a top view of the up conductor layer 322 seen from the bottom.
  • FIG. 3B shows the second build-up located on the core layer 2 side of the second build-up insulating layer 321 and the second build-up conductor layer 322 included in the second build-up unit 32. It is a top view which looked at the insulation layer 321 and the 2nd build-up conductor layer 322 from the bottom.
  • FIG. 3C is a plan view of the core layer 2 as viewed from below.
  • the grounding conductor layer 322G has an overhanging portion that projects in a direction approaching the outer peripheral edge of the second build-up insulating layer 321 and surrounds the signal second pad P2S. That is, the signal second pad P2S is completely surrounded by the grounding conductor layer 322G including the band-shaped body 322G'.
  • the strip-shaped body 322G' projects only W1 from the outer periphery of the (planar) grounding conductor layer 322G toward the outer peripheral edge of the second build-up insulating layer 321.
  • the band-shaped body 322G' overhangs only W1 and completely surrounds the signal second pad P2S, thereby reducing external noise from entering the signal second pad P2S and preventing a short circuit. It is also advantageous from the viewpoint of reducing capacitance. Further, since the strip-shaped body 322G'is relatively narrow in width unlike the planar layer, it easily bites into the second build-up insulating layer 321 in the bonding allowance 321a. Therefore, it does not affect the adhesion between the second build-up insulating layers 321.
  • the dimension W1 overhanging the strip-shaped body 322G' is not limited as long as it has a width that does not affect short-circuit prevention and adhesion.
  • the dimension W1 may be, for example, 50 ⁇ m or more and 250 ⁇ m or less in order to prevent a short circuit or to have almost no effect on the adhesion between the second build-up insulating layers 321.
  • the average width (other than the width up to the strip 322G') from the outer peripheral edge of the second build-up insulating layer 321 to the outer periphery of the (planar) grounding conductor layer 322G is W2 between the second build-up insulating layers 321. It is not limited as long as it can adhere to each other.
  • W2 may be 300 ⁇ m or more and 500 ⁇ m or less. If W2 is smaller than 300 ⁇ m, the adhesiveness cannot be secured, and if it is larger than 500 ⁇ m, the region for forming the conductor layer may not be secured.
  • the width of the strip-shaped body 322G' which is a part of the grounding conductor layer 322G, is not limited as long as it is strip-shaped.
  • the band-shaped body 322G' may have a width of, for example, 20 ⁇ m or more and 50 ⁇ m or less.
  • the band-shaped body 322G' has such a width, the band-shaped body 322G' is unlikely to become excessively thick, and it is possible to further prevent a decrease in insulation reliability between the upper and lower sides of the second build-up conductor layer 322. .. Further, it is possible to make it less likely to affect the adhesion between the second build-up insulating layers 321.
  • the second build-up insulating layer 321 and the second build-up conductor layer 322, and the core insulating layer 21 and the core conductor layer 22 located in other than the outermost layer are also shown in FIG.
  • a structure similar to the structure shown in 3 (A) is adopted. That is, it has the same structure as that shown in FIG. 3A except that the land 322a'is electrically connected to the second signal pad P2S instead of the second signal pad P2S. ..
  • the land 322a' is also in the second opening 52 formed in the grounding conductor layer 322G located in the same layer as the land 322a', like the signal second pad P2S. It exists through a gap with the grounding conductor layer 322G.
  • the second opening 52 is a signal pad P2S located in the outermost row of the second mounting area 32a on the lower surface of the second build-up insulating layer 321 located on the lower surface of the core insulating layer 21 and the outermost layer. It means an opening in which an electrically connected land 322a'is present.
  • the land 322a' is generally smaller than the second pad P2S for signals. Therefore, the second opening 52 may be smaller than the first opening 51. However, when the second opening 52 is made smaller so that, for example, the second pad P2S for signals having different potentials and the conductor layer 322G for grounding face each other via the second build-up insulating layer 321, the facing portion becomes a capacitor and is static. The capacitance increases and impedance mismatch occurs. Therefore, when the second build-up conductor layer 322 existing in the second build-up portion 32 is viewed through a plane, the second opening 52 is preferably present at a position overlapping the first opening 51. It is preferable that the first opening 51 and the second opening 52 overlap at substantially the same position and with substantially the same size.
  • the wiring board of the present disclosure is not limited to the above-described embodiment.
  • a pair pad is adopted as the second pad P2S for signals.
  • the second pad P2S for signals is not limited to the pair pad, and may be a single pad.
  • the first build-up section 31 and the second build-up section 32 each have two layers, a first build-up insulating layer 311 and a second build-up insulating layer 321.
  • the first build-up insulating layer 311 and the second build-up insulating layer 321 may be present one layer at a time, or three or more layers may be present at a time.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
PCT/JP2021/009763 2020-03-25 2021-03-11 配線基板 Ceased WO2021193092A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020227031731A KR102763739B1 (ko) 2020-03-25 2021-03-11 배선 기판
EP21776416.6A EP4132231A4 (en) 2020-03-25 2021-03-11 PRINTED CIRCUIT BOARD
US17/913,050 US12144105B2 (en) 2020-03-25 2021-03-11 Wiring board
CN202180022103.6A CN115299185A (zh) 2020-03-25 2021-03-11 布线基板
JP2022509905A JP7391184B2 (ja) 2020-03-25 2021-03-11 配線基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-053937 2020-03-25
JP2020053937 2020-03-25

Publications (1)

Publication Number Publication Date
WO2021193092A1 true WO2021193092A1 (ja) 2021-09-30

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Application Number Title Priority Date Filing Date
PCT/JP2021/009763 Ceased WO2021193092A1 (ja) 2020-03-25 2021-03-11 配線基板

Country Status (6)

Country Link
US (1) US12144105B2 (https=)
EP (1) EP4132231A4 (https=)
JP (1) JP7391184B2 (https=)
KR (1) KR102763739B1 (https=)
CN (1) CN115299185A (https=)
WO (1) WO2021193092A1 (https=)

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JP2023175319A (ja) * 2022-05-30 2023-12-12 京セラ株式会社 配線基板

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JP7784351B2 (ja) 2022-05-30 2025-12-11 京セラ株式会社 配線基板

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EP4132231A1 (en) 2023-02-08
US12144105B2 (en) 2024-11-12
KR20220143068A (ko) 2022-10-24
EP4132231A4 (en) 2024-05-01
JP7391184B2 (ja) 2023-12-04
KR102763739B1 (ko) 2025-02-07
US20230217581A1 (en) 2023-07-06
JPWO2021193092A1 (https=) 2021-09-30
CN115299185A (zh) 2022-11-04

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