WO2021182149A1 - Dispositif à semiconducteur et procédé de fabrication de dispositif à semiconducteur - Google Patents

Dispositif à semiconducteur et procédé de fabrication de dispositif à semiconducteur Download PDF

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Publication number
WO2021182149A1
WO2021182149A1 PCT/JP2021/007655 JP2021007655W WO2021182149A1 WO 2021182149 A1 WO2021182149 A1 WO 2021182149A1 JP 2021007655 W JP2021007655 W JP 2021007655W WO 2021182149 A1 WO2021182149 A1 WO 2021182149A1
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Prior art keywords
semiconductor element
semiconductor device
heat
resistant resin
via hole
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PCT/JP2021/007655
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English (en)
Japanese (ja)
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創一 坂元
洋暁 一戸
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三菱電機株式会社
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Priority to JP2022505924A priority Critical patent/JP7162775B2/ja
Publication of WO2021182149A1 publication Critical patent/WO2021182149A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Definitions

  • the present application relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • a semiconductor element such as a silicon semiconductor or a compound semiconductor is mounted on a semiconductor device for high-frequency communication. Electrodes are formed on the back surface of these semiconductor elements by metallizing, and in the case of a general semiconductor device, the back surface electrodes and the package are bonded by a bonding material such as solder or a conductive paste. These bonding materials are a path for releasing the heat generated by the semiconductor element to a cooling mechanism such as a heat sink, and as described above, high thermal conductivity is desired in order to efficiently release the increasingly increasing heat generation.
  • Sintered bonding can be performed at a temperature much lower than the metal melting point by utilizing the particle size effect or the reaction of organic components and solvents that coat the particle surface, and after sintering, it becomes a bulk metal. It is characterized by having similar thermal conductivity and heat resistance. Conventionally, a via hole has been used to electrically connect an electrode pad on the surface of a semiconductor element and a ground (GND).
  • the metal foil of the via hole electrode may be broken or cracked due to the difference in expansion coefficient due to the entry of the bonding material for die bonding of the semiconductor element into the beer hole.
  • the via hole has been covered with a protective film that prevents the solder from getting wet (see, for example, Patent Document 1).
  • the present application discloses a technique for solving the above-mentioned problems, and provides a semiconductor device and a method for manufacturing the semiconductor device, which can prevent the shape around the via hole from being deformed and suppress a decrease in reliability.
  • the purpose is to do.
  • the semiconductor device disclosed in the present application includes a semiconductor element in which a via hole is formed between a front surface electrode and a back surface electrode provided on the opposite side of the front surface electrode, and a heat-resistant resin that covers the back surface electrode side of the via hole.
  • the method for manufacturing a semiconductor device disclosed in the present application includes a step of preparing a semiconductor element in which a via hole is formed between a front surface electrode and a back surface electrode provided on the opposite side of the front surface electrode, and the step of preparing the via hole.
  • the present invention includes a step of joining the semiconductor element and the base material with a bonding layer containing the metal sintered material as a main component by heating the metal sintered material paste.
  • a method for manufacturing a semiconductor device and a semiconductor device that can prevent the shape around the via hole from being deformed and suppress a decrease in reliability can be obtained.
  • FIG. It is a top view which shows the semiconductor device by Embodiment 1.
  • FIG. It is a top view which shows the internal structure of the semiconductor device according to Embodiment 1.
  • FIG. It is sectional drawing of the line AA of FIG.
  • FIG. It is a top view which shows the back surface of the semiconductor element of the semiconductor device according to Embodiment 1.
  • FIG. It is sectional drawing of BB line of FIG.
  • FIG. It is an enlarged sectional view around the via hole of the semiconductor device according to Embodiment 1.
  • FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1.
  • FIG. It is a top view which shows the back surface of the semiconductor element of the semiconductor device by Embodiment 2.
  • FIG. 1 is a plan view showing a semiconductor device according to the first embodiment.
  • FIG. 2 is a plan view showing the internal structure of the semiconductor device according to the first embodiment, and shows the internal structure of the semiconductor device 110 from which the sealing resin 5 is removed from the semiconductor device 110 of FIG.
  • FIG. 3 is a cross-sectional view taken along the line AA of FIG.
  • a semiconductor element 1 made of silicon (Si) is mounted on the upper surface of a heat sink 6 made of copper (Cu) via a bonding layer 15.
  • a plurality of via holes 12 are formed in the semiconductor element 1.
  • the bonding layer 15 is obtained by sintering a metal sintered material paste 15a such as a silver (Ag) sintered material to obtain a metal sintered material.
  • the heat sink 6 and the semiconductor element 1 are connected via a bonding layer 15.
  • a circuit board 2 for matching high-frequency characteristics is connected to a heat sink 6 via a bonding layer 15.
  • the circuit board 2 is, for example, a microwave integrated circuit (MIC) substrate in which a thin film pattern is processed on a ceramic substrate.
  • the electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected by a bonding wire 3.
  • the electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected to the reed 4 by the bonding wire 3, respectively.
  • the electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected to an external substrate (not shown) via bonding wires 3 and leads 4, respectively.
  • the semiconductor element 1 and the circuit board 2 are covered with, for example, a sealing resin 5 by a transfer mold in order to isolate from the influence of external moisture, contamination, heat, electromagnetic field, etc. and to secure the insulating property.
  • FIG. 4A is a plan view showing the back surface of the semiconductor element of the semiconductor device according to the first embodiment. Further, FIG. 4B is a cross-sectional view taken along the line BB of FIG.
  • a conductive layer 14 such as a gold (Au) plating layer is formed on the back surface of the semiconductor element 1 and the surface layer of the via hole 12.
  • the electrode pad 7 and the heat sink 6 are connected by a conductive layer 14 formed on the surface layer of the via hole 12.
  • the conductive layer 14 is formed by subjecting the entire back surface of the semiconductor element 1 to, for example, gold (Au) plating, and forming an Au layer inside the via hole 12 which is an opening.
  • the heat sink 6 and the conductive layer 14 such as the gold (Au) plating layer formed on the back surface of the semiconductor element 1 are connected via the bonding layer 15.
  • the solder filled inside the via hole crawls up to the surface of the electrode pad when heated. Therefore, in order to prevent the solder from crawl up, the Au plating layer, which is a conductor layer, is used.
  • a barrier metal such as a nickel film was further formed on the surface layer.
  • a joining method using a metal sintered material having excellent heat resistance has been studied, and in that case, the metal sintered material paste and the barrier metal such as a nickel film are incompatible with each other, and it may be difficult to perform sintering bonding. I know. As a result, there is a problem that the shape of the joint portion around the via hole is deformed and cracks are generated starting from the deformed joint portion during the temperature cycle test.
  • the Au plating layer may peel off due to heat shrinkage during heat sintering, or the semiconductor element may crack in some cases. There was a problem that occurred.
  • the heat-resistant resin 13 is formed in a bump shape on the back electrode 16 side of the semiconductor element 1 to heat-heat the back electrode 16 side of the via hole 12. It is covered with the sex resin 13. That is, the heat-resistant resin 13 is provided as a heat-resistant resin bump on the back surface electrode 16 side of the via hole 12, and is also filled inside the via hole 12.
  • the heat-resistant resin 13 is a resin having heat resistance that does not melt at the operating temperature of the semiconductor device 110, such as an epoxy-based resin that has a relatively high Young's modulus and is a hard resin, or a silicone-based resin that is relatively soft and can absorb deformation due to thermal stress. All you need is.
  • the heat-resistant resin 13 can be appropriately selected in consideration of the glass transition temperature, the wetting of the semiconductor element 1 with the back surface electrode 16, and the like. Further, as the heat-resistant resin 13, a heat-resistant resin containing metal particles may be used. In this case, the metal particles inside the via hole 12 and the metal sintered material paste 15a serving as the bonding layer 15 are sintered and bonded, so that a further effect of improving the bondability can be expected.
  • FIGS. 5A and 5B are enlarged cross-sectional views of the periphery of the via hole of the semiconductor device according to the first embodiment.
  • the heat-resistant resin 13 and the metal sintered material paste 15a are basically not sintered and joined. Therefore, as the angle of contact between the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 becomes 30 degrees or less, the unbonded region becomes like a cut between the back electrode 16 of the semiconductor element 1 and the metal sintered material paste 15a. It affects the temperature cycle life.
  • FIG. 1 As shown in FIG.
  • the heat-resistant resin 13 is formed in a bump shape so that the angle ⁇ 1 at which the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 come into contact with each other is larger than 30 degrees.
  • the angle ⁇ 1 is an angle at which the tangent line 17 and the back surface electrode 16 at the end of the heat-resistant resin 13 intersect.
  • the angle ⁇ 2 is an angle at which the tangent line 17 and the back surface electrode 16 at the end of the heat-resistant resin 13 intersect.
  • the heat-resistant resin 13 is formed so that the angle ⁇ 2 is 90 degrees or more, it is necessary to select a resin material that easily gets wet with the back electrode 16 of the semiconductor element 1. Further, since the height H2 of the protruding portion is reduced, the role of the protruding portion as a spacer is reduced.
  • the angle ⁇ 1 or the angle ⁇ 2 at which the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 come into contact with each other may be determined in consideration of the film thickness of the bonding layer 15 required for various uses of the semiconductor device 110.
  • the heat-resistant resin 13 may at least cover the opening of the via hole 12 to which the stress due to heat shrinkage during sintering is most applied. However, the more the heat-resistant resin 13 is filled inside the via hole 12, the more the heat-resistant resin 13 relaxes the thermal stress during the temperature cycle. Therefore, it is more desirable that the inside is filled with the heat-resistant resin 13.
  • FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment.
  • the heat-resistant resin 13 is formed by applying and curing the heat-resistant resin on the back surface of the semiconductor element 1 with a dispensing device or the like.
  • the metal sintered material paste 15a is applied onto the surface of the heat sink 6 by a dispensing device or printing, and the semiconductor element 1 prepared in 6A is applied onto the metal sintered material paste 15a. It is sintered by mounting it on a device and heating it to 200 ° C. or higher.
  • the bonding layer 15 is formed on the heat sink 6.
  • the circuit board 2 which is an electronic component, the semiconductor element 1, and the lead 4 for external connection are electrically connected by the bonding wire 3. Finally, the resin is sealed by a transfer mold. Through the above process, the semiconductor device 110 of the first embodiment is manufactured.
  • the heat sink 6 is not limited to the one made of copper (Cu) as long as it has a function of dissipating heat generated by the operation of the semiconductor element 1. ..
  • the heat sink 6 iron, tungsten, molybdenum, nickel, cobalt, alloys thereof, or a composite material thereof may be used.
  • the heat sink material having high thermal conductivity the heat generated from the semiconductor element 1 can be efficiently released to the outside, and the thermal stress strain applied to the bonding layer 15 can be reduced.
  • the shape of the heat sink 6 may be a square pillar, a polygonal pillar, a cylinder, an elliptical pillar, or a shape in which a step is provided in a part thereof.
  • a heat sink 6 made of tungsten having a thermal expansion coefficient relatively close to that of the semiconductor element 1 is mounted on a heat sink 6 made of copper (Cu) having a larger thermal expansion coefficient than that of the semiconductor element 1.
  • the mismatch of the thermal expansion coefficient between the element 1 and the heat sink 6 immediately below the element 1 can be reduced, and the thermal stress strain applied to the bonding layer 15 can be reduced.
  • the heat sink 6 is plated with gold (Au), it may be metal-plated which is compatible with each metal sintered material other than gold (Au), and is a heat sink made of copper (Cu).
  • Metal plating may not be required as long as the bondability with 6 can be ensured. Further, in the first embodiment, the case where the semiconductor element 1 is mounted on a base material such as a heat sink 6 is shown, but it may be mounted on a base material such as an insulating substrate. Further, if it is necessary to improve the adhesion with the sealing resin 5, roughened rough plating or the like may be applied to the metal plating surface.
  • gallium arsenide GaAs
  • gallium nitride GaN
  • has various merits such as high electron speed, high breakdown voltage due to wide bandgap, high power operation, wide operation bandwidth, and high temperature operation, resulting in miniaturization and cost reduction. ..
  • the semiconductor element 1 for high-frequency communication having different lengths of the long side and the short side is shown as an example, but the semiconductor element 1 having the same length of the long side and the short side is used. You may. Further, in the semiconductor device 110 according to the first embodiment, an example in which one semiconductor element 1 is mounted is shown, but a plurality of semiconductor elements 1 may be mounted, and gallium nitride (GaN) and gallium arsenal may be mounted. Different semiconductor elements 1 such as id (GaAs) may be combined. Further, in the semiconductor device 110 according to the first embodiment, an example in which the circuit board 2 is mounted is shown, but at least the semiconductor element 1 may be mounted. Further, similarly to the semiconductor element 1, a plurality of circuit boards 2 having different shapes or different sizes may be mounted in order to match the high frequency characteristics.
  • the metal sintered material paste 15a having a higher thermal conductivity than the conventional solder is effective.
  • the metal sintered material paste 15a generally has submicron, nano-sized or mixed metal particles, a protective film covering the particle surface, and a solvent for dispersing the particles. In addition to spheres, there are various shapes such as flakes or spheres covered with needles. When sintered at a low temperature of about 200 ° C., the protective film or solvent is completely volatilized to form a bonding layer 15 containing only neck-sintered metal particles. Therefore, it has thermal conductivity and heat resistance close to those of bulk metal.
  • the required sintering temperature varies depending on the size of the metal particles, the sintering accelerator contained in the paste, and the like, and sintering at room temperature is also possible.
  • the sintering of metal particles or the sintering of metal particles and an object to be joined progresses depending on the sintering temperature and the sintering time. Therefore, the joining reliability required for various applications of the semiconductor device 110 is required.
  • the sintering process may be determined in consideration of.
  • the metal sintered material paste 15a includes a silver (Ag) sintered material, a copper (Cu) sintered material, a gold (Au) sintered material, a palladium (Pd) sintered material, a platinum (Pt) sintered material, and the like.
  • Sintered materials based on metals classified as precious metals sintered materials based on metal particles classified other than precious metals such as nickel (Ni) sintered materials, silver oxide sintered materials, copper oxide sintered materials Sintered material that obtains a sintering reaction by reducing fine oxides such as, etc.
  • metal fine particles silver (Ag) -palladium (Pd) sintered material, gold (Au) -silicon (Si) sintered material ,
  • a sintered material paste based on an alloy such as a gold (Au) -germanium (Ge) sintered material or a gold (Au) -copper (Cu) sintered material may be used.
  • the thickness of the bonding layer 15 is preferably 30 ⁇ mt or more, and the life for the temperature cycle test can be further improved.
  • the bonding layer 15 thicker, it is possible to further improve the life for the temperature cycle test, but even though the metal sintered material paste 15a having a high thermal conductivity (200 W / mK or more) is used. Since the thermal resistance and the member cost increase by increasing the thickness of the bonding layer 15, the thickness may be determined in consideration of the thermal design of the semiconductor device 110. Further, the film thickness of the heat-resistant resin 13 formed on the back surface electrode 16 side may be 1/10 or more of the thickness of the semiconductor element 1.
  • the semiconductor device 110 according to the first embodiment is covered with the sealing resin 5 such as the semiconductor element 1, it may have a hollow structure in which a ceramic cap, a metal cap, or the like is adhered and joined.
  • the sealing resin 5 having a high dielectric constant does not exist on the surface of the semiconductor element 1, and high high frequency characteristics can be obtained.
  • the semiconductor device 110 according to the first embodiment is the semiconductor element 1 in which the via hole 12 is formed between the front surface electrode such as the electrode pad 7 and the back surface electrode 16 provided on the opposite side of the front surface electrode.
  • a heat-resistant resin 13 that covers the back surface electrode 16 side of the via hole 12, a base material such as a heat sink 6 on which the semiconductor element 1 is mounted, and a metal sintered material as a main component, the semiconductor element 1 and the base material. It has a bonding layer 15 and a bonding layer 15 for bonding.
  • a semiconductor element 1 in which a via hole 12 is formed between a front surface electrode such as an electrode pad 7 and a back surface electrode 16 provided on the opposite side of the front surface electrode is prepared.
  • the semiconductor device 110 can suppress peeling of the conductive layer 14 or cracking of the semiconductor element 1 due to heat shrinkage during heat sintering, and also suppresses the protrusion portion of the heat-resistant resin 13.
  • the protruding portion acts as a spacer, the thickness of the bonding layer 15 can be secured, and the life for the temperature cycle test can be improved.
  • FIG. 7 is a plan view showing the back surface of the semiconductor element of the semiconductor device according to the second embodiment.
  • the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.
  • the structure in which the via hole 12 covered with the heat-resistant resin 13 is provided in the center of the semiconductor element 1 is illustrated, but the positions where the via hole 12 and the heat-resistant resin bump are formed are not limited to this. No.
  • the via hole 12 covered with the heat-resistant resin 13 is the center of the semiconductor element 1 and the entire circumference of the outer peripheral end surface of the semiconductor element 1. Is formed in.
  • the arrangement shown in 7A of FIG. 7 forms the largest number of via holes 12 and heat-resistant resin bumps, the thickness of the bonding layer 15 can be secured most reliably, and the in-plane height of the semiconductor element 1 can be secured. The variation can be minimized. Therefore, the semiconductor device 110 on which the semiconductor element 1 shown in 7A of FIG. 7 is mounted can stably obtain high reliability.
  • the metal sintered material paste 15a when the metal sintered material paste 15a is applied to a base material such as a heat sink 6 by a dispensing device and the semiconductor element 1 is mounted, the metal sintered material paste 15a applied to the center is spread outward.
  • the central bonding layer 15 of the semiconductor element 1 becomes thicker, and the thickness of the bonding layer 15 becomes thinner toward the outer peripheral end of the semiconductor element 1.
  • the metal sintered material paste 15a does not melt and spread wet, so that the sintered joint is often completed with a non-uniform thickness. Since the stress strain during the temperature cycle is most concentrated at the outer peripheral end of the joint layer 15, even if the average thickness of the joint layer 15 can be secured, the thickness is not uniform and the thinned joint layer 15 is cracked.
  • the force for pushing the metal sintered material paste 15a at the time of mounting becomes weak, and the force directly under the via hole 12 tends to be a more porous and sparse bonding layer.
  • the porous and sparse bonding layer is also weak in strength and tends to be a starting point for cracks in the reliability test.
  • the metal sintered material paste 15a can be pushed in in the same manner as other regions such as the outer peripheral end portion at the time of mounting, and a uniform and dense bonding layer 15 can be obtained. be able to.
  • the via hole 12 covered with the heat-resistant resin 13 is formed on two opposite sides of the central and outer peripheral end faces of the semiconductor element 1. Are formed in any pair when is paired with each other. Even if the via holes 12 and the heat-resistant resin 13 are formed only on any one pair of two sides, there is no problem in ensuring the thickness of the bonding layer 15. In addition, the solvent volatilized during the sintering of the metal sintering material paste 15a easily escapes from the pair of two sides on which the via hole 12 and the heat-resistant resin 13 are not formed, thereby suppressing voids generated inside the bonding layer 15. And by promoting heat shrinkage, a denser bonding layer 15 can be obtained.
  • the via holes 12 covered with the heat-resistant resin 13 are formed at the center and the four corners of the semiconductor element 1.
  • the 7D structure has the smallest number of via holes 12 and heat-resistant resin 13, the most volatile solvent can be easily released, and the densest bonding layer 15 can be obtained.
  • the positions or numbers of the via holes 12 and the heat-resistant resin 13 described above may be appropriately determined depending on the bonding thickness and variation required for each semiconductor device 110, the thermal conductivity of the bonding layer 15, or the state inside the bonding layer 15. good.
  • the semiconductor element 1 for high frequency communication is generally rectangular in order to obtain high high frequency characteristics. That is, there are a pair of short and long sides.
  • the via holes 12 and the heat-resistant resin 13 formed only on either pair of two sides of the semiconductor element 1 have been described, but the rectangular semiconductor element 1 is formed only on the short side. By doing so, high reliability can be ensured.
  • the solvent volatilized from the long side is preferentially released. Therefore, the via hole 12 and the heat-resistant resin 13 are provided only on the short side.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur et un procédé de fabrication d'un dispositif à semi-conducteur qui peut empêcher la déformation de la forme de la périphérie de trous d'interconnexion (12), et supprimer une diminution de fiabilité. Ce dispositif à semi-conducteur (110) comprend : un élément semi-conducteur (1) dans lequel des trous d'interconnexion (12) sont formés entre une électrode de surface (7) et des électrodes arrière (16) disposées sur le côté opposé à l'électrode de surface (7) ; une résine résistante à la chaleur (13) qui recouvre les côtés d'électrode arrière (16) des trous d'interconnexion (12) ; une base (6) sur laquelle est montée l'élément semi-conducteur (1) ; et une couche de jonction (15) qui comprend un matériau fritté métallique en tant que composant principal, et joint l'élément semi-conducteur (1) et la base (6).
PCT/JP2021/007655 2020-03-12 2021-03-01 Dispositif à semiconducteur et procédé de fabrication de dispositif à semiconducteur WO2021182149A1 (fr)

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JP2020-042632 2020-03-12

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128179A (ja) * 1985-11-29 1987-06-10 Nec Corp 半導体装置
JP2004165602A (ja) * 2002-09-24 2004-06-10 Hamamatsu Photonics Kk 半導体装置及びその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128179A (ja) * 1985-11-29 1987-06-10 Nec Corp 半導体装置
JP2004165602A (ja) * 2002-09-24 2004-06-10 Hamamatsu Photonics Kk 半導体装置及びその製造方法

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JPWO2021182149A1 (fr) 2021-09-16

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