CN110931479A - 半导体封装体 - Google Patents

半导体封装体 Download PDF

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Publication number
CN110931479A
CN110931479A CN201910885427.7A CN201910885427A CN110931479A CN 110931479 A CN110931479 A CN 110931479A CN 201910885427 A CN201910885427 A CN 201910885427A CN 110931479 A CN110931479 A CN 110931479A
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China
Prior art keywords
layer
semiconductor chip
substrate
heat dissipation
semiconductor
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CN201910885427.7A
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English (en)
Inventor
邵栋梁
王仁佑
吴仲融
董志航
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110931479A publication Critical patent/CN110931479A/zh
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Abstract

一种半导体封装体，包括一基底及位于基底上的半导体晶圆。一散热特征部件覆盖基底及半导体晶圆，且复合热界面材料(thermal interface material,TIM)结构热接合于半导体晶圆与散热特征部件之间。复合TIM结构包括含金属的基材层及埋入含金属的基材层内的高分子颗粒。

Description

半导体封装体
技术领域
本发明实施例涉及一种半导体封装技术，且特别涉及一种半导体封装体及其制造方法。
背景技术
半导体集成电路(IC)工业经历了快速地增长。IC材料及设计的技术演进已经产生了几世代的IC，其中每一世代都具有比上一世代更小更复杂的电路。近来对小型电子装置的需求也在增长，因此已增加对于使用于半导体芯片的更小和更有创意的封装技术的需求。拜技术发展所赐，微电子装置的封装密度增加，制造商不断缩小微电子装置的尺寸，以满足对小型电子装置日益增长的需求。现代微电子装置的另一趋势是增加更高功耗的电路的使用。为了适应更密集封装具有更高功耗的微电子装置，需要提高集成电路封装的散热性能。
在集成电路的封装中，可将一或多个半导体芯片接合至散热片(heat spreader)(有时称作散热鳍片(heat sink))，以进行散热。然而，散热为半导体封装中的挑战。瓶颈在于妨碍半导体封装体的内部芯片所产生的热量的有效消散。
发明内容
一种半导体封装体包括：一基底；一半导体芯片，位于基底上；一散热特征部件，位于基底上方并覆盖半导体芯片；以及一复合热界面材料(TIM)结构，热性接合于半导体芯片与散热特征部件之间。复合TIM结构包括：一含金属的基材层；以及多个高分子颗粒，埋入含金属的基材层内的。
一种半导体封装体包括：一散热盖；一第一半导体芯片，具有一上表面覆盖于散热盖，其中第一半导体芯片的上表面具有至少一热点区域与热点区域之外的一区域；一接合层，热性连接于第一半导体芯片与散热盖之间；以及多个核-壳结构，形成于接合层内，其中每一核-壳结构包括一高分子核体及一金属壳，其中热点区域上方的核-壳结构的密度大于热点区域之外的区域上方的核-壳结构的密度。
在一些实施例中，一种半导体封装体的制造方法包括形成一金属化堆叠层于一半导体芯片上；装设多个高分子颗粒于金属化堆叠层上，其中每一高分子颗粒涂有一第一接合层；通过回流第一接合层接合一散热盖至半导体芯片，其中在接合期间，形成一复合热界面材料(TIM)结构于散热盖与半导体芯片之间，且其中复合TIM结构包括第一接合层及埋入第一接合层内的高分子颗粒。
附图说明
图1A至图1E示出根据一些实施例的形成半导体封装体的各个阶段的剖面示意图。
图2为图1B中区域A的放大剖面示意图。
图3为图1C中区域B的放大剖面示意图。
图4A至图4F示出根据一些实施例的形成半导体封装体的各个阶段的剖面示意图。
图5示出根据一些实施例的复合热界面材料(TIM)结构内核-壳结构的排置的平面示意图。
图6示出根据一些实施例的半导体封装体剖面示意图。
图7示出根据一些实施例的半导体封装体剖面示意图。
附图标记说明：
100、310、310a、310b、310c、320、320a、320b、320c 半导体芯片
100a 上表面
101 热点区域
102、202、212、314、316311、321、324 导电连接器
103、A、B 区域
104 底胶材料
110 钛层
112 铜层
114 镍层
116 锡银(Sn/Ag)合金层
120、312、322 金属化堆叠层
122、122a、124、126 接合层
130 核-壳结构
132 高分子颗粒
134 第一层
136 第二层
137 金属盖层
138 焊料材料层
140 含金属的基材层
150 复合热界面材料(TIM)结构
158 腔室
160 散热特征部件
160a 内表面
161 平板部
162 粘着层
163 壁部
200 基底
200a、200b 表面
210 中介层
330、340 半导体芯片堆叠
具体实施方式
以下的公开内容提供许多不同的实施例或范例，以实施本发明的不同特征部件。而以下的公开内容是叙述各个构件及其排列方式的特定范例，以求简化本公开内容。当然，这些仅为范例说明并非用以限定本发明。举例来说，若是以下的公开内容叙述了将一第一特征部件形成于一第二特征部件的上或上方，即表示其包含了所形成的上述第一特征部件与上述第二特征部件是直接接触的实施例，亦包含了尚可将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间，而使上述第一特征部件与上述第二特征部件可能未直接接触的实施例。另外，本公开内容在各个不同范例中会重复标号及/或文字。在整个说明书中，除非另有说明，否则不同附图中的相同标号表示通过使用相同或相似材料及方法所形成的相同或相似部件。
再者，在空间上的相关用语，例如＂下方＂、＂之下＂、＂下＂、＂上方＂、＂上＂等等在此处是用以容易表达出本说明书中所示出的附图中元件或特征部件与另外的元件或特征部件的关系。这些空间上的相关用语除了涵盖附图所示出的方位外，还涵盖装置于使用或操作中的不同方位。此装置可具有不同方位(旋转90度或其他方位)且此处所使用的空间上的相关符号同样有相应的解释。
以下叙述本文的一些实施例。可在这些实施例中所述的阶段之前，期间及/或之后提供额外操作步骤。对于不同的实施例，可替换或排除所述的某些阶段。可以将额外特征部件加入于半导体装置结构内。对于不同的实施例，可以替换或排除下面所述的某些特征部件。尽管以特定顺序进行的操作步骤对一些实施例进行讨论，然而可以另一逻辑顺序进行这些操作步骤。
根据各种示例性实施例提供了一种具有改善散热能力的半导体封装体及其制造方法。也示出形成半导体封装体的中间阶段及讨论实施例的变化。在各种示意图及说明性实施例中，相同的附图标记用于表示相同的部件。
半导体封装体的制造包括形成一复合热界面材料(TIM)结构于散热特征部件(例如，散热盖)与一或多个半导体芯片之间。复合TIM结构包括含金属的基材层。复合TIM结构也包括分别涂覆于一金属盖层的高分子颗粒，并埋入含金属的基材层中。含金属的基材层提供良好的导热性，使得半导体芯片所产生的热可有效地传导至散热特征部件。涂覆有高分子颗粒的金属盖层为半导体芯片提供应力缓冲，且为复合TIM结构提供机械性支撑。如此一来，可防止半导体芯片在热处理期间发生破裂，或者至少可减轻这种破裂情形。再者，复合TIM结构在热处理后可达到均匀的厚度，从而降低半导体芯片与散热特征部件之间的热阻。
图1A至图1E示出根据一些实施例的形成半导体封装体的各个阶段的剖面示意图。根据一些实施例，提供具有两个相对表面200a及200b的一基底200，如图1A所示。在一些实施例中，基底200也称作封装部件，例如封装基底、中介层或印刷电路板(PCB)等。在一些实施例中，封装部件(即，基底200)为封装基底，其包括一绝缘层及一或多个图案化导电层(用作导电走线并设置在绝缘层的不同层位)。绝缘层与图案化导电层的组合在基底200中形成重分布层(RDL)结构(其也称作扇出型结构)。
在一些实施例中，基底200的绝缘层由有机材料(例如高分子基材料)、非有机材料(例如氮化硅、氧化硅)或高k值电介质材料等形成。在一些实施例中，基底200内的那些图案化导电层由金属形成。为了简化附图，仅示出一平坦的基底。在一些实施例中，分离的被动装置(未示出)，诸如电阻器、电容器、变压器等也接合至基底200的两相对侧中的至少一者。
根据一些实施例，提供一半导体芯片100，并将其装设至基底200的上表面200a上，如图1A所示。在一些实施例中，半导体芯片100包括多个导电连接器102(例如金属凸块、焊球等)。通过使用导电连接器102的覆晶接合工艺，将半导体芯片100接合至基底200，使半导体芯片100经由导电连接器102电性连接至基底200。在一些实施例中，半导体芯片100为系统芯片(system-on-chip,SoC)，例如逻辑芯片。举例来说，逻辑芯片可为中央处理单元(central processing unit,CPU)，图形处理单元(graphics processing unit,GPU)，存储器控制器等。
在一些实施例中，在堆叠半导体芯片100于基底200上之后，对导电连接器102进行一回流工艺，使半导体芯片100装设于基底200上。在一些实施例中，填充一选择性的底胶材料104(例如环氧树脂)于半导体芯片100与基底200之间的间隙内，以对导电连接器102进行封胶。底胶材料104提供机械性支撑、连接部件(即，导电连接器102)的电性隔离以及保护主动电路免受外在环境影响。
根据一些实施例，在装设半导体芯片100至基底200上之后，形成一接合层122于半导体芯片100的上表面100a(有时称作非主动表面)上，如图1B所示。在一些实施例中，接合层122具有良好的导热性(例如，约40W/mK至约50W/mK或更高)。在一些实施例中，接合层122由焊膏、银膏、铟膏或纳米金属墨水制成。在一些其他实施例中，接合层122为助焊层。
在一些实施例中，为了促进接合层122与半导体芯片100之间的粘着性，在形成接合层122之前，沉积一金属化堆叠层120于半导体芯片100的上表面100a上。金属化堆叠层120包括易于粘着至半导体芯片100的一粘着层、易于润湿粘着层的一润湿层以及防止由于润湿层之间的反应而快速形成金属间化合物(intermetallic compound,IMC)层的一保护层。金属化堆叠层120的结构详细示出于图2中，其为图1B中区域A的放大剖面示意图。在一些实施例中，金属化堆叠层120的结构包括一钛层110、形成于钛层110上的一铜层112、形成于铜层112上的一镍层114以及形成于镍层114上的一锡银(Sn/Ag)合金层116。钛层110可作为金属化堆叠层120的粘着层。铜层112及Sn/Ag合金层116可作为金属化堆叠层120的润湿层。镍层114可用为金属化堆叠层120的保护层。在一些实施例中，通过沉积工艺形成金属化堆叠层120，例如电镀工艺、蒸镀工艺、溅镀工艺、化学气相沉积(CVD)工艺或其他合适的沉积工艺。
根据一些实施例，提供一散热特征部件160，如图1C所示。在一些实施例中，散热特征部件160为散热盖，且包括一平板部161以及自平板部161的边缘垂直延伸的一壁部163。在一些其他实施例中，散热特征部件160包括平板部161而不具有壁部163。在一些实施例中，散热特征部件160具有高导热性，例如，在约100W/mK至约500W/mK之间或更高，并且可由金属、金属合金等制成。举例来说，散热特征部件160可包括金属及/或金属合金，例如铝(Al)、铜(Cu)、镍(Ni)、钴(Co)、及其组合等。散热特征部件160也可以由复合材料形成，例如碳化硅、氮化铝、或石墨等。
之后，涂覆一接合层124于散热特征部件160的平板部161的内表面160a。在一些实施例中，接合层124也具有良好的导热性(例如，自约40W/mK至约50W/mK或更高)。在一些实施例中，接合层124由焊膏、银膏、铟膏或纳米金属墨水制成。在一些其他实施例中，接合层124是助焊层。在一些实施例中，接合层124与接合层122的材料由不同的材料制成。举例来说，接合层124由焊膏制成，而接合层122由助焊剂制成。或者，接合层122由焊膏制成，而接合层124由助焊剂制成。
根据一些实施例，在形成接合层124于散热特征部件160的平板部161的内表面160a上之后，放置多个核-壳结构130于接合层124上，如图1C所示。在一些实施例中，每个核-壳结构130包括高分子颗粒(其也称作高分子核)以及围绕或密封高分子颗粒的金属盖层(也称为金属壳)。
如图3(其为图1C中区域B的放大剖面示意图，以详细示出核-壳结构130)所示。在一些实施例中，每个核-壳结构130包括高分子颗粒(或高分子核体)132和围绕高分子颗粒132的金属盖层(或金属壳)137。
在一些实施例中，高分子颗粒132由聚苯乙烯(polystyrene,PS)或聚甲基丙烯酸甲酯(polymethyl methacrylate,PMMA)等制成。在一些实施例中，金属盖层137包括围绕或密封高分子颗粒132的一第一层134以及围绕或密封第一层134的第二层136。在一些实施例中，第一层134由不同于第二层136材料的金属材料制成。在一些实施例中，使用第一层134作为种子层并通过电镀工艺形成金属盖层137。在这些情况下，第一层134由镍制成，而第二层136由铜(Cu)、银(Ag)、或金(Au)等制成。
在一些实施例中，每个核-壳结构130也包括围绕或密封金属盖层137的一选择性焊料材料层(例如Sn/Ag焊料层)138及形成于焊料材料层138与金属盖层137之间的一金属间化合物(intermetallic compound,IMC)层(未示出)。在一些实施例中，IMC层包括Cu6Sn5、Cu3Sn、AuSn4、或Ag3Sn等，且其于加热工艺或接合工艺期间形成。在一些其他实施例中，当接合层124由焊膏、银膏、铟膏或纳米金属墨水制成时，核-壳结构130不具有焊料材料层138。
根据一些实施例，在放置核-壳结构130于接合层124上之后，进行一回流工艺，使那些核-壳结构130装设于平板部161的内表面160a上。虽然核-壳结构130装设于散热特征部件160上(如图1C所示)，然而根据一些其他实施例，那些核-壳结构130可通过接合层122装设于金属化堆叠层120上。
在一些实施例中，那些核-壳结构130规则地及/或均匀地排置于接合层124或接合层122上。在一些其他实施例中，那些核-壳结构130不规则地排置于接合层124或接合层122上。
根据一些实施例，在形成核-壳结构130之后，具有接合层124和核-壳结构130的散热特征部件160接合到基底200及半导体芯片100，如图1D所示。在一些实施例中，在散热特征部件160贴附至基底200的表面200a之后，散热特征部件160的内表面160a(如图1C所示)面向半导体芯片200上方的接合层122。
在一些实施例中，在贴附散热特征部件160至基底200之前，形成一粘着层162于基底200的表面200a上并围绕基底200的周边。在一些实施例中，粘着层162具有更好的粘着能力，以允许散热特征部件160的壁部163(如图1C所标示)的一端贴附于半导体芯片100与基底200的周边周围。举例来说，粘着层162可由环氧化物或硅氧树脂等制成。
在一些实施例中，在贴附散热特征部件160至基底200期间或之后，在一温度下(例如，约在220℃大约250℃的范围)，进行一热工艺，例如热压接合(thermal compressionbonding,TCB)工艺，使散热特征部件160经由接合层122及接合层124热接合至半导体芯片100。在热工艺期间，接合层122及接合层124与每一核-壳结构130的焊接材料层138(若存在)发生回流，以彼此结合或合而为一。如此一来，一含金属的基材层140由接合层122及接合层124与焊料材料层138(若存在)形成，且每一核-壳结构130包括金属盖层137及高分子颗粒132(未示出，而如图3所标示)并埋入于含金属的基材层140中。因此，具有核-壳结构130的含金属的基材层140形成一复合热界面材料(TIM)结构150，且复合热界面材料(TIM)结构150热连接于散热特征部件160与半导体芯片100之间。在散热特征部件160通过粘着层162接合至基底200及通过复合热界面材料(TIM)结构150接合至半导体芯片100之后，形成一腔室158于散热特征部件160与基底200之间，而半导体芯片100及复合热界面材料(TIM)结构150位于腔室158内。
在一些实施例中，半导体芯片100的上表面100a(如图1B所标示)具有一第一区域(未示出)以及位于第一区域之外的一第二区域(未示出)。对应于第一区域的核-壳结构130的密度不同于对应于第二区域的核-壳结构130的密度。举例来说，第一区域包括一或多个热点区域，而第二区域为第一区域之外的区域。再者，对应于第一区域的核-壳结构130的密度大于对应于第二区域的核-壳结构130的密度。核-壳结构130包括Cu、Ag或Au，使通过增加对应于此第一区域的核-壳结构130的密度，来自热点区域的热量可以有效地传导至散热特征部件160。
根据一些实施例，在将散热特征部件160贴附至基底200之后，形成多个导电连接器202于基底的表面200b上，如图1E所示。在一些实施例中，导电连接器202包括金属凸块、或焊球等，且排置成形成球形阵列(ball grid array,BGA)。导电连接器202可用于电性连接主机板(未示出)或其他电子装置部件。
尽管在贴附散热特征部件160至基底200之后导电连接器202形成于基底200的表面200b上，然而可在半导体芯片100装设至基底200的表面200a之前形成导电连接器202于基底200上。
在一些其他实施例中，在贴附散热特征部件160至基底200之后，提供一封胶材料(例如，模塑材料(未示出))于图1D所示的结构上。封胶材料具有形成于腔室158内的一第一部以及通过散热特征部件160隔开第一部的一第二部。举例来说，散热特征部件160覆盖封胶材料的第一部，且封胶材料的第一部围绕半导体芯片100。再者，封胶材料的第二部围绕散热特征部件160的外侧壁，且露出位于半导体芯片100上方局部的散热特征部件160。或者，散热特征部件160覆盖形成的封胶材料而封胶材料并未包围散热特征部件160的外侧壁。在一些实施例中，模塑料由环氧化物、或树脂等制成。
在一些其他实施例中，在贴附散热特征部件160至基底200之前，提供封胶材料(未示出)于图1B所示的结构上。之后，可研磨封胶材料以露出金属化堆叠层120。在图1E所示的半导体封装体中，复合TIM结构150的含金属基材层140由接合层122与接合层124(分别标示于图1B及图1C)形成，其提供良好的导热性，以传导半导体芯片100所产生的热量至散热特征部件160。如此一来，改善了半导体封装结构的散热。
再者，在含金属的基材层140中，高分子颗粒132可作为半导体芯片100的应力缓冲，以消除或降低由热工艺产生的热机械应力(例如，TCB工艺)。因此，可以防止或减轻在热工艺期间在半导体芯片100内形成裂缝。如此一来，增加了半导体封装体的可靠度。
另外，涂覆有金属盖层137的每个高分子颗粒132可作为间隔物，以为复合TIM结构150提供机械性支撑。因此，复合TIM结构150的高度或厚度可通过调整金属盖层137的尺寸(例如，直径)加以控制。再者，复合TIM结构150可在进行热工艺之后获得均匀的厚度，进而降低半导体芯片100与散热特征部件160之间的热阻。如此一来，进一步改善了半导体封装结构的散热。
可对本文的实施例进行许多变化及/或修改。举例来说，图1B示出金属化堆叠层120上方的接合层122为一连续层，然而本文的实施例并未受限于此。金属化堆叠层120上的接合层可为图案化或不连续层。图4A至图4F图示出根据一些实施例的形成半导体封装体的各个阶段的剖面示意图。图4A至图4F中所示的阶段相似于图1A至图1E中所示的那些阶段。在一些实施例中，图1A至图1E中所示的半导体封装体的材料、形成方法及/或益处也可以应用于图4A至图4F中所示的实施例中，因此不再重复。
根据一些实施例，图4A中提供相似于图1B的结构。与图1B中所示的结构不同，形成一图案化或不连续的接合层122a于金属化堆叠层120上。在一些实施例中，接合层122a由相同或相似图1B中所示的接合层122的材料制成。在一些实施例中，接合层122a包括在金属化堆叠层120上规则地及/或均匀地排置的多个岛型部。在一些其他实施例中，那些岛型部不规则地布置在金属化堆叠层120上。在一些实施例中，接合层122a由焊膏制成。
根据一些实施例，在形成接合层122a之后，分别放置核-壳结构于接合层122a的岛型部上，如图4B所示。相似于图3中所示的核-壳结构130，每一核-壳结构包括一高分子颗粒(或高分子核体)132(未示出，且如图3所标示)及围绕或密封高分子颗粒132的金属盖层(或金属壳)137。在一些实施例中，核-壳结构包括围绕或密封金属盖层137的(未示出，且如图3所标示)的一选性焊料材料层(例如，Sn/Ag焊料层)138与形成于焊料材料层138与金属盖层137之间的一金属间化合物(IMC)层(未示出)。IMC层可于加热工艺或粘合工艺期间形成。在一些其他实施例中，二或更多个核-壳结构放置于接合层122a的至少一个岛型部上。
在一些实施例中，在放置核-壳结构之后，对由焊膏制成的接合层122a进行一回流工艺，使核-壳结构涂覆有接合层122a，如图4C的实施例所示。在一些实施例中，在进行回流工艺之后，接合层122a的岛型部围绕或密封对应的金属盖层137(即，核-壳结构)。如此一来，具有高分子颗粒且覆盖于接合层122a的对应岛型部的每一金属盖层137装设于金属化堆叠层120上。
在一些其他实施例中，接合层122a由助焊剂制成，且核-壳结构分别放置于接合层122a的岛型部上。在这些情况下，每一核-壳结构由按序通过金属盖层137及接合层(未示出，例如焊膏层)覆盖高分子颗粒132(未示出，且如图3所标示)而形成。再者，形成一IMC层(未示出)于接合层(例如，焊膏层)与金属盖层137之间。在放置核-壳结构之后，对包括焊膏层的核-壳结构进行一回流工艺，使其内具有高分子颗粒且覆盖对应的焊膏层的每一金属盖层137装设于金属化堆叠层120上。
根据一些实施例，在金属盖层137装设在金属化堆叠层120上之后，形成一选择性的接合层126于金属化堆叠层120上，以覆盖接合层122a或围绕对应金属盖层137的焊膏层，如图4D所示。在一些实施例中，接合层126具有良好的导热性(例如，约在40W/mK与50W/mK之间或更高)，且由相同于接合层122a的材料制成。在一些实施例中，接合层126由焊膏、银膏或铟膏制成。
之后，根据一些实施例，具有一选择性的接合层124(未示出，且如图1C所标示)的一散热特征部件160接合至基底200及半导体芯片100，如图4E所示。在一些实施例中，散热特征部件160的接合方法相同或相似于图1D中所述的方法。
如此一来，含金属的基材层140由接合层122a、接合层124及126(若存在)以及焊接材料层138(若存在)形成。再者，包括金属盖层137及高分子颗粒132(未示出，且如图3所标示)的每一核-壳结构埋入于含金属的基材层140内，以产生复合TIM结构150，因此复合TIM结构150热性连接于散热特征部件160与半导体芯片100之间。形成一腔室158于散热特征部件160与基底200之间，且半导体芯片100与复合TIM结构150形成于腔室158内。
根据一些实施例，位于复合TIM结构150下方的半导体芯片100的上表面具有一或多个热点区域(例如，热点区域101)及位于热点区域101之外的区域103，如图5所示。在一些实施例中，对应于热点区域101的核-壳结构(例如，金属盖层137)的密度大于对应于热点区域101之外的区域103的核-壳结构的密度，使来自热点区域101的热量可通过增加对应于热点区域101的核-壳结构的密度，以有效地传导至散热特征部件160。
根据一些实施例，在贴附散热特征部件160至基底200之后，形成多个导电连接器202至基底200的表面200b上，如图4F所示。
在一些其他实施例中，可在半导体芯片100装设至基底200的上表面200a上之前，形成导电连接器202于基底200上。在一些其他实施例中，在贴附散热特征部件160于基底200上之后，以相同或相似于提供一封胶材料(未示出)于图1D中的结构的方式，提供一封胶材料(未示出，例如模塑材料)于图4E所示的结构上。在一些实施例中，封装材料(例如，模塑材料)覆盖并围绕半导体芯片100。
可对本文的实施例进行许多变化及/或修改。举例来说，第1E或4F图示出半导体芯片100装设于基底200上，且被复合TIM结构150覆盖，然而本文的实施例未受限于此。复合TIM结构150可覆盖一个以上的半导体芯片，且可装设于不同于基底200的另一封装部件上。图6示出根据一些实施例的半导体封装的剖面示意图。图6所示的封装结构相似于图1E或图4F所示的封装结构。在一些实施例中，图1E或图4F中所示的半导体封装体的材料、形成方法及/或益处也可应用于图6所示的实施例中，因此不再重复。
不同于图1E或图4F中所示的半导体封装体，根据一些实施例，图6的半导体封装体还包括一封装部件(例如，中介层210)位于基底200(例如，封装基底)与半导体芯片100之间。在一些实施例中，图6中所示的半导体封装体还包括一或多个半导体芯片，装设于中介层210以及半导体芯片100上，且可具有并排的配置。举例来说，半导体芯片100、310及320可分别具有多个导电连接器102、314及316，且那些导电连接器102、314及316装设于中介层210上。导电连接器314及316的材料、尺寸以及间距可相同或相似于导电连接器102的材料、尺寸以及间距。半导体芯片310及320可排置于半导体芯片100的两相对侧上，使那些半导体芯片100、310及320并排配置。
在一些实施例中，半导体芯片100为SoC芯片，且半导体芯片310及320为存储器芯片，例如高频宽存储器(high bandwidth memory,HBM)芯片。
在一些实施例中，绝缘层(未示出)与图案化导电层(未示出)的组合形成RDL结构(或扇出型结构)于在中介层210内，使中介层210通过此RDL结构电性连接那些半导体芯片100、310及320。在一些实施例中，中介层210具有多个导电连接器212，且导电连接器212装设于基底200上方并通过基底200内的RDL结构(未示出)而电性连接至基底200。导电连接器212的材料可相同或相似于导电连接器102的材料。在一些实施例中，导电连接器212的尺寸及间距大于导电连接器102的尺寸及间距。
在一些实施例中，半导体芯片310及半导体芯片320分别具有金属化堆叠层312及金属化堆叠层322，金属化堆叠层312及金属化堆叠层322热性连接至复合TIM结构150。如此一来，半导体芯片100、310及320位于复合TIM结构150与中介层210之间，且位于散热特征部件160与基底200之间的腔室158内。在一些实施例中，金属化堆叠层312及金属化堆叠层322的材料及结构相同或相似于半导体芯片100的金属化堆叠层120的材料及结构。
可对本文实施例进行许多变化及/或修改。举例来说，图6示出半导体芯片310及320排置于半导体芯片100的两相对侧上，然而本文的实施例并未受限于此。半导体芯片堆叠可排置于半导体芯片100的两相对侧上，使半导体芯片堆叠与半导体芯片100具有并排配置。图7示出根据一些实施例的半导体封装体的剖面示意图。图7所示的封装结构相似于图6所示的封装结构。在一些实施例中，图6中所示的半导体封装体的材料、形成方法及/或益处也可以应用于图7所示的实施例中，因此不再重复。
不同于图6中所示的半导体封装体，根据一些实施例，图7的半导体封装体还包括半导体芯片堆叠330及340排置在半导体芯片100的两相对侧上，使半导体芯片堆叠与半导体芯片100具有并排配置。举例来说，半导体芯片堆叠330包括半导体芯片310a、310b及310c，其通过多个导电连接器314按序堆叠并装设于中介层210上，且通过多个导电连接器311(其可为微凸块)而彼此电性连接。再者，位于半导体芯片堆叠330的最上面的半导体芯片(例如，半导体芯片310c)具有热性连接至复合TIM结构150的金属化堆叠层312。
相似地，半导体芯片堆叠340包括按序堆叠并经由多个导电连接器324装设于中介层210上方的半导体芯片320a、320b及320c，且通过多个导电连接器321(其可为微凸块)而彼此电性连接。再者，位于半导体芯片堆叠340的最上面的半导体芯片(例如，半导体芯片320c)具有热性连接至复合TIM结构150的金属化堆叠层322。
在一些实施例中，那些半导体芯片310a、310b、310c、320a、320b及320c为存储器芯片，例如HBM芯片。
上述实施例提供了半导体封装体及其制造方法。半导体封装体包括复合热界面材料(TIM)结构150，其热性接合于半导体芯片100与散热特征部件160之间。复合TIM结构150的制作包括形成一金属化堆叠层120于半导体芯片100上。之后，涂覆有金属盖层137并埋入含金属的基材层140中的每一高分子颗粒132装设于金属化堆叠层120上。含金属的基材层140提供良好的导热性，以传导半导体芯片产生的热量至散热特征部件。涂覆有金属盖层137的高分子颗粒132提供半导体芯片100应力缓冲的用，以在热工艺期间防止或减轻半导体芯片100中裂缝的形成。涂覆有金属盖层137的高分子颗粒132也提供复合TIM结构150机械性支撑之用，使复合TIM结构150在经过热工艺之后可以得到均匀的厚度，进而降低半导体芯片100与散热特征部件160之间的热阻。如此一来，提高了半导体封装体的散热性，并提高了半导体封装体的可靠度。
上述实施例提供了半导体封装体及其制造方法。半导体封装体包括一复合热界面材料(TIM)结构位于半导体芯片与散热部件之间。复合TIM结构的制作包括形成一含金属的基材层于半导体上，并形成多个高分子颗粒于含金属的基材层内。含金属的基材层提供良好的导热性，用于将半导体芯片产生的热量传导至散热特征部件。高分子颗粒提供半导体芯片应力缓冲的用，以在热工艺期间防止或减轻半导体芯片内形成裂缝。如此一来，改善了半导体封装体的散热，并且提高了半导体封装体的可靠度。
在一些实施例中，提供了一种半导体封装体。半导体封装包括一基底及位于基底上的一半导体芯片。半导体封装体也包括位于基底上方并覆盖半导体芯片的一散热特征部件，以及热性接合于半导体芯片与散热特征部件之间的一复合热界面材料(TIM)结构。复合TIM结构包括一含金属的基材层及埋入含金属的基材层内的多个高分子颗粒。
在一些实施例中，复合TIM结构还包括多个金属盖层分别围绕上述高分子颗粒。在一些实施例中，每一金属盖层包括第一层及围绕第一层的一第二层，且其中第一层油不同于第二层材料的一金属材料制成。在一些实施例中，第二层由铜、银或金制成。在一些实施例中，含金属基材层由焊膏、银膏、铟膏或纳米金属墨水制成，且每一高分子颗粒由聚苯乙烯或聚甲基丙烯酸甲酯制成。在一些实施例中，半导体封装体还包括一金属化堆叠层形成于半导体芯片与复合TIM结构之间，其中金属化堆叠层包括一钛层、一铜层、一镍层以及锡与银的合金层。在一些实施例中，半导体芯片具有一第一区及一第二区，且对应于第一区的高分子颗粒的密度不同于对应于第二区的高分子颗粒的密度。在一些实施例中，散热特征部件接合至基底，以形成一腔室位于散热特征部件与基底之间，且其中半导体芯片及复合TIM结构位于腔室内。
在一些实施例中，提供了一种半导体封装体。半导体封装体包括一散热盖以及第一半导体芯片，第一半导体芯片具有一上表面覆盖于散热盖。第一半导体芯片的上表面具有至少一热点区域与热点区域之外的一区域。半导体封装也包括热性连接于第一半导体芯片与散热盖之间的一接合层，以及形成于接合层内的多个核-壳结构。每一核-壳结构包括一高分子核体及一金属壳。热点区域上方的核-壳结构的密度大于热点区域之外的区域上方的核-壳结构的密度。
在一些实施例中，半导体封装体还包括一第二半导体芯片，具有一上表面覆盖于散热盖，使第一半导体芯片及第二半导体芯片具有并排配置。在一些实施例中，半导体封装体还包括一第三半导体芯片叠置于第二半导体芯片下方。在一些实施例中，接合层由焊膏、银膏、铟膏或纳米金属墨水制成，且高分子颗粒由聚苯乙烯或聚甲基丙烯酸甲酯制成。在一些实施例中，金属壳包括一第一层及围绕第一层的一第二层，且其中第一层及第二层由不同的金属材料制成。在一些实施例中，半导体封装体还包括一金属化堆层形成于第一半导体芯片与接合层之间。
在一些实施例中，提供了一种半导体封装体的制造方法。上述方法包括形成一金属化堆叠层于一半导体芯片上。上述方法也包括装设多个高分子颗粒于金属化堆叠层上。每一高分子颗粒涂有第一接合层。上述方法也包括通过回流第一接合层接合一散热盖至半导体芯片。在接合期间，形成一复合热界面材料(TIM)结构于散热盖与半导体芯片之间。复合TIM结构包括第一接合层及埋入第一接合层内的高分子颗粒。
在一些实施例中，第一接合层为一焊膏层，且装设上述高分子颗粒于金属化堆叠层的步骤包括：以焊膏层涂覆金属化堆叠层；以一金属盖层覆盖每一高分子颗粒；放置具有金属盖层的每一高分子颗粒于焊膏层上；以及回流焊膏层。在一些实施例中，金属盖层包括一第一层及围绕第一层的一第二层，且其中第一层由不同于第二层材料的一金属材料制成。在一些实施例中，半导体封装体的制造方法还包括在接合散热盖之前，形成一第二接合层以覆盖第一接合层，其中第二接合层由相同于第一接合层材料相同的一材料制成。在一些实施例中，第一接合层为一焊膏层，且装设上述高分子颗粒于金属化堆叠层的步骤包括：以一助焊层涂覆金属化堆叠层；以一金属盖层及焊膏层按序覆盖每一高分子颗粒；放置具有金属盖层及焊膏层的每一高分子颗粒于助焊层上；以及回流焊膏层。在一些实施例中，半导体芯片的一上表面具有至少一热点区域与热点区域之外的一区域，且其中热点区域上方高分子颗粒的密度大于热点区域之外的区域上方高分子颗粒的密度。
以上概略说明了本发明数个实施例的特征，使所属技术领域中技术人员对于本公开的形态可更为容易理解。任何所属技术领域中技术人员应了解到可轻易利用本公开作为其它工艺或结构的变更或设计基础，以进行相同于此处所述实施例的目的及/或获得相同的优点。任何所属技术领域中技术人员也可理解与上述等同的结构并未脱离本公开的构思和保护范围内，且可在不脱离本公开的构思和范围内，当可作变动、替代与润饰。

Claims (1)

1.一种半导体封装体，包括：
一基底；
一半导体芯片，位于该基底上；
一散热特征部件，位于该基底上方并覆盖该半导体芯片；以及
一复合热界面材料结构，热性接合于该半导体芯片与该散热特征部件之间，其中该复合热界面材料结构包括：
一含金属的基材层；以及
多个高分子颗粒，埋入含金属的基材层内。
CN201910885427.7A 2018-09-19 2019-09-19 半导体封装体 Pending CN110931479A (zh)

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