CN112447615A - 半导体器件封装组件及其制造方法 - Google Patents

半导体器件封装组件及其制造方法 Download PDF

Info

Publication number
CN112447615A
CN112447615A CN202010923426.XA CN202010923426A CN112447615A CN 112447615 A CN112447615 A CN 112447615A CN 202010923426 A CN202010923426 A CN 202010923426A CN 112447615 A CN112447615 A CN 112447615A
Authority
CN
China
Prior art keywords
die attach
molding compound
attach paddle
semiconductor device
device package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010923426.XA
Other languages
English (en)
Inventor
林承園
金正大
全五燮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Publication of CN112447615A publication Critical patent/CN112447615A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49524Additional leads the additional leads being a tape carrier or flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明题为“半导体器件封装组件及其制造方法”。在一个整体方面,半导体器件封装件可包括管芯附接桨叶,该管芯附接桨叶具有第一表面和与第一表面相对的第二表面。封装件还可包括与管芯附接桨叶的第一表面耦接的半导体管芯。封装件还可包括直接键合金属(DBM)衬底。DBM衬底可包括:陶瓷层,陶瓷层具有第一表面和与第一表面相对的第二表面;第一金属层,第一金属层设置在陶瓷层的第一表面上并且与管芯附接桨叶的第二表面耦接;以及第二金属层,第二金属层设置在陶瓷层的第二表面上。第二金属层可暴露于半导体器件封装件的外部。第二金属层可通过陶瓷层与第一金属层电隔离。

Description

半导体器件封装组件及其制造方法
技术领域
本发明整体涉及半导体器件封装组件,诸如具有电隔离的外部热耗散表面的半导体器件封装组件,以及相关联的制造方法。
背景技术
半导体器件封装件的具体实施可包括外部暴露表面(例如,金属表面),该外部暴露表面用于耗散由相关联的(一个或多个)半导体器件的操作产生的热量,其中外部热耗散表面(直接或间接)电连接到半导体器件(管芯)和/或包括在封装件中的半导体器件,诸如通过管芯的表面、管芯附接桨叶(paddle)、金属散热块等。在此类具体实施中,还可使用外部热传递机构(例如,散热器(heatsink)、散热管(heat pipe)等)(结合封装件的散热表面)来耗散半导体器件在操作期间产生的热量,并且热界面材料(TIM)可设置在封装件的外部热耗散表面与外部热传递机构之间。
在此类具体实施中,TIM可在外部热传递机构与封装件的外部暴露的散热表面之间提供电隔离。然而,此类TIM可能不期望地增加一个或多个半导体器件(一个或多个半导体管芯)与外部热传递机构(例如,散热器、散热管等)之间的热阻。此类热阻可称为结沉热阻(Rthj-s)。此类增加的热阻可导致半导体器件(例如,功率半导体器件)的过度加热,这可对半导体器件(或包括半导体器件的系统中的其他部件)造成损坏,并且/或者可缩短器件或相关联的部件的操作寿命(例如,降低器件和/或系统可靠性)。此外,使用此类TIM可至少由于材料成本以及与将TIM与相关联的半导体器件封装件和外部热传递机构耦接相关联的处理操作而增加制造和/或产品成本。
发明内容
在一个整体方面,半导体器件封装件可包括管芯附接桨叶,该管芯附接桨叶具有第一表面和与第一表面相对的第二表面。封装件还可包括与管芯附接桨叶的第一表面耦接的半导体管芯。封装件还可包括第一直接键合金属(DBM)衬底。DBM衬底可包括:陶瓷层,陶瓷层具有第一表面和与第一表面相对的第二表面;第一金属层,第一金属层设置在陶瓷层的第一表面上并且与管芯附接桨叶的第二表面耦接;以及第二金属层,第二金属层设置在陶瓷层的第二表面上。第二金属层可暴露于半导体器件封装件的外部。第二金属层可通过陶瓷层与第一金属层电隔离。
一个或多个具体实施的细节在附随附图和以下描述中阐明。其他特征将从说明书和附图中以及从权利要求书中显而易见。
附图说明
图1是示意性地示出半导体器件封装组件的图。
图2A至图2D是示出半导体器件封装组件和半导体器件封装组件的部件的各种等轴视图的图。
图3A至图3D是示出图2A至图2D的半导体器件封装组件和半导体器件封装组件的部件的侧视图的图。
图4是示出半导体器件封装组件的管芯附接桨叶的图。
图5是示出可包括在半导体器件封装件中的组件的一部分的侧视图的图。
图6是示意性地示出半导体器件封装件和外部散热器的图。
图7是示出一种用于制造半导体器件封装组件(诸如本文所述的那些)的方法的流程图。
在附图中,对于那些元件中的每个元件,可能未示出相同或类似元件的参考标号。另外,来自给定具体实施的一个视图的参考标号在相关视图中可以不重复。此外,在一些情况下,出于比较不同视图的目的,来自给定具体实施的一个视图的参考标号可以在其他视图中重复,但是可以不相对于每个视图进行具体讨论。
具体实施方式
半导体器件组件(例如,半导体器件封装件、封装的半导体器件、封装的器件等),诸如本文所述的那些,可包括管芯附接桨叶、一个或多个半导体管芯(例如,设置在管芯附接桨叶上)、一个或多个信号引线、将该一个或多个半导体管芯和/或该一个或多个信号引线彼此电耦接的一个或多个引线键合、以及隔离衬底。本文所述的示例性具体实施可克服上面讨论的缺点中的至少一些缺点。例如,在一些具体实施中,隔离衬底可包括陶瓷衬底,该陶瓷衬底将外部散热表面(例如,设置在陶瓷衬底上的金属层)与一个或多个半导体管芯、管芯附接桨叶等电隔离。此外,诸如在本文所述的示例性具体实施中,使用隔离衬底可允许消除热界面材料(TIM)、消除TIM相关联的制造操作,并且/或者可减小封装的半导体器件和散热器的整体热阻(例如,Rthj-s)。
图1是示意性地示出半导体器件封装组件(封装件)100的图。如图1所示,封装件100包括管芯附接桨叶(DAP)110、半导体管芯(或多个半导体管芯)120以及隔离衬底130。封装件100还包括信号引线(或多个信号引线)140和引线键合150,其中引线键合150将信号引线140与半导体管芯120电耦接(或可将不同半导体管芯120彼此电耦接,或可将半导体管芯120与DAP 110电耦接)。如图1中进一步所示,封装件100还可包括模塑料160,该模塑料至少部分地包封封装件100的其他元件。
如图1所示,DAP 110具有第一表面112和与第一表面112相对的第二表面114。在封装件100中,半导体管芯120设置在(与其耦接等)DAP 110的第一表面112上。在该示例中,DAP 110具有沿线L1测量的厚度T1,其中线L1正交于DAP 110的第一表面112和第二表面114。在一些具体实施中,DAP 110的厚度T1可大于或等于0.5毫米(mm),这可允许DAP 110有效地吸收(例如,移除等)与半导体管芯120所产生的热量的快速变化(瞬态)相关联的热能。以类似于电路的方式,DAP 110可充当快速移除(存储)由半导体管芯120产生的热量的热电容器(以及热导体),其中所吸收(移除)的热量随后通过隔离衬底130传递到封装件100的外部。
如图1所示,DAP 110可包括突出部(突片、凸缘、伸出部等)116。突出部116可至少部分地围绕DAP 110的周边延伸,诸如在下文所述的图4所示的示例中。在一些具体实施中,可使用金属型锻、压印、蚀刻等形成突出部116。突出部116可例如被构造成充当封装件100的模塑料锁。例如,突出部116可包括与模塑料160接触(形成与该模塑料的界面等)的多个表面,使得突出部116有助于将模塑料160固定(牢固地固定)在封装件100中的适当位置,以便防止模塑料160从DAP 110、从半导体管芯120和/或从隔离衬底130分层。此类分层可例如由于封装件100的元件的相应热膨胀系数(CTE)之间的失配而发生,诸如在DAP 110和模塑料160之间。
另外,在一些具体实施中,为了进一步防止此类分层,可选择包括在DAP 110中的材料以减少此类CTE失配。例如,根据特定具体实施,与其他DAP材料相比,DAP 110可包括铜,铜合金,铝,包括铜、铁和铜的堆叠的熔覆金属结构,包括铜、镍、铁和铜的堆叠的熔覆金属结构等,其中选择包括在DAP 110中的一种或多种材料以便减少DAP 110和例如模塑料160之间的CTE失配。在一些具体实施中,模塑料160可为例如环氧树脂模塑料,但可使用其他模塑料物质。
虽然在下面进一步详细讨论,但是相对于图1简述,在一些具体实施中,隔离衬底130可为耦接到DAP 110的第二表面114(设置在其上等)的直接键合金属(DBM)衬底。如图1所示,隔离衬底130可具有沿线L1测量的厚度T2,其中厚度T2可在例如4.5mm至6.0mm的范围内。同样如图1所示,封装件100的包封的部分可具有同样沿线L1测量的厚度T3,其中厚度T3可在4.5mm至6.0mm的范围内。
如图1所示,在封装件100中,模塑料160包封(例如,完全包封)DAP 110、半导体管芯120和引线键合150。此外,在示例性封装件100中,模塑料160部分地包封隔离衬底130和信号引线140。例如,如图1所示,隔离衬底130具有通过模塑料160暴露的表面(例如,金属、热耗散表面)。另外,信号引线140包括设置在模塑料160内(被其包封)的第一部分140a,以及设置在模塑料160之外(未被其包封)的第二部分140b。
图2A至图2D是示出半导体器件封装组件(封装件)200和封装件200的部件(例如,子元件)的各种等轴视图的图,其中封装件200可为图1中的封装件100的具体实施。图2A和图2B分别从第一侧面(图2A)和第二侧面(图2B)示出了封装件200的等轴视图。如图2A和图2B所示,封装件200包括隔离衬底230、信号引线240和模塑料260。与封装件100一样,模塑料260可至少部分地包封封装件200的元件。例如,如图2A和图2B所示,信号引线240可从模塑料260延伸(例如,可部分地包封在模塑料260中)。
如图2B所示,隔离衬底230可包括通过模塑料260暴露的金属层234。如本文所讨论,金属层234可与封装件200的其他元件诸如DAP、半导体管芯等电隔离。此外,金属层234可为封装件200提供(充当、用作等)热耗散表面。如本文所述,外部热传递器件(机构)诸如散热器或散热管可与金属层234直接耦接(例如,使用焊料材料、烧结料和/或其他导热材料)。与包括TIM的布置(其可被称为间接冷却布置)相比,图6所示的此类构型可被称为直接冷却布置。
参见图2C,示出了组件200a,其中组件200a是不包括隔离衬底230或模塑料260的封装200的子组件。图2D是示出隔离衬底230的图。如图2C所示,组件200包括DAP 210、第一半导体管芯220a、第二半导体管芯220b、信号引线240和引线键合250。如图2C所示,半导体管芯220a和220b使用焊料或其他适当的管芯附接材料(诸如导电环氧树脂)设置在DAP 210上(与其耦接)。
另外如图2C所示,DAP 210包括突出部216,该突出部可被构造成(如与封装件100的突出部116一样)用作模塑料锁。如图2C所示,组件200a还包括引线键合,该引线键合将信号引线240与半导体管芯220a和220b电耦接,以及将半导体管芯220a与半导体管芯220b电耦接。
图2D示出了与封装件200分开的隔离衬底230。如图2D所示,隔离衬底230可包括非导电(例如,陶瓷)层232和金属层234,如图2B所示,该金属层可通过封装件200的模塑料260暴露以提供热耗散表面。如本文所述,隔离衬底230可为直接键合金属(DBM)衬底,诸如直接键合铜(DBC)衬底,如下文相对于例如图3B进一步详细描述的。在一些具体实施中,金属层234可以设置在非导电(例如,陶瓷)层232的表面(例如,图3B中所示的表面232a)的至少一部分(例如,大于90%)以上。
图3A至图3D是示出图2A至图2D中所示的封装件200的组件200a和部件的侧视图的图。例如,图3A示出了组件200a的侧视图,其中仅示出了信号引线240的一部分,如切割线所示。如图3A所示,半导体管芯220a和220b与DAP 210(例如,DAP 210的第一表面)耦接。在一些具体实施中,DAP 210可具有厚度诸如厚度T1,如上文相对于封装件100的DAP 110所讨论的。
另外如图3A所示,引线键合250提供信号引线240与半导体管芯220a和220b之间的电连接,以及半导体管芯220a与半导体管芯220b之间的电连接。另外如图3A所示,DAP 210的突出部216可围绕DAP 210的至少一部分延伸。
参见图3B,示出了隔离衬底230的示例。如上所述,隔离衬底230可为DBM衬底,诸如DBC衬底。如图3B所示,隔离衬底230可包括具有第一表面232a以及与第一表面232a相对的第二表面232b的非导电(例如,陶瓷)层232。图3B中的隔离衬底230的金属(例如,铜)层234设置在层232的第一表面232a上。在一些具体实施中,非导电(例如,陶瓷)层232可包括氧化铝(Al2O3)、氮化铝(AlN)或氮化硅(SiN)中的至少一者。
如图3B中进一步所示,隔离衬底230包括设置在非导电(例如,陶瓷)层232的第二表面232b上的另一金属(例如,铜)层236。类似于表面232a上的金属层234,金属层236可设置在非导电(例如,陶瓷)层232的表面232b的至少一部分(例如,大于90%)以上。在该示例中,并且在本文所述的其他示例性具体实施中,非导电层(例如,陶瓷层)232将两个金属层234和236彼此电隔离,使得外部暴露的金属层234与耦接到DAP 210的金属层236电隔离。在一些具体实施中,隔离衬底230可具有厚度诸如厚度T2,如上文相对于封装件100的隔离衬底130所讨论的。
图3C示出了图2A中所示的组件200a的部分,其中隔离衬底230与DAP 210耦接,例如,在DAP 210的与半导体管芯220a和220b耦接到的DAP 210的表面相对的表面上,从而形成组件200(没有模塑料260)。在一些具体实施中,可使用焊料材料将隔离衬底与DAP 210耦接。在其他具体实施中,其他导热和/或导电粘合剂材料可用于将隔离衬底230与DAP 210耦接。
图3D是示出组件200的如图3C所示在用于将组件200的部分包封在模塑料260中的模塑操作之后的一部分的图,如图3D的示例性具体实施所示。出于说明的目的,在图3D中仅示出了模塑料260的轮廓,使得在图3D中可看到模塑料260内部(设置在该模塑料内、由该模塑料包封等)的组件200的元件。
如图3D所示,DAP 210的突出部216、DAP 210在突出部216和隔离衬底230之间的部分210a形成台阶218,该台阶限定在隔离衬底230和DAP 210的突出部216之间的开口238(例如,腔体、凹陷区域)。即,突出部216和隔离衬底可从DAP 210的部分210a延伸(突出等)以形成开口238。在一些具体实施中,诸如该示例,开口238可围绕DAP 210的周边延伸。如图3D所示,由突出部216、台阶218、DAP 210(例如,部分210a)和隔离衬底230形成的开口238可改善模塑料锁定(例如,由于模塑料延伸到开口238中),并且因此降低模塑料260从组件200分层的风险。模塑料锁定的该进一步改善可进一步降低模塑料分层的风险。
另外如图3D所示,金属层234可通过模塑料暴露。在一些具体实施中,热耗散机构(例如,散热器等)可与金属层234耦接(例如,焊接到该金属层等)以耗散在组件200的操作期间产生的热量。在该示例中,热耗散机构将通过隔离衬底230的非导电层232与组件200的内部元件电隔离。
图4是示出半导体器件封装组件的DAP的图,在该示例中,该图示出了封装件200的DAP 210。图4还示出了封装件200的信号引线240的一部分,例如示出它们相对于DAP 210的相对布置。如图4所示,突出部216围绕DAP的整个周边延伸。如图4所示,示出了在封装件200中与隔离衬底230耦接的DAP 210的表面。图4中未示出半导体管芯220a和220b耦接在其上的DAP 210的表面,因为它将位于DAP 210的下侧,如图所示。
图5是示出可包括在半导体器件封装件(封装件)诸如封装件200中的组件500a的一部分的侧视图的图。在图5中的组件500a的图示中,未具体示出信号引线,但在一些具体实施中,信号引线可包括在包括组件500a的半导体器件封装件中。
类似于图2C、图3A和图3C中的组件200a,组件500a包括DAP 520、半导体管芯520、隔离衬底(例如DBM衬底或DBC衬底)530以及引线键合550。如图5所示,其未相对于封装件100或200示出,引线键合550中的一个或多个引线键合可用于将半导体管芯520与DAP 510电耦接。
另外如图5所示,DAP 510包括突出部516,诸如DAP 210的突出部216。在组件500a中,DAP 510包括在隔离衬底530和DAP 510的突出部516之间形成开口538的台阶518,类似于上文所讨论的DAP 210的突出部216和封装件200的隔离衬底230的布置(例如,台阶)。如图5所示,由台阶518、DAP 510和隔离衬底530形成的开口可与突出部516结合,进一步改善模塑料锁定(尽管模塑料未在图5中具体示出)。模塑料锁定的该进一步改善可进一步降低模塑料分层的风险。另外如图5所示,组件500a包括用于将隔离衬底530耦接到DAP 510的焊料(或其他粘合剂材料)。
图6是示意性地示出包括半导体器件封装件(封装件)600和外部散热器620的组件的图。以举例的方式,封装件600可为上文所讨论的封装件100或200的具体实施。如图6所示,散热器620能够以直接冷却构型耦接到封装件600(例如,耦接到隔离衬底的暴露的金属层)。例如,在图6的示例中,散热器620使用导热和/或导电材料610直接耦接到封装件600。在一些具体实施中,材料610可为焊接材料、烧结材料等。在一些具体实施中,与具有间接冷却布置(例如,使用TIM)的类似组件相比,图6的组件可具有减小75%或更多的热阻Rthj-s
图7是示出一种用于制造半导体器件封装组件(诸如本文所述的那些)的方法700的流程图。出于说明的目的,并且以举例的方式,将进一步参考例如图2A至图2D所示的封装件200以及图6所示的组件来描述方法700。然而,方法700可用于生产具有其他构型或布置的半导体器件封装件和/或组件。
如图7所示,方法700包括(参考封装件200)在框710处将半导体管芯220a和220b附接(耦接)到DAP 210。在框720处,方法700包括在框710处在隔离衬底(例如,DBM或DBC)210上和/或在DAP 210的与半导体管芯220a和220b耦接到的DAP 210的表面相对的表面上执行焊料印刷。在框730处,方法700包括执行焊料回流操作以使用框720的焊料印刷将隔离衬底230与管芯附接桨叶耦接。在框740处,方法700包括形成引线键合,诸如本文所述的引线键合(例如,引线键合150、250和/或550)。在框750处,方法700包括执行模塑(包封)操作以包封(例如,完全或部分地)封装件200的元件,诸如在本文所述的示例性布置中。在框760处,可对封装的半导体器件200执行修整(例如,去毛刺、去毛边、电镀、切割等)和电测试操作。在框770处,能够以直接冷却布置将散热器附接到封装件200,诸如图6中所示和相对于该图所述。
将理解,在前述描述中,当元件被提及为在另一个元件上、连接到另一个元件、电连接到另一个元件、耦接到另一个元件或电耦接到另一个元件时,该元件可以是直接地在另一个元件上、连接或耦接到另一个元件,或可以存在一个或多个中间元件。相反,当元件被提及直接在另一个元件上、直接连接到另一个元件、或直接耦接到另一个元件时,不存在中间元件。虽然在整个具体实施方式中可能不会使用术语直接在…上、直接连接到…、或直接耦接到…,但是被示为直接在元件上、直接连接或直接耦接的元件能以此类方式提及。本申请的权利要求书(如果存在的话)可被修订以叙述在说明书中描述或者在附图中示出的示例性关系。
如在本说明书中所使用的,除非根据上下文明确地指出特定情况,否则单数形式可包括复数形式。除了附图中所示的取向之外,空间相对术语(例如,在…上方、在…上面、在…之上、在…下方、在…下面、在…之下、在…之以下等)旨在涵盖器件在使用或操作中的不同取向。在一些具体实施中,在…上面和在…下面的相对术语可分别包括竖直地在…上面和竖直地在…下面。在一些具体实施中,术语邻近能包括横向邻近或水平邻近。
本文所述的各种技术的具体实施可在数字电子电路中、计算机硬件、固件、软件中或它们的组合中实现(例如,包括在其中)。一些具体实施可使用各种半导体处理和/或封装技术来实现。一些具体实施可使用与半导体基板相关联的各种类型的半导体处理技术来实现,该半导体基板包含但不限于,例如硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、碳化硅(SiC)等。
虽然所描述的具体实施的某些特征已经如本文所述进行了说明,但是本领域技术人员现在将想到许多修改形式、替代形式、变化形式和等同形式。因此,应当理解,所附权利要求书旨在涵盖落入具体实施的范围内的所有此类修改形式和变化形式。应当理解,这些修改形式和变化形式仅仅以举例而非限制的方式呈现,并且可以进行形式和细节上的各种变化。除了相互排斥的组合以外,本文所述的装置和/或方法的任何部分可以任意组合进行组合。本文所述的具体实施能包括所描述的不同具体实施的功能、部件和/或特征的各种组合和/或子组合。

Claims (12)

1.一种半导体器件封装件,包括:
管芯附接桨叶,所述管芯附接桨叶具有第一表面和与所述第一表面相对的第二表面;
半导体管芯,所述半导体管芯与所述管芯附接桨叶的所述第一表面耦接;和
直接键合金属衬底,所述直接键合金属衬底包括:
陶瓷层,所述陶瓷层具有第一表面和与所述第一表面相对的第二表面;
第一金属层,所述第一金属层设置在所述陶瓷层的所述第一表面上并且与所述管芯附接桨叶的所述第二表面耦接;和
第二金属层,所述第二金属层设置在所述陶瓷层的所述第二表面上并且暴露于所述半导体器件封装件的外部,所述第二金属层通过所述陶瓷层与所述第一金属层电隔离。
2.根据权利要求1所述的半导体器件封装件,还包括:
至少一个信号引线;
引线键合,所述引线键合将所述至少一个信号引线中的信号引线与所述半导体管芯电耦接;和
模塑料,所述模塑料:
包封所述管芯附接桨叶、所述半导体管芯和所述引线键合;以及
部分地包封所述DBM衬底和所述信号引线,
所述第二金属层通过所述模塑料暴露,
所述信号引线的第一部分设置在所述模塑料内,并且
所述信号引线的第二部分设置在所述模塑料之外。
3.根据权利要求1所述的半导体器件封装件,还包括散热器,
所述散热器使用焊料材料或烧结材料中的一者直接耦接到所述第二金属层,并且
所述第一金属层使用焊料材料与所述管芯附接桨叶的所述第二表面耦接。
4.根据权利要求1所述的半导体器件封装件,其中所述管芯附接桨叶具有大于或等于0.5毫米的厚度,所述厚度沿从所述管芯附接桨叶的所述第一表面正交地延伸到所述管芯附接桨叶的所述第二表面的线。
5.根据权利要求1所述的半导体器件封装件,其中所述第一金属层和所述第二金属层分别设置在所述陶瓷层的所述第一表面的至少90%以上和所述陶瓷层的所述第二表面的至少90%以上。
6.根据权利要求1所述的半导体器件封装件,其中所述管芯附接桨叶包括围绕所述管芯附接桨叶的周边延伸的突出部,使得所述管芯附接桨叶的台阶限定在所述突出部与所述DBM衬底之间,
所述半导体器件封装件还包括模塑料,所述模塑料包封所述管芯附接桨叶和所述半导体管芯,所述突出部具有与所述模塑料接触的至少一个表面。
7.一种半导体器件封装件,包括:
管芯附接桨叶,所述管芯附接桨叶具有第一表面和与所述第一表面相对的第二表面;
半导体管芯,所述半导体管芯与所述管芯附接桨叶的所述第一表面耦接;
多个信号引线;
至少一个引线键合,所述至少一个引线键合将所述多个信号引线中的信号引线与所述半导体管芯电耦接;
直接键合铜衬底,所述直接键合铜衬底包括:
陶瓷层,所述陶瓷层具有第一表面和与所述第一表面相对的第二表面;
第一铜层,所述第一铜层设置在所述陶瓷层的所述第一表面上并且与所述管芯附接桨叶的所述第二表面耦接;和
第二铜层,所述第二铜层设置在所述陶瓷层的所述第二表面上并且暴露于所述半导体器件封装件的外部,所述第二铜层通过所述陶瓷层与所述第一铜层电隔离;以及
模塑料,所述模塑料:
包封所述管芯附接桨叶、所述半导体管芯和所述至少一个引线键合;以及
部分地包封所述DBC衬底和所述多个信号引线,
所述第二铜层通过所述模塑料暴露,
所述多个信号引线中的每个信号引线的相应第一部分设置在所述模塑料内,并且
所述多个信号引线中的每个信号引线的相应第二部分设置在所述模塑料之外。
8.根据权利要求7所述的半导体器件封装件,其中所述管芯附接桨叶包括围绕所述管芯附接桨叶、桨叶的周边延伸的突出部,使得所述管芯附接桨叶的台阶限定在所述突出部与所述DBC衬底之间,
所述半导体器件封装件还包括包封所述管芯附接桨叶、所述半导体管芯和所述至少一个引线键合的模塑料,
所述突出部具有与所述模塑料接触的至少一个表面。
9.一种用于生产半导体器件封装件的方法,所述方法包括:
将半导体管芯与管芯附接桨叶的第一表面耦接;以及
将直接键合金属衬底与所述管芯附接桨叶的第二表面耦接,所述第二表面与所述第一表面相对,
所述DBM衬底包括:
陶瓷层,所述陶瓷层具有第一表面和与所述第一表面相对的第二表面;
第一金属层,所述第一金属层设置在所述陶瓷层的所述第一表面上,所述第一金属层与所述管芯附接桨叶的所述第二表面耦接;和
第二金属层,所述第二金属层设置在所述陶瓷层的所述第二表面上,所述第二金属层通过所述陶瓷层与所述第一金属层电隔离。
10.根据权利要求9所述的方法,其中将所述DBM衬底与所述管芯附接桨叶的所述第二表面耦接包括:将所述DBM衬底的所述第一金属层焊接到所述管芯附接桨叶的所述第二表面。
11.根据权利要求9所述的方法,还包括:形成引线键合以将所述半导体器件封装件的信号引线电连接到所述半导体管芯。
12.根据权利要求11所述的方法,还包括执行模塑操作以:
将所述管芯附接桨叶、所述半导体管芯和所述引线键合包封在模塑料中;以及
将所述DBM衬底和所述信号引线部分地包封在所述模塑料中,
所述第二金属层通过所述模塑料暴露,
所述信号引线的第一部分设置在所述模塑料内,并且
所述信号引线的第二部分设置在所述模塑料之外。
CN202010923426.XA 2019-09-04 2020-09-04 半导体器件封装组件及其制造方法 Pending CN112447615A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962895877P 2019-09-04 2019-09-04
US62/895,877 2019-09-04
US16/668,401 US11521921B2 (en) 2019-09-04 2019-10-30 Semiconductor device package assemblies and methods of manufacture
US16/668,401 2019-10-30

Publications (1)

Publication Number Publication Date
CN112447615A true CN112447615A (zh) 2021-03-05

Family

ID=74680090

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010923426.XA Pending CN112447615A (zh) 2019-09-04 2020-09-04 半导体器件封装组件及其制造方法

Country Status (2)

Country Link
US (1) US11521921B2 (zh)
CN (1) CN112447615A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240162110A1 (en) 2022-11-10 2024-05-16 Semiconductor Components Industries, Llc Semiconductor device package assemblies and methods of manufacture

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404065B1 (en) * 1998-07-31 2002-06-11 I-Xys Corporation Electrically isolated power semiconductor package
KR100335480B1 (ko) * 1999-08-24 2002-05-04 김덕중 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지
KR101505551B1 (ko) * 2007-11-30 2015-03-25 페어차일드코리아반도체 주식회사 온도 감지소자가 장착된 반도체 파워 모듈 패키지 및 그제조방법
KR101321282B1 (ko) * 2011-06-17 2013-10-28 삼성전기주식회사 전력 모듈 패키지 및 이를 구비한 시스템 모듈
US8987777B2 (en) * 2011-07-11 2015-03-24 International Rectifier Corporation Stacked half-bridge power module
KR101222831B1 (ko) * 2011-09-16 2013-01-15 삼성전기주식회사 전력 모듈 패키지
KR101555301B1 (ko) * 2014-05-13 2015-09-23 페어차일드코리아반도체 주식회사 반도체 패키지
KR102008278B1 (ko) * 2017-12-07 2019-08-07 현대오트론 주식회사 파워칩 통합 모듈과 이의 제조 방법 및 양면 냉각형 파워 모듈 패키지

Also Published As

Publication number Publication date
US20210066174A1 (en) 2021-03-04
US11521921B2 (en) 2022-12-06

Similar Documents

Publication Publication Date Title
CN111446217B (zh) 半导体装置
US6330158B1 (en) Semiconductor package having heat sinks and method of fabrication
KR102585450B1 (ko) 브레이징된 전기 전도성 층을 포함하는 칩 캐리어를 구비한 몰딩된 패키지
JP2548350B2 (ja) テープ自動結合に使用される熱放散相互接続テープ
US6261868B1 (en) Semiconductor component and method for manufacturing the semiconductor component
US9263375B2 (en) System, method and apparatus for leadless surface mounted semiconductor package
US8053876B2 (en) Multi lead frame power package
US7005734B2 (en) Double-sided cooling isolated packaged power semiconductor device
US20120175755A1 (en) Semiconductor device including a heat spreader
CN110392924B (zh) 半导体装置
CN109637983B (zh) 芯片封装
US5299091A (en) Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same
US9466588B2 (en) Method and apparatus for multi-chip structure semiconductor package
US20240096734A1 (en) Leadframe spacer for double-sided power module
CN218730875U (zh) 垂直型功率器件封装结构和电子装置
US11380601B2 (en) Semiconductor device and method for manufacturing semiconductor device
KR102199360B1 (ko) 반도체 패키지
EP3739624A1 (en) Semiconductor arrangement with a compressible contact element encapsulated between two carriers and corresponding manufacturing method
CN114005812A (zh) 一种扇出型封装结构及其构造方法
JP2003282751A (ja) 高周波用パッケージならびに高周波用パワーモジュール基板及びその製造方法
CN112447615A (zh) 半导体器件封装组件及其制造方法
US20230253393A1 (en) Dual cool power module with stress buffer layer
JP2012049224A (ja) 実装構造体および実装構造体の製造方法
JP2018116960A (ja) 電力用半導体装置
US20240162110A1 (en) Semiconductor device package assemblies and methods of manufacture

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination