WO2021182149A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2021182149A1
WO2021182149A1 PCT/JP2021/007655 JP2021007655W WO2021182149A1 WO 2021182149 A1 WO2021182149 A1 WO 2021182149A1 JP 2021007655 W JP2021007655 W JP 2021007655W WO 2021182149 A1 WO2021182149 A1 WO 2021182149A1
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Prior art keywords
semiconductor element
semiconductor device
heat
resistant resin
via hole
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PCT/JP2021/007655
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French (fr)
Japanese (ja)
Inventor
創一 坂元
洋暁 一戸
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三菱電機株式会社
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Priority to JP2022505924A priority Critical patent/JP7162775B2/en
Publication of WO2021182149A1 publication Critical patent/WO2021182149A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Definitions

  • the present application relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • a semiconductor element such as a silicon semiconductor or a compound semiconductor is mounted on a semiconductor device for high-frequency communication. Electrodes are formed on the back surface of these semiconductor elements by metallizing, and in the case of a general semiconductor device, the back surface electrodes and the package are bonded by a bonding material such as solder or a conductive paste. These bonding materials are a path for releasing the heat generated by the semiconductor element to a cooling mechanism such as a heat sink, and as described above, high thermal conductivity is desired in order to efficiently release the increasingly increasing heat generation.
  • Sintered bonding can be performed at a temperature much lower than the metal melting point by utilizing the particle size effect or the reaction of organic components and solvents that coat the particle surface, and after sintering, it becomes a bulk metal. It is characterized by having similar thermal conductivity and heat resistance. Conventionally, a via hole has been used to electrically connect an electrode pad on the surface of a semiconductor element and a ground (GND).
  • the metal foil of the via hole electrode may be broken or cracked due to the difference in expansion coefficient due to the entry of the bonding material for die bonding of the semiconductor element into the beer hole.
  • the via hole has been covered with a protective film that prevents the solder from getting wet (see, for example, Patent Document 1).
  • the present application discloses a technique for solving the above-mentioned problems, and provides a semiconductor device and a method for manufacturing the semiconductor device, which can prevent the shape around the via hole from being deformed and suppress a decrease in reliability.
  • the purpose is to do.
  • the semiconductor device disclosed in the present application includes a semiconductor element in which a via hole is formed between a front surface electrode and a back surface electrode provided on the opposite side of the front surface electrode, and a heat-resistant resin that covers the back surface electrode side of the via hole.
  • the method for manufacturing a semiconductor device disclosed in the present application includes a step of preparing a semiconductor element in which a via hole is formed between a front surface electrode and a back surface electrode provided on the opposite side of the front surface electrode, and the step of preparing the via hole.
  • the present invention includes a step of joining the semiconductor element and the base material with a bonding layer containing the metal sintered material as a main component by heating the metal sintered material paste.
  • a method for manufacturing a semiconductor device and a semiconductor device that can prevent the shape around the via hole from being deformed and suppress a decrease in reliability can be obtained.
  • FIG. It is a top view which shows the semiconductor device by Embodiment 1.
  • FIG. It is a top view which shows the internal structure of the semiconductor device according to Embodiment 1.
  • FIG. It is sectional drawing of the line AA of FIG.
  • FIG. It is a top view which shows the back surface of the semiconductor element of the semiconductor device according to Embodiment 1.
  • FIG. It is sectional drawing of BB line of FIG.
  • FIG. It is an enlarged sectional view around the via hole of the semiconductor device according to Embodiment 1.
  • FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1.
  • FIG. It is a top view which shows the back surface of the semiconductor element of the semiconductor device by Embodiment 2.
  • FIG. 1 is a plan view showing a semiconductor device according to the first embodiment.
  • FIG. 2 is a plan view showing the internal structure of the semiconductor device according to the first embodiment, and shows the internal structure of the semiconductor device 110 from which the sealing resin 5 is removed from the semiconductor device 110 of FIG.
  • FIG. 3 is a cross-sectional view taken along the line AA of FIG.
  • a semiconductor element 1 made of silicon (Si) is mounted on the upper surface of a heat sink 6 made of copper (Cu) via a bonding layer 15.
  • a plurality of via holes 12 are formed in the semiconductor element 1.
  • the bonding layer 15 is obtained by sintering a metal sintered material paste 15a such as a silver (Ag) sintered material to obtain a metal sintered material.
  • the heat sink 6 and the semiconductor element 1 are connected via a bonding layer 15.
  • a circuit board 2 for matching high-frequency characteristics is connected to a heat sink 6 via a bonding layer 15.
  • the circuit board 2 is, for example, a microwave integrated circuit (MIC) substrate in which a thin film pattern is processed on a ceramic substrate.
  • the electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected by a bonding wire 3.
  • the electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected to the reed 4 by the bonding wire 3, respectively.
  • the electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected to an external substrate (not shown) via bonding wires 3 and leads 4, respectively.
  • the semiconductor element 1 and the circuit board 2 are covered with, for example, a sealing resin 5 by a transfer mold in order to isolate from the influence of external moisture, contamination, heat, electromagnetic field, etc. and to secure the insulating property.
  • FIG. 4A is a plan view showing the back surface of the semiconductor element of the semiconductor device according to the first embodiment. Further, FIG. 4B is a cross-sectional view taken along the line BB of FIG.
  • a conductive layer 14 such as a gold (Au) plating layer is formed on the back surface of the semiconductor element 1 and the surface layer of the via hole 12.
  • the electrode pad 7 and the heat sink 6 are connected by a conductive layer 14 formed on the surface layer of the via hole 12.
  • the conductive layer 14 is formed by subjecting the entire back surface of the semiconductor element 1 to, for example, gold (Au) plating, and forming an Au layer inside the via hole 12 which is an opening.
  • the heat sink 6 and the conductive layer 14 such as the gold (Au) plating layer formed on the back surface of the semiconductor element 1 are connected via the bonding layer 15.
  • the solder filled inside the via hole crawls up to the surface of the electrode pad when heated. Therefore, in order to prevent the solder from crawl up, the Au plating layer, which is a conductor layer, is used.
  • a barrier metal such as a nickel film was further formed on the surface layer.
  • a joining method using a metal sintered material having excellent heat resistance has been studied, and in that case, the metal sintered material paste and the barrier metal such as a nickel film are incompatible with each other, and it may be difficult to perform sintering bonding. I know. As a result, there is a problem that the shape of the joint portion around the via hole is deformed and cracks are generated starting from the deformed joint portion during the temperature cycle test.
  • the Au plating layer may peel off due to heat shrinkage during heat sintering, or the semiconductor element may crack in some cases. There was a problem that occurred.
  • the heat-resistant resin 13 is formed in a bump shape on the back electrode 16 side of the semiconductor element 1 to heat-heat the back electrode 16 side of the via hole 12. It is covered with the sex resin 13. That is, the heat-resistant resin 13 is provided as a heat-resistant resin bump on the back surface electrode 16 side of the via hole 12, and is also filled inside the via hole 12.
  • the heat-resistant resin 13 is a resin having heat resistance that does not melt at the operating temperature of the semiconductor device 110, such as an epoxy-based resin that has a relatively high Young's modulus and is a hard resin, or a silicone-based resin that is relatively soft and can absorb deformation due to thermal stress. All you need is.
  • the heat-resistant resin 13 can be appropriately selected in consideration of the glass transition temperature, the wetting of the semiconductor element 1 with the back surface electrode 16, and the like. Further, as the heat-resistant resin 13, a heat-resistant resin containing metal particles may be used. In this case, the metal particles inside the via hole 12 and the metal sintered material paste 15a serving as the bonding layer 15 are sintered and bonded, so that a further effect of improving the bondability can be expected.
  • FIGS. 5A and 5B are enlarged cross-sectional views of the periphery of the via hole of the semiconductor device according to the first embodiment.
  • the heat-resistant resin 13 and the metal sintered material paste 15a are basically not sintered and joined. Therefore, as the angle of contact between the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 becomes 30 degrees or less, the unbonded region becomes like a cut between the back electrode 16 of the semiconductor element 1 and the metal sintered material paste 15a. It affects the temperature cycle life.
  • FIG. 1 As shown in FIG.
  • the heat-resistant resin 13 is formed in a bump shape so that the angle ⁇ 1 at which the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 come into contact with each other is larger than 30 degrees.
  • the angle ⁇ 1 is an angle at which the tangent line 17 and the back surface electrode 16 at the end of the heat-resistant resin 13 intersect.
  • the angle ⁇ 2 is an angle at which the tangent line 17 and the back surface electrode 16 at the end of the heat-resistant resin 13 intersect.
  • the heat-resistant resin 13 is formed so that the angle ⁇ 2 is 90 degrees or more, it is necessary to select a resin material that easily gets wet with the back electrode 16 of the semiconductor element 1. Further, since the height H2 of the protruding portion is reduced, the role of the protruding portion as a spacer is reduced.
  • the angle ⁇ 1 or the angle ⁇ 2 at which the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 come into contact with each other may be determined in consideration of the film thickness of the bonding layer 15 required for various uses of the semiconductor device 110.
  • the heat-resistant resin 13 may at least cover the opening of the via hole 12 to which the stress due to heat shrinkage during sintering is most applied. However, the more the heat-resistant resin 13 is filled inside the via hole 12, the more the heat-resistant resin 13 relaxes the thermal stress during the temperature cycle. Therefore, it is more desirable that the inside is filled with the heat-resistant resin 13.
  • FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment.
  • the heat-resistant resin 13 is formed by applying and curing the heat-resistant resin on the back surface of the semiconductor element 1 with a dispensing device or the like.
  • the metal sintered material paste 15a is applied onto the surface of the heat sink 6 by a dispensing device or printing, and the semiconductor element 1 prepared in 6A is applied onto the metal sintered material paste 15a. It is sintered by mounting it on a device and heating it to 200 ° C. or higher.
  • the bonding layer 15 is formed on the heat sink 6.
  • the circuit board 2 which is an electronic component, the semiconductor element 1, and the lead 4 for external connection are electrically connected by the bonding wire 3. Finally, the resin is sealed by a transfer mold. Through the above process, the semiconductor device 110 of the first embodiment is manufactured.
  • the heat sink 6 is not limited to the one made of copper (Cu) as long as it has a function of dissipating heat generated by the operation of the semiconductor element 1. ..
  • the heat sink 6 iron, tungsten, molybdenum, nickel, cobalt, alloys thereof, or a composite material thereof may be used.
  • the heat sink material having high thermal conductivity the heat generated from the semiconductor element 1 can be efficiently released to the outside, and the thermal stress strain applied to the bonding layer 15 can be reduced.
  • the shape of the heat sink 6 may be a square pillar, a polygonal pillar, a cylinder, an elliptical pillar, or a shape in which a step is provided in a part thereof.
  • a heat sink 6 made of tungsten having a thermal expansion coefficient relatively close to that of the semiconductor element 1 is mounted on a heat sink 6 made of copper (Cu) having a larger thermal expansion coefficient than that of the semiconductor element 1.
  • the mismatch of the thermal expansion coefficient between the element 1 and the heat sink 6 immediately below the element 1 can be reduced, and the thermal stress strain applied to the bonding layer 15 can be reduced.
  • the heat sink 6 is plated with gold (Au), it may be metal-plated which is compatible with each metal sintered material other than gold (Au), and is a heat sink made of copper (Cu).
  • Metal plating may not be required as long as the bondability with 6 can be ensured. Further, in the first embodiment, the case where the semiconductor element 1 is mounted on a base material such as a heat sink 6 is shown, but it may be mounted on a base material such as an insulating substrate. Further, if it is necessary to improve the adhesion with the sealing resin 5, roughened rough plating or the like may be applied to the metal plating surface.
  • gallium arsenide GaAs
  • gallium nitride GaN
  • has various merits such as high electron speed, high breakdown voltage due to wide bandgap, high power operation, wide operation bandwidth, and high temperature operation, resulting in miniaturization and cost reduction. ..
  • the semiconductor element 1 for high-frequency communication having different lengths of the long side and the short side is shown as an example, but the semiconductor element 1 having the same length of the long side and the short side is used. You may. Further, in the semiconductor device 110 according to the first embodiment, an example in which one semiconductor element 1 is mounted is shown, but a plurality of semiconductor elements 1 may be mounted, and gallium nitride (GaN) and gallium arsenal may be mounted. Different semiconductor elements 1 such as id (GaAs) may be combined. Further, in the semiconductor device 110 according to the first embodiment, an example in which the circuit board 2 is mounted is shown, but at least the semiconductor element 1 may be mounted. Further, similarly to the semiconductor element 1, a plurality of circuit boards 2 having different shapes or different sizes may be mounted in order to match the high frequency characteristics.
  • the metal sintered material paste 15a having a higher thermal conductivity than the conventional solder is effective.
  • the metal sintered material paste 15a generally has submicron, nano-sized or mixed metal particles, a protective film covering the particle surface, and a solvent for dispersing the particles. In addition to spheres, there are various shapes such as flakes or spheres covered with needles. When sintered at a low temperature of about 200 ° C., the protective film or solvent is completely volatilized to form a bonding layer 15 containing only neck-sintered metal particles. Therefore, it has thermal conductivity and heat resistance close to those of bulk metal.
  • the required sintering temperature varies depending on the size of the metal particles, the sintering accelerator contained in the paste, and the like, and sintering at room temperature is also possible.
  • the sintering of metal particles or the sintering of metal particles and an object to be joined progresses depending on the sintering temperature and the sintering time. Therefore, the joining reliability required for various applications of the semiconductor device 110 is required.
  • the sintering process may be determined in consideration of.
  • the metal sintered material paste 15a includes a silver (Ag) sintered material, a copper (Cu) sintered material, a gold (Au) sintered material, a palladium (Pd) sintered material, a platinum (Pt) sintered material, and the like.
  • Sintered materials based on metals classified as precious metals sintered materials based on metal particles classified other than precious metals such as nickel (Ni) sintered materials, silver oxide sintered materials, copper oxide sintered materials Sintered material that obtains a sintering reaction by reducing fine oxides such as, etc.
  • metal fine particles silver (Ag) -palladium (Pd) sintered material, gold (Au) -silicon (Si) sintered material ,
  • a sintered material paste based on an alloy such as a gold (Au) -germanium (Ge) sintered material or a gold (Au) -copper (Cu) sintered material may be used.
  • the thickness of the bonding layer 15 is preferably 30 ⁇ mt or more, and the life for the temperature cycle test can be further improved.
  • the bonding layer 15 thicker, it is possible to further improve the life for the temperature cycle test, but even though the metal sintered material paste 15a having a high thermal conductivity (200 W / mK or more) is used. Since the thermal resistance and the member cost increase by increasing the thickness of the bonding layer 15, the thickness may be determined in consideration of the thermal design of the semiconductor device 110. Further, the film thickness of the heat-resistant resin 13 formed on the back surface electrode 16 side may be 1/10 or more of the thickness of the semiconductor element 1.
  • the semiconductor device 110 according to the first embodiment is covered with the sealing resin 5 such as the semiconductor element 1, it may have a hollow structure in which a ceramic cap, a metal cap, or the like is adhered and joined.
  • the sealing resin 5 having a high dielectric constant does not exist on the surface of the semiconductor element 1, and high high frequency characteristics can be obtained.
  • the semiconductor device 110 according to the first embodiment is the semiconductor element 1 in which the via hole 12 is formed between the front surface electrode such as the electrode pad 7 and the back surface electrode 16 provided on the opposite side of the front surface electrode.
  • a heat-resistant resin 13 that covers the back surface electrode 16 side of the via hole 12, a base material such as a heat sink 6 on which the semiconductor element 1 is mounted, and a metal sintered material as a main component, the semiconductor element 1 and the base material. It has a bonding layer 15 and a bonding layer 15 for bonding.
  • a semiconductor element 1 in which a via hole 12 is formed between a front surface electrode such as an electrode pad 7 and a back surface electrode 16 provided on the opposite side of the front surface electrode is prepared.
  • the semiconductor device 110 can suppress peeling of the conductive layer 14 or cracking of the semiconductor element 1 due to heat shrinkage during heat sintering, and also suppresses the protrusion portion of the heat-resistant resin 13.
  • the protruding portion acts as a spacer, the thickness of the bonding layer 15 can be secured, and the life for the temperature cycle test can be improved.
  • FIG. 7 is a plan view showing the back surface of the semiconductor element of the semiconductor device according to the second embodiment.
  • the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.
  • the structure in which the via hole 12 covered with the heat-resistant resin 13 is provided in the center of the semiconductor element 1 is illustrated, but the positions where the via hole 12 and the heat-resistant resin bump are formed are not limited to this. No.
  • the via hole 12 covered with the heat-resistant resin 13 is the center of the semiconductor element 1 and the entire circumference of the outer peripheral end surface of the semiconductor element 1. Is formed in.
  • the arrangement shown in 7A of FIG. 7 forms the largest number of via holes 12 and heat-resistant resin bumps, the thickness of the bonding layer 15 can be secured most reliably, and the in-plane height of the semiconductor element 1 can be secured. The variation can be minimized. Therefore, the semiconductor device 110 on which the semiconductor element 1 shown in 7A of FIG. 7 is mounted can stably obtain high reliability.
  • the metal sintered material paste 15a when the metal sintered material paste 15a is applied to a base material such as a heat sink 6 by a dispensing device and the semiconductor element 1 is mounted, the metal sintered material paste 15a applied to the center is spread outward.
  • the central bonding layer 15 of the semiconductor element 1 becomes thicker, and the thickness of the bonding layer 15 becomes thinner toward the outer peripheral end of the semiconductor element 1.
  • the metal sintered material paste 15a does not melt and spread wet, so that the sintered joint is often completed with a non-uniform thickness. Since the stress strain during the temperature cycle is most concentrated at the outer peripheral end of the joint layer 15, even if the average thickness of the joint layer 15 can be secured, the thickness is not uniform and the thinned joint layer 15 is cracked.
  • the force for pushing the metal sintered material paste 15a at the time of mounting becomes weak, and the force directly under the via hole 12 tends to be a more porous and sparse bonding layer.
  • the porous and sparse bonding layer is also weak in strength and tends to be a starting point for cracks in the reliability test.
  • the metal sintered material paste 15a can be pushed in in the same manner as other regions such as the outer peripheral end portion at the time of mounting, and a uniform and dense bonding layer 15 can be obtained. be able to.
  • the via hole 12 covered with the heat-resistant resin 13 is formed on two opposite sides of the central and outer peripheral end faces of the semiconductor element 1. Are formed in any pair when is paired with each other. Even if the via holes 12 and the heat-resistant resin 13 are formed only on any one pair of two sides, there is no problem in ensuring the thickness of the bonding layer 15. In addition, the solvent volatilized during the sintering of the metal sintering material paste 15a easily escapes from the pair of two sides on which the via hole 12 and the heat-resistant resin 13 are not formed, thereby suppressing voids generated inside the bonding layer 15. And by promoting heat shrinkage, a denser bonding layer 15 can be obtained.
  • the via holes 12 covered with the heat-resistant resin 13 are formed at the center and the four corners of the semiconductor element 1.
  • the 7D structure has the smallest number of via holes 12 and heat-resistant resin 13, the most volatile solvent can be easily released, and the densest bonding layer 15 can be obtained.
  • the positions or numbers of the via holes 12 and the heat-resistant resin 13 described above may be appropriately determined depending on the bonding thickness and variation required for each semiconductor device 110, the thermal conductivity of the bonding layer 15, or the state inside the bonding layer 15. good.
  • the semiconductor element 1 for high frequency communication is generally rectangular in order to obtain high high frequency characteristics. That is, there are a pair of short and long sides.
  • the via holes 12 and the heat-resistant resin 13 formed only on either pair of two sides of the semiconductor element 1 have been described, but the rectangular semiconductor element 1 is formed only on the short side. By doing so, high reliability can be ensured.
  • the solvent volatilized from the long side is preferentially released. Therefore, the via hole 12 and the heat-resistant resin 13 are provided only on the short side.

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Abstract

Provided are a semiconductor device and a method for manufacturing a semiconductor device that can prevent deformation of the shape of the periphery of via holes (12), and suppress a decrease in reliability. This semiconductor device (110) comprises: a semiconductor element (1) in which via holes (12) are formed between a surface electrode (7) and back electrodes (16) provided on the opposite side to the surface electrode (7); a heat-resistant resin (13) that covers the back electrode (16) sides of the via holes (12); a base (6) on which the semiconductor element (1) is mounted; and a joining layer (15) that includes a metal-sintered material as a main component, and joins the semiconductor element (1) and the base (6).

Description

半導体装置および半導体装置の製造方法Semiconductor devices and manufacturing methods for semiconductor devices
　本願は、半導体装置および半導体装置の製造方法に関するものである。 The present application relates to a semiconductor device and a method for manufacturing the semiconductor device.
　近年、著しい速さで情報通信分野の技術が発展しており、マイクロ波帯からミリ波帯へとより高い周波数帯の信号を取り扱うようになってきている。移動体通信または防災無線などに用いる高周波通信用の半導体装置においても、数十ＧＨｚのミリ波を扱うことが見込まれており、ますます増加する発熱への対策が急務となる。
　高周波通信用の半導体装置には、シリコン半導体または化合物半導体等の半導体素子が搭載されている。これらの半導体素子の裏面にはメタライズにより電極が形成されており、一般的な半導体装置の場合、裏面電極とパッケージとがはんだ、または導電性ペースト等の接合材料により接合されている。これらの接合材料は、半導体素子の発熱をヒートシンクなどの冷却機構に逃がすための経路であり、前述したように、ますます増加する発熱を効率よく逃がすために、高い熱伝導率が望まれる。 In recent years, the technology in the information and communication field has been developed at a remarkable speed, and it has come to handle signals in higher frequency bands from the microwave band to the millimeter wave band. It is expected that semiconductor devices for high-frequency communication used for mobile communication or disaster prevention radio will also handle millimeter waves of several tens of GHz, and it is urgent to take measures against the increasing heat generation.
A semiconductor element such as a silicon semiconductor or a compound semiconductor is mounted on a semiconductor device for high-frequency communication. Electrodes are formed on the back surface of these semiconductor elements by metallizing, and in the case of a general semiconductor device, the back surface electrodes and the package are bonded by a bonding material such as solder or a conductive paste. These bonding materials are a path for releasing the heat generated by the semiconductor element to a cooling mechanism such as a heat sink, and as described above, high thermal conductivity is desired in order to efficiently release the increasingly increasing heat generation.
　一方近年、サブミクロン、ナノサイズの金属粒子を低温で焼結させる焼結接合技術の半導体装置への適用が検討されている。焼結接合は、粒子サイズ効果または粒子表面に被覆する有機成分、溶剤の反応を利用することで、金属融点よりはるかに低い温度で焼結接合が可能であるとともに、焼結後はバルク金属に近い熱伝導率、耐熱性を有するという特徴がある。
　従来、半導体素子の表面上の電極パッドとグランド（ＧＮＤ）とを電気的に接続するため、ビアホールが用いられている。ビアーホールに半導体素子のダイボンド用の接合材料が入り込むことによって、膨張係数差により、ビアホール電極の金属箔が断線したりクラックが発生する懸念があった。
　その対策として、ビアホールをはんだが濡れにくい保護膜で覆う等がされてきた（例えば、特許文献１参照）。 On the other hand, in recent years, application of a sintering bonding technology for sintering submicron and nano-sized metal particles at a low temperature to a semiconductor device has been studied. Sintered bonding can be performed at a temperature much lower than the metal melting point by utilizing the particle size effect or the reaction of organic components and solvents that coat the particle surface, and after sintering, it becomes a bulk metal. It is characterized by having similar thermal conductivity and heat resistance.
Conventionally, a via hole has been used to electrically connect an electrode pad on the surface of a semiconductor element and a ground (GND). There is a concern that the metal foil of the via hole electrode may be broken or cracked due to the difference in expansion coefficient due to the entry of the bonding material for die bonding of the semiconductor element into the beer hole.
As a countermeasure, the via hole has been covered with a protective film that prevents the solder from getting wet (see, for example, Patent Document 1).
特許第３７２４１１０号公報Japanese Patent No. 3724110
　しかしながら、特許文献１に開示された半導体装置では、半導体素子の接合を前述した金属焼結材などの接合材料で行う場合、その保護膜の影響でビアホール周辺の形状が変形し、信頼性が低下する問題があった。 However, in the semiconductor device disclosed in Patent Document 1, when the semiconductor element is bonded with a bonding material such as the metal sintered material described above, the shape around the via hole is deformed due to the influence of the protective film, and the reliability is lowered. There was a problem to do.
　本願は、上記のような課題を解決するための技術を開示するものであり、ビアホール周辺の形状が変形することを防止し、信頼性の低下を抑制できる半導体装置および半導体装置の製造方法を提供することを目的とする。 The present application discloses a technique for solving the above-mentioned problems, and provides a semiconductor device and a method for manufacturing the semiconductor device, which can prevent the shape around the via hole from being deformed and suppress a decrease in reliability. The purpose is to do.
　本願に開示される半導体装置は、表面電極と前記表面電極の反対側に設けられた裏面電極との間にビアホールが形成された半導体素子と、前記ビアホールの前記裏面電極側を被覆する耐熱性樹脂と、前記半導体素子を搭載する基材と、金属焼結材を主成分として含み、前記半導体素子と前記基材とを接合する接合層と、を備えたものである。
　また、本願に開示される半導体装置の製造方法は、表面電極と前記表面電極の反対側に設けられた裏面電極との間にビアホールが形成された半導体素子を準備する工程と、前記ビアホールの前記裏面電極側を被覆する耐熱性樹脂を形成する工程と、基材の表面上に金属焼結材ペーストを塗布して、前記金属焼結材ペーストの上に前記半導体素子を搭載する工程と、前記金属焼結材ペーストを加熱することにより、前記半導体素子と前記基材とを金属焼結材を主成分として含む接合層で接合する工程と、を備えたものである。 The semiconductor device disclosed in the present application includes a semiconductor element in which a via hole is formed between a front surface electrode and a back surface electrode provided on the opposite side of the front surface electrode, and a heat-resistant resin that covers the back surface electrode side of the via hole. A base material on which the semiconductor element is mounted, and a bonding layer containing the metal sintered material as a main component and joining the semiconductor element and the base material.
Further, the method for manufacturing a semiconductor device disclosed in the present application includes a step of preparing a semiconductor element in which a via hole is formed between a front surface electrode and a back surface electrode provided on the opposite side of the front surface electrode, and the step of preparing the via hole. A step of forming a heat-resistant resin that covers the back electrode side, a step of applying a metal sintered material paste on the surface of the base material, and a step of mounting the semiconductor element on the metal sintered material paste, and the above-mentioned The present invention includes a step of joining the semiconductor element and the base material with a bonding layer containing the metal sintered material as a main component by heating the metal sintered material paste.
　本願に開示される半導体装置および半導体装置の製造方法によれば、ビアホール周辺の形状が変形することを防止し、信頼性の低下を抑制できる半導体装置および半導体装置の製造方法が得られる。 According to the method for manufacturing a semiconductor device and a semiconductor device disclosed in the present application, a method for manufacturing a semiconductor device and a semiconductor device that can prevent the shape around the via hole from being deformed and suppress a decrease in reliability can be obtained.
実施の形態１による半導体装置を示す平面図である。It is a top view which shows the semiconductor device by Embodiment 1. FIG. 実施の形態１による半導体装置の内部構造を示す平面図である。It is a top view which shows the internal structure of the semiconductor device according to Embodiment 1. FIG. 図１のＡ‐Ａ線の断面図である。It is sectional drawing of the line AA of FIG. 実施の形態１による半導体装置の半導体素子の裏面を示す平面図である。It is a top view which shows the back surface of the semiconductor element of the semiconductor device according to Embodiment 1. FIG. 図２のＢ‐Ｂ線の断面図である。It is sectional drawing of BB line of FIG. 実施の形態１による半導体装置のビアホール周辺の拡大断面図である。It is an enlarged sectional view around the via hole of the semiconductor device according to Embodiment 1. FIG. 実施の形態１による半導体装置のビアホール周辺の拡大断面図である。It is an enlarged sectional view around the via hole of the semiconductor device according to Embodiment 1. FIG. 実施の形態１による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by Embodiment 1. FIG. 実施の形態２による半導体装置の半導体素子の裏面を示す平面図である。It is a top view which shows the back surface of the semiconductor element of the semiconductor device by Embodiment 2. FIG.
実施の形態１．
　以下、図面に基づいて実施の形態１について説明する。なお、各図面において、同一符号は同一あるいは相当部分を示す。 Embodiment 1.
Hereinafter, the first embodiment will be described with reference to the drawings. In each drawing, the same reference numerals indicate the same or corresponding parts.
　図１は、実施の形態１による半導体装置を示す平面図である。また、図２は、実施の形態１による半導体装置の内部構造を示す平面図であり、図１の半導体装置１１０から封止樹脂５を取り除いた半導体装置１１０の内部構造を示す。また、図３は、図１のＡ－Ａ線の断面図である。
　図１から図３に示すように、例えば銅（Ｃｕ）製のヒートシンク６の上面には、接合層１５を介して例えばシリコン（Ｓｉ）製の半導体素子１が搭載されている。また、半導体素子１には複数のビアホール１２が形成されている。接合層１５は、銀（Ａｇ）焼結材等の金属焼結材ペースト１５ａを焼結させて金属焼結材としたものである。ヒートシンク６と半導体素子１とは、接合層１５を介して接続されている。 FIG. 1 is a plan view showing a semiconductor device according to the first embodiment. Further, FIG. 2 is a plan view showing the internal structure of the semiconductor device according to the first embodiment, and shows the internal structure of the semiconductor device 110 from which the sealing resin 5 is removed from the semiconductor device 110 of FIG. Further, FIG. 3 is a cross-sectional view taken along the line AA of FIG.
As shown in FIGS. 1 to 3, for example, a semiconductor element 1 made of silicon (Si) is mounted on the upper surface of a heat sink 6 made of copper (Cu) via a bonding layer 15. Further, a plurality of via holes 12 are formed in the semiconductor element 1. The bonding layer 15 is obtained by sintering a metal sintered material paste 15a such as a silver (Ag) sintered material to obtain a metal sintered material. The heat sink 6 and the semiconductor element 1 are connected via a bonding layer 15.
　また、例えば高周波通信用の半導体装置１１０において、高周波特性の整合を取るための回路基板２が接合層１５を介してヒートシンク６に接続されている。回路基板２は、例えば、セラミック基板に薄膜パターン加工したマイクロ波集積回路（ＭＩＣ：Ｍｉｃｒｏｗａｖｅ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）基板である。
　半導体素子１の電極パターン（図示なし）と回路基板２はボンディングワイヤ３により電気的に接続されている。また半導体素子１の電極パターン（図示なし）と回路基板２は、ボンディングワイヤ３によりそれぞれリード４と電気的に接続されている。半導体素子１の電極パターン（図示せず）および回路基板２は、それぞれボンディングワイヤ３、リード４を介して外部基板（図示せず）に電気的に接続されている。
　さらに、半導体素子１および回路基板２は、外部の湿気、汚染、熱または電磁界等の影響から隔離して絶縁性を確保するため、例えばトランスファーモールドによる封止樹脂５によって覆われている。 Further, for example, in a semiconductor device 110 for high-frequency communication, a circuit board 2 for matching high-frequency characteristics is connected to a heat sink 6 via a bonding layer 15. The circuit board 2 is, for example, a microwave integrated circuit (MIC) substrate in which a thin film pattern is processed on a ceramic substrate.
The electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected by a bonding wire 3. Further, the electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected to the reed 4 by the bonding wire 3, respectively. The electrode pattern (not shown) of the semiconductor element 1 and the circuit board 2 are electrically connected to an external substrate (not shown) via bonding wires 3 and leads 4, respectively.
Further, the semiconductor element 1 and the circuit board 2 are covered with, for example, a sealing resin 5 by a transfer mold in order to isolate from the influence of external moisture, contamination, heat, electromagnetic field, etc. and to secure the insulating property.
　図４Ａは、実施の形態１による半導体装置の半導体素子の裏面を示す平面図である。また、図４Ｂは、図２のＢ‐Ｂ線の断面図である。
　図４Ａ、図４Ｂに示すように、半導体素子１の裏面およびビアホール１２の表層には、金（Ａｕ）めっき層などの導電層１４が形成されている。電極パッド７とヒートシンク６とは、ビアホール１２の表層に形成された導電層１４により接続されている。一般的に、導電層１４は、半導体素子１の裏面全体に対して例えば金（Ａｕ）めっきを施し、開口部であるビアホール１２内部にＡｕ層を成膜することで形成される。ヒートシンク６と半導体素子１の裏面に形成された金（Ａｕ）めっき層などの導電層１４とは、接合層１５を介して接続されている。 FIG. 4A is a plan view showing the back surface of the semiconductor element of the semiconductor device according to the first embodiment. Further, FIG. 4B is a cross-sectional view taken along the line BB of FIG.
As shown in FIGS. 4A and 4B, a conductive layer 14 such as a gold (Au) plating layer is formed on the back surface of the semiconductor element 1 and the surface layer of the via hole 12. The electrode pad 7 and the heat sink 6 are connected by a conductive layer 14 formed on the surface layer of the via hole 12. Generally, the conductive layer 14 is formed by subjecting the entire back surface of the semiconductor element 1 to, for example, gold (Au) plating, and forming an Au layer inside the via hole 12 which is an opening. The heat sink 6 and the conductive layer 14 such as the gold (Au) plating layer formed on the back surface of the semiconductor element 1 are connected via the bonding layer 15.
　従来のはんだを用いた接合方法では、ビアホール内部に充填されたはんだが加熱の際に電極パッドの表面にまで這い上がる現象が起きるため、はんだの這い上がりを防ぐために導体層であるＡｕめっき層の表層に更にニッケル膜などのバリアメタルを形成していた。しかしながら、耐熱性に優れた金属焼結材を用いた接合方法が検討されており、その場合、金属焼結材ペーストとニッケル膜などのバリアメタルとは相性が悪く、焼結接合しにくいことが分かっている。結果として、ビアホール周辺の接合部分の形状が変形し、温度サイクル試験時に変形した接合部分を起点にしたクラックが発生するなどの問題点があった。一方で、ニッケル膜などのバリアメタルがなく、金属焼結材ペーストがビアホール内部に充填されると、加熱焼結時の熱収縮によってＡｕめっき層の剥がれ、または場合によっては半導体素子の割れなどが発生する問題があった。 In the conventional joining method using solder, the solder filled inside the via hole crawls up to the surface of the electrode pad when heated. Therefore, in order to prevent the solder from crawl up, the Au plating layer, which is a conductor layer, is used. A barrier metal such as a nickel film was further formed on the surface layer. However, a joining method using a metal sintered material having excellent heat resistance has been studied, and in that case, the metal sintered material paste and the barrier metal such as a nickel film are incompatible with each other, and it may be difficult to perform sintering bonding. I know. As a result, there is a problem that the shape of the joint portion around the via hole is deformed and cracks are generated starting from the deformed joint portion during the temperature cycle test. On the other hand, if there is no barrier metal such as a nickel film and the metal sintered material paste is filled inside the via hole, the Au plating layer may peel off due to heat shrinkage during heat sintering, or the semiconductor element may crack in some cases. There was a problem that occurred.
　そこで、実施の形態１による半導体装置１１０では、図４Ｂに示すように、半導体素子１の裏面電極１６側に耐熱性樹脂１３をバンプ状に形成することにより、ビアホール１２の裏面電極１６側を耐熱性樹脂１３により被覆している。つまり、耐熱性樹脂１３は、ビアホール１２の裏面電極１６側に耐熱性樹脂バンプとして設けられるとともにビアホール１２の内部にも充填されている。耐熱性樹脂１３は、比較的ヤング率が高く硬い樹脂であるエポキシ系または比較的柔らかく熱応力による変形を吸収することができるシリコーン系など半導体装置１１０の動作温度で溶融しない耐熱性を有する樹脂であればよい。耐熱性樹脂１３は、ガラス転移温度または半導体素子１の裏面電極１６との濡れなどを考慮して適宜選定することが可能である。
　また、耐熱性樹脂１３として金属粒子を含有した耐熱性樹脂を用いてもよい。この場合は、ビアホール１２内部の金属粒子と接合層１５となる金属焼結材ペースト１５ａとが焼結接合することで、更なる接合性の改善効果も見込まれる。 Therefore, in the semiconductor device 110 according to the first embodiment, as shown in FIG. 4B, the heat-resistant resin 13 is formed in a bump shape on the back electrode 16 side of the semiconductor element 1 to heat-heat the back electrode 16 side of the via hole 12. It is covered with the sex resin 13. That is, the heat-resistant resin 13 is provided as a heat-resistant resin bump on the back surface electrode 16 side of the via hole 12, and is also filled inside the via hole 12. The heat-resistant resin 13 is a resin having heat resistance that does not melt at the operating temperature of the semiconductor device 110, such as an epoxy-based resin that has a relatively high Young's modulus and is a hard resin, or a silicone-based resin that is relatively soft and can absorb deformation due to thermal stress. All you need is. The heat-resistant resin 13 can be appropriately selected in consideration of the glass transition temperature, the wetting of the semiconductor element 1 with the back surface electrode 16, and the like.
Further, as the heat-resistant resin 13, a heat-resistant resin containing metal particles may be used. In this case, the metal particles inside the via hole 12 and the metal sintered material paste 15a serving as the bonding layer 15 are sintered and bonded, so that a further effect of improving the bondability can be expected.
　図５Ａ、図５Ｂは、実施の形態１による半導体装置のビアホール周辺の拡大断面図である。図５Ａおよび図５Ｂに示すように、耐熱性樹脂１３と金属焼結材ペースト１５ａは、基本的に焼結接合しない。そのため、半導体素子１の裏面電極１６と耐熱性樹脂１３とが接する角度が３０度以下となるほど、未接合領域が半導体素子１の裏面電極１６と金属焼結材ペースト１５ａの間の切り口のようになり、温度サイクル寿命に影響する。
　実施の形態１では、図５Ａに示すように、半導体素子１の裏面電極１６と耐熱性樹脂１３とが接する角度θ１が３０度よりも大きくなるように耐熱性樹脂１３をバンプ状に形成している。角度θ１は、耐熱性樹脂１３の端部における接線１７と裏面電極１６とが交差する角度である。半導体素子１の裏面電極１６に濡れにくい樹脂材料を選定し、裏面電極１６と耐熱性樹脂１３とが接する角度θ１が３０度よりも大きくなるようにすることで、未接合領域が鋭利な切り口にならないため、そこを起点に発生するクラックを抑制することが可能となる。
　さらに、耐熱性樹脂バンプの突起部分の高さＨ１を制御することで、突起部分がスペーサーの役割を果たすこととなり、接合層１５の厚さを確保できる。 5A and 5B are enlarged cross-sectional views of the periphery of the via hole of the semiconductor device according to the first embodiment. As shown in FIGS. 5A and 5B, the heat-resistant resin 13 and the metal sintered material paste 15a are basically not sintered and joined. Therefore, as the angle of contact between the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 becomes 30 degrees or less, the unbonded region becomes like a cut between the back electrode 16 of the semiconductor element 1 and the metal sintered material paste 15a. It affects the temperature cycle life.
In the first embodiment, as shown in FIG. 5A, the heat-resistant resin 13 is formed in a bump shape so that the angle θ1 at which the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 come into contact with each other is larger than 30 degrees. There is. The angle θ1 is an angle at which the tangent line 17 and the back surface electrode 16 at the end of the heat-resistant resin 13 intersect. By selecting a resin material that does not easily get wet with the back electrode 16 of the semiconductor element 1 and making the angle θ1 between the back electrode 16 and the heat-resistant resin 13 larger than 30 degrees, the unbonded region becomes a sharp cut. Therefore, it is possible to suppress cracks generated from that point.
Further, by controlling the height H1 of the protruding portion of the heat-resistant resin bump, the protruding portion serves as a spacer, and the thickness of the bonding layer 15 can be secured.
　また、図５Ｂに示すように、半導体素子１の裏面電極１６と耐熱性樹脂１３とが接する角度θ２を９０度以上とすることで、より未接合領域を起点としたクラックを抑制することが可能になる。角度θ２は、耐熱性樹脂１３の端部における接線１７と裏面電極１６とが交差する角度である。
　一方で、角度θ２が９０度以上になるように耐熱性樹脂１３を形成する場合、半導体素子１の裏面電極１６に濡れやすい樹脂材料を選定する必要がある。また、突起部分の高さＨ２が小さくなるため、突起部分のスペーサーとしての役割が低減する。
　したがって、半導体素子１の裏面電極１６と耐熱性樹脂１３とが接する角度θ１または角度θ２に関しては、半導体装置１１０の各種用途に必要な接合層１５の膜厚を考慮して決定すればよい。
　また、耐熱性樹脂１３は、焼結時の熱収縮による応力が最も加わるビアホール１２の開口部を少なくとも覆っていればよい。ただし、ビアホール１２の内部に耐熱性樹脂１３が充填されているほど、温度サイクル時の熱応力を耐熱性樹脂１３が緩和するため、内部を耐熱性樹脂１３で充填している方がより望ましい。 Further, as shown in FIG. 5B, by setting the angle θ2 at which the back surface electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 are in contact with each other at 90 degrees or more, it is possible to further suppress cracks starting from the unbonded region. become. The angle θ2 is an angle at which the tangent line 17 and the back surface electrode 16 at the end of the heat-resistant resin 13 intersect.
On the other hand, when the heat-resistant resin 13 is formed so that the angle θ2 is 90 degrees or more, it is necessary to select a resin material that easily gets wet with the back electrode 16 of the semiconductor element 1. Further, since the height H2 of the protruding portion is reduced, the role of the protruding portion as a spacer is reduced.
Therefore, the angle θ1 or the angle θ2 at which the back electrode 16 of the semiconductor element 1 and the heat-resistant resin 13 come into contact with each other may be determined in consideration of the film thickness of the bonding layer 15 required for various uses of the semiconductor device 110.
Further, the heat-resistant resin 13 may at least cover the opening of the via hole 12 to which the stress due to heat shrinkage during sintering is most applied. However, the more the heat-resistant resin 13 is filled inside the via hole 12, the more the heat-resistant resin 13 relaxes the thermal stress during the temperature cycle. Therefore, it is more desirable that the inside is filled with the heat-resistant resin 13.
　図６は、実施の形態１による半導体装置の製造方法を示す断面図である。図６において、６Ａに示すように、まず、半導体素子１の裏面に耐熱性樹脂をディスペンス装置などで塗布、キュアすることで耐熱性樹脂１３を形成する。続いて、図６の６Ｂに示すように、ヒートシンク６の表面上に金属焼結材ペースト１５ａをディスペンス装置もしくは印刷にて塗布し、６Ａにおいて準備した半導体素子１を金属焼結材ペースト１５ａの上に搭載して２００℃以上に加熱することで焼結させる。これにより、図６の６Ｃに示すように、ヒートシンク６上に接合層１５が形成される。
　続いて、図６の６Ｄに示すように、電子部品である回路基板２と半導体素子１と外部接続用のリード４間をボンディングワイヤ３によって電気的に接続する。最後に、トランスファーモールドにより樹脂封止する。以上のプロセスを経て、実施の形態１の半導体装置１１０が作製される。 FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment. In FIG. 6, as shown in 6A, first, the heat-resistant resin 13 is formed by applying and curing the heat-resistant resin on the back surface of the semiconductor element 1 with a dispensing device or the like. Subsequently, as shown in 6B of FIG. 6, the metal sintered material paste 15a is applied onto the surface of the heat sink 6 by a dispensing device or printing, and the semiconductor element 1 prepared in 6A is applied onto the metal sintered material paste 15a. It is sintered by mounting it on a device and heating it to 200 ° C. or higher. As a result, as shown in 6C of FIG. 6, the bonding layer 15 is formed on the heat sink 6.
Subsequently, as shown in 6D of FIG. 6, the circuit board 2 which is an electronic component, the semiconductor element 1, and the lead 4 for external connection are electrically connected by the bonding wire 3. Finally, the resin is sealed by a transfer mold. Through the above process, the semiconductor device 110 of the first embodiment is manufactured.
　また、ヒートシンク６として銅（Ｃｕ）製のヒートシンクを用いた事例を示したが、ヒートシンク６は、半導体素子１の動作によって発生する熱を逃がす機能があればよく、銅（Ｃｕ）製に限定されない。例えば、ヒートシンク６として、鉄、タングステン、モリブデン、ニッケル、コバルト、これらの合金、又はこれらの複合材料を用いてもよい。熱伝導率の高いヒートシンク材を用いることにより、半導体素子１から発生する熱を効率よく外に逃がすことができ、接合層１５に加わる熱応力歪みを低減できる。
　また、ヒートシンク６の形状は、四角柱の他、多角柱、円柱、楕円柱、これらの一部に段差を設けた形状であってもよい。 Further, although an example in which a heat sink made of copper (Cu) is used as the heat sink 6, the heat sink 6 is not limited to the one made of copper (Cu) as long as it has a function of dissipating heat generated by the operation of the semiconductor element 1. .. For example, as the heat sink 6, iron, tungsten, molybdenum, nickel, cobalt, alloys thereof, or a composite material thereof may be used. By using the heat sink material having high thermal conductivity, the heat generated from the semiconductor element 1 can be efficiently released to the outside, and the thermal stress strain applied to the bonding layer 15 can be reduced.
Further, the shape of the heat sink 6 may be a square pillar, a polygonal pillar, a cylinder, an elliptical pillar, or a shape in which a step is provided in a part thereof.
　また、ヒートシンク６として銅（Ｃｕ）製のヒートシンク単体を用いた事例を示したが、複数枚の異なる金属を重ねて用いても良い。例えば、半導体素子１と比較して熱膨張係数の大きい銅（Ｃｕ）製のヒートシンク６の上に、半導体素子１に比較的近い熱膨張係数を有するタングステン製のヒートシンク６を搭載することで、半導体素子１とその直下のヒートシンク６との熱膨張係数のミスマッチを低減することができ、接合層１５に加わる熱応力歪みを低減することができる。
　また、ヒートシンク６には、金（Ａｕ）めっきが施されているが、金（Ａｕ）以外にも各金属焼結材と相性の良い金属めっきであってもよく、銅（Ｃｕ）製のヒートシンク６との接合性が確保できるようであれば金属めっきがなくでも構わない。さらに、実施の形態１では、半導体素子１をヒートシンク６などの基材に搭載する事例を示したが、例えば絶縁基板などの基材に搭載されてもよい。
　また、封止樹脂５との密着性を向上させる必要があれば、金属めっき表面に荒らした粗化めっきなど施してもよい。 Further, although an example in which a single copper (Cu) heat sink is used as the heat sink 6, a plurality of different metals may be stacked and used. For example, a heat sink 6 made of tungsten having a thermal expansion coefficient relatively close to that of the semiconductor element 1 is mounted on a heat sink 6 made of copper (Cu) having a larger thermal expansion coefficient than that of the semiconductor element 1. The mismatch of the thermal expansion coefficient between the element 1 and the heat sink 6 immediately below the element 1 can be reduced, and the thermal stress strain applied to the bonding layer 15 can be reduced.
Further, although the heat sink 6 is plated with gold (Au), it may be metal-plated which is compatible with each metal sintered material other than gold (Au), and is a heat sink made of copper (Cu). Metal plating may not be required as long as the bondability with 6 can be ensured. Further, in the first embodiment, the case where the semiconductor element 1 is mounted on a base material such as a heat sink 6 is shown, but it may be mounted on a base material such as an insulating substrate.
Further, if it is necessary to improve the adhesion with the sealing resin 5, roughened rough plating or the like may be applied to the metal plating surface.
　なお、ここでは、半導体素子1として、シリコン製の半導体素子１を事例として説明したが、その他の半導体素子１として、例えば、化合物半導体であるガリウムアーセナイド（ＧａＡｓ）、窒化ガリウム（ＧａＮ）などを用いてもよい。窒化ガリウム（ＧａＮ）は、高い電子速度、ワイドバンドギャップによる高い絶縁破壊電圧、大電力動作可能、広い動作帯域幅、高温動作可能のため小型化、低コスト化といった様々なメリットを有している。 Although the semiconductor element 1 made of silicon has been described as an example of the semiconductor element 1, other semiconductor elements 1 include, for example, gallium arsenide (GaAs) and gallium nitride (GaN), which are compound semiconductors. May be used. Gallium nitride (GaN) has various merits such as high electron speed, high breakdown voltage due to wide bandgap, high power operation, wide operation bandwidth, and high temperature operation, resulting in miniaturization and cost reduction. ..
　実施の形態１による半導体装置１１０では、長辺と短辺の長さが異なる高周波通信用の半導体素子１を事例として示したが、長辺と短辺の長さが等しい半導体素子１を使用してもよい。
　また、実施の形態１による半導体装置１１０では、半導体素子１が１つ搭載された事例を示したが、複数個の半導体素子１が搭載されていてもよく、窒化ガリウム（ＧａＮ）とガリウムアーセナイド（ＧａＡｓ）といった異なる半導体素子１が組み合わされていても構わない。
　また、実施の形態１による半導体装置１１０では、回路基板２を実装する事例を示したが、少なくとも半導体素子１が搭載されていればよい。また、半導体素子１と同様に高周波特性の整合を取るために複数枚、異なる形状または異なるサイズの回路基板２が搭載されていてもよい。 In the semiconductor device 110 according to the first embodiment, the semiconductor element 1 for high-frequency communication having different lengths of the long side and the short side is shown as an example, but the semiconductor element 1 having the same length of the long side and the short side is used. You may.
Further, in the semiconductor device 110 according to the first embodiment, an example in which one semiconductor element 1 is mounted is shown, but a plurality of semiconductor elements 1 may be mounted, and gallium nitride (GaN) and gallium arsenal may be mounted. Different semiconductor elements 1 such as id (GaAs) may be combined.
Further, in the semiconductor device 110 according to the first embodiment, an example in which the circuit board 2 is mounted is shown, but at least the semiconductor element 1 may be mounted. Further, similarly to the semiconductor element 1, a plurality of circuit boards 2 having different shapes or different sizes may be mounted in order to match the high frequency characteristics.
　窒化ガリウム（ＧａＮ）を用いた半導体素子１のような高温動作が求められる半導体装置１１０においては、従来のはんだと比較して高い熱伝導率を有する金属焼結材ペースト１５ａが有効である。金属焼結材ペースト１５ａは、一般的にサブミクロン、ナノサイズまたはそれらを混合した金属粒子と、粒子表面を覆っている保護膜と、粒子を分散させる溶剤とを有している。また、球体だけでなく、フレーク状または球体に針状で覆われたものなど様々な形状もある。約２００℃の低温で焼結すると、保護膜または溶剤が全て揮発し、ネッキング焼結した金属粒子のみの接合層１５となる。そのため、バルクの金属に近い熱伝導率、耐熱性を有する。必要な焼結温度は、金属粒子のサイズまたはペーストに含まれる焼結促進剤などによって異なっており、常温での焼結も可能である。
　一般的に、焼結温度と焼結時間によって、金属粒子同士の焼結または、金属粒子と被接合体との焼結が進行していくため、半導体装置１１０の各種用途に必要な接合信頼性を考慮して焼結プロセスを決定すればよい。 In the semiconductor device 110 that requires high-temperature operation such as the semiconductor element 1 using gallium nitride (GaN), the metal sintered material paste 15a having a higher thermal conductivity than the conventional solder is effective. The metal sintered material paste 15a generally has submicron, nano-sized or mixed metal particles, a protective film covering the particle surface, and a solvent for dispersing the particles. In addition to spheres, there are various shapes such as flakes or spheres covered with needles. When sintered at a low temperature of about 200 ° C., the protective film or solvent is completely volatilized to form a bonding layer 15 containing only neck-sintered metal particles. Therefore, it has thermal conductivity and heat resistance close to those of bulk metal. The required sintering temperature varies depending on the size of the metal particles, the sintering accelerator contained in the paste, and the like, and sintering at room temperature is also possible.
In general, the sintering of metal particles or the sintering of metal particles and an object to be joined progresses depending on the sintering temperature and the sintering time. Therefore, the joining reliability required for various applications of the semiconductor device 110 is required. The sintering process may be determined in consideration of.
　なお、金属焼結材ペースト１５ａは、銀（Ａｇ）焼結材、銅（Ｃｕ）焼結材、金（Ａｕ）焼結材、パラジウム（Ｐｄ）焼結材、白金（Ｐｔ）焼結材等の貴金属に分類される金属をベースにした焼結材、ニッケル（Ｎｉ）焼結材等の貴金属以外に分類される金属粒子をベースにした焼結材、酸化銀焼結材、酸化銅焼結等の微細な酸化物を還元し金属微粒子を形成することで焼結反応を得る焼結材、銀（Ａｇ）‐パラジウム（Ｐｄ）焼結材、金（Ａｕ）‐シリコン（Ｓｉ）焼結材、金（Ａｕ）‐ゲルマニウム（Ｇｅ）焼結材、金（Ａｕ）‐銅（Ｃｕ）焼結材等の合金をベースにした焼結材ペースト等を用いればよい。 The metal sintered material paste 15a includes a silver (Ag) sintered material, a copper (Cu) sintered material, a gold (Au) sintered material, a palladium (Pd) sintered material, a platinum (Pt) sintered material, and the like. Sintered materials based on metals classified as precious metals, sintered materials based on metal particles classified other than precious metals such as nickel (Ni) sintered materials, silver oxide sintered materials, copper oxide sintered materials Sintered material that obtains a sintering reaction by reducing fine oxides such as, etc. to form metal fine particles, silver (Ag) -palladium (Pd) sintered material, gold (Au) -silicon (Si) sintered material , A sintered material paste based on an alloy such as a gold (Au) -germanium (Ge) sintered material or a gold (Au) -copper (Cu) sintered material may be used.
　また、半導体装置１１０の各種用途によって必要な接合信頼性は異なるが、接合層１５の厚さは、３０μｍｔ以上を確保することが好ましく、より温度サイクル試験に対する寿命を向上できる。接合層１５をより厚くすることで、温度サイクル試験に対する寿命をさらに向上させることが可能であるが、熱伝導率（２００Ｗ／ｍＫ以上）の高い金属焼結材ペースト１５ａを用いているとはいえ、接合層１５を厚くすることで熱抵抗および部材コストが増加するため、半導体装置１１０の熱設計を考慮してその厚さを決定すればよい。
　また、裏面電極１６側に形成された耐熱性樹脂１３の膜厚は、半導体素子１の厚みの１／１０以上であればよい。 Further, although the required bonding reliability varies depending on various uses of the semiconductor device 110, the thickness of the bonding layer 15 is preferably 30 μmt or more, and the life for the temperature cycle test can be further improved. By making the bonding layer 15 thicker, it is possible to further improve the life for the temperature cycle test, but even though the metal sintered material paste 15a having a high thermal conductivity (200 W / mK or more) is used. Since the thermal resistance and the member cost increase by increasing the thickness of the bonding layer 15, the thickness may be determined in consideration of the thermal design of the semiconductor device 110.
Further, the film thickness of the heat-resistant resin 13 formed on the back surface electrode 16 side may be 1/10 or more of the thickness of the semiconductor element 1.
　また、実施の形態１による半導体装置１１０は、封止樹脂５によって半導体素子１などが覆われているが、セラミックキャップまたはメタルキャップなどを接着、接合した中空構造であってもよい。中空構造を採用することで、半導体素子１の表面に誘電率の高い封止樹脂５が存在せず、高い高周波特性を得ることができる。
　以上のように、実施の形態１による半導体装置１１０は、例えば電極パッド７等の表面電極と表面電極の反対側に設けられた裏面電極１６との間にビアホール１２が形成された半導体素子１と、ビアホール１２の裏面電極１６側を被覆する耐熱性樹脂１３と、半導体素子１を搭載する例えばヒートシンク６等の基材と、金属焼結材を主成分として含み、半導体素子１と基材とを接合する接合層１５と、を有している。 Further, although the semiconductor device 110 according to the first embodiment is covered with the sealing resin 5 such as the semiconductor element 1, it may have a hollow structure in which a ceramic cap, a metal cap, or the like is adhered and joined. By adopting the hollow structure, the sealing resin 5 having a high dielectric constant does not exist on the surface of the semiconductor element 1, and high high frequency characteristics can be obtained.
As described above, the semiconductor device 110 according to the first embodiment is the semiconductor element 1 in which the via hole 12 is formed between the front surface electrode such as the electrode pad 7 and the back surface electrode 16 provided on the opposite side of the front surface electrode. , A heat-resistant resin 13 that covers the back surface electrode 16 side of the via hole 12, a base material such as a heat sink 6 on which the semiconductor element 1 is mounted, and a metal sintered material as a main component, the semiconductor element 1 and the base material. It has a bonding layer 15 and a bonding layer 15 for bonding.
　また、実施の形態１による半導体装置の製造方法は、例えば電極パッド７等の表面電極と表面電極の反対側に設けられた裏面電極１６との間にビアホール１２が形成された半導体素子１を準備する工程と、ビアホール１２の裏面電極１６側を被覆する耐熱性樹脂１３を形成する工程と、基材の表面上に金属焼結材ペースト１５ａを塗布して、金属焼結材ペースト１５ａの上に半導体素子１を搭載する工程と、金属焼結材ペースト１５ａを加熱することにより、半導体素子１と基材とを金属焼結材を主成分として含む接合層１５で接合する工程と、を有している。
　これにより、実施の形態１による半導体装置１１０は、加熱焼結時の熱収縮による導電層１４の剥がれ、または半導体素子１の割れなどを抑制することができるとともに、耐熱性樹脂１３の突起部分の高さＨ１、Ｈ２を制御することで、突起部分がスペーサーの役割を果たすこととなり、接合層１５の厚さを確保でき、温度サイクル試験に対する寿命を向上することができる。 Further, in the method for manufacturing a semiconductor device according to the first embodiment, for example, a semiconductor element 1 in which a via hole 12 is formed between a front surface electrode such as an electrode pad 7 and a back surface electrode 16 provided on the opposite side of the front surface electrode is prepared. The step of forming the heat-resistant resin 13 that covers the back surface electrode 16 side of the via hole 12, and the step of applying the metal sintered material paste 15a on the surface of the base material and on the metal sintered material paste 15a. It includes a step of mounting the semiconductor element 1 and a step of joining the semiconductor element 1 and the base material with a bonding layer 15 containing the metal sintered material as a main component by heating the metal sintered material paste 15a. ing.
As a result, the semiconductor device 110 according to the first embodiment can suppress peeling of the conductive layer 14 or cracking of the semiconductor element 1 due to heat shrinkage during heat sintering, and also suppresses the protrusion portion of the heat-resistant resin 13. By controlling the heights H1 and H2, the protruding portion acts as a spacer, the thickness of the bonding layer 15 can be secured, and the life for the temperature cycle test can be improved.
実施の形態２．
　図７は、実施の形態２による半導体装置の半導体素子の裏面を示す平面図である。なお、実施の形態２による半導体装置１１０の説明について、実施の形態１と同様の構成部分は、同一の符号を付して適宜説明を省略する。
　実施の形態１では、耐熱性樹脂１３で覆われたビアホール１２が、半導体素子１の中央に設けられた構造について図示したが、ビアホール１２および耐熱性樹脂バンプの形成位置はこれに限られるものではない。 Embodiment 2.
FIG. 7 is a plan view showing the back surface of the semiconductor element of the semiconductor device according to the second embodiment. Regarding the description of the semiconductor device 110 according to the second embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted as appropriate.
In the first embodiment, the structure in which the via hole 12 covered with the heat-resistant resin 13 is provided in the center of the semiconductor element 1 is illustrated, but the positions where the via hole 12 and the heat-resistant resin bump are formed are not limited to this. No.
　図７の７Ａに示すように、実施の形態２による半導体装置１１０の半導体素子１において、耐熱性樹脂１３で覆われたビアホール１２は、半導体素子１の中央および半導体素子１の外周端面の全周に形成されている。図７の７Ａに示した配置が最も多くのビアホール１２および耐熱性樹脂バンプが形成されるものであり、接合層１５の厚さを最も確実に確保でき、半導体素子１の面内の高さのばらつきを最も小さくすることができる。そのため、図７の７Ａに示す半導体素子１が搭載された半導体装置１１０は、安定的に高い信頼性が得られる。 As shown in 7A of FIG. 7, in the semiconductor element 1 of the semiconductor device 110 according to the second embodiment, the via hole 12 covered with the heat-resistant resin 13 is the center of the semiconductor element 1 and the entire circumference of the outer peripheral end surface of the semiconductor element 1. Is formed in. The arrangement shown in 7A of FIG. 7 forms the largest number of via holes 12 and heat-resistant resin bumps, the thickness of the bonding layer 15 can be secured most reliably, and the in-plane height of the semiconductor element 1 can be secured. The variation can be minimized. Therefore, the semiconductor device 110 on which the semiconductor element 1 shown in 7A of FIG. 7 is mounted can stably obtain high reliability.
　特に、ディスペンス装置にて金属焼結材ペースト１５ａを例えばヒートシンク６等の基材に塗布し、半導体素子１をマウントする場合、中央に塗布した金属焼結材ペースト１５ａを外側に向かって押し拡げるため、半導体素子１の中央の接合層１５が厚くなり、半導体素子１の外周端部になるほど接合層１５の厚さが薄くなる。さらに、はんだ材とは異なり、金属焼結材ペースト１５ａは溶融して濡れ拡がることがないため、不均一な厚みのまま焼結接合が完了することが多い。温度サイクル時の応力歪みは、接合層１５の外周端部に最も集中するため、接合層１５の平均厚さは確保できていたとしても厚さ不均一により、薄くなった接合層１５からクラックの発生、進展が生じてしまう。図７の７Ａに示すように、実施の形態２による半導体装置１１０によれば、均一な厚みで接合層１５が得られることによって、外周端部に発生する亀裂、進展を抑制することが可能となる。 In particular, when the metal sintered material paste 15a is applied to a base material such as a heat sink 6 by a dispensing device and the semiconductor element 1 is mounted, the metal sintered material paste 15a applied to the center is spread outward. The central bonding layer 15 of the semiconductor element 1 becomes thicker, and the thickness of the bonding layer 15 becomes thinner toward the outer peripheral end of the semiconductor element 1. Further, unlike the solder material, the metal sintered material paste 15a does not melt and spread wet, so that the sintered joint is often completed with a non-uniform thickness. Since the stress strain during the temperature cycle is most concentrated at the outer peripheral end of the joint layer 15, even if the average thickness of the joint layer 15 can be secured, the thickness is not uniform and the thinned joint layer 15 is cracked. Occurrence and progress will occur. As shown in 7A of FIG. 7, according to the semiconductor device 110 according to the second embodiment, it is possible to suppress cracks and growth generated at the outer peripheral end portion by obtaining the bonding layer 15 with a uniform thickness. Become.
　また、ビアホール１２の直下は、マウント時に金属焼結材ペースト１５ａを押し込む力が弱くなり、ビアホール１２の直下がよりポーラスで疎な接合層になりやすい。ポーラスで疎な接合層は、強度的にも弱く、信頼性試験でのクラック発生の起点にもなりやすい。しかしながら、ビアホール１２内部を耐熱性樹脂１３で覆うことで、マウント時に金属焼結材ペースト１５ａを例えば外周端部などの他の領域と同様に押し込むことができ、均一で密な接合層１５を得ることができる。 Further, directly under the via hole 12, the force for pushing the metal sintered material paste 15a at the time of mounting becomes weak, and the force directly under the via hole 12 tends to be a more porous and sparse bonding layer. The porous and sparse bonding layer is also weak in strength and tends to be a starting point for cracks in the reliability test. However, by covering the inside of the via hole 12 with the heat-resistant resin 13, the metal sintered material paste 15a can be pushed in in the same manner as other regions such as the outer peripheral end portion at the time of mounting, and a uniform and dense bonding layer 15 can be obtained. be able to.
　図７の７Ｂおよび７Ｃに示すように、実施の形態２による半導体装置１１０の半導体素子１において、耐熱性樹脂１３で覆われたビアホール１２は、半導体素子１の中央および外周端面の対向する２辺を一対とした場合のいずれかの一対に形成されている。いずれか一対の２辺にのみにビアホール１２および耐熱性樹脂１３を形成したとしても、接合層１５の厚さを確保することに問題はない。また、ビアホール１２および耐熱性樹脂１３が形成されていない一対の２辺から金属焼結材ペースト１５ａの焼結時に揮発した溶剤が外に抜けやすくなり、接合層１５の内部に発生するボイドを抑制することができ、また熱収縮を促進させることでより密な接合層１５を得られる。 As shown in 7B and 7C of FIG. 7, in the semiconductor element 1 of the semiconductor device 110 according to the second embodiment, the via hole 12 covered with the heat-resistant resin 13 is formed on two opposite sides of the central and outer peripheral end faces of the semiconductor element 1. Are formed in any pair when is paired with each other. Even if the via holes 12 and the heat-resistant resin 13 are formed only on any one pair of two sides, there is no problem in ensuring the thickness of the bonding layer 15. In addition, the solvent volatilized during the sintering of the metal sintering material paste 15a easily escapes from the pair of two sides on which the via hole 12 and the heat-resistant resin 13 are not formed, thereby suppressing voids generated inside the bonding layer 15. And by promoting heat shrinkage, a denser bonding layer 15 can be obtained.
　図７の７Ｄに示すように、実施の形態２による半導体装置１１０の半導体素子１において、耐熱性樹脂１３で覆われたビアホール１２は、半導体素子1の中央および四隅に形成されている。７Ｄの構造が最もビアホール１２および耐熱性樹脂１３の数が少ないものの、最も揮発した溶剤が抜けやすくなり、最も密な接合層１５を得ることができる。前述したビアホール１２および耐熱性樹脂１３の形成位置または数に関しては、各々の半導体装置１１０に求められる接合厚さ、ばらつき、接合層１５の熱伝導率または接合層１５内部の状態によって適宜決定すればよい。 As shown in 7D of FIG. 7, in the semiconductor element 1 of the semiconductor device 110 according to the second embodiment, the via holes 12 covered with the heat-resistant resin 13 are formed at the center and the four corners of the semiconductor element 1. Although the 7D structure has the smallest number of via holes 12 and heat-resistant resin 13, the most volatile solvent can be easily released, and the densest bonding layer 15 can be obtained. The positions or numbers of the via holes 12 and the heat-resistant resin 13 described above may be appropriately determined depending on the bonding thickness and variation required for each semiconductor device 110, the thermal conductivity of the bonding layer 15, or the state inside the bonding layer 15. good.
　高周波通信用の半導体素子１は、高い高周波特性を得るために、一般的に長方形であることが多い。即ち、対の短辺と長辺が存在する。図７の７Ｂおよび７Ｃにおいて、半導体素子１のどちらか一対の２辺にのみに形成されたビアホール１２および耐熱性樹脂１３について説明したが、長方形の半導体素子１に関して、特に短辺側のみに形成することで高い信頼性を確保可能である。半導体素子１のアスペクト比により、半導体素子１の中心から外周端面までの距離を考えると長辺側から揮発した溶剤が優先的に抜けていくため、短辺側のみにビアホール１２および耐熱性樹脂１３を形成することで接合層１５の厚さの確保とポーラス構造の抑制を効率よく実現することができる。 The semiconductor element 1 for high frequency communication is generally rectangular in order to obtain high high frequency characteristics. That is, there are a pair of short and long sides. In 7B and 7C of FIG. 7, the via holes 12 and the heat-resistant resin 13 formed only on either pair of two sides of the semiconductor element 1 have been described, but the rectangular semiconductor element 1 is formed only on the short side. By doing so, high reliability can be ensured. Considering the distance from the center of the semiconductor element 1 to the outer peripheral end surface due to the aspect ratio of the semiconductor element 1, the solvent volatilized from the long side is preferentially released. Therefore, the via hole 12 and the heat-resistant resin 13 are provided only on the short side. By forming the above, it is possible to efficiently secure the thickness of the bonding layer 15 and suppress the porous structure.
　本願は、様々な例示的な実施の形態及び実施例が記載されているが、１つ、または複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるのではなく、単独で、または様々な組み合わせで実施の形態に適用可能である。
　従って、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。例えば、少なくとも１つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも１つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。 Although the present application describes various exemplary embodiments and examples, the various features, embodiments, and functions described in one or more embodiments are applications of a particular embodiment. It is not limited to, but can be applied to embodiments alone or in various combinations.
Therefore, innumerable variations not illustrated are envisioned within the scope of the techniques disclosed herein. For example, it is assumed that at least one component is modified, added or omitted, and further, at least one component is extracted and combined with the components of other embodiments.
　１　半導体素子、２　回路基板、３　ボンディングワイヤ、４　リード、５　封止樹脂、６　ヒートシンク、７　電極パッド、１２　ビアホール、１３　耐熱性樹脂、１４　導電層、１５　接合層、１５ａ　金属焼結材ペースト、１６　裏面電極、１７　接線、θ１、θ２　角度、Ｈ１、Ｈ２　突起部分の高さ、１１０　半導体装置 1 semiconductor element, 2 circuit board, 3 bonding wire, 4 lead, 5 sealing resin, 6 heat sink, 7 electrode pad, 12 via hole, 13 heat resistant resin, 14 conductive layer, 15 bonding layer, 15a metal sintered material paste, 16 back electrode, 17 tangent wire, θ1, θ2 angle, H1, H2 height of protrusion, 110 semiconductor device

Claims (11)

  1. 　表面電極と前記表面電極の反対側に設けられた裏面電極との間にビアホールが形成された半導体素子と、
    　前記ビアホールの前記裏面電極側を被覆する耐熱性樹脂と、
    　前記半導体素子を搭載する基材と、
    　金属焼結材を主成分として含み、前記半導体素子と前記基材とを接合する接合層と、を備えた半導体装置。     A semiconductor device in which a via hole is formed between the front surface electrode and the back surface electrode provided on the opposite side of the front surface electrode, and
    A heat-resistant resin that covers the back electrode side of the via hole,
    The base material on which the semiconductor element is mounted and
    A semiconductor device including a metal sintered material as a main component and a bonding layer for joining the semiconductor element and the base material.
  2. 　前記耐熱性樹脂は、前記裏面電極側にバンプ状に設けられるとともに前記ビアホールの内部に充填されたことを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the heat-resistant resin is provided in a bump shape on the back electrode side and is filled inside the via hole.
  3. 　前記半導体素子の前記裏面電極と前記耐熱性樹脂とが接する角度は、３０度よりも大きいことを特徴とする請求項１または請求項２に記載の半導体装置。 The semiconductor device according to claim 1 or 2, wherein the angle at which the back electrode of the semiconductor element and the heat-resistant resin are in contact with each other is larger than 30 degrees.
  4. 　前記半導体素子の前記裏面電極と前記耐熱性樹脂とが接する角度は、９０度以上であることを特徴とする請求項１から請求項３のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3, wherein the angle of contact between the back electrode of the semiconductor element and the heat-resistant resin is 90 degrees or more.
  5. 　前記裏面電極側に形成された前記耐熱性樹脂の膜厚は、前記半導体素子の厚みの１／１０以上であることを特徴とする請求項１から請求項４のいずれか１項に記載の半導体装置。 The semiconductor according to any one of claims 1 to 4, wherein the film thickness of the heat-resistant resin formed on the back surface electrode side is 1/10 or more of the thickness of the semiconductor element. Device.
  6. 　前記耐熱性樹脂は、金属粒子を含むことを特徴とする請求項１から請求項５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, wherein the heat-resistant resin contains metal particles.
  7. 　前記耐熱性樹脂で覆われた前記ビアホールは、前記半導体素子の中央部に設けられたことを特徴とする請求項１から請求項６のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 6, wherein the via hole covered with the heat-resistant resin is provided in the central portion of the semiconductor element.
  8. 　前記耐熱性樹脂で覆われた前記ビアホールは、前記半導体素子の外周に設けられたことを特徴とする請求項１から請求項７のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, wherein the via hole covered with the heat-resistant resin is provided on the outer periphery of the semiconductor element.
  9. 　前記耐熱性樹脂で覆われた前記ビアホールは、前記半導体素子の外周の対向する２辺に設けられたことを特徴とする請求項１から請求項７のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, wherein the via holes covered with the heat-resistant resin are provided on two opposite sides of the outer periphery of the semiconductor element.
  10. 　前記耐熱性樹脂で覆われた前記ビアホールが、前記半導体素子の裏面の四隅に設けられたことを特徴とする請求項１から請求項７のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 7, wherein the via holes covered with the heat-resistant resin are provided at four corners on the back surface of the semiconductor element.
  11. 　表面電極と前記表面電極の反対側に設けられた裏面電極との間にビアホールが形成された半導体素子を準備する工程と、
    　前記ビアホールの前記裏面電極側を被覆する耐熱性樹脂を形成する工程と、
    　基材の表面上に金属焼結材ペーストを塗布して、前記金属焼結材ペーストの上に前記半導体素子を搭載する工程と、
    　前記金属焼結材ペーストを加熱することにより、前記半導体素子と前記基材とを金属焼結材を主成分として含む接合層で接合する工程と、を備えた半導体装置の製造方法。     A step of preparing a semiconductor device in which a via hole is formed between a front surface electrode and a back surface electrode provided on the opposite side of the front surface electrode, and a step of preparing a semiconductor element.
    A step of forming a heat-resistant resin that covers the back electrode side of the via hole, and
    A process of applying a metal sintered material paste on the surface of a base material and mounting the semiconductor element on the metal sintered material paste, and a process of mounting the semiconductor element on the metal sintered material paste.
    A method for manufacturing a semiconductor device, comprising a step of joining the semiconductor element and the base material with a bonding layer containing the metal sintering material as a main component by heating the metal sintering material paste.
PCT/JP2021/007655 2020-03-12 2021-03-01 Semiconductor device and method for manufacturing semiconductor device WO2021182149A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128179A (en) * 1985-11-29 1987-06-10 Nec Corp Semiconductor device
JP2004165602A (en) * 2002-09-24 2004-06-10 Hamamatsu Photonics Kk Semiconductor device and its manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128179A (en) * 1985-11-29 1987-06-10 Nec Corp Semiconductor device
JP2004165602A (en) * 2002-09-24 2004-06-10 Hamamatsu Photonics Kk Semiconductor device and its manufacturing method

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