JP6854810B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6854810B2
JP6854810B2 JP2018514257A JP2018514257A JP6854810B2 JP 6854810 B2 JP6854810 B2 JP 6854810B2 JP 2018514257 A JP2018514257 A JP 2018514257A JP 2018514257 A JP2018514257 A JP 2018514257A JP 6854810 B2 JP6854810 B2 JP 6854810B2
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metal
metal member
circuit pattern
semiconductor device
electrode
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悠矢 清水
悠矢 清水
藤野　純司
純司 藤野
裕史 川島
裕史 川島
和彦 作谷
和彦 作谷
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

本発明は、半導体素子を備えた半導体装置に関する。 The present invention relates to a semiconductor device including a semiconductor element.

半導体装置では、半導体素子を基板の回路パターンへ接合する際の接合材としてはんだ材料が広く使用されている。また、半導体装置の低コスト化、製造工程の簡素化を目的として、導電性接着剤をはんだ材料に代わる接合材として用いた半導体装置も普及しつつある。 In semiconductor devices, a solder material is widely used as a bonding material when bonding a semiconductor element to a circuit pattern of a substrate. Further, for the purpose of reducing the cost of semiconductor devices and simplifying the manufacturing process, semiconductor devices using a conductive adhesive as a bonding material instead of a solder material are becoming widespread.

導電性接着剤により半導体素子を基板の回路パターンへ接合する場合には、一般に、半導体装置の回路パターンが銅やアルミニウムなどで形成され、回路パターンの表面には自然酸化膜が存在するため、半導体素子と回路パターンとは酸化膜を介して接合される。この酸化膜の存在により、半導体素子と回路パターンとの間の電気抵抗は、酸化膜が無い場合に比べて大きくなる。また、酸化膜の膜厚や膜質などの状態は個体毎にばらつくため、半導体素子と回路パターンとの間の電気抵抗や熱抵抗が個体毎にばらつくといった問題がある。 When a semiconductor element is bonded to a circuit pattern of a substrate with a conductive adhesive, the circuit pattern of the semiconductor device is generally formed of copper, aluminum, or the like, and a natural oxide film is present on the surface of the circuit pattern. The element and the circuit pattern are joined via an oxide film. Due to the presence of this oxide film, the electrical resistance between the semiconductor element and the circuit pattern becomes larger than in the case without the oxide film. Further, since the state of the oxide film such as the film thickness and the film quality varies from individual to individual, there is a problem that the electrical resistance and thermal resistance between the semiconductor element and the circuit pattern vary from individual to individual.

このような問題点を解決するために、従来の半導体装置では、ワイヤボンディング装置により難酸化性金属材料からなるワイヤの先端を溶融してボール状ワイヤを形成し、ボール状ワイヤを第１の金属部材に載せた後、ボール状ワイヤに超音波を印加してワイヤと第１の金属部材との接合を行っていた。これにより、第１の金属部材の表面上に存在する酸化膜が除去され、接続電極であるボール状ワイヤと第１の金属部材とが酸化膜を介さずに金属結合により接合され、第１の金属部材と接続電極との間の電気抵抗を無視できるほどに小さくしていた（例えば、特許文献１参照）。 In order to solve such a problem, in a conventional semiconductor device, a wire bonding device melts the tip of a wire made of a refractory metal material to form a ball-shaped wire, and the ball-shaped wire is made of a first metal. After being placed on the member, ultrasonic waves were applied to the ball-shaped wire to bond the wire to the first metal member. As a result, the oxide film existing on the surface of the first metal member is removed, and the ball-shaped wire as the connection electrode and the first metal member are joined by a metal bond without passing through the oxide film, and the first metal member is formed. The electrical resistance between the metal member and the connecting electrode was made so small that it could be ignored (see, for example, Patent Document 1).

特開２００２−１１０７５０号公報Japanese Unexamined Patent Publication No. 2002-11750

しかしながら、特許文献１に記された従来の半導体装置では、第１の金属部材と接続電極との電気抵抗は良好なものにできるものの、接続電極の表面積が小さいので、接続電極と導電性接合層との間の接触面積も小さくなり、導電性接合層内を電流が流れる実質的な断面積が小さくなる。この結果、第１の金属部材と第２の金属部材との間の電気抵抗を十分に小さくすることができないという問題点があった。 However, in the conventional semiconductor device described in Patent Document 1, although the electrical resistance between the first metal member and the connecting electrode can be made good, the surface area of the connecting electrode is small, so that the connecting electrode and the conductive bonding layer are formed. The contact area between the two is also small, and the substantial cross-sectional area where the current flows in the conductive bonding layer is small. As a result, there is a problem that the electric resistance between the first metal member and the second metal member cannot be sufficiently reduced.

本発明は、上述のような問題を解決するためになされたもので、第１の金属部材と第２の金属部材との間の電気抵抗を小さくすることができる半導体装置を提供することを目的とする。 The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of reducing the electric resistance between the first metal member and the second metal member. And.

本発明に係る半導体装置は、第１の金属部材と、第１の金属部材と電気的に接続される第２の金属部材と、第１の金属部材と第２の金属部材との間に設けられ、第１の金属部材と第２の金属部材とに接合された導電性接合層と、第１の金属部材に接合された第１の端部および導電性接合層内に設けられた胴体部を有し、胴体部が第１の金属部材の表面に沿って延伸した金属線と、を備える。 The semiconductor device according to the present invention is provided between the first metal member, the second metal member electrically connected to the first metal member, and the first metal member and the second metal member. The conductive bonding layer joined to the first metal member and the second metal member, the first end portion joined to the first metal member, and the body portion provided in the conductive bonding layer. The body portion is provided with a metal wire extending along the surface of the first metal member.

本発明に係る半導体装置によれば、第１の金属部材に端部が接合された金属線の胴体部が第１の金属部材の表面に沿って延伸して設けられているため、金属線と導電性接合層との接触面積を大きくすることができ、導電性接合層で接合された第１の金属部材と第２の金属部材との間の電気抵抗を小さくすることができる。 According to the semiconductor device according to the present invention, the body portion of the metal wire whose end is joined to the first metal member is provided so as to extend along the surface of the first metal member. The contact area with the conductive bonding layer can be increased, and the electrical resistance between the first metal member and the second metal member bonded by the conductive bonding layer can be reduced.

本発明の実施の形態１における半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device in Embodiment 1 of this invention. 本発明の実施の形態１におけるリードフレームと半導体素子との接合部の構成を示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a configuration of a joint portion between a lead frame and a semiconductor element according to the first embodiment of the present invention. 本発明の実施の形態１におけるリードフレームの半導体素子との接合部の構成を示す拡大平面図である。It is an enlarged plan view which shows the structure of the junction part with the semiconductor element of the lead frame in Embodiment 1 of this invention. 本発明の実施の形態１における他の構成のリードフレームの半導体素子との接合部の構成を示す拡大平面図である。It is an enlarged plan view which shows the structure of the joint part with the semiconductor element of the lead frame of another structure in Embodiment 1 of this invention. 本発明の実施の形態１における他の構成のリードフレームと半導体素子との接合部の構成示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a configuration of a joint portion between a lead frame having another configuration and a semiconductor element according to the first embodiment of the present invention. 本発明の実施の形態１における半導体装置の金属線を接合する製造方法を示す図である。It is a figure which shows the manufacturing method which joins the metal wire of the semiconductor device in Embodiment 1 of this invention. 本発明の実施の形態２における半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device in Embodiment 2 of this invention. 本発明の実施の形態３における半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device in Embodiment 3 of this invention. 本発明の実施の形態３における回路パターンとリード端子との接合部の構成を示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a configuration of a joint portion between a circuit pattern and a lead terminal in the third embodiment of the present invention. 本発明の実施の形態３における回路パターンとリード端子との接合部の他の構成を示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing another configuration of a joint portion between a circuit pattern and a lead terminal in the third embodiment of the present invention. 本発明の実施の形態４における半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device in Embodiment 4 of this invention. 本発明の実施の形態４における半導体装置のＩＧＢＴとリードフレームとの接合部の構成を示す拡大断面図である。It is an enlarged cross-sectional view which shows the structure of the joint part of the IGBT and the lead frame of the semiconductor device in Embodiment 4 of this invention. 本発明の実施の形態５における半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device in Embodiment 5 of this invention. 本発明の実施の形態５における半導体装置のＩＧＢＴと配線基板との接合部の構成を示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a configuration of a joint portion between an IGBT of a semiconductor device and a wiring board according to a fifth embodiment of the present invention. 本発明の実施の形態５における半導体装置の他の構成のＩＧＢＴと配線基板との接合部の構成を示す拡大断面図および拡大平面図である。It is an enlarged cross-sectional view and the enlarged plan view which show the structure of the joint part of the IGBT and the wiring board of another structure of the semiconductor device in Embodiment 5 of this invention.

実施の形態１．
まず、本発明の実施の形態１における半導体装置の構成を説明する。図１は、本発明の実施の形態１における半導体装置を示す断面図である。Embodiment 1.
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention.

図１において、半導体装置１００は、電力用の半導体素子であるＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲートバイポーラトランジスタ）とＦＷＤ（Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄｅ：還流ダイオード）と、ＩＧＢＴのスイッチングを制御するための集積回路（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ、以下ＩＣと称する）が形成されたＩＣチップやダイオードなどの制御用の半導体素子と、各半導体素子を配線する配線部材であるリードフレームとが、半導体装置のケースとなる封止樹脂内に一体的に形成された構成をしている。 In FIG. 1, the semiconductor device 100 includes an IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode), which are semiconductor elements for electric power, and an integrated circuit for controlling switching of the IGBT. A sealing resin in which a semiconductor element for control such as an IC chip or a diode on which (Insulated Circuit, hereinafter referred to as an IC) is formed and a lead frame which is a wiring member for wiring each semiconductor element form a case of a semiconductor device. It has a structure that is integrally formed inside.

半導体装置１００は、配線部材であるリードフレーム１ａ、１ｂ、１ｃと、リードフレーム１ａに接合された電力用の半導体素子であるＩＧＢＴ２およびＦＷＤ３と、リードフレーム１ｃに接合された制御用の半導体素子８ａ、８ｂとを備えている。また、ＩＧＢＴ２およびＦＷＤ３は、リードフレーム１ａに接合された側と反対側の面に設けられた電極に接合されたアルミニウムなどの金属ワイヤ５ａ、５ｂによりリードフレーム１ｂに電気的に接続されている。さらに、制御用の半導体素子８ａ、８ｂは、リードフレーム１ｃに接合された側と反対側の面に設けられた電極に接合されたアルミニウムなどの金属ワイヤ１２ａ、１２ｂによりＩＧＢＴ２に電気的に接続されている。 The semiconductor device 100 includes lead frames 1a, 1b, and 1c, which are wiring members, IGBT2 and FWD3, which are semiconductor elements for electric power bonded to the lead frame 1a, and a control semiconductor element 8a, which is bonded to the lead frame 1c. , 8b and. Further, the IGBT 2 and the FWD 3 are electrically connected to the lead frame 1b by metal wires 5a and 5b such as aluminum bonded to electrodes provided on a surface opposite to the side bonded to the lead frame 1a. Further, the control semiconductor elements 8a and 8b are electrically connected to the IGBT 2 by metal wires 12a and 12b such as aluminum bonded to electrodes provided on the surface opposite to the side bonded to the lead frame 1c. ing.

表面にＩＧＢＴ２およびＦＷＤ３が接合されたリードフレーム１ａの裏面には、絶縁層６が設けられ、絶縁層６の裏面にはアルミニウムや銅などの熱伝導率が高い金属材料からなる金属板７が設けられている。絶縁層６は、リードフレーム１ａと金属板７との電気的な絶縁を確保しつつ、ＩＧＢＴ２およびＦＷＤ３からの熱を金属板７に伝熱するための層である。絶縁層６は、シリカ粒子、アルミナ粒子、窒化アルミ粒子などの熱伝導率が高い絶縁物の粒子をエポキシ樹脂などの絶縁物の樹脂に混合して形成され、放熱性と絶縁性とを両立している。金属板７は、絶縁層６を介してＩＧＢＴ２およびＦＷＤ３から伝熱してきた熱を金属板７の面方向に拡散し、金属板７の裏面に設けられるヒートシンク(図示せず)に伝熱し、ＩＧＢＴ２およびＦＷＤ３で発熱した熱はヒートシンクから半導体装置１００の外部に放熱される。 An insulating layer 6 is provided on the back surface of the lead frame 1a to which the IGBT 2 and FWD 3 are bonded to the front surface, and a metal plate 7 made of a metal material having high thermal conductivity such as aluminum or copper is provided on the back surface of the insulating layer 6. Has been done. The insulating layer 6 is a layer for transferring heat from the IGBT 2 and the FWD 3 to the metal plate 7 while ensuring electrical insulation between the lead frame 1a and the metal plate 7. The insulating layer 6 is formed by mixing particles of an insulator having high thermal conductivity such as silica particles, alumina particles, and aluminum nitride particles with an insulating resin such as an epoxy resin, and has both heat dissipation and insulating properties. ing. The metal plate 7 diffuses the heat transferred from the IGBT 2 and the FWD 3 through the insulating layer 6 toward the surface of the metal plate 7 and transfers the heat to a heat sink (not shown) provided on the back surface of the metal plate 7 to transfer the heat to the IGBT 2 The heat generated by the FWD 3 is dissipated from the heat sink to the outside of the semiconductor device 100.

リードフレーム１ａおよびリードフレーム１ａに接合されたＩＧＢＴ２、ＦＷＤ３と、リードフレーム１ｂと、リードフレーム１ｃおよびリードフレーム１ｃに接合された制御用の半導体素子８ａ、８ｂと、絶縁層６と、金属板７と、各素子や各リードフレームを電気的に接続する金属ワイヤ５ａ、５ｂ、１２ａ、１２ｂとを、エポキシ樹脂にシリカ粒子を混合して形成した封止樹脂１０で封止して、半導体装置１００は一体的に形成される。図１に示すように、リードフレーム１ａ、１ｂ、１ｃのそれぞれは一端側が封止樹脂１０の外部に露出しており、外部端子１１ａ、１１ｂ、１１ｃを構成している。半導体装置１００は、外部端子１１ａ、１１ｂ、１１ｃを介して外部の電気回路に電気的に接続される。 The IGBTs 2 and FWD3 bonded to the lead frame 1a and the lead frame 1a, the lead frame 1b, the control semiconductor elements 8a and 8b bonded to the lead frame 1c and the lead frame 1c, the insulating layer 6, and the metal plate 7 And the metal wires 5a, 5b, 12a, 12b that electrically connect each element and each lead frame are sealed with a sealing resin 10 formed by mixing silica particles with an epoxy resin, and the semiconductor device 100 Is formed integrally. As shown in FIG. 1, one end of each of the lead frames 1a, 1b, and 1c is exposed to the outside of the sealing resin 10, and constitutes the external terminals 11a, 11b, and 11c. The semiconductor device 100 is electrically connected to an external electric circuit via the external terminals 11a, 11b, and 11c.

リードフレーム１ａ、１ｂ、１ｃはアルミニウムまたは銅などの酸化されやすい金属材料で形成されている。ここで、酸化されやすい金属材料とは、金や銀などの貴金属（Ｐｒｅｃｉｏｕｓ ｍｅｔａｌ）材料よりも酸化されやすい金属材料をいい、卑金属（Ｂａｓｅ ｍｅｔａｌ）材料を指す。さらに具体的に言えば本発明でいう卑金属材料は、好ましくはアルミニウム（Ａｌ）、銅（Ｃｕ）、ニッケル（Ｎｉ）、錫（Ｓｎ）のいずれかであり、アルミニウム、銅、ニッケル、錫のいずれかを主成分とする合金を含む。また、具体的に言えば本発明でいう貴金属材料は、好ましくは金（Ａｕ）、銀（Ａｇ）のいずれかであり、金、銀のいずれかを主成分とする合金を含む。 The lead frames 1a, 1b and 1c are made of an easily oxidizable metal material such as aluminum or copper. Here, the metal material that is easily oxidized means a metal material that is more easily oxidized than a precious metal (Precious metal) material such as gold or silver, and refers to a base metal material. More specifically, the base metal material referred to in the present invention is preferably any one of aluminum (Al), copper (Cu), nickel (Ni), and tin (Sn), and any of aluminum, copper, nickel, and tin. Includes alloys whose main component is nickel. Specifically, the noble metal material referred to in the present invention is preferably either gold (Au) or silver (Ag), and contains an alloy containing either gold or silver as a main component.

また、本発明でいう２つの金属材料を比較した場合の酸化されにくさ、酸化されやすさとは、その２つの金属材料の主成分となる金属元素のイオン化傾向の大小関係をもっていうことができる。すなわち、イオン化傾向が小さい金属材料ほど酸化されにくい金属材料であり、イオン化傾向が大きい金属材料ほど酸化されやすい金属材料である。例えば、上に例示した貴金属材料と卑金属材料とをイオン化傾向が小さい順に列挙すると、金、銀、銅、錫、ニッケル、アルミニウムとなる。従って、酸化されにくい順に列挙すると、金、銀、銅、錫、ニッケル、アルミニウムとなる。また、これらの金属元素を主成分とする合金についても同様であり、例えば、銀合金は銅合金よりも酸化されにくく、銅合金はアルミニウム合金よりも酸化されにくい。 Further, the difficulty of oxidation and the ease of oxidation when the two metal materials referred to in the present invention are compared can be said to have a magnitude relationship of the ionization tendency of the metal element which is the main component of the two metal materials. That is, a metal material having a lower ionization tendency is a metal material that is less likely to be oxidized, and a metal material having a higher ionization tendency is a metal material that is more easily oxidized. For example, if the precious metal materials and base metal materials exemplified above are listed in ascending order of ionization tendency, they are gold, silver, copper, tin, nickel, and aluminum. Therefore, when listed in order of resistance to oxidation, they are gold, silver, copper, tin, nickel, and aluminum. The same applies to alloys containing these metal elements as main components. For example, silver alloys are less likely to be oxidized than copper alloys, and copper alloys are less likely to be oxidized than aluminum alloys.

なお、本発明でいう卑金属材料および貴金属材料は、上に例示した金属材料に限らず他の金属材料であってもよい。上に例示した金属材料は、工業的に多く使用されており、入手のしやすさなどから工業的に好ましい。また、以下において、金属材料をその金属元素の名前で呼ぶ場合には、その金属材料は、その金属元素単体からなる純金属である場合の他にその金属元素を主成分とする合金である場合を含み、純金属と合金との区別を必要とする場合のみ、純金属と合金とを明示して説明する。 The base metal material and the noble metal material referred to in the present invention are not limited to the metal materials exemplified above, and may be other metal materials. The metal materials exemplified above are widely used industrially and are industrially preferable because of their availability. In the following, when a metal material is referred to by the name of the metal element, the metal material is not only a pure metal composed of the metal element alone but also an alloy containing the metal element as a main component. Only when it is necessary to distinguish between a pure metal and an alloy, the pure metal and the alloy will be described explicitly.

リードフレーム１ａ、１ｂ、１ｃはアルミニウムや銅で形成されるが、リードフレーム１ａ、１ｂ、１ｃの一端側に設けられた外部端子１１ａ、１１ｂ、１１ｃには、ニッケルめっきや銀めっきなど、外部の電気回路とはんだ付けで接続するために、はんだ材料との濡れ性を良くするためのメタライズ処理が施されていてもよい。 The lead frames 1a, 1b and 1c are made of aluminum or copper, but the external terminals 11a, 11b and 11c provided on one end side of the lead frames 1a, 1b and 1c are externally plated with nickel or silver. In order to connect to the electric circuit by soldering, a metallizing process may be applied to improve the wettability with the solder material.

リードフレーム１ａは、封止樹脂１０の内部に設けられた部分にもはんだ材料との濡れ性を良くするためのメタライズ処理が施されており、リードフレーム１ａ上にＩＧＢＴ２とＦＷＤ３とが、はんだ材料４ａとはんだ材料４ｂとにより接合されている。 The lead frame 1a is also subjected to metallizing treatment to improve the wettability with the solder material at the portion provided inside the sealing resin 10, and the IGBT 2 and FWD 3 are formed on the lead frame 1a with the solder material. It is joined by 4a and the solder material 4b.

リードフレーム１ｂは、封止樹脂１０の内部に設けられた部分にもメタライズ処理を施してもよいが、メタライズ処理を施さなくてもよい。リードフレーム１ｂは、アルミニウムや銅などの酸化されやすい金属材料で形成されているが、金属ワイヤ５ｂは、ワイヤボンディング装置などを用いた超音波接合により接合されるため、接合時に印加される超音波によりリードフレーム１ｂ上の酸化膜が除去され、リードフレーム１ｂと金属ワイヤ５ｂとが金属結合により接合される。 The lead frame 1b may be metallized at a portion provided inside the sealing resin 10, but may not be metallized. The lead frame 1b is made of an easily oxidizable metal material such as aluminum or copper, but since the metal wire 5b is bonded by ultrasonic bonding using a wire bonding device or the like, ultrasonic waves applied at the time of bonding are applied. The oxide film on the lead frame 1b is removed, and the lead frame 1b and the metal wire 5b are bonded by a metal bond.

リードフレーム１ｃは、封止樹脂１０の内部に設けられた部分には銀めっきによるメタライズ処理が施されておらず、リードフレーム１ｃの母材であるアルミニウムあるいは銅が表面に露出した構成や、アルミニウムや銅を母材として表面にニッケルめっきや錫めっきを施した構成をしている。すなわち、リードフレーム１ｃの封止樹脂１０の内部の部分は、表面が卑金属材料で形成されている。リードフレーム１ｃと、制御用の半導体素子８ａおよび８ｂとは、導電性接合層９ａおよび９ｂで接合されている。 In the lead frame 1c, the portion provided inside the sealing resin 10 is not metallized by silver plating, and aluminum or copper, which is the base material of the lead frame 1c, is exposed on the surface, or aluminum. The surface is nickel-plated or tin-plated using copper or copper as the base material. That is, the surface of the inner portion of the sealing resin 10 of the lead frame 1c is formed of a base metal material. The lead frame 1c and the control semiconductor elements 8a and 8b are joined by conductive bonding layers 9a and 9b.

導電性接合層９ａ、９ｂは、例えば、エポキシ樹脂やシリコン樹脂に直径が１μｍ以上１０μｍ以下の球状または鱗片状の銀や銅などの金属粒子を混合した導電性接着剤である。エポキシ樹脂中やシリコン樹脂中では、複数の金属粒子が互いに接触して存在しているため、金属粒子同士の接触を通じて電気伝導と熱伝導とが行われる。この結果、導電性接合層９ａ、９ｂにより制御用の半導体素子８ａ、８ｂとリードフレーム１ｃとが電気的および熱的に接続される。従って、導電性接着剤に用いられる金属粒子としては、粒子表面が酸化されにくい貴金属粒子が好ましく銀粒子がより好ましい。 The conductive bonding layers 9a and 9b are, for example, conductive adhesives obtained by mixing an epoxy resin or a silicon resin with spherical or scaly metal particles such as silver or copper having a diameter of 1 μm or more and 10 μm or less. Since a plurality of metal particles are present in contact with each other in an epoxy resin or a silicon resin, electrical conduction and heat conduction are performed through contact between the metal particles. As a result, the control semiconductor elements 8a and 8b and the lead frame 1c are electrically and thermally connected by the conductive bonding layers 9a and 9b. Therefore, as the metal particles used in the conductive adhesive, noble metal particles whose surface is less likely to be oxidized are preferable, and silver particles are more preferable.

また、導電性接着剤に含有される金属粒子として、直径が１ｎｍ以上１０００ｎｍ未満の金属粒子である金属ナノ粒子を単体で、あるいは直径が１μｍ以上１０μｍ以下の金属粒子と金属ナノ粒子とを混合して用いてもよい。導電性接着剤に金属ナノ粒子を含有させて、金属ナノ粒子の焼結温度以上に加熱すると、金属ナノ粒子が他の金属粒子と金属結合して焼結体となるため、金属ナノ粒子を含有しない導電性接着剤に比べてさらに良好な電気伝導と熱伝導とを得ることができるので好ましい。なお、ここでいう金属粒子は、直径が１ｎｍ以上１０００ｎｍ未満の金属ナノ粒子と直径が１μｍ以上１０μｍ以下の金属粒子との両方を指す。 Further, as the metal particles contained in the conductive adhesive, metal nanoparticles having a diameter of 1 nm or more and less than 1000 nm are used alone, or metal particles having a diameter of 1 μm or more and 10 μm or less are mixed with metal nanoparticles. May be used. When the conductive adhesive contains metal nanoparticles and is heated above the sintering temperature of the metal nanoparticles, the metal nanoparticles are metal-bonded to other metal particles to form a sintered body, and thus contain the metal nanoparticles. It is preferable because better electrical conduction and thermal conduction can be obtained as compared with the conductive adhesive that does not. The metal particles referred to here refer to both metal nanoparticles having a diameter of 1 nm or more and less than 1000 nm and metal particles having a diameter of 1 μm or more and 10 μm or less.

次に、導電性接合層９ａ、９ｂによるリードフレーム１ｃと半導体素子８ａ、８ｂとの接合部の構成についてさらに詳しく説明する。 Next, the configuration of the joint portion between the lead frame 1c and the semiconductor elements 8a and 8b by the conductive joint layers 9a and 9b will be described in more detail.

図２は、本発明の実施の形態１におけるリードフレームと半導体素子との接合部の構成を示す拡大断面図である。図２の拡大断面図は、図１におけるリードフレーム１ｃと制御用の半導体素子８ａとの接合部の構成を示したものである。なお、図２では、半導体素子８ａのリードフレーム１ｃ側と反対側の電極に接合された金属ワイヤ１２ａ、１２ｂを省略して示した。 FIG. 2 is an enlarged cross-sectional view showing a configuration of a joint portion between a lead frame and a semiconductor element according to the first embodiment of the present invention. The enlarged cross-sectional view of FIG. 2 shows the configuration of the joint portion between the lead frame 1c and the semiconductor element 8a for control in FIG. In FIG. 2, the metal wires 12a and 12b joined to the electrodes on the side opposite to the lead frame 1c side of the semiconductor element 8a are omitted.

図２に示すように、半導体素子８ａは、リードフレーム１ｃの一部であり、封止樹脂１０で封止された半導体装置１００の内部に設けられた領域である第１の金属部材２５に接合されている。第１の金属部材２５の表面には自然酸化により酸化膜２０が形成されている。また、第１の金属部材２５の表面側には、一端に第１の端部２１ａを有し、他端に第２の端部２３ａを有する金属線２２ａが設けられており、第１の端部２１ａと第１の金属部材２５の表面とが金属結合により接合され、第２の端部２３ａと第１の金属部材２５の表面とが金属結合により接合されている。同様に、第１の金属部材２５の表面側には、一端に第１の端部２１ｄを有し、他端に第２の端部２３ｄを有する金属線２２ｄが設けられており、第１の端部２１ｄと第１の金属部材２５の表面とが金属結合により接合され、第２の端部２３ｄと第１の金属部材２５の表面とが金属結合により接合されている。 As shown in FIG. 2, the semiconductor element 8a is a part of the lead frame 1c and is joined to the first metal member 25 which is a region provided inside the semiconductor device 100 sealed with the sealing resin 10. Has been done. An oxide film 20 is formed on the surface of the first metal member 25 by natural oxidation. Further, on the surface side of the first metal member 25, a metal wire 22a having a first end portion 21a at one end and a second end portion 23a at the other end is provided, and the first end is provided. The portion 21a and the surface of the first metal member 25 are joined by a metal bond, and the second end portion 23a and the surface of the first metal member 25 are joined by a metal bond. Similarly, on the surface side of the first metal member 25, a metal wire 22d having a first end portion 21d at one end and a second end portion 23d at the other end is provided, and the first metal wire 22d is provided. The end portion 21d and the surface of the first metal member 25 are joined by a metal bond, and the second end portion 23d and the surface of the first metal member 25 are joined by a metal bond.

なお、ここでいう第１の端部２１ａ、２１ｄと第１の金属部材２５との金属結合、および第２の端部２３ａ、２３ｄと第１の金属部材２５との金属結合とは、化学結合の一形態である金属結合のことであり、自由電子を媒介として陽イオンとなった金属原子が結びついた状態をいう。従って、第１の端部２１ａ、２１ｄおよび第２の端部２３ａ、２３ｄのそれぞれと第１の金属部材２５とは酸化膜を介さずに電気的に接続されている。以下では、金属線２２ａについて説明するが、金属線２２ｄについても金属線２２ａと同様の構造をしている。 The metal bond between the first end portions 21a and 21d and the first metal member 25 and the metal bond between the second end portions 23a and 23d and the first metal member 25 are chemically bonded. It is a form of metal bonding, and refers to a state in which metal atoms that have become cations are bound via free electrons. Therefore, each of the first end portions 21a and 21d and the second end portions 23a and 23d and the first metal member 25 are electrically connected to each other without an oxide film. Hereinafter, the metal wire 22a will be described, but the metal wire 22d also has the same structure as the metal wire 22a.

図２に示すように、金属線２２ａの第１の端部２１ａの断面積は、金属線２２ａのうち両端部を除いた部分である胴体部の断面積よりも大きくなっている。金属線２２ａの胴体部の断面積よりも断面積が大きい第１の端部２１ａは、第１の金属部材２５の表面に対して突起状に盛り上がるように形成されて第１の金属部材２５の表面に接合されている。金属線２２ａは、ワイヤボンディング装置による超音波接合により第１の金属部材２５の表面に接合されている。 As shown in FIG. 2, the cross-sectional area of the first end portion 21a of the metal wire 22a is larger than the cross-sectional area of the body portion, which is a portion of the metal wire 22a excluding both ends. The first end portion 21a, which has a cross-sectional area larger than the cross-sectional area of the body portion of the metal wire 22a, is formed so as to bulge with respect to the surface of the first metal member 25 in a protruding shape. It is joined to the surface. The metal wire 22a is bonded to the surface of the first metal member 25 by ultrasonic bonding using a wire bonding device.

ワイヤボンディング装置による超音波接合には、接合始点にボールを形成して超音波接合を行うボールボンディングと、接合始点にボールを形成せずに超音波接合を行うウェッジボンディングとがある。図２に示す金属線２２ａの第１の端部２１ａは、ワイヤボンディング装置を用いたボールボンディングにより形成することができる。金属線２２ａの第１の端部２１ａの断面積を、金属線２２ａの胴体部の断面積よりも大きくすることで、金属線２２ａの第１の端部２１ａと第１の金属部材２５との間の金属結合の面積を大きくすることができる。また、金属線２２ａの第１の端部２１ａと導電性接合層９ａとの接触面積を大きくすることができる。この結果、導電性接合層９ａと第１の金属部材２５との間の電気抵抗を小さくすることができる。 Ultrasonic bonding by a wire bonding device includes ball bonding in which a ball is formed at a bonding start point and ultrasonic bonding is performed, and wedge bonding in which a ball is not formed at the bonding start point and ultrasonic bonding is performed. The first end portion 21a of the metal wire 22a shown in FIG. 2 can be formed by ball bonding using a wire bonding device. By making the cross-sectional area of the first end 21a of the metal wire 22a larger than the cross-sectional area of the body of the metal wire 22a, the first end 21a of the metal wire 22a and the first metal member 25 can be combined. The area of the metal bond between them can be increased. Further, the contact area between the first end portion 21a of the metal wire 22a and the conductive bonding layer 9a can be increased. As a result, the electrical resistance between the conductive bonding layer 9a and the first metal member 25 can be reduced.

金属線２２ａは、第１の金属部材２５の表面を形成する金属材料よりも酸化されにくい金属材料を胴体部の表面に有する、胴体部の直径が２０μｍ〜１００μｍ程度の細線である。第１の金属部材２５の表面がアルミニウムである場合には、金属線２２ａは胴体部の表面にアルミニウムより酸化されにくいニッケルや銅を有していてもよいが、より好ましくは、金属線２２ａはより酸化されにくい貴金属材料を有している方が好ましい。具体的には、金属線２２ａは、金線、銀線、あるいは貴金属材料を表面にコーティングした銅線が好ましい。本実施の形態１では、金属線２２ａは、例えば、直径が３７．５μｍの金線である。 The metal wire 22a is a thin wire having a metal material on the surface of the body portion, which is less likely to be oxidized than the metal material forming the surface of the first metal member 25, and having a diameter of the body portion of about 20 μm to 100 μm. When the surface of the first metal member 25 is aluminum, the metal wire 22a may have nickel or copper on the surface of the body portion, which is less likely to be oxidized than aluminum, but more preferably, the metal wire 22a is It is preferable to have a noble metal material that is less likely to be oxidized. Specifically, the metal wire 22a is preferably a gold wire, a silver wire, or a copper wire whose surface is coated with a noble metal material. In the first embodiment, the metal wire 22a is, for example, a gold wire having a diameter of 37.5 μm.

導電性接合層９ａが、第１の金属部材２５の表面上に、金属線２２ａを埋設した状態で設けられるため、導電性接合層９ａが金属線２２ａの表面と接触して、導電性接合層９ａと金属線２２ａとが電気的に接続される。金属線２２ａの胴体部は導電性接合層９ａ内に設けられており、金属線２２ａの胴体部は、第１の端部２１ａが接合された第１の金属部材２５の表面に沿って延伸している。また、金属線２２ａの胴体部は第１の金属部材２５の表層に存在する酸化膜上に設けられている。金属線２２ａは両端部を除く胴体部では、第１の金属部材２５の表面との間に間隙を有しているため、導電性接合層９ａがこの間隙に入り込むことで、導電性接合層９ａが、金属線２２ａの胴体部と第１の金属部材２５の表面との間にも設けられる。この結果、金属線２２ａと導電性接合層９ａとの接触面積が増大して金属線２２ａと導電性接合層９ａとの間の電気抵抗が低減し、さらに導電性接合層９ａが金属線２２ａによるアンカー効果によって第１の金属部材２５の表面上に強固に接合される。 Since the conductive bonding layer 9a is provided with the metal wire 22a embedded on the surface of the first metal member 25, the conductive bonding layer 9a comes into contact with the surface of the metal wire 22a, and the conductive bonding layer 9a comes into contact with the surface of the metal wire 22a. The 9a and the metal wire 22a are electrically connected. The body portion of the metal wire 22a is provided in the conductive bonding layer 9a, and the body portion of the metal wire 22a extends along the surface of the first metal member 25 to which the first end portion 21a is bonded. ing. Further, the body portion of the metal wire 22a is provided on an oxide film existing on the surface layer of the first metal member 25. Since the metal wire 22a has a gap between the metal wire 22a and the surface of the first metal member 25 in the body portion excluding both ends, the conductive joint layer 9a enters the gap, so that the conductive joint layer 9a Is also provided between the body portion of the metal wire 22a and the surface of the first metal member 25. As a result, the contact area between the metal wire 22a and the conductive bonding layer 9a is increased, the electrical resistance between the metal wire 22a and the conductive bonding layer 9a is reduced, and the conductive bonding layer 9a is formed by the metal wire 22a. It is firmly joined on the surface of the first metal member 25 by the anchor effect.

金属線２２ａは金線であるので、金属線２２ａの表面には酸化膜が存在せず、金属線２２ａは、金属線２２ａの第１の端部２１ａの表面積と金属線２２ａの胴体部の表面積とからなる大きな表面積により導電性接合層９ａと接触するので、導電性接合層９ａと金属線２２ａとが非常に小さな電気抵抗で電気的に接続される。また、金属線２２ａの第１の端部２１ａおよび第２の端部２３ａと第１の金属部材２５の表面とが金属結合により接合されているので、金属線２２ａと第１の金属部材２５との間の電気抵抗も非常に小さくなる。従って、導電性接合層９ａは第１の金属部材２５の表面上に酸化膜２０を介して設けられるが、導電性接合層９ａと第１の金属部材２５との間の電気抵抗は、酸化膜２０の影響を受けず非常に小さくなる。すなわち、第１の金属部材２５と導電性接合層９ａとは、第１の金属部材２５と金属線２２ａとの金属結合による接合部、金属線２２ａの胴体部および端部の表面と導電性接合層９ａとの接触面とを介して小さな電気抵抗で電気的に接続される。金属線２２ｄについても同様である。 Since the metal wire 22a is a gold wire, there is no oxide film on the surface of the metal wire 22a, and the metal wire 22a has the surface area of the first end portion 21a of the metal wire 22a and the surface area of the body portion of the metal wire 22a. Since the conductive bonding layer 9a is in contact with the conductive bonding layer 9a due to the large surface area formed by the above, the conductive bonding layer 9a and the metal wire 22a are electrically connected with a very small electric resistance. Further, since the first end portion 21a and the second end portion 23a of the metal wire 22a and the surface of the first metal member 25 are joined by a metal bond, the metal wire 22a and the first metal member 25 are joined together. The electrical resistance between them is also very small. Therefore, the conductive bonding layer 9a is provided on the surface of the first metal member 25 via the oxide film 20, but the electrical resistance between the conductive bonding layer 9a and the first metal member 25 is the oxide film. It is not affected by 20 and becomes very small. That is, the first metal member 25 and the conductive bonding layer 9a are jointed by metal bonding between the first metal member 25 and the metal wire 22a, and conductively bonded to the surface of the body portion and the end portion of the metal wire 22a. It is electrically connected with a small electric resistance via a contact surface with the layer 9a. The same applies to the metal wire 22d.

第１の金属部材２５の表面上に超音波接合された金属線２２ａは第１の端部２１ａに加えて第１の金属部材２５の表面に沿って延伸した胴体部を有しているため、第１の金属部材２５の表面上に第１の端部２１ａのみを超音波接合する場合に比べて、金属線２２ａと導電性接合層９ａとの間の接触面積を大きくすることができるため、金属線２２ａと導電性接合層９ａとの間の電気抵抗をより小さくすることができる。この結果、第１の金属部材２５と導電性接合層９ａとをより小さな電気抵抗で電気的に接続することができる。 Since the metal wire 22a ultrasonically bonded onto the surface of the first metal member 25 has a body portion extending along the surface of the first metal member 25 in addition to the first end portion 21a. Since the contact area between the metal wire 22a and the conductive bonding layer 9a can be increased as compared with the case where only the first end portion 21a is ultrasonically bonded onto the surface of the first metal member 25. The electrical resistance between the metal wire 22a and the conductive bonding layer 9a can be made smaller. As a result, the first metal member 25 and the conductive bonding layer 9a can be electrically connected with a smaller electric resistance.

そして、導電性接合層９ａ上に制御用の半導体素子８ａの電極２４が接触して設けられる。電極２４は、表面が銀などの酸化されにくい金属材料でメタライズ処理されており、半導体素子８ａの電極２４と導電性接合層９ａとが酸化膜を介さずに電気的に接合される。電極２４は導電性接合層９ａ上に設けられ、導電性接合層９ａと電気的に接続される第２の金属部材である。 Then, the electrode 24 of the semiconductor element 8a for control is provided in contact with the conductive bonding layer 9a. The surface of the electrode 24 is metallized with a metal material such as silver that is not easily oxidized, and the electrode 24 of the semiconductor element 8a and the conductive bonding layer 9a are electrically bonded without an oxide film. The electrode 24 is a second metal member provided on the conductive bonding layer 9a and electrically connected to the conductive bonding layer 9a.

以上の構成により、第１の金属部材２５が設けられたリードフレーム１ｃと、第２の金属部材である電極２４が設けられた半導体素子８ａとが、導電性接合層９ａにより接合されて、配線部材であるリードフレーム１ｃと半導体素子８ａとが小さな電気抵抗で電気的に接合される。 With the above configuration, the lead frame 1c provided with the first metal member 25 and the semiconductor element 8a provided with the electrode 24, which is the second metal member, are joined by the conductive bonding layer 9a and wired. The lead frame 1c, which is a member, and the semiconductor element 8a are electrically joined with a small electric resistance.

なお、金属線２２ａおよび２２ｄが金線などの貴金属線でなく、第１の金属部材２５よりも酸化されにくい卑金属材料で金属線２２ａおよび２２ｄの胴体部表面が形成されている場合には、導電性接合層９ａと金属線２２ａおよび２２ｄとが、金属線２２ａおよび２２ｄの表面に存在する自然酸化膜を介して電気的に接続される場合もあり得る。しかし、その場合であっても金属線２２ａおよび２２ｄの胴体部表面は、第１の金属部材２５の表面よりも酸化されにくいので、第１の金属部材２５と導電性接合層９ａとが第１の金属部材２５の表面の酸化膜のみを介して電気的に接続される場合よりも、第１の金属部材２５と導電性接合層９ａとの間の電気抵抗を小さくすることができる。 When the metal wires 22a and 22d are not precious metal wires such as gold wires and the body surface of the metal wires 22a and 22d is formed of a base metal material that is less likely to be oxidized than the first metal member 25, the metal wires 22a and 22d are conductive. The sex bonding layer 9a and the metal wires 22a and 22d may be electrically connected via a natural oxide film existing on the surfaces of the metal wires 22a and 22d. However, even in that case, the surfaces of the body portions of the metal wires 22a and 22d are less likely to be oxidized than the surface of the first metal member 25, so that the first metal member 25 and the conductive bonding layer 9a are first. The electrical resistance between the first metal member 25 and the conductive bonding layer 9a can be reduced as compared with the case where the metal member 25 is electrically connected only through the oxide film on the surface of the metal member 25.

図３は、本発明の実施の形態１におけるリードフレームの半導体素子との接合部の構成を示す拡大平面図である。図３の拡大平面図は、図２で示した接合部におけるリードフレーム１ｃの表面の構成を示したものである。 FIG. 3 is an enlarged plan view showing the configuration of the joint portion of the lead frame with the semiconductor element according to the first embodiment of the present invention. The enlarged plan view of FIG. 3 shows the configuration of the surface of the lead frame 1c at the joint shown in FIG.

図３において、破線で示した四角形の内部の領域が、リードフレーム１ｃの一部であって半導体装置１００の内部に設けられた第１の金属部材２５の表面上に導電性接合層９ａが設けられる接合領域である。図３に示すように、第１の金属部材２５には、複数の金属線２２ａ、２２ｂ、２２ｃ、２２ｄ、２２ｅ、および２２ｆが接合領域の中心側から外周側に向かって放射状に設けられている。図３では、金属線の数を６としているが、これに限るものではなく、好ましくは複数であればよい。金属線２２ａ、２２ｂ、２２ｃ、２２ｄ、２２ｅ、および２２ｆは、それぞれ第１の端部２１ａ、２１ｂ、２１ｃ、２１ｄ、２１ｅ、および２１ｆを備えており、それぞれ第２の端部２３ａ、２３ｂ、２３ｃ、２３ｄ、２３ｅ、および２３ｆを備えている。各第１の端部および各第２の端部は第１の金属部材２５の表面に金属結合により接合されている。図３では、金属線の胴体部の断面積よりも断面積が大きい第１の端部を、隣り合う金属線同士で第１の金属部材２５上の接合領域の中心側と外周側とに交互に位置するように設けたが、第１の端部は全て第１の金属部材２５の接合領域の外周側に位置していてもよく、全て第１の金属部材２５の接合領域の中心側に位置していてもよい。 In FIG. 3, the region inside the quadrangle shown by the broken line is a part of the lead frame 1c, and the conductive bonding layer 9a is provided on the surface of the first metal member 25 provided inside the semiconductor device 100. The junction area to be formed. As shown in FIG. 3, the first metal member 25 is provided with a plurality of metal wires 22a, 22b, 22c, 22d, 22e, and 22f radially from the central side to the outer peripheral side of the joint region. .. In FIG. 3, the number of metal wires is set to 6, but the number is not limited to this, and preferably a plurality of metal wires may be used. The metal wires 22a, 22b, 22c, 22d, 22e, and 22f each include first ends 21a, 21b, 21c, 21d, 21e, and 21f, respectively, and second ends 23a, 23b, 23c, respectively. , 23d, 23e, and 23f. Each first end and each second end is joined to the surface of the first metal member 25 by a metal bond. In FIG. 3, the first end portion having a cross-sectional area larger than the cross-sectional area of the body portion of the metal wire is alternated between the adjacent metal wires on the central side and the outer peripheral side of the joint region on the first metal member 25. However, all the first ends may be located on the outer peripheral side of the joint region of the first metal member 25, and all of them may be located on the central side of the joint region of the first metal member 25. It may be located.

また、金属線２２ａ、２２ｂ、２２ｃ、２２ｄ、２２ｅ、および２２ｆは、ウェッジボンディングにより形成されて、第１の端部の断面積を金属線の胴体部の断面積よりも大きくせずに、第１の端部と第２の端部とがほぼ同一の構成で形成されていてもよい。 Further, the metal wires 22a, 22b, 22c, 22d, 22e, and 22f are formed by wedge bonding, and the cross-sectional area of the first end portion is not larger than the cross-sectional area of the body portion of the metal wire. The end portion of 1 and the end portion of the second end may be formed in substantially the same configuration.

図３に示すように、第１の金属部材２５の接合領域に複数の金属線がほぼ等角度で放射状に設けられているため、リードフレーム１ｃ内の第１の金属部材２５と半導体素子８ａの電極２４からなる第２の金属部材との間の導電性接合層９ａに流れる電流を均等に分散して電流の集中を抑制して、第１の金属部材２５と第２の金属部材との間の電気抵抗を小さくすることができる。 As shown in FIG. 3, since a plurality of metal wires are radially provided in the joint region of the first metal member 25 at substantially equal angles, the first metal member 25 and the semiconductor element 8a in the lead frame 1c The current flowing through the conductive bonding layer 9a between the second metal member composed of the electrodes 24 is evenly distributed to suppress the concentration of the current, and between the first metal member 25 and the second metal member. The electrical resistance of the can be reduced.

金属線２２ａの線膨張係数は、金の場合で約１５ｐｐｍ／Ｋであり、銀の場合で約１９ｐｐｍ／Ｋである。金属線２２ａの線膨張係数は、導電性接合層９ａの線膨張係数（数十ｐｐｍ／Ｋ以上）と、半導体素子８ａの線膨張係数（約３ｐｐｍ／Ｋ）との中間であるため、金属線２２ａが導電性接合層９ａ内に設けられ第１の金属部材２５の表面に沿って延伸していることで、導電性接合層９ａに生じる熱応力を低減することができる。この結果、半導体装置１００の熱信頼性を向上させることができる。 The coefficient of linear expansion of the metal wire 22a is about 15 ppm / K in the case of gold and about 19 ppm / K in the case of silver. Since the coefficient of linear expansion of the metal wire 22a is between the coefficient of linear expansion of the conductive bonding layer 9a (several tens of ppm / K or more) and the coefficient of linear expansion of the semiconductor element 8a (about 3 ppm / K), the metal wire Since the 22a is provided in the conductive bonding layer 9a and extends along the surface of the first metal member 25, the thermal stress generated in the conductive bonding layer 9a can be reduced. As a result, the thermal reliability of the semiconductor device 100 can be improved.

また、第１の金属部材２５の表面上に超音波接合した金属線２２ａの胴体部を、第１の金属部材２５の超音波接合した表面に沿って延伸させているので、１回のワイヤボンディングで第１の金属部材２５の表面の広い範囲に形成することができる。このため、短い加工時間で熱応力を効果的に低減することができるので、半導体装置１００の製造コストを低減することができる。 Further, since the body portion of the metal wire 22a ultrasonically bonded on the surface of the first metal member 25 is stretched along the surface of the first metal member 25 ultrasonically bonded, one wire bonding is performed. Can be formed over a wide range of the surface of the first metal member 25. Therefore, since the thermal stress can be effectively reduced in a short processing time, the manufacturing cost of the semiconductor device 100 can be reduced.

また、導電性接合層９ａに用いられる導電性接着剤の導電率および熱伝導率は、第１の金属部材２５に端部を接合した金属線２２ａ〜２２ｆに比較して１桁〜２桁小さい場合があるため、図３に示すように金属線２２ａ〜２２ｆを放射状に設けることによって、金属線２２ａ〜２２ｆが半導体素子８ａに流れる電流や半導体素子８ａの発熱を半導体素子８ａの中心側から外周側に伝達するため、導電性接着剤を用いて半導体素子８ａを第１の金属部材２５に接合した場合でも接合部の電気伝導および熱伝導を良好にすることができる。動作中の半導体装置では半導体素子の中央部が最も高温となるが、本発明の半導体装置１００では、金属線２２ａ〜２２ｆが半導体素子８ａの中心側から外周側へ熱を逃がすことができるため、動作中の半導体素子８ａの温度を効果的に低減することができる。 Further, the conductivity and thermal conductivity of the conductive adhesive used for the conductive bonding layer 9a are one to two orders of magnitude smaller than those of the metal wires 22a to 22f whose ends are bonded to the first metal member 25. Therefore, as shown in FIG. 3, by providing the metal wires 22a to 22f radially, the current flowing through the semiconductor element 8a and the heat generated by the semiconductor element 8a are generated from the center side to the outer periphery of the semiconductor element 8a. Since the electric current is transmitted to the side, even when the semiconductor element 8a is joined to the first metal member 25 by using a conductive adhesive, the electric conduction and the heat conduction of the joint portion can be improved. In the semiconductor device in operation, the central portion of the semiconductor element has the highest temperature, but in the semiconductor device 100 of the present invention, the metal wires 22a to 22f can release heat from the central side to the outer peripheral side of the semiconductor element 8a. The temperature of the semiconductor element 8a during operation can be effectively reduced.

導電性接着剤に含まれる金属粒子が銀粒子の場合、導電性接着剤の質量に対する銀粒子の含有率が７０ｗｔ％未満であれば電気伝導および熱伝導の改善効果が特に大きくなるので、金属線２２ａ〜２２ｆを放射状に設けることが好ましい。また、導電性接着剤に含まれる金属粒子が銅粒子の場合には、銅粒子の含有率がさらにさらに高い場合であっても電気伝導および熱伝導の改善効果が得られるので、金属線２２ａ〜２２ｆを放射状に設けることが好ましい。 When the metal particles contained in the conductive adhesive are silver particles, if the content of the silver particles with respect to the mass of the conductive adhesive is less than 70 wt%, the effect of improving electrical conduction and heat conduction is particularly large, so that the metal wire It is preferable that 22a to 22f are provided radially. Further, when the metal particles contained in the conductive adhesive are copper particles, the effect of improving electric conduction and heat conduction can be obtained even when the content of the copper particles is even higher. Therefore, the metal wires 22a to It is preferable that 22f is provided radially.

さらに、図３に示すように金属線２２ａ〜２２ｆを第１の金属部材２５の接合領域の中心側から外周側に放射状に設けることによって、第１の金属部材２５の接合領域の表面上に導電性接着剤を塗布する場合に、金属線２２ａ〜２２ｆをガイドとして導電性接着剤が第１の金属部材２５の接合領域に濡れ広がるので、生産性に優れたディスペンサを用いて導電性接着剤を第１の金属部材２５の接合領域に形成することができる。導電性接着剤に含まれる金属粒子の含有率が小さい場合、導電性接着剤は流動しやすくなるため、金属線２２ａ〜２２ｆの胴体部と第１の金属部材２５の表面との間の間隙に導電性接着剤を容易に充填することができる。なお、導電性接着剤における金属粒子の充填率が８５ｗｔ％以上の場合には、狭い間隙への充填性を向上させるために金属粒子に直径が１μｍ未満の金属ナノ粒子を含む方が好ましい。 Further, as shown in FIG. 3, the metal wires 22a to 22f are radially provided from the center side to the outer peripheral side of the joint region of the first metal member 25 to conduct conductivity on the surface of the joint region of the first metal member 25. When applying the conductive adhesive, the conductive adhesive spreads wet over the joint region of the first metal member 25 using the metal wires 22a to 22f as a guide, so that the conductive adhesive is applied using a highly productive dispenser. It can be formed in the joint region of the first metal member 25. When the content of the metal particles contained in the conductive adhesive is small, the conductive adhesive tends to flow, so that the gap between the body portion of the metal wires 22a to 22f and the surface of the first metal member 25 The conductive adhesive can be easily filled. When the filling rate of the metal particles in the conductive adhesive is 85 wt% or more, it is preferable that the metal particles contain metal nanoparticles having a diameter of less than 1 μm in order to improve the filling property into a narrow gap.

図４は、本発明の実施の形態１における他の構成のリードフレームの半導体素子との接合部の構成を示す拡大平面図である。図４の拡大平面図は、図３と同様に図２で示した接合部におけるリードフレーム１ｃの表面の構成を示したものであり、図３の構成とは、金属線が第１の端部と第２の端部との間に、第１の金属部材に金属結合により接合された接合部を備えた構成が異なる。なお、図３と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。 FIG. 4 is an enlarged plan view showing a configuration of a joint portion of a lead frame having another configuration according to the first embodiment of the present invention with a semiconductor element. The enlarged plan view of FIG. 4 shows the configuration of the surface of the lead frame 1c at the joint shown in FIG. 2 as in FIG. 3, and the configuration of FIG. 3 is that the metal wire is the first end portion. The configuration is different in that the first metal member is provided with a joint portion joined by a metal bond between the second end portion and the second end portion. The ones with the same reference numerals as those in FIG. 3 indicate the same or corresponding configurations, and the description thereof will be omitted.

図４に示すように、第１の金属部材２５には、Ｖ字状の３本の金属線２２ｇ、２２ｈ、２２ｉが第１の金属部材２５の接合領域の中心側から外周側に向かって放射状に設けられている。金属線２２ｇは、第１の端部２１ｇと第２の端部２３ｇとの間に接合部２９ｇを有しており、接合部２９ｇは第１の金属部材２５に金属接合により接合されている。同様に、金属線２２ｈは、第１の端部２１ｈと第２の端部２３ｈとの間に接合部２９ｈを有し、金属線２２ｉは、第１の端部２１ｉと第２の端部２３ｉとの間に接合部２９ｉを有しており、接合部２９ｈおよび接合部２９ｉはそれぞれ第１の金属部材２５に金属結合により接合されている。 As shown in FIG. 4, in the first metal member 25, three V-shaped metal wires 22g, 22h, and 22i radiate from the central side to the outer peripheral side of the joint region of the first metal member 25. It is provided in. The metal wire 22 g has a joint portion 29 g between the first end portion 21 g and the second end portion 23 g, and the joint portion 29 g is joined to the first metal member 25 by metal bonding. Similarly, the metal wire 22h has a joint portion 29h between the first end portion 21h and the second end portion 23h, and the metal wire 22i has a first end portion 21i and a second end portion 23i. A joint portion 29i is provided between the joint portion 29i and the joint portion 29h and the joint portion 29i, respectively, which are joined to the first metal member 25 by a metal bond.

より詳しく説明すれば、金属線２２ｇは胴体部の断面積より大きい断面積を有する第１の端部２１ｇと第１の金属部材２５とが金属結合により接合されており、第２の端部２３ｇと第１の金属部材２５とが金属結合により接合されている。そして、第１の端部２１ｇと第２の端部２３ｇとの間に接合部２９ｇが設けられ、接合部２９と第１の金属部材２５とが金属結合により接合されている。金属線２２ｈおよび金属線２２ｉについても同様である。 More specifically, in the metal wire 22g, the first end portion 21g having a cross-sectional area larger than the cross-sectional area of the body portion and the first metal member 25 are joined by a metal bond, and the second end portion 23g. And the first metal member 25 are joined by a metal bond. Then, a joint portion 29 g is provided between the first end portion 21 g and the second end portion 23 g, and the joint portion 29 and the first metal member 25 are joined by a metal bond. The same applies to the metal wire 22h and the metal wire 22i.

なお、図４では、１本の金属線が第１の端部と第２の端部との間に１つの接合部を設けた場合について示したが、第１の端部と第２の端部との間に設ける接合部の数は１に限るものではなく、複数の接合部が設けられ、それぞれの接合部が第１の金属部材２５の表面に金属結合により接合されていてもよい。 Although FIG. 4 shows a case where one metal wire is provided with one joint portion between the first end portion and the second end portion, the first end portion and the second end portion are shown. The number of joints provided between the portions is not limited to one, and a plurality of joints may be provided, and each joint may be joined to the surface of the first metal member 25 by a metal bond.

図５は、本発明の実施の形態１における他の構成のリードフレームと半導体素子との接合部の構成を示す拡大断面図である。図５の拡大断面図は、図２の構成とは、半導体素子の電極が金属線と接触している構成が異なる。なお、図２と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。 FIG. 5 is an enlarged cross-sectional view showing a configuration of a joint portion between a lead frame having another configuration and a semiconductor element according to the first embodiment of the present invention. The enlarged cross-sectional view of FIG. 5 is different from the configuration of FIG. 2 in that the electrode of the semiconductor element is in contact with the metal wire. The ones with the same reference numerals as those in FIG. 2 indicate the same or corresponding configurations, and the description thereof will be omitted.

図５に示すように、第１の金属部材２５に超音波接合された金属線２２ａおよび２２ｄは、胴体部の一部が半導体素子８ａの電極２４に接触して、金属線２２ａおよび２２ｄが導電性接合層９ａを介さずに半導体素子８ａの電極２４に電気的に接続されている。このため、導電性接合層９ａを介さずに金属線２２ａおよび２２ｄの胴体部から電極２４へ熱や電気を流すことができるため、放熱性をさらに向上させ、第１の金属部材２５と半導体素子８ａの電極２４との間の電気抵抗をさらに小さくすることができる。 As shown in FIG. 5, in the metal wires 22a and 22d ultrasonically bonded to the first metal member 25, a part of the body portion contacts the electrode 24 of the semiconductor element 8a, and the metal wires 22a and 22d are conductive. It is electrically connected to the electrode 24 of the semiconductor element 8a without passing through the sex bonding layer 9a. Therefore, heat and electricity can flow from the body portions of the metal wires 22a and 22d to the electrodes 24 without passing through the conductive bonding layer 9a, so that heat dissipation is further improved, and the first metal member 25 and the semiconductor element are further improved. The electrical resistance between the 8a and the electrode 24 can be further reduced.

次に、本発明の半導体装置の製造方法について説明する。 Next, a method for manufacturing the semiconductor device of the present invention will be described.

図６は、本発明の実施の形態１における半導体装置の金属線を接合する製造方法を示す図である。図６は、アルミニウムや銅などの表面に酸化膜を有する金属材料で形成された第１の金属部材２５の表面に、図３および図４で示した金属線をワイヤボンディング装置による超音波接合を用いて接合する方法を示している。 FIG. 6 is a diagram showing a manufacturing method for joining metal wires of a semiconductor device according to the first embodiment of the present invention. FIG. 6 shows that the metal wires shown in FIGS. 3 and 4 are ultrasonically bonded to the surface of the first metal member 25 formed of a metal material having an oxide film on the surface such as aluminum or copper by a wire bonding device. It shows the method of joining using.

図６（ａ）に示すように、リードフレーム１ｃの一部である第１の金属部材２５の表面には酸化膜２０が存在する。ワイヤボンディング装置は、キャピラリ３０を有しており、キャピラリ３０に設けられた貫通穴に金線３１が挿入されている。なお、前述のように金線３１の代わりに他の貴金属線や貴金属をコーティングした銅線などの卑金属線を用いてもよい。金線３１は、キャピラリ３０の貫通穴を通って、キャピラリ３０の先端からキャピラリ３０の外部に繰り出されるようになっている。キャピラリ３０の先端からは所定長の金線３１が排出されており、テール３２を構成している。 As shown in FIG. 6A, the oxide film 20 is present on the surface of the first metal member 25 which is a part of the lead frame 1c. The wire bonding apparatus has a capillary 30, and a gold wire 31 is inserted into a through hole provided in the capillary 30. As described above, instead of the gold wire 31, a base metal wire such as another noble metal wire or a copper wire coated with a noble metal may be used. The gold wire 31 is extended from the tip of the capillary 30 to the outside of the capillary 30 through the through hole of the capillary 30. A gold wire 31 having a predetermined length is discharged from the tip of the capillary 30 to form the tail 32.

次に、図６（ｂ）に示すように、ワイヤボンディング装置は、キャピラリ３０の先端から排出されたテール３２を放電により溶融させて、キャピラリ３０の先端にボール３３を形成する。ボール３３の直径は、ボール３３を形成する前のテール３２の長さによって調整可能であるが、例えば、金線３１の直径の１．２倍〜１．５倍程度であってよい。 Next, as shown in FIG. 6B, the wire bonding apparatus melts the tail 32 discharged from the tip of the capillary 30 by electric discharge to form a ball 33 at the tip of the capillary 30. The diameter of the ball 33 can be adjusted by the length of the tail 32 before forming the ball 33, but may be, for example, about 1.2 to 1.5 times the diameter of the gold wire 31.

次に、図６（ｃ）に示すように、先端にボール３３を形成したキャピラリ３０の先端を第１の金属部材２５の表面に押し当て、ワイヤボンディング装置がキャピラリ３０の先端に超音波を印加する。この結果、第１の金属部材２５の表面のボール３３が押し当てられた部分の酸化膜２０が除去される。また、ボール３３は印加された超音波のエネルギーによって溶融して変形し、第１の金属部材２５の表面と金属結合により接合され、第１の端部２１ｊが形成される。第１の端部２１ｊはボール３３を押し潰して形成されるため、第１の端部２１ｊの断面積は金線３１の断面積よりも大きくなる。 Next, as shown in FIG. 6C, the tip of the capillary 30 having the ball 33 formed at the tip is pressed against the surface of the first metal member 25, and the wire bonding device applies ultrasonic waves to the tip of the capillary 30. To do. As a result, the oxide film 20 on the surface of the first metal member 25 against which the ball 33 is pressed is removed. Further, the ball 33 is melted and deformed by the energy of the applied ultrasonic waves, and is joined to the surface of the first metal member 25 by a metal bond to form the first end portion 21j. Since the first end portion 21j is formed by crushing the ball 33, the cross-sectional area of the first end portion 21j is larger than the cross-sectional area of the gold wire 31.

次に、図６（ｄ）に示すように、ワイヤボンディング装置は、キャピラリ３０の先端を引き上げて第１の金属部材２５の表面から離し、第２の端部２３ｊを第１の金属部材２５に接合する場所にキャピラリ３０の先端を移動する。これにより第１の金属部材２５の表面に沿って延伸した胴体部が形成される。そして、再びキャピラリ３０の先端を第１の金属部材２５の表面に押し当てて超音波を印加する。この結果、キャピラリ３０の先端が押し当てられた部分の酸化膜２０が除去され、金線３１は変形して第１の金属部材２５の表面に金属結合により接合される。 Next, as shown in FIG. 6D, the wire bonding apparatus pulls up the tip of the capillary 30 to separate it from the surface of the first metal member 25, and separates the second end portion 23 j from the surface of the first metal member 25. Move the tip of the capillary 30 to the place where it joins. As a result, a body portion extending along the surface of the first metal member 25 is formed. Then, the tip of the capillary 30 is pressed against the surface of the first metal member 25 again to apply ultrasonic waves. As a result, the oxide film 20 at the portion where the tip of the capillary 30 is pressed is removed, and the gold wire 31 is deformed and bonded to the surface of the first metal member 25 by a metal bond.

図３に示した金属線が第１の端部と第２の端部との間に接合部を有しない場合は、図６（ｄ）の工程の次に、図６（ｅ）に示す工程が行われる。一方、図４に示した金属線が第１の端部と第２の端部との間に接合部を有する場合は、図６（ｄ）の工程の次に、図６（ｆ）に示す工程が行われる。 When the metal wire shown in FIG. 3 does not have a joint between the first end and the second end, the step shown in FIG. 6 (e) is followed by the step shown in FIG. 6 (d). Is done. On the other hand, when the metal wire shown in FIG. 4 has a joint portion between the first end portion and the second end portion, it is shown in FIG. 6 (f) after the step of FIG. 6 (d). The process is carried out.

図６（ｅ）に示す工程では、ワイヤボンディング装置が金線３１を第２の端部２３ｊから切り離す。この結果、金属線２２ｊは、第１の端部２１ｊが第１の金属部材２５の表面に金属結合により接合され、第２の端部２３ｊが第１の金属部材２５の表面に金属結合により接合された構成となる。そして、キャピラリ３０の先端にはテール３２が設けられ、再び図６（ａ）の工程に戻り、他の金属線を第１の金属部材２５の表面に接合して、図３に示すように複数の金属線が第１の金属部材２５の表面に設けられる。 In the step shown in FIG. 6E, the wire bonding apparatus separates the gold wire 31 from the second end 23j. As a result, in the metal wire 22j, the first end portion 21j is bonded to the surface of the first metal member 25 by a metal bond, and the second end portion 23j is bonded to the surface of the first metal member 25 by a metal bond. It becomes the composition that was done. Then, a tail 32 is provided at the tip of the capillary 30, and the process returns to the step of FIG. 6A again, another metal wire is joined to the surface of the first metal member 25, and a plurality of metal wires are joined as shown in FIG. Metal wire is provided on the surface of the first metal member 25.

図６（ｆ）に示す工程では、ワイヤボンディング装置が接合部２９ｊを第１の金属部材２５の表面に接合した後に、金線３１を切断せずに、キャピラリ３０の先端を引き上げて第１の金属部材２５の表面から離し、横方向に移動させることによってキャピラリ３０の貫通穴を通って繰り出される金線３１が接合部と第２の端部との間の金属線２２ｊとなる。そして、第２の端部を第１の金属部材２５に接合する場所に、キャピラリ３０の先端を移動して、キャピラリ３０に超音波を印加して金属線２２ｊの第２の端部を第１の金属部材２５の表面に金属結合により接合する。このような工程により、図４に示すように第１の端部と第２の端部との間に第１の金属部材２５に金属結合された接合部を有する金属線が第１の金属部材２５の表面に設けられる。 In the step shown in FIG. 6 (f), after the wire bonding apparatus joins the bonding portion 29j to the surface of the first metal member 25, the tip of the capillary 30 is pulled up without cutting the gold wire 31 to obtain the first metal member 25. By moving the metal member 25 away from the surface and moving it laterally, the gold wire 31 drawn out through the through hole of the capillary 30 becomes the metal wire 22j between the joint portion and the second end portion. Then, the tip of the capillary 30 is moved to a place where the second end is joined to the first metal member 25, ultrasonic waves are applied to the capillary 30, and the second end of the metal wire 22j is first. It is joined to the surface of the metal member 25 of the above by a metal bond. By such a step, as shown in FIG. 4, a metal wire having a joint portion metal-bonded to the first metal member 25 between the first end portion and the second end portion is the first metal member. It is provided on the surface of 25.

以上のような工程により、図３あるいは図４に示すようにリードフレーム１ｃの一部に設けられた第１の金属部材２５の表面に複数の金属線を接合した後、第１の金属部材２５の表面上に導電性接着剤を塗布し、導電性接着剤上に、半導体素子８ａの第２の金属部材である電極２４と導電性接着剤とが接するように設置する。そして、加熱処理により導電性接着剤を硬化させて、第１の金属部材２５と半導体素子８ａとが導電性接着剤により接合されて、第１の金属部材２５の表面と半導体素子８ａの電極２４である第２の金属部材との間に導電性接合層９ａが形成される。なお、半導体素子８ａを配置する際に、半導体素子８ａに加圧して、図５に示した半導体装置のように、半導体素子８ａの電極２４と金属線２２ａ、２２ｄの胴体部とを接触させてもよい。この場合、金属線２２ａ、２２ｄがスペーサとして機能するため、導電性接合層９ａの厚みを一定にすることができる。 By the above steps, as shown in FIG. 3 or 4, after joining a plurality of metal wires to the surface of the first metal member 25 provided in a part of the lead frame 1c, the first metal member 25 A conductive adhesive is applied on the surface of the semiconductor element 8a, and the electrode 24, which is a second metal member of the semiconductor element 8a, is installed on the conductive adhesive so as to be in contact with the conductive adhesive. Then, the conductive adhesive is cured by heat treatment, and the first metal member 25 and the semiconductor element 8a are joined by the conductive adhesive, and the surface of the first metal member 25 and the electrode 24 of the semiconductor element 8a are joined. A conductive bonding layer 9a is formed between the metal member and the second metal member. When arranging the semiconductor element 8a, the semiconductor element 8a is pressurized so that the electrode 24 of the semiconductor element 8a and the body portions of the metal wires 22a and 22d are brought into contact with each other as in the semiconductor device shown in FIG. May be good. In this case, since the metal wires 22a and 22d function as spacers, the thickness of the conductive bonding layer 9a can be made constant.

上述のようにリードフレーム１ｃ上に半導体素子８ａ、８ｂを導電性接合層９ａ、９ｂで接合する。また、リードフレーム１ａ上にＩＧＢＴ２、ＦＷＤ３をはんだ材料４ａ、４ｂで接合し、ＩＧＢＴ２およびＦＷＤ３とリードフレーム１ｂとを金属ワイヤ５ａ、５ｂで電気的に接続し、半導体素子８ａ、８ｂとＩＧＢＴ２とを金属ワイヤ１２ａ、１２ｂで電気的に接続する。そして、リードフレーム１ａのＩＧＢＴ２およびＦＷＤ３を接合した側と反対側に絶縁層６を設け、さらに金属板７を設けて、これらを封止樹脂１０により一体的に封止することで半導体装置１００は製造される。 As described above, the semiconductor elements 8a and 8b are bonded to the lead frame 1c by the conductive bonding layers 9a and 9b. Further, the IGBTs 2 and FWD3 are joined on the lead frame 1a with solder materials 4a and 4b, the IGBTs 2 and FWD3 and the lead frame 1b are electrically connected by metal wires 5a and 5b, and the semiconductor elements 8a and 8b and the IGBT 2 are connected to each other. It is electrically connected by metal wires 12a and 12b. Then, an insulating layer 6 is provided on the side of the lead frame 1a opposite to the side where the IGBT 2 and FWD 3 are joined, and a metal plate 7 is further provided, and these are integrally sealed by the sealing resin 10, whereby the semiconductor device 100 is formed. Manufactured.

なお、本実施の形態１では、制御用の半導体素子８ａおよび８ｂとリードフレーム１ｃとの接合に導電性接着剤を用いた場合について説明したが、ＩＧＢＴ２およびＦＷＤ３とリードフレーム１ａとの接合に導電性接着剤を用いてもよい。ＩＧＢＴ２およびＦＷＤ３とリードフレーム１ａとの接合に導電性接着剤を用いる場合であっても、リードフレーム１ａの表面がアルミや銅などの酸化されやすい金属材料で形成されている場合には、上述のようにリードフレーム１ａの表面の第１の金属部材の表面に、酸化されにくい金属材料を表面に有する金属線を接合して、この金属線を埋設した状態で導電性接着剤を設けるとよい。これにより、リードフレーム１ａの表面上に銀めっき処理を施すなどのメタライズ処理を省略することができ、製造工程の簡略化により製造コストを低減することができる。 In the first embodiment, the case where the conductive adhesive is used for joining the control semiconductor elements 8a and 8b and the lead frame 1c has been described, but the conductive adhesive is used for joining the IGBT 2 and FWD 3 and the lead frame 1a. A sex adhesive may be used. Even when a conductive adhesive is used to join the IGBT 2 and FWD 3 to the lead frame 1a, if the surface of the lead frame 1a is made of a metal material that is easily oxidized, such as aluminum or copper, the above-mentioned As described above, it is preferable to join a metal wire having a metal material that is hard to be oxidized to the surface of the first metal member on the surface of the lead frame 1a, and to provide a conductive adhesive in a state where the metal wire is embedded. As a result, metallizing processing such as silver plating on the surface of the lead frame 1a can be omitted, and the manufacturing cost can be reduced by simplifying the manufacturing process.

ＩＧＢＴ２あるいはＦＷＤ３を導電性接着剤でリードフレームに接合する場合には、制御用の半導体素子８ａ、８ｂを導電性接着剤で接合する場合に比べて、接合面に流れる電流密度が大きくなる。第１の金属部材の表面に接合する金属線として、例えば、直径３７．５μｍの金線を用いた場合には、図２に示した構成の金属線１本当たり１８Ａの電流を流すことができる。従って、例えば、ＩＧＢＴ２あるいはＦＷＤ３に流れる最大電流が１００Ａの場合には、図３に示すように６本の金属線を第１の金属部材の表面に接合すればよい。 When the IGBT 2 or FWD3 is bonded to the lead frame with a conductive adhesive, the current density flowing through the bonding surface is higher than when the control semiconductor elements 8a and 8b are bonded with the conductive adhesive. When, for example, a gold wire having a diameter of 37.5 μm is used as the metal wire to be joined to the surface of the first metal member, a current of 18 A can be passed through each metal wire having the configuration shown in FIG. .. Therefore, for example, when the maximum current flowing through the IGBT 2 or FWD 3 is 100 A, six metal wires may be joined to the surface of the first metal member as shown in FIG.

以上のように、本発明の実施の形態１の半導体装置は、表面が酸化されやすい金属材料で形成されたリードフレームの表面に、リードフレームの表面の金属材料よりも酸化されにくい金属材料を表面に有する金属線を金属結合により接合し、この金属線を埋設した状態で導電性接合層を設け、すなわち、金属線の胴体部を導電性接合層内に設け、導電性接合層上に半導体素子を設けて、リードフレームと半導体素子とを電気的に接続したので、リードフレームと半導体素子との間の電気抵抗を小さくすることができる。 As described above, in the semiconductor device of the first embodiment of the present invention, a metal material that is less likely to be oxidized than the metal material on the surface of the lead frame is surfaced on the surface of the lead frame whose surface is made of a metal material that is easily oxidized. The metal wire held in the above is joined by a metal bond, and a conductive bonding layer is provided in a state where the metal wire is embedded, that is, a body portion of the metal wire is provided in the conductive bonding layer, and a semiconductor element is provided on the conductive bonding layer. Is provided to electrically connect the lead frame and the semiconductor element, so that the electrical resistance between the lead frame and the semiconductor element can be reduced.

また、リードフレームの表面に接合する金属線を放射状に複数設けたので、半導体素子とリードフレームとの間の電気伝導および熱伝導の均一化を図ることができる。また、リードフレームの表面に放射状に設けた複数の金属線が、導電性接着剤を塗布する際のガイドの役割をするので、導電性接着剤を塗布するための製造コストを低減することができる。 Further, since a plurality of metal wires to be joined to the surface of the lead frame are provided radially, it is possible to make the electric conduction and the heat conduction between the semiconductor element and the lead frame uniform. Further, since the plurality of metal wires provided radially on the surface of the lead frame serve as a guide when applying the conductive adhesive, the manufacturing cost for applying the conductive adhesive can be reduced. ..

実施の形態２．
図７は、本発明の実施の形態２における半導体装置を示す断面図である。図７において、図１と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。本発明の実施の形態１とは、半導体素子がリードフレーム上ではなく、絶縁基板の回路パターン上に接合された構成が相違している。Embodiment 2.
FIG. 7 is a cross-sectional view showing the semiconductor device according to the second embodiment of the present invention. In FIG. 7, those having the same reference numerals as those in FIG. 1 indicate the same or corresponding configurations, and the description thereof will be omitted. The configuration in which the semiconductor elements are bonded not on the lead frame but on the circuit pattern of the insulating substrate is different from the first embodiment of the present invention.

図７において、絶縁基板１３は、金属ベース板１３ｃ上に樹脂あるいはセラミックスなどの絶縁物からなる絶縁層１３ｂが設けられ、絶縁層１３ｂ上に銅またはアルミニウムで形成された配線部である回路パターン１３ａが設けられて構成されている。ＩＧＢＴ２、ＦＷＤ３、および制御用の半導体素子８ａ、８ｂは、絶縁基板１３の回路パターン１３ａに接合されている。ＩＧＢＴ２およびＦＷＤ３ははんだ材料４ａ、４ｂで回路パターン１３ａに接合されているが、導電性接合層で回路パターン１３ａに接合されてもよい。半導体素子８ａ、８ｂは導電性接合層９ａ、９ｂで回路パターン１３ａに接合されているが、はんだ材料で回路パターン１３ａに接合されてもよい。 In FIG. 7, the insulating substrate 13 has a circuit pattern 13a which is a wiring portion in which an insulating layer 13b made of an insulating material such as resin or ceramics is provided on a metal base plate 13c and is formed of copper or aluminum on the insulating layer 13b. Is provided and configured. The IGBTs 2 and FWD 3 and the control semiconductor elements 8a and 8b are joined to the circuit pattern 13a of the insulating substrate 13. Although the IGBTs 2 and FWD3 are bonded to the circuit pattern 13a with the solder materials 4a and 4b, they may be bonded to the circuit pattern 13a with the conductive bonding layer. Although the semiconductor elements 8a and 8b are bonded to the circuit pattern 13a by the conductive bonding layers 9a and 9b, they may be bonded to the circuit pattern 13a with a solder material.

ＩＧＢＴ２、ＦＷＤ３、半導体素子８ａ、８ｂなどの半導体素子を導電性接着剤で回路パターン１３ａに接合する場合には、実施の形態１で示したように、回路パターン１３ａの表面の金属材料よりも酸化されにくい金属材料を胴体部の表面に有する金属線が、回路パターン１３ａの接合面となる第１の金属部材の表面に金属結合により接合され、半導体素子と回路パターン１３ａとが小さな電気抵抗で電気的に接続される。 When semiconductor elements such as IGBT2, FWD3, and semiconductor elements 8a and 8b are bonded to the circuit pattern 13a with a conductive adhesive, as shown in the first embodiment, they are more oxidized than the metal material on the surface of the circuit pattern 13a. A metal wire having a metal material that is difficult to be easily formed on the surface of the body is joined to the surface of the first metal member that is the joint surface of the circuit pattern 13a by metal bonding, and the semiconductor element and the circuit pattern 13a are electrically connected with a small electric resistance. Is connected.

そして、半導体素子が接合された絶縁基板１３の周囲にケース１４が設けられ、ケース１４に設けられたケース端子１６ｄにＩＧＢＴ２およびＦＷＤ３がアルミワイヤなどの金属ワイヤ５ａ、５ｂにより電気的に接続され、ケース１４に設けられたケース端子１６ｅと回路パターン１３ａとがアルミワイヤなどの金属線１２ｃにより電気的に接続される。制御用の半導体素子８ａ、８ｂはアルミワイヤなどの金属ワイヤ１２ａ、１２ｂによりＩＧＢＴ２に電気的に接続される。そして、ケース１４の内側を封止樹脂１０で封止して半導体装置２００は構成される。ケース端子１６ｄおよび１６ｅはアルミや銅などの導電率が大きい金属で形成された配線部材であり、ケース端子１６ｄおよび１６ｅのうち半導体装置２００の外部に露出した部分は外部の電気回路と接続するための外部端子１１ｄおよび１１ｅとなっている。 Then, a case 14 is provided around the insulating substrate 13 to which the semiconductor elements are bonded, and the IGBTs 2 and FWD 3 are electrically connected to the case terminals 16d provided on the case 14 by metal wires 5a and 5b such as aluminum wires. The case terminal 16e provided on the case 14 and the circuit pattern 13a are electrically connected by a metal wire 12c such as an aluminum wire. The control semiconductor elements 8a and 8b are electrically connected to the IGBT 2 by metal wires 12a and 12b such as aluminum wires. Then, the inside of the case 14 is sealed with the sealing resin 10, and the semiconductor device 200 is configured. The case terminals 16d and 16e are wiring members made of a metal having a high conductivity such as aluminum or copper, and the portion of the case terminals 16d and 16e exposed to the outside of the semiconductor device 200 is connected to an external electric circuit. External terminals 11d and 11e.

このように、導電性接着剤からなる導電性接合層で接合される半導体素子は、実施の形態１で述べたようにリードフレームに限らず、本実施の形態２で述べたように絶縁基板の回路パターンに接合されてもよい。このような場合であっても、銅やアルミニウムなどの卑金属材料で形成された回路パターンの表面に、銀めっきなどのメタライズ処理を施さなくても、半導体素子と配線部材である回路パターンとの間の電気抵抗を小さくして、半導体素子と回路パターンとを電気的に接続することができる。 As described above, the semiconductor element bonded by the conductive bonding layer made of the conductive adhesive is not limited to the lead frame as described in the first embodiment, but the insulating substrate as described in the second embodiment. It may be joined to a circuit pattern. Even in such a case, the surface of the circuit pattern formed of a base metal material such as copper or aluminum can be separated between the semiconductor element and the circuit pattern which is a wiring member without performing metallization treatment such as silver plating. The electrical resistance of the semiconductor element can be reduced to electrically connect the semiconductor element and the circuit pattern.

実施の形態３．
図８は、本発明の実施の形態３における半導体装置を示す断面図である。図８において、図１および図７と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。本発明の実施の形態１および２とは、絶縁基板上の回路パターンと配線部材であるリード端子とを導電性接合層で接合した構成が相違している。Embodiment 3.
FIG. 8 is a cross-sectional view showing the semiconductor device according to the third embodiment of the present invention. In FIG. 8, those having the same reference numerals as those in FIGS. 1 and 7 indicate the same or corresponding configurations, and the description thereof will be omitted. The configuration in which the circuit pattern on the insulating substrate and the lead terminal which is a wiring member are joined by a conductive joining layer is different from the first and second embodiments of the present invention.

図８に示す半導体装置３００は、銅やアルミニウムで形成された回路パターン１３ａとＩＧＢＴ２、ＦＷＤ３とがはんだ材料４ａ、４ｂにより接合され、回路パターン１３ａと制御用の半導体素子８ａ、８ｂとが導電性接合層９ａ、９ｂにより接合されている。各半導体素子と回路パターン１３ａとの接合部は実施の形態１と同様に構成されている。 In the semiconductor device 300 shown in FIG. 8, the circuit pattern 13a made of copper or aluminum and the IGBTs 2 and FWD 3 are joined by the solder materials 4a and 4b, and the circuit pattern 13a and the semiconductor elements 8a and 8b for control are conductive. It is joined by the joining layers 9a and 9b. The junction between each semiconductor element and the circuit pattern 13a is configured in the same manner as in the first embodiment.

各半導体素子と半導体装置３００の外部の電気回路とを接続するための外部端子１１ｆおよび１１ｇが、アルミニウムや銅などの卑金属材料で形成されたリード端子１７ｆおよび１７ｇの一端に設けられている。配線部材であるリード端子１７ｆおよび１７ｇは、外部端子１１ｆおよび１１ｇが設けられた側と反対側が導電性接合層９ｃおよび９ｄにより、配線部材である回路パターン１３ａに接合され、リード端子１７ｆと回路パターン１３ａとが電気的に接続され、リード端子１７ｇと回路パターン１３ａとが電気的に接続されている。リード端子１７ｆと回路パターン１３ａとの接合部、およびリード端子１７ｇと回路パターン１３ａとの接合部は実施の形態１で説明したような構成をしているので、それぞれ小さな電気抵抗で電気的に接続されている。 External terminals 11f and 11g for connecting each semiconductor element and an external electric circuit of the semiconductor device 300 are provided at one end of lead terminals 17f and 17g made of a base metal material such as aluminum or copper. The lead terminals 17f and 17g, which are wiring members, are joined to the circuit pattern 13a, which is a wiring member, on the side opposite to the side where the external terminals 11f and 11g are provided by the conductive bonding layers 9c and 9d, and the lead terminals 17f and the circuit pattern. The 13a is electrically connected, and the lead terminal 17g and the circuit pattern 13a are electrically connected. Since the joint portion between the lead terminal 17f and the circuit pattern 13a and the joint portion between the lead terminal 17g and the circuit pattern 13a have the configuration as described in the first embodiment, they are electrically connected with a small electric resistance. Has been done.

図９は、本発明の実施の形態３における回路パターンとリード端子との接合部の構成を示す拡大断面図である。また、図１０は、本発明の実施の形態３における回路パターンとリード端子との接合部の他の構成を示す拡大断面図である。図９は、回路パターンの表面に金属線が接合された構成の接合部であり、図１０は、リード端子の表面に金属線が接合された構成の接合部である。 FIG. 9 is an enlarged cross-sectional view showing the configuration of the joint portion between the circuit pattern and the lead terminal according to the third embodiment of the present invention. Further, FIG. 10 is an enlarged cross-sectional view showing another configuration of the joint portion between the circuit pattern and the lead terminal in the third embodiment of the present invention. FIG. 9 is a joint having a metal wire bonded to the surface of the circuit pattern, and FIG. 10 is a joint having a metal wire bonded to the surface of the lead terminal.

図９は、回路パターン１３ａが銅やアルミニウムなどの卑金属材料で形成され、回路パターン１３ａの表面に銀めっきなどのメタライズ処理が施されていない場合、あるいは回路パターン１３ａの表面にニッケルめっきや錫めっきが施されている場合である。リード端子１７ｆはアルミニウムや銅で形成されており、表面に銀めっきなどのメタライズ処理が施されている。 In FIG. 9, when the circuit pattern 13a is formed of a base metal material such as copper or aluminum and the surface of the circuit pattern 13a is not metallized such as silver plating, or the surface of the circuit pattern 13a is nickel-plated or tin-plated. Is given. The lead terminal 17f is made of aluminum or copper, and its surface is metallized by silver plating or the like.

図９では、回路パターン１３ａが第１の金属部材２５となっており、リード端子１７ｆが第２の金属部材となっている。実施の形態１で説明したように第１の金属部材２５の表面には複数の金属線２２ａ、２２ｄが金属結合により接合されている。そして、第１の金属部材２５である回路パターン１３ａと第２の金属部材であるリード端子１７ｆとの間に導電性接合層９ｃが設けられている。この結果、配線部材である回路パターン１３ａと配線部材であるリード端子１７ｆとが小さな電気抵抗で電気的に接続される。 In FIG. 9, the circuit pattern 13a is the first metal member 25, and the lead terminal 17f is the second metal member. As described in the first embodiment, a plurality of metal wires 22a and 22d are joined to the surface of the first metal member 25 by metal bonding. A conductive bonding layer 9c is provided between the circuit pattern 13a, which is the first metal member 25, and the lead terminal 17f, which is the second metal member. As a result, the circuit pattern 13a, which is a wiring member, and the lead terminal 17f, which is a wiring member, are electrically connected with a small electric resistance.

一方、図１０は、回路パターン１３ａが銅やアルミニウムなどの卑金属材料で形成され、回路パターン１３ａの表面に銀めっきなどのメタライズ処理が施されている。リード端子１７ｆはアルミニウムや銅で形成されており、表面にはメタライズ処理が施されていない場合、あるいはニッケルめっきや錫めっきが施されている場合である。 On the other hand, in FIG. 10, the circuit pattern 13a is formed of a base metal material such as copper or aluminum, and the surface of the circuit pattern 13a is metallized by silver plating or the like. The lead terminal 17f is made of aluminum or copper, and the surface thereof is not metallized, or is nickel-plated or tin-plated.

図１０では、リード端子１７ｆが第１の金属部材２５となっており、回路パターン１３ａが第２の金属部材となっている。実施の形態１で説明したように第１の金属部材２５の表面には複数の金属線２２ａ、２２ｄが金属結合により接合されている。そして、第１の金属部材２５であるリード端子１７ｆと第２の金属部材である回路パターン１３ａとの間に導電性接合層９ｃが設けられている。この結果、配線部材である回路パターン１３ａと配線部材であるリード端子１７ｆとが小さな電気抵抗で電気的に接続される。 In FIG. 10, the lead terminal 17f is the first metal member 25, and the circuit pattern 13a is the second metal member. As described in the first embodiment, a plurality of metal wires 22a and 22d are joined to the surface of the first metal member 25 by metal bonding. A conductive bonding layer 9c is provided between the lead terminal 17f, which is the first metal member 25, and the circuit pattern 13a, which is the second metal member. As a result, the circuit pattern 13a, which is a wiring member, and the lead terminal 17f, which is a wiring member, are electrically connected with a small electric resistance.

なお、図９および図１０では、回路パターン１３ａあるいはリード端子１７ｆのいずれか一方に銀めっきなどのメタライズ処理が施されている場合について説明したが、回路パターン１３ａおよびリード端子１７ｆの両方に銀めっきなどのメタライズ処理が施されておらず、両方の表面が酸化されやすい卑金属材料で形成されている場合には、回路パターン１３ａおよびリード端子１７ｆの両方の表面に貴金属材料の表面を有する金属線を接合して、回路パターン１３ａとリード端子１７ｆとを導電性接合層９ｃで接合すればよい。この場合、リード端子１７ｆ側に接合された金属線と、回路パターン１３ａ側に接合された金属線とが、重ならないようにそれぞれの第１の金属部材の表面に接合することで、リード端子１７ｆと回路パターン１３ａとの接合部の厚さを厚くせずに良好な電気伝導および熱伝導を得ることができる。 In addition, in FIGS. 9 and 10, the case where either one of the circuit pattern 13a and the lead terminal 17f is subjected to metallization processing such as silver plating has been described, but both the circuit pattern 13a and the lead terminal 17f are silver-plated. When both surfaces are made of a base metal material that is easily oxidized, a metal wire having a surface of a noble metal material is provided on both surfaces of the circuit pattern 13a and the lead terminal 17f. After joining, the circuit pattern 13a and the lead terminal 17f may be joined by the conductive joining layer 9c. In this case, the metal wire joined to the lead terminal 17f side and the metal wire joined to the circuit pattern 13a side are joined to the surface of each first metal member so as not to overlap, so that the lead terminal 17f is joined. Good electrical conduction and heat conduction can be obtained without increasing the thickness of the joint between the wire and the circuit pattern 13a.

本実施の形態３で示すように、絶縁基板１３の回路パターン１３ａに外部端子が設けられたリード端子１７ｆを接合して、回路パターン１３ａとリード端子１７ｆとを電気的に接続することで、外部端子と回路パターンとをアルミワイヤで電気的に接続するよりも多くの電流を流すことができる。絶縁基板１３の回路パターン１３ａにＩＧＢＴ２およびＦＷＤ３をはんだ接合により接合する場合には、回路パターン１３ａをアルミニウムに比べて酸化されにくい銅で形成している場合であっても、はんだ接合時の加熱処理によって回路パターン１３ａの表面がより多く酸化されている。このような場合、一般的には、回路パターン１３ａの表面の酸化膜を除去するために還元処理を施さなければ、回路パターン１３ａとリード端子１７ｆとを導電性接着剤で接合した場合に良好な電気伝導が得られない。しかし、本実施の形態３に示したように回路パターン１３ａの表面に金線などの酸化されにくい金属線を接合して、導電性接着剤により回路パターン１３ａとリード端子１７ｆとを接合することで良好な電気伝導を得ることができる。この結果、回路パターン１３ａにＩＧＢＴ２やＦＷＤ３をはんだ接合した場合であっても、還元処理が不要となるので半導体装置３００の生産性を向上することができる。 As shown in the third embodiment, the circuit pattern 13a of the insulating substrate 13 is joined to the lead terminal 17f provided with the external terminal, and the circuit pattern 13a and the lead terminal 17f are electrically connected to the outside. More current can flow than when the terminals and circuit patterns are electrically connected with aluminum wires. When the IGBT 2 and FWD3 are joined to the circuit pattern 13a of the insulating substrate 13 by solder joining, even if the circuit pattern 13a is made of copper, which is less likely to be oxidized than aluminum, the heat treatment at the time of solder joining is performed. The surface of the circuit pattern 13a is more oxidized by. In such a case, it is generally good when the circuit pattern 13a and the lead terminal 17f are joined with a conductive adhesive unless a reduction treatment is performed to remove the oxide film on the surface of the circuit pattern 13a. No electrical conduction can be obtained. However, as shown in the third embodiment, by joining a metal wire such as a gold wire which is hard to be oxidized to the surface of the circuit pattern 13a and joining the circuit pattern 13a and the lead terminal 17f with a conductive adhesive. Good electrical conduction can be obtained. As a result, even when the IGBT 2 or FWD 3 is solder-bonded to the circuit pattern 13a, the reduction process becomes unnecessary, so that the productivity of the semiconductor device 300 can be improved.

また、本発明により外部端子が設けられたリード端子として、軽量、安価なアルミニウムで形成されたリード端子を用いることができるので、半導体装置の軽量化、低コスト化を行うことができる。さらに、外部端子が設けられたリード端子と回路パターンとの双方に本発明を適用することにより、生産性を向上させて半導体装置のさらなる低コスト化が可能となる。 Further, according to the present invention, as a lead terminal provided with an external terminal, a lightweight and inexpensive lead terminal made of aluminum can be used, so that the weight and cost of the semiconductor device can be reduced. Further, by applying the present invention to both the lead terminal provided with the external terminal and the circuit pattern, the productivity can be improved and the cost of the semiconductor device can be further reduced.

なお、本実施の形態３では、外部端子が設けられたリード端子と回路パターンとを接合する場合に、第１の金属部材に酸化されにくい金属線を接合して良好な電気伝導を得る場合について説明したが、これに限るものではなく、例えば、半導体装置内部の異なる回路パターン間を配線部材である帯状の金属板で電気的に接続する場合に、回路パターンあるいは帯状の金属板の一方または両方の接合面に、接合面の金属材料よりも酸化されにくい金属線を接合して、回路パターンと帯状の金属板とを導電性接着剤からなる導電性接合層で接合してもよい。 In the third embodiment, when the lead terminal provided with the external terminal and the circuit pattern are joined, a metal wire that is hard to be oxidized is joined to the first metal member to obtain good electrical conduction. Although described above, the present invention is not limited to this, and for example, when electrically connecting different circuit patterns inside a semiconductor device with a strip-shaped metal plate which is a wiring member, one or both of the circuit pattern and the strip-shaped metal plate are used. A metal wire that is less likely to be oxidized than the metal material of the joint surface may be joined to the joint surface of the above, and the circuit pattern and the strip-shaped metal plate may be joined by a conductive joint layer made of a conductive adhesive.

実施の形態４．
図１１は、本発明の実施の形態４における半導体装置を示す断面図である。図１１において、図１と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。本発明の実施の形態１とは、ＩＧＢＴ２およびＦＷＤ３をアルミワイヤの代わりに外部端子が設けられたリードフレームに導電性接合層で接合した構成が相違している。Embodiment 4.
FIG. 11 is a cross-sectional view showing the semiconductor device according to the fourth embodiment of the present invention. In FIG. 11, those having the same reference numerals as those in FIG. 1 indicate the same or corresponding configurations, and the description thereof will be omitted. The configuration is different from that of the first embodiment of the present invention in that the IGBT 2 and the FWD 3 are bonded to a lead frame provided with an external terminal instead of an aluminum wire by a conductive bonding layer.

図１１に示すように、外部端子１１ａが設けられたリードフレーム１ａにはんだ材料４ａおよび４ｂで接合されたＩＧＢＴ２およびＦＷＤ３が、外部端子１１ｈが設けられたリードフレーム１ｈに導電性接合層９ｅおよび９ｆで接合されている。また、ＩＧＢＴ２は金線からなる金属ワイヤ１５ａ、１５ｂによって制御用の半導体素子８ａ、８ｂと電気的に接続されている。 As shown in FIG. 11, the IGBTs 2 and FWD3 bonded to the lead frame 1a provided with the external terminals 11a with the solder materials 4a and 4b are connected to the lead frame 1h provided with the external terminals 11h, and the conductive bonding layers 9e and 9f are attached to the lead frame 1h provided with the external terminals 11h. It is joined with. Further, the IGBT 2 is electrically connected to the control semiconductor elements 8a and 8b by metal wires 15a and 15b made of gold wire.

図１２は、本発明の実施の形態４における半導体装置のＩＧＢＴとリードフレームとの接合部の構成を示す拡大断面図である。図１２は、図１１のＩＧＢＴ２の接合部の構成を拡大して示したものである。 FIG. 12 is an enlarged cross-sectional view showing a configuration of a joint portion between the IGBT and the lead frame of the semiconductor device according to the fourth embodiment of the present invention. FIG. 12 is an enlarged view of the configuration of the joint portion of the IGBT 2 of FIG.

図１２に示すように、電力用の半導体素子であるＩＧＢＴ２は縦方向に電極２６および電極２７を有している。ＦＷＤ３についても同様に縦方向に２つの電極を有している（図示せず）。電極２６は、例えばＩＧＢＴ２のエミッタ電極であり、電極２７は、例えばＩＧＢＴ２のコレクタ電極である。図１２では、ＩＧＢＴ２の電極２６が第１の金属部材２５となっており、リードフレーム１ｈが第２の金属部材となっている。 As shown in FIG. 12, the IGBT 2 which is a semiconductor element for electric power has an electrode 26 and an electrode 27 in the vertical direction. Similarly, the FWD3 has two electrodes in the vertical direction (not shown). The electrode 26 is, for example, an emitter electrode of IGBT2, and the electrode 27 is, for example, a collector electrode of IGBT2. In FIG. 12, the electrode 26 of the IGBT 2 is the first metal member 25, and the lead frame 1h is the second metal member.

ＩＧＢＴ２は、電極２７とリードフレーム１ａとがはんだ材料４ａによりはんだ接合されて、リードフレーム１ａ上に設けられている。なお、ＩＧＢＴ２とリードフレーム１ａとは、実施の形態１で述べたように導電性接着剤で接合してもよく、ＩＧＢＴ２の電極２７あるいはリードフレーム１ａの表面が銅やアルミニウムなどの酸化されやすい金属で形成されている場合には、電極２７あるいはリードフレーム１ａの接合面に金線などの酸化されにくい金属線を接合して、導電性接着剤でＩＧＢＴ２の電極２７とリードフレーム１ａとを接合すればよい。 The IGBT 2 is provided on the lead frame 1a by solder-bonding the electrode 27 and the lead frame 1a with the solder material 4a. The IGBT 2 and the lead frame 1a may be joined with a conductive adhesive as described in the first embodiment, and the surface of the electrode 27 of the IGBT 2 or the lead frame 1a is a metal such as copper or aluminum that is easily oxidized. In the case of being formed of, a metal wire such as a gold wire that is hard to be oxidized is joined to the joint surface of the electrode 27 or the lead frame 1a, and the electrode 27 of the IGBT 2 and the lead frame 1a are joined with a conductive adhesive. Just do it.

ＩＧＢＴ２の電極２６はアルミニウム膜などの酸化されやすい金属膜で形成されている。図１２に示すように、ＩＧＢＴ２の電極２６には、制御用の半導体素子８ａと電気的に接続するための金線である金属ワイヤ１５ａが、ワイヤボンディング装置による超音波接合で接合されている。金属ワイヤ１５ａと電極２６との接合部には、ボールボンディング部２８が形成されている。ＩＧＢＴ２の電極２６のリードフレーム１ｈとの接合領域である第１の金属部材２５の表面には、金線で構成された金属線２２ａと２２ｄとが、金属結合により接合されている。すなわち、金属線２２ａでは、金属線２２ａの胴体部の断面積より断面積が大きい第１の端部２１ａと電極２６とが金属結合により接合され、第２の端部２３ａと電極２６とが金属結合により接合されており、金属線２２ｄでは、金属線２２ｄの胴体部の断面積より断面積が大きい第１の端部２１ｄと電極２６とが金属結合により接合され、第２の端部２３ｄと電極２６とが金属結合により接合されている。 The electrode 26 of the IGBT 2 is formed of an easily oxidizable metal film such as an aluminum film. As shown in FIG. 12, a metal wire 15a, which is a gold wire for electrically connecting to a control semiconductor element 8a, is bonded to the electrode 26 of the IGBT 2 by ultrasonic bonding using a wire bonding device. A ball bonding portion 28 is formed at the bonding portion between the metal wire 15a and the electrode 26. A junction region between the lead frame 1h of IGBT2 electrode 26 on the surface of the first metal member 25, and the metal wire 22a and 22d constituted by gold wire is bonded by a metal bond. That is, in the metal wire 22a, the first end portion 21a having a cross-sectional area larger than the cross-sectional area of the body portion of the metal wire 22a and the electrode 26 are joined by a metal bond, and the second end portion 23a and the electrode 26 are made of metal. In the metal wire 22d, the first end portion 21d having a cross-sectional area larger than the cross-sectional area of the body portion of the metal wire 22d and the electrode 26 are joined by metal bonding to the second end portion 23d. The electrode 26 is joined by a metal bond.

金属線２２ａおよび金属線２２ｄは、ワイヤボンディング装置による超音波接合で制御用の半導体素子８ａとＩＧＢＴ２の電極２６とを金線からなる金属ワイヤ１５ａにより電気的に接続する工程で、同じワイヤボンディング装置により電極２６の第１の金属部材２５に接合してもよい。こうすることで、金属線２２ａおよび金属線２２ｄをＩＧＢＴ２の電極２６の第１の金属部材２５に接合するための新たな工程が不要となるので、生産性を低下させずに本発明の半導体装置を製造することができる。 The metal wire 22a and the metal wire 22d are the same wire bonding apparatus in a step of electrically connecting the semiconductor element 8a for control and the electrode 26 of the IGBT 2 by a metal wire 15a made of a gold wire by ultrasonic bonding by a wire bonding apparatus. May be bonded to the first metal member 25 of the electrode 26. This eliminates the need for a new step for joining the metal wire 22a and the metal wire 22d to the first metal member 25 of the electrode 26 of the IGBT 2, so that the semiconductor device of the present invention does not reduce productivity. Can be manufactured.

ＩＧＢＴ２の電極２６の第１の金属部材２５の表面上には、金属線２２ａおよび金属線２２ｄを埋設した状態で導電性接合層９ｅが設けられており、導電性接合層９ｅ上に第２の金属部材であるリードフレーム１ｈが設けられている。リードフレーム１ｈがアルミニウムなどの酸化されやすい金属で形成されている場合には、リードフレーム１ｈの表面に銀めっきなどのメタライズ処理が施されている。あるいは、実施の形態１で説明したように、リードフレーム１ｈにメタライズ処理を施さずに金などの酸化されにくい金属線を接合してもよい。これにより、半導体素子であるＩＧＢＴ２と配線部材であるリードフレーム１ｈとが導電性接合層９ｅにより電気的に接続され、ＩＧＢＴ２とリードフレーム１ｈとの間の電気抵抗を小さくして良好な電気伝導を得ることができる。 A conductive bonding layer 9e is provided on the surface of the first metal member 25 of the electrode 26 of the IGBT 2 with the metal wire 22a and the metal wire 22d embedded therein, and the second metal wire 9e is provided on the conductive bonding layer 9e. A lead frame 1h, which is a metal member, is provided. When the lead frame 1h is made of an easily oxidizable metal such as aluminum, the surface of the lead frame 1h is subjected to a metallizing treatment such as silver plating. Alternatively, as described in the first embodiment, the lead frame 1h may be joined with a metal wire that is hard to be oxidized, such as gold, without performing the metallization treatment. As a result, the IGBT 2 which is a semiconductor element and the lead frame 1h which is a wiring member are electrically connected by the conductive bonding layer 9e, and the electric resistance between the IGBT 2 and the lead frame 1h is reduced to obtain good electrical conduction. Obtainable.

電力用の半導体素子であるＩＧＢＴ２およびＦＷＤ３と外部端子とを電気的に接続する場合に、アルミワイヤではなく、外部端子が設けられたリードフレームを直接ＩＧＢＴ２やＦＷＤ３に接合することによって、アルミワイヤを用いた場合よりも多くの電流を流すことができる。また、アルミワイヤを接合するための余計な面積が不要になるので、外部端子が設けられたリードフレームの面積を小さくすることができ、半導体装置を小型化することができる。 When electrically connecting the external terminals to the IGBTs 2 and FWD3, which are semiconductor elements for electric power, the aluminum wires are joined by directly joining the lead frame provided with the external terminals to the IGBTs 2 and FWD3 instead of the aluminum wires. More current can flow than when used. Further, since an extra area for joining the aluminum wires is not required, the area of the lead frame provided with the external terminal can be reduced, and the semiconductor device can be miniaturized.

また、ＩＧＢＴ２やＦＷＤ３など、電極がアルミニウム成膜で形成された半導体素子の電極に、銀めっきなどのメタライズ処理を施さずに、半導体素子と配線部材であるリードフレームとを導電性接着剤で接合して良好な電気伝導を得ることができるので、生産性を向上して低コストに半導体装置を製造することができる。 Further, the electrodes of a semiconductor element such as IGBT2 or FWD3 whose electrodes are formed by forming an aluminum film are bonded to the semiconductor element and a lead frame which is a wiring member with a conductive adhesive without performing metallizing treatment such as silver plating. Therefore, good electrical conductivity can be obtained, so that the productivity can be improved and the semiconductor device can be manufactured at low cost.

さらに、ＩＧＢＴ２およびＦＷＤ３の電極上に外部端子が設けられたリードフレームを接合する場合には接合部の信頼性が問題となるが、第１の金属部材２５に接合された金属線がスペーサとして機能するため、ＩＧＢＴ２およびＦＷＤ３とリードフレームとの間の導電性接合層の厚さを十分に確保することができるため、十分な接合信頼性が得られる。また、図３あるいは図４に示したように第１の金属部材に均等に金属線を接合することで、導電性接合層の厚さを接合面内で均等にすることができる。 Further, when joining a lead frame having an external terminal provided on the electrodes of IGBT 2 and FWD 3, the reliability of the joining portion becomes a problem, but the metal wire joined to the first metal member 25 functions as a spacer. Therefore, it is possible to secure a sufficient thickness of the conductive bonding layer between the IGBT 2 and FWD 3 and the lead frame, so that sufficient bonding reliability can be obtained. Further, by joining the metal wire evenly to the first metal member as shown in FIG. 3 or FIG. 4, the thickness of the conductive joining layer can be made uniform in the joining surface.

なお、本実施の形態４では、ＩＧＢＴ２およびＦＷＤ３の電極と外部端子が設けられたリードフレーム１ｈとを導電性接合層９ｅで接合する場合について説明したが、これに限るものではなく、ＩＧＢＴ２およびＦＷＤ３の電極と半導体装置の内部の配線部材である板状の金属板とを導電性接合層で接合する場合であっても同様の構成とすることができる。 In the fourth embodiment, the case where the electrodes of the IGBT 2 and FWD 3 and the lead frame 1h provided with the external terminal are joined by the conductive bonding layer 9e has been described, but the present invention is not limited to this, and the IGBT 2 and FWD 3 are not limited to this. The same configuration can be obtained even when the electrode of the above and the plate-shaped metal plate which is the wiring member inside the semiconductor device are joined by the conductive joining layer.

実施の形態５．
図１３は、本発明の実施の形態５における半導体装置を示す断面図である。図１３において、図７と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。本発明の実施の形態２とは、絶縁基板上に接合したＩＧＢＴ２、ＦＷＤ３、およびケース端子１６ｄ、１６ｅを、金属ワイヤの代わりに回路パターンが形成された配線基板を用いて導電性接合層で接合した構成が相違している。Embodiment 5.
FIG. 13 is a cross-sectional view showing the semiconductor device according to the fifth embodiment of the present invention. In FIG. 13, those having the same reference numerals as those in FIG. 7 indicate the same or corresponding configurations, and the description thereof will be omitted. In the second embodiment of the present invention, the IGBTs 2 and FWD3 bonded on the insulating substrate and the case terminals 16d and 16e are bonded by a conductive bonding layer using a wiring board in which a circuit pattern is formed instead of a metal wire. The configuration is different.

図１３に示すように、半導体装置５００は、絶縁基板１３の回路パターン１３ａ上にＩＧＢＴ２およびＦＷＤ３がはんだ材料４ａおよび４ｂで接合されており、絶縁基板１３に接合された側と反対側の面に位置するＩＧＢＴ２のエミッタ電極とＦＷＤ３のアノード電極とが導電性接合層９ｅおよび９ｆにより配線基板３５に接合されている。また、ＩＧＢＴ２のゲート電極も導電性接合層９ｇにより配線基板３５に接合されている。配線基板３５は、ガラスエポキシなどの基材部３５ｂの両面に回路パターン３５ａが形成されて構成されている。回路パターン３５ａは銅やアルミニウムなどの導電率が高い金属で形成されている。また、配線基板３５は基材部３５ｂの縁部にスルーホール３５ｃが形成されている。 As shown in FIG. 13, in the semiconductor device 500, the IGBTs 2 and FWD 3 are bonded to the circuit pattern 13a of the insulating substrate 13 with the solder materials 4a and 4b, and the surface is opposite to the side bonded to the insulating substrate 13. The position emitter electrode of the IGBT 2 and the anode electrode of the FWD 3 are bonded to the wiring board 35 by the conductive bonding layers 9e and 9f. Further, the gate electrode of the IGBT 2 is also bonded to the wiring board 35 by the conductive bonding layer 9g. The wiring board 35 is configured by forming a circuit pattern 35a on both sides of a base material portion 35b such as glass epoxy. The circuit pattern 35a is made of a metal having high conductivity such as copper or aluminum. Further, the wiring board 35 has a through hole 35c formed at the edge of the base material portion 35b.

図１３に示すように、半導体装置５００のケース１４には、外部端子１１ｄ、１１ｅとなるケース端子１６ｄ、１６ｅが設けられており、ケース端子１６ｄ、１６ｅの外部端子１１ｄ、１１ｅと反対側の端部が配線基板３５のスルーホール３５ｃに挿入されている。そして、スルーホール３５ｃに挿入されたケース端子１６ｄ、１６ｅと配線基板３５の回路パターン３５ａとを導電性接合層９ｉで接合して、回路パターン３５ａとケース端子１６ｄ、１６ｅとを電気的に接続している。また、絶縁基板１３の回路パターン１３ａと配線基板３５の回路パターン３５ａとが導電性接合層９ｈで接合され、絶縁基板１３の回路パターン１３ａと配線基板３５の回路パターン３５ａとが電気的に接続されている。 As shown in FIG. 13, the case 14 of the semiconductor device 500 is provided with case terminals 16d and 16e serving as external terminals 11d and 11e, and the ends of the case terminals 16d and 16e opposite to the external terminals 11d and 11e. The portion is inserted into the through hole 35c of the wiring board 35. Then, the case terminals 16d and 16e inserted into the through holes 35c and the circuit pattern 35a of the wiring board 35 are joined by the conductive bonding layer 9i, and the circuit pattern 35a and the case terminals 16d and 16e are electrically connected. ing. Further, the circuit pattern 13a of the insulating substrate 13 and the circuit pattern 35a of the wiring board 35 are joined by the conductive bonding layer 9h, and the circuit pattern 13a of the insulating substrate 13 and the circuit pattern 35a of the wiring board 35 are electrically connected. ing.

図１４は、本発明の実施の形態５における半導体装置のＩＧＢＴと配線基板との接合部の構成を示す拡大断面図である。図１４は、図１３のＩＧＢＴ２の接合部の構成を拡大して示した断面図である。ＦＷＤ３の接合部も同様の構成をしている。 FIG. 14 is an enlarged cross-sectional view showing a configuration of a joint portion between the IGBT of the semiconductor device and the wiring board according to the fifth embodiment of the present invention. FIG. 14 is an enlarged cross-sectional view showing the configuration of the joint portion of the IGBT 2 of FIG. The joint portion of FWD3 has a similar structure.

図１４に示すように、第１の金属部材２５であるＩＧＢＴ２の電極２６はエミッタ電極である。電極２６は、アルミニウム膜などの酸化されやすい金属からなる膜で形成されている。電極２６上に金属線２２ａの第１の端部２１ａと第２の端部２３ａとが超音波接合され、金属線２２ａの胴体部が第１の端部２１ａが接合された電極２６の表面に沿って延伸している。また、ＩＧＢＴ２のゲート電極２ａ上には、ボールボンディングによりゲート電極２ａの表面に接合した第１の端部３６のみが接合されている。 As shown in FIG. 14, the electrode 26 of the IGBT 2 which is the first metal member 25 is an emitter electrode. The electrode 26 is formed of a film made of a metal that is easily oxidized, such as an aluminum film. The first end 21a and the second end 23a of the metal wire 22a are ultrasonically bonded onto the electrode 26, and the body portion of the metal wire 22a is bonded to the surface of the electrode 26 to which the first end 21a is bonded. It extends along. Further, only the first end portion 36 bonded to the surface of the gate electrode 2a by ball bonding is bonded onto the gate electrode 2a of the IGBT 2.

配線基板３５に形成された回路パターン３５ａは、ＩＧＢＴ２の電極２６とＦＷＤ３の電極やケース端子１６ｅとの電気配線や、ＩＧＢＴ２のゲート電極２ａとケース端子１６ｄや制御用の半導体素子との電気配線をパターニングしたものである。配線基板３５は、リードフレームとは異なり、例えば、ゲート電位とエミッタ電位といった異なる電位の回路パターンを同一の配線基板３５内に形成することができるので、ワイヤボンディングを使用せずに半導体装置５００内の電気回路を形成することができるので、半導体装置を小型化することができる。 The circuit pattern 35a formed on the wiring board 35 provides electrical wiring between the electrode 26 of the IGBT 2 and the electrode of the FWD 3 and the case terminal 16e, and electrical wiring between the gate electrode 2a of the IGBT 2 and the case terminal 16d and the semiconductor element for control. It is patterned. Unlike the lead frame, the wiring board 35 can form circuit patterns of different potentials such as a gate potential and an emitter potential in the same wiring board 35, so that the wiring board 35 can be formed in the semiconductor device 500 without using wire bonding. Since the electric circuit of the above can be formed, the semiconductor device can be miniaturized.

図１４に示すように、ＩＧＢＴ２の電極２６と配線基板３５の回路パターン３５ａとの間には導電性接合層９ｅが設けられ、導電性接合層９ｅが金属線２２ａの胴体部を埋設している。つまり、本実施の形態５では、ＩＧＢＴ２の電極２６やＦＷＤ３の電極が第１の金属部材２５であって、配線基板３５の回路パターン３５ａが第２の金属部材である。また、ＩＧＢＴ２のゲート電極２ａよりも酸化されにくい金属からなる第１の端部３６のみが接合されたゲート電極２ａも導電性接合層９ｇにより配線基板３５の回路パターン３５ａに接合される。なお、金属線を配線基板３５の回路パターン３５ａ側に設けて、回路パターン３５ａを第１の金属部材とし、ＩＧＢＴ２やＦＷＤ３の回路パターン３５ａに接合される側の電極を第２の金属部材としてもよい。 As shown in FIG. 14, the conductive bonding layer 9 e is provided between the electrode 26 of the IGBT2 and the circuit pattern 35a of the wiring board 35, the conductive bonding layer 9 e is embedded body portion of the metal wire 22a ing. That is, in the fifth embodiment, the electrode 26 of the IGBT 2 and the electrode of the FWD 3 are the first metal member 25, and the circuit pattern 35a of the wiring board 35 is the second metal member. Further, the gate electrode 2a to which only the first end portion 36 made of a metal that is less likely to be oxidized than the gate electrode 2a of the IGBT 2 is bonded is also bonded to the circuit pattern 35a of the wiring board 35 by the conductive bonding layer 9g. A metal wire may be provided on the circuit pattern 35a side of the wiring board 35, the circuit pattern 35a may be used as the first metal member, and the electrode bonded to the circuit pattern 35a of the IGBT 2 or FWD3 may be used as the second metal member. Good.

図１３および図１４に示す半導体装置５００は、例えば、以下のような工程により製造することができる。まず、絶縁基板１３の回路パターン１３ａ上に、ＩＧＢＴ２およびＦＷＤ３をはんだ材料４ａ、４ｂで接合する。次に、ＩＧＢＴ２の電極２６表面に金属線２２ａを超音波接合する。同様に、ＦＷＤ３の電極表面に金属線を超音波接合する。なお、ＩＧＢＴ２の電極２６およびＦＷＤ３の電極に金属線を超音波接合する工程は、ＩＧＢＴ２およびＦＷＤ３を絶縁基板１３にはんだ付けする前に行ってもよい。 The semiconductor device 500 shown in FIGS. 13 and 14 can be manufactured, for example, by the following steps. First, the IGBTs 2 and FWD 3 are joined with the solder materials 4a and 4b on the circuit pattern 13a of the insulating substrate 13. Next, the metal wire 22a is ultrasonically bonded to the surface of the electrode 26 of the IGBT 2. Similarly, a metal wire is ultrasonically bonded to the electrode surface of FWD3. The step of ultrasonically bonding the metal wire to the electrode 26 of the IGBT 2 and the electrode of the FWD 3 may be performed before soldering the IGBT 2 and FWD 3 to the insulating substrate 13.

次に、ＩＧＢＴ２の金属線２２ａを接合した電極２６上、ＦＷＤ３の金属線を接合した電極上、および絶縁基板１３の回路パターン１３ａの所定の位置に導電性接着剤をディスペンサなどで供給する。そして、位置決め治具などを用いて配線基板３５のスルーホール３５ｃをケース端子１６ｄ、１６ｅに挿入し、導電性接着剤上に配線基板３５の回路パターン３５ａを配置する。次に、配線基板３５のスルーホール３５ｃに導電性接着剤を塗布する。そして、加熱して導電性接着剤を硬化させることで、図１３に示す導電性接合層９ｅ、９ｆ、９ｇ、９ｈ、９ｉが形成される。その後、ＩＧＢＴ２、ＦＷＤ３、配線基板３５などを封止樹脂で封止することで半導体装置５００を製造することができる。 Next, the conductive adhesive is supplied to a predetermined position on the electrode 26 to which the metal wire 22a of the IGBT 2 is joined, on the electrode to which the metal wire of the FWD 3 is joined, and the circuit pattern 13a of the insulating substrate 13 by a dispenser or the like. Then, the through holes 35c of the wiring board 35 are inserted into the case terminals 16d and 16e using a positioning jig or the like, and the circuit pattern 35a of the wiring board 35 is arranged on the conductive adhesive. Next, a conductive adhesive is applied to the through holes 35c of the wiring board 35. Then, by heating and curing the conductive adhesive, the conductive bonding layers 9e, 9f, 9g, 9h, and 9i shown in FIG. 13 are formed. After that, the semiconductor device 500 can be manufactured by sealing the IGBT 2, FWD3, the wiring board 35, and the like with a sealing resin.

図１５は、本発明の実施の形態５における半導体装置の他の構成のＩＧＢＴと配線基板との接合部の構成を示す拡大断面図および拡大平面図である。図１５（ａ）は、ＩＧＢＴ２と絶縁基板１３および配線基板３５との接合部の構成を示す拡大断面図であって、図１５（ｂ）は、絶縁基板１３の表面側の様子を示した拡大平面図である。図１５に示す半導体装置は、図１３および図１４に示す半導体装置とは、位置決め治具を用いずに製造できる構成が相違する。 FIG. 15 is an enlarged cross-sectional view and an enlarged plan view showing a configuration of a joint portion between the IGBT and the wiring board of another configuration of the semiconductor device according to the fifth embodiment of the present invention. FIG. 15A is an enlarged cross-sectional view showing the configuration of the joint portion between the IGBT 2 and the insulating substrate 13 and the wiring board 35, and FIG. 15B is an enlarged view showing the state of the surface side of the insulating substrate 13. It is a plan view. The semiconductor device shown in FIG. 15 differs from the semiconductor device shown in FIGS. 13 and 14 in a configuration that can be manufactured without using a positioning jig.

図１５（ａ）に示すように、配線基板３５のスルーホール３５ｃ内には、金属からなるピン端子３７が設けられており、ピン端子３７によって絶縁基板１３と配線基板３５とが電気的に接続されている。絶縁基板１３の回路パターン１３ａとピン端子３７とは導電性接合層９ｊによって接合され、配線基板３５の回路パターン３５ａとピン端子３７とは導電性接合層９ｉによって接合されている。 Figure 15 (a), the In the through hole 35c of the wiring board 35, and the pin terminals 37 made of metallic is provided by the pin terminal 37 and the insulating substrate 13 and the wiring board 35 is electrically It is connected. The circuit pattern 13a of the insulating substrate 13 and the pin terminal 37 are bonded by the conductive bonding layer 9j, and the circuit pattern 35a of the wiring board 35 and the pin terminal 37 are bonded by the conductive bonding layer 9i.

また、図１５（ｂ）に示すように、ＩＧＢＴ２がはんだ材料４ａで接合された絶縁基板１３は、ＩＧＢＴ２の角部およびピン端子３７の周辺において、回路パターン１３ａが一部除去されている。このため、絶縁基板１３は、回路パターン１３ａが形成された側からＩＧＢＴ２の角部およびピン端子３７の周辺において、絶縁層１３ｂを視認することができる構成となっている。 Further, as shown in FIG. 15B, the circuit pattern 13a is partially removed from the corner portion of the IGBT 2 and the periphery of the pin terminal 37 in the insulating substrate 13 to which the IGBT 2 is bonded with the solder material 4a. Therefore, the insulating substrate 13 has a configuration in which the insulating layer 13b can be visually recognized from the side where the circuit pattern 13a is formed around the corner portion of the IGBT 2 and the pin terminal 37.

図１５に示す半導体装置は、図１３および図１４の半導体装置とは異なり、位置決め治具を用いずに製造することができる。配線基板３５が大型の場合、位置決め治具も大型になるため、位置決め治具を用いて位置決めしようとすると、取り回しが困難となり作業性が悪化する。また、位置決め治具を用いずに配線基板３５を接合しようとすると、面積が小さいゲート電極２ａの位置ずれが大きくなり、特性不良が生じやすくなる。 Unlike the semiconductor devices shown in FIGS. 13 and 14, the semiconductor device shown in FIG. 15 can be manufactured without using a positioning jig. When the wiring board 35 is large, the positioning jig is also large. Therefore, when positioning is performed using the positioning jig, handling becomes difficult and workability deteriorates. Further, if the wiring board 35 is to be joined without using the positioning jig, the misalignment of the gate electrode 2a having a small area becomes large, and the characteristic defect is likely to occur.

図１５に示す半導体装置では、図１５（ｂ）に示すように絶縁基板１３におけるＩＧＢＴ２の角部およびピン端子３７の周辺の回路パターン１３ａを除去しているため、ＩＧＢＴ２を絶縁基板１３の回路パターン１３ａにはんだ付けする際のはんだの濡れ力により、ＩＧＢＴ２およびピン端子３７の位置を一意的に決めることができる。従って、図１５（ｂ）に示すようにＩＧＢＴ２の角部およびピン端子３７の周辺の回路パターン１３ａを除去した絶縁基板１３にＩＧＢＴ２やＦＷＤ３をはんだ付けした後に、２本以上のピン端子３７を配線基板３５のスルーホール３５ｃに挿入することで配線基板３５の位置決めを行うことができる。この結果、配線基板３５の回路パターン３５ａとＩＧＢＴ２との位置関係のばらつきを小さくして、特性不良の発生を抑制することができる。 In the semiconductor device shown in FIG. 15, since the circuit pattern 13a around the corners of the IGBT 2 and the pin terminal 37 on the insulating substrate 13 is removed as shown in FIG. 15B, the IGBT 2 is used as the circuit pattern of the insulating substrate 13. The positions of the IGBT 2 and the pin terminal 37 can be uniquely determined by the wetting force of the solder when soldering to the 13a. Therefore, as shown in FIG. 15B, after soldering the IGBT 2 and FWD 3 to the insulating substrate 13 from which the circuit pattern 13a around the corners of the IGBT 2 and the pin terminals 37 has been removed, two or more pin terminals 37 are wired. The wiring board 35 can be positioned by inserting it into the through hole 35c of the board 35. As a result, the variation in the positional relationship between the circuit pattern 35a of the wiring board 35 and the IGBT 2 can be reduced, and the occurrence of characteristic defects can be suppressed.

上記実施の形態１〜５では、第１の金属部材に接合される金属線は、第１の端部と第２の端部の両方が第１の金属部材の表面に金属結合により接合されている場合について説明したが、第１の端部のみが第１の金属部材の表面に金属結合により接合されていてもよい。 In the first to fifth embodiments, the metal wire to be joined to the first metal member has both the first end and the second end joined to the surface of the first metal member by metal bonding. However, only the first end portion may be bonded to the surface of the first metal member by a metal bond.

また、上記実施の形態１〜５では、導電性接合層にエポキシ樹脂やシリコン樹脂に銀粒子などの金属粒子を含有する導電性接着剤である場合につて説明したが、導電性接合層はこれに限るものではなく、はんだ材料など他の導電性接合層であってもよい。 Further, in the above-described first to fifth embodiments, the case where the conductive adhesive is a conductive adhesive containing metal particles such as silver particles in an epoxy resin or a silicon resin in the conductive bonding layer has been described. However, it may be another conductive bonding layer such as a solder material.

１ａ、１ｂ、１ｃ、１ｈ リードフレーム
２ ＩＧＢＴ
３ ＦＷＤ
８ａ、８ｂ 半導体素子
９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆ 導電性接合層
１３ 絶縁基板、１３ａ 回路パターン、１３ｂ 絶縁層、１３ｃ 金属ベース板
１６ｄ、１６ｅ ケース端子
１７ｆ、１７ｇ リード端子
２０ 酸化膜
２１ａ、２１ｂ、２１ｃ、２１ｄ、２１ｅ、２１ｆ、２１ｇ、２１ｉ、２１ｊ 第１の端部
２２ａ、２２ｂ、２２ｃ、２２ｄ、２２ｅ、２２ｆ、２２ｇ、２２ｉ、２２ｊ 金属線
２３ａ、２３ｂ、２３ｃ、２３ｄ、２３ｅ、２３ｆ、２３ｇ、２３ｉ、２３ｊ 第２の端部
２４ 電極（第２の金属部材）
２５ 第１の金属部材
２９ｇ、２９ｈ、２９ｉ、２９ｊ 接合部
３５ 配線基板、３５ａ 回路パターン、３５ｂ 基材部、３５ｃ スルーホール
３７ ピン端子1a, 1b, 1c, 1h lead frame 2 IGBT
3 FWD
8a, 8b Semiconductor elements 9a, 9b, 9c, 9d, 9e, 9f Conductive bonding layer 13 Insulation substrate, 13a Circuit pattern, 13b Insulation layer, 13c Metal base plate 16d, 16e Case terminal 17f, 17g Lead terminal 20 Oxide film 21a , 21b, 21c, 21d, 21e, 21f, 21g, 21i, 21j First end 22a, 22b, 22c, 22d, 22e, 22f, 22g, 22i, 22j Metal wire 23a, 23b, 23c, 23d, 23e, 23f, 23g, 23i, 23j Second end 24 electrode (second metal member)
25 First metal member 29g, 29h, 29i, 29j Joint 35 Wiring board, 35a circuit pattern, 35b Base material, 35c Through hole 37 pin terminal

Claims (17)

第１の金属部材と、
前記第１の金属部材と電気的に接続される第２の金属部材と、
前記第１の金属部材と前記第２の金属部材との間に設けられ、前記第１の金属部材と前記第２の金属部材とに接合された導電性接合層と、
前記第１の金属部材に接合された第１の端部および前記導電性接合層内に設けられた胴体部を有し、前記胴体部が前記第１の金属部材の表面に沿って延伸した金属線と、
を備えた半導体装置。 The first metal member and
A second metal member that is electrically connected to the first metal member,
A conductive bonding layer provided between the first metal member and the second metal member and bonded to the first metal member and the second metal member.
A metal having a first end portion joined to the first metal member and a body portion provided in the conductive joint layer, the body portion extending along the surface of the first metal member. Lines and,
Semiconductor device equipped with. 前記金属線の前記胴体部が、前記第２の金属部材と接触している請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the body portion of the metal wire is in contact with the second metal member. 前記金属線は、第２の端部をさらに有し、
前記第２の端部が、前記第１の金属部材に接合された請求項１または２に記載の半導体装置。 The metal wire further has a second end and
The semiconductor device according to claim 1 or 2, wherein the second end is joined to the first metal member. 前記金属線は、前記第１の端部と前記第２の端部との間に設けられた接合部を有し、前記接合部が前記第１の金属部材に接合された請求項３に記載の半導体装置。 The third aspect of claim 3, wherein the metal wire has a joint portion provided between the first end portion and the second end portion, and the joint portion is joined to the first metal member. Semiconductor device. 前記金属線を複数有し、
前記複数の金属線が放射状に設けられた請求項１から４のいずれか１項に記載の半導体装置。 Having a plurality of the metal wires
The semiconductor device according to any one of claims 1 to 4, wherein the plurality of metal wires are provided radially. 前記金属線の第１の端部の断面積は、前記金属線の胴体部の断面積よりも大きい請求項１から５のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 5, wherein the cross-sectional area of the first end portion of the metal wire is larger than the cross-sectional area of the body portion of the metal wire. 前記第１の金属部材は、卑金属または卑金属を含有する金属である請求項１から６のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 6, wherein the first metal member is a base metal or a metal containing a base metal. 前記卑金属は、アルミニウム、銅、ニッケル、錫のいずれかである請求項７に記載の半導体装置。 The base metal is aluminum, copper, nickel, semi-conductor device according to claim 7 is any one of tin. 前記金属線の前記胴体部の表面は、貴金属または貴金属を含有する合金である請求項１から８のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 8, wherein the surface of the body portion of the metal wire is a noble metal or an alloy containing the noble metal. 前記貴金属は、金、銀のいずれかである請求項９に記載の半導体装置。 The semiconductor device according to claim 9, wherein the precious metal is either gold or silver. 前記導電性接合層は、金属粒子を含有する導電性接着剤である請求項１から１０のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 10, wherein the conductive bonding layer is a conductive adhesive containing metal particles. 前記導電性接着剤は、前記金属粒子と金属結合した金属ナノ粒子を含有する請求項１１に記載の半導体装置。 The semiconductor device according to claim 11, wherein the conductive adhesive contains metal nanoparticles metal-bonded to the metal particles. 電極を有する半導体素子と、
前記半導体素子の電極と電気的に接続されたリードフレームと、
を備えた半導体装置であって、
前記半導体素子の電極または前記リードフレームのいずれか一方が前記第１の金属部材であり、前記半導体素子の電極または前記リードフレームの他方が前記第２の金属部材である請求項１から１２のいずれか１項に記載の半導体装置。 Semiconductor devices with electrodes and
A lead frame electrically connected to the electrodes of the semiconductor element,
It is a semiconductor device equipped with
Any of claims 1 to 12, wherein either the electrode of the semiconductor element or the lead frame is the first metal member, and the electrode of the semiconductor element or the other of the lead frame is the second metal member. The semiconductor device according to item 1. 半導体素子が接合された基板に設けられた回路パターンと、
前記回路パターンに電気的に接続されたリード端子と、
を備えた半導体装置であって、
前記回路パターンまたは前記リード端子のいずれか一方が前記第１の金属部材であり、前記回路パターンまたは前記リード端子の他方が前記第２の金属部材である請求項１から１２のいずれか１項に記載の半導体装置。 The circuit pattern provided on the substrate to which the semiconductor elements are bonded and
Lead terminals electrically connected to the circuit pattern,
It is a semiconductor device equipped with
The invention according to any one of claims 1 to 12, wherein either one of the circuit pattern or the lead terminal is the first metal member, and the other of the circuit pattern or the lead terminal is the second metal member. The semiconductor device described. 電極を有する半導体素子と、
前記半導体素子が接合された基板に設けられ、前記半導体素子の電極と電気的に接続された回路パターンと、
を備えた半導体装置であって、
前記半導体素子の電極または前記回路パターンのいずれか一方が前記第１の金属部材であり、前記半導体素子の電極または前記回路パターンの他方が前記第２の金属部材である請求項１から１２のいずれか１項に記載の半導体装置。 Semiconductor devices with electrodes and
A circuit pattern provided on a substrate to which the semiconductor element is bonded and electrically connected to an electrode of the semiconductor element, and a circuit pattern.
It is a semiconductor device equipped with
Any of claims 1 to 12, wherein either the electrode of the semiconductor element or the circuit pattern is the first metal member, and the electrode of the semiconductor element or the other of the circuit pattern is the second metal member. The semiconductor device according to item 1. 第１の電極および前記第１の電極の裏側に第２の電極を有する半導体素子と、
前記半導体素子が接合された第１の基板に設けられ、前記半導体素子の前記第１の電極と電気的に接続された第１の回路パターンと、
前記半導体素子が接合された第２の基板に設けられ、前記半導体素子の前記第２の電極と電気的に接続された第２の回路パターンと、
を備えた半導体装置であって、
前記半導体素子の前記第２の電極または前記第２の回路パターンのいずれか一方が前記第１の金属部材であり、前記半導体素子の前記第２の電極または前記第２の回路パターンの他方が前記第２の金属部材である請求項１から１２のいずれか１項に記載の半導体装置。 A semiconductor device having a first electrode and a second electrode on the back side of the first electrode,
A first circuit pattern provided on a first substrate to which the semiconductor element is bonded and electrically connected to the first electrode of the semiconductor element, and a first circuit pattern.
A second circuit pattern provided on the second substrate to which the semiconductor element is bonded and electrically connected to the second electrode of the semiconductor element, and a second circuit pattern.
It is a semiconductor device equipped with
Either one of the second electrode or the second circuit pattern of the semiconductor element is the first metal member, and the second electrode of the semiconductor element or the other of the second circuit pattern is said. The semiconductor device according to any one of claims 1 to 12, which is a second metal member. 前記第２の基板はスルーホールを有し、
前記第２の回路パターンが前記スルーホールに挿入されたピン端子を介して前記第１の回路パターンに電気的に接続された請求項１６に記載の半導体装置。 The second substrate has through holes and has a through hole.
The semiconductor device according to claim 16, wherein the second circuit pattern is electrically connected to the first circuit pattern via a pin terminal inserted into the through hole.
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